JP2011229001A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the prevention of false detection of a signal loss in a receiver provided for a high-speed interface.SOLUTION: A receiver includes a quantization section for quantizing an input signal inputted through a transmission path to generate a digital signal, an input equalizer section for generating a signal which emphasizes a first frequency component included in the input signal, a loss detection section for detecting a loss of the input signal when the amplitude of the signal generated by the input equalizer falls short of a first threshold, and a amplification control section for controlling the amount of amplification of the first frequency component generated by the input equalizer section based on the digital signal obtained by the quantization section.

Description

  The present invention relates to a receiving device provided in a high-speed interface in an integrated circuit chip or between chips.

  As high-speed interface standards for connecting integrated circuit chips, chips on boards, and chips mounted on different boards, various high-speed interfaces are widely used. Examples of such high-speed interfaces include Serial-ATA (Advanced Technology Attachment), PCI (Peripheral Component Interconnect) -Express, USB 3.0, and 10 Gbit-Ethernet (registered trademark).

  The reception device provided in the high-speed interface as described above is provided with a function of automatically switching the signal processing circuit in the reception device to the power saving mode when there is no reception signal. Such a power saving control function by hardware is realized, for example, by detecting a stop of the received signal by a signal loss detection device and controlling the power supply to the signal processing circuit by the power supply control unit accordingly. (See Patent Document 1).

  This signal loss detection device generates, for example, a signal loss detection signal indicating that the input signal has disappeared when the amplitude of the signal input via the transmission line falls below a predetermined threshold, A configuration for notifying the control unit is provided.

  In the above-mentioned standards for high-speed interfaces such as PCI-Express and USB3.0, the range of the amplitude of the transmitted signal is defined. Then, based on the standard regarding the amplitude range of the transmission signal, threshold values used for determining whether or not the reception signal is stopped by the signal loss detection device described above are set.

JP 2009-176294 A

  By the way, in the conventional signal loss detection apparatus, the stop of the transmission signal is detected by applying the same threshold value regardless of the waveform of the transmission signal.

  However, in the transmission line, the high frequency signal component is attenuated more than the low frequency signal component. For this reason, in the transmission signal transmitted from the transmission side, the amplitude attenuation rate differs between the case where the period of the same signal level is relatively long and the case where the signal level frequently changes.

  For example, in a transmission signal transmitted corresponding to data with continuous bit values such as “00001111”, the section in which the signal level corresponding to the bit values “0” and “1” is maintained is relatively long. That is, in such a transmission signal, the ratio of the low frequency component is large and is not easily affected by transmission loss. On the other hand, in the transmission signal transmitted corresponding to the data in which the bit values appear alternately like “01010101...”, The signal level corresponding to the bit values “0” and “1” is maintained. The section is very short. In such a transmission signal, since the ratio of the high frequency component is large, the amplitude of the signal corresponding to each bit value is attenuated by the loss in the transmission path. In some cases, the amplitude of the signal that reaches the receiving apparatus falls below a threshold defined by the standard.

  In the conventional signal loss detection device, when the attenuated signal continuously arrives for a predetermined period, the signal loss is erroneously detected even though the signal transmission from the transmission side continues. There was a case.

  An object of the present disclosure is to provide a receiving device capable of preventing erroneous detection of signal loss.

  The above-described object can be achieved by the receiving device disclosed below.

  A receiving apparatus according to one aspect includes a quantization unit that quantizes an input signal input via a transmission path to generate a digital signal, and an input that generates a signal that emphasizes a first frequency component included in the input signal. Based on the digital signal obtained by the equalizer unit, the loss detection unit that detects the loss of the input signal when the amplitude of the signal generated by the input equalizer unit falls below the first threshold, and the digital signal obtained by the quantization unit An amplification strength control unit that controls the amount of amplification of the first frequency component by the equalizer unit.

  According to the receiving device of the present disclosure, it is possible to prevent erroneous detection of signal loss.

It is a figure which shows one Embodiment of a receiver. It is a figure explaining a transmission loss. It is a figure which shows another embodiment of a signal loss detection part. It is a flowchart showing signal loss detection operation. It is a figure which shows another embodiment of a receiver. It is a figure which shows one Embodiment of an input buffer equalizer. It is a flowchart showing signal loss detection operation. It is a figure which shows another embodiment of a receiver. It is a figure which shows another embodiment of a receiver.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 shows an embodiment of a receiving device.

  1 includes an input buffer (BF) 101, an analog / digital converter (ADC) 102, a demultiplexer (DMX) 103, a signal processor 104, a power control circuit 105, and a signal loss. And a detection unit 110.

  An input signal transmitted by the opposing transmission device and reaching the reception device is input to the analog / digital conversion unit 102 via the input buffer 101. The analog / digital conversion unit 102 converts the input signal into digital data by sampling the input signal according to a predetermined clock signal CLK. The analog / digital conversion unit 102 corresponds to a quantization unit. The digital data obtained by the analog / digital conversion unit 102 is input to the signal processing unit 104 after being parallelized by the demultiplexer 103. The signal processing unit 104 performs adaptive equalization processing, clock recovery processing, and the like on the parallel digital signals, and outputs the processing results as output data of the receiving device.

  The power supply control circuit 105 controls power supply to the analog circuit unit and the digital circuit unit in accordance with the loss detection signal from the signal loss detection unit 110. In the example shown in FIG. 1, the analog circuit unit includes an input buffer 101, an analog / digital conversion unit 102, a demultiplexer 103, an input equalizer unit 111 and a loss detection unit 112 of the signal loss detection unit 110. ing. The digital circuit unit includes a signal processing unit 104 and an amplification control unit 113 of the signal loss detection unit 110.

  In the signal loss detection unit 110 illustrated in FIG. 1, the input signal is input to the loss detection unit 112 via the input equalizer unit 111. The input equalizer unit 111 amplifies the high frequency component included in the input signal in accordance with the equalizer control signal from the amplification control unit 113. Therefore, by appropriately controlling the amount of amplification by the input equalizer unit 111, an input signal that compensates for the attenuation of the high-frequency component in the transmission path can be input to the loss detection unit 112.

  Here, the relationship between the magnitude of the transmission loss in the transmission path and the frequency of the transmission signal will be described.

  FIG. 2 is a diagram illustrating transmission loss. FIG. 2A shows a transmission signal waveform. On the other hand, FIG. 2B shows a reception signal waveform corresponding to the transmission signal shown in FIG. In FIG. 2B, the signal loss detection threshold is indicated by a broken line.

  As can be seen from the comparison between FIGS. 2A and 2B, the transmission signal is a high-frequency signal as in section A as compared to section B of the low-frequency signal having a long flat portion in the transmission signal waveform. In the section, the difference between the amplitude of the reception signal and the amplitude of the transmission signal is large. In the example shown in FIG. 2B, in the section A, the amplitude of the received signal is below the signal loss detection threshold. The conventional signal loss detection unit may erroneously detect the signal loss in such a section.

  The difference between the transmission loss in the section in which the transmission signal is a high frequency signal and the transmission loss in the section in which the transmission signal is a low frequency signal corresponds to, for example, the difference between the amplitude of the reception signal in section B and the amplitude of the reception signal in section A.

The amplification control unit 113 illustrated in FIG. 1 can obtain the difference d between the amplitude a _L of the low frequency signal and the amplitude a _{H of the} high frequency signal based on the digital data output from the demultiplexer 103. Based on this difference d, the input equalizer unit 111 can selectively amplify the high-frequency component included in the received signal. By performing such amplification control, the amplitude of the output signal output from the input equalizer unit 111 when a high-frequency signal is input can be increased. As a result, the amplitude of the output signal of the input equalizer 111 described above can be maintained at or above the signal loss detection threshold even in a section in which the signal of the first frequency component having a large transmission loss arrives from the transmission device. Therefore, the loss detection unit 112 does not erroneously detect the period in which the high frequency component signal corresponding to the first frequency component signal is received as the period in which the signal is lost.

  By preventing erroneous detection of signal loss, the power supply to the analog circuit part and digital circuit part of the receiving device is reliably maintained over the period in which the transmission signal exists, regardless of the frequency component of the transmitted signal. Can do. That is, in the receiving device provided with the signal loss detection unit 110 as illustrated in FIG. 1, the operating state of the receiving device does not shift to the power saving mode according to the frequency component of the transmission signal. Thus, by preventing the transition to the unnecessary power saving mode, the stability of data transmission from the transmission device to the reception device can be improved.

Next, a method for estimating the difference in transmission loss between the high frequency component and the low frequency component and controlling the amplification amount in the input equalizer unit 111 based on the estimation result will be described.
(Embodiment 2)
FIG. 3 shows another embodiment of the signal loss detection unit. 3 that are equivalent to the components shown in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

  In the example illustrated in FIG. 3, the input equalizer unit 111 includes a variable capacitance circuit corresponding to the differential inputs in and inx. Each variable capacitance circuit includes three capacitors and switches corresponding to these capacitors. The three capacitors described above are connected in parallel to the input resistance by corresponding switches according to the equalizer control signal. The differential outputs out and outx of the input equalizer unit 111 are differentially input to the loss detection unit 112.

  The loss detection unit 112 includes comparators C and Cx corresponding to the differential inputs in and inx and an OR gate. These comparators C and Cx compare the reference voltages Ref and Refx corresponding to the signal loss detection threshold described above with the differential inputs in and inx. The OR gate calculates the logical sum of the output signals of the comparators C and Cx, and the output of the OR gate is input to the power supply control circuit 105 as a signal loss detection signal. In the example shown in FIG. 3, when the absolute value of the amplitude of the input signal represented by the differential inputs in and inx falls below the signal loss detection threshold described above, the signal loss detection signal becomes logic “1”. It is indicated that the state where the transmission signal is lost has started. On the other hand, when at least one of the absolute values of the amplitudes exceeds the signal loss detection threshold described above, the loss detection unit 112 sets the signal loss detection signal to logic “0” and cancels the signal loss state to the power supply control circuit 105. Notice.

  The amplification control unit 113 illustrated in FIG. 3 includes a signal determination unit 114, an amplitude detection unit 115, a memory 116, a loss calculation unit 117, and an amplification amount table 118. The digital signal output from the demultiplexer 103 is input to the signal determination unit 114 and the amplitude detection unit 115.

  The signal discriminating unit 114 discriminates a test pattern transmitted from the transmission device when communication is started in the high-speed interface. The signal discriminating unit 114 can discriminate, for example, LFPS (Low Frequency Periodic Signal) transmitted at the start of transmission as a test pattern for low frequency components in accordance with USB 3.0 regulations. Further, the signal determination unit 114 can determine the adaptive equalization control adjustment signal transmitted subsequent to the LFPS as a test pattern for high frequency components.

In response to an instruction from the signal determination unit 114, the amplitude detection unit 115 performs processing for detecting the amplitude of the received signal waveform represented by the input digital signal. For example, the signal determination unit 114 can instruct the amplitude detection unit 115 to detect the amplitude of the received signal when detecting the test patterns for the low frequency component and the high frequency component described above. This makes it possible to pass the amplitude S _L when the received signal is a low frequency signal, when the received signal is a high frequency signal the amplitude S _H respectively detected, the loss calculation unit 117 via the memory 116 .

Loss calculation unit 117, for example, based on the difference between the amplitude S _L and the amplitude S _H stored in the memory 116, obtains the transmission size of the loss R _H of the high-frequency signal based on the transmission loss of the low frequency signal be able to.

Also, the amplification amount table 118 holds equalizer control signals for setting an appropriate amplification amount in the above-described input equalizer 111 in order to compensate for transmission losses of various sizes. . Then, in response to the input of the transmission loss _RH of the high frequency signal, the amplification amount table 118 outputs the equalizer control signal held corresponding to the input transmission loss value.

In the example illustrated in FIG. 3, the amplification amount table 118 includes 3-bit equalizer control signals respectively input to the variable capacitance circuits for the differential inputs in and inx corresponding to the values of the transmission loss _RH. Is retained. Each bit of the equalizer control signal corresponds to three switches provided in the variable capacitance circuit, and controls ON / OFF of each switch. Thus, when the equalizer control signal input to each variable capacitance circuit is 3 bits, the equalizer control signal is 6 bits in total. Note that the number of capacitors provided in the variable capacitance circuit can be less than 3, and conversely, the input equalizer unit 111 can be configured using a variable capacitance circuit including four or more capacitors.

  FIG. 4 is a flowchart showing the signal loss detection operation.

  A test pattern for a low frequency signal is transmitted from the transmission device when communication is started or restarted. In response to receiving this test pattern, the signal discriminating unit 114 detects the test pattern for the low frequency signal (step 301). At this time, the loss detection unit 112 notifies the power supply control circuit 105 of the cancellation of the signal loss state (step 302), and the entire analog circuit unit and digital circuit unit of the receiving apparatus are in the operating state.

Furthermore, in response to detection of the test pattern for the low-frequency signal as described above, the amplitude detector 115, the amplitude S _L of the test pattern for the low-frequency signal is detected (step 303), stored in the memory 116.

Subsequent to the test pattern for low frequency signals described above, when a signal for adaptive equalization control adjustment is received, the signal discrimination unit 114 detects a test pattern for high frequency signals (step 304). In response to this, the amplitude detector 115, the amplitude S _H of the test pattern for the high-frequency signal is detected (step 305), stored in the memory 116.

Loss calculation unit 117, the amplitude S _L held in the memory _116, based on the S _H, calculates the transmission size of the loss R _H of the high-frequency signal based on the transmission loss of the low frequency signal (step 306). Then, by inputting this transmission loss to the amplification amount table 118, a corresponding equalizer control signal is read (step 307), and the variable capacitance circuit of the input equalizer unit 111 is set based on this equalizer control signal. (Step 308).

  In this manner, the input equalizer unit 111 can be set so as to compensate for the attenuation of the high-frequency signal in the transmission path based on the test pattern sent from the transmission device when communication is started or restarted.

  Thereafter, the signal loss detection unit repeats steps 309 and 310 to perform the signal loss monitoring process as in the prior art. As described above, in the signal loss detection unit 110 configured as shown in FIG. 3, the loss detection unit 112 compensates for the transmission loss of the high-frequency component of the signal compared with the signal loss detection threshold. Therefore, as long as communication is continued, the signal loss detection signal is maintained at logic “0”, and power supply to the analog circuit unit and the digital circuit unit by the power supply control circuit 105 is continued.

  Then, when the communication is completed and the reception signal reaching the reception device is lost, the loss detection unit 112 detects the signal loss only (positive determination at step 310), and the power supply control circuit 105 is detected based on the signal loss detection signal. Is notified that the signal loss state has started (step 311).

Instead of compensating the transmission loss of the high frequency signal for the input signal branched for the detection of the signal loss, the transmission loss of the high frequency signal is compensated for the input signal itself inputted to each part of the analog / digital converter 102 and the subsequent stage. You can also Hereinafter, a receiving apparatus including a signal loss detection unit that detects signal loss based on an input signal with compensated transmission loss will be described.
(Embodiment 3)
FIG. 5 shows another embodiment of the receiving apparatus. Note that among the components shown in FIG. 5, components equivalent to those shown in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

  The signal loss detection unit 120 illustrated in FIG. 5 includes a threshold setting unit 121, an input buffer equalizer 124, a loss detection unit 112, and an adaptive equalization control unit 125. In this signal loss detection unit 120, the output signal of the input buffer equalizer unit 124 is passed to the analog / digital conversion unit 102 and also to the loss detection unit 112. The adaptive equalization control unit 125 included in the signal processing unit 104 performs adaptive equalization control using a digital equalizer (not shown) provided in the digital signal input via the demultiplexer 103. Has the ability to do. And by this adaptive equalization control, the waveform of the transmission signal transmitted from the transmission device is digitally restored. Note that the restored transmission signal is subjected to processing by a clock recovery unit (CDR) 108.

  Further, the threshold setting unit 121 illustrated in FIG. 5 includes a DC generation unit 122 and a setting adjustment unit 123. The DC generator 122 is connected to the input terminal of the input buffer equalizer 124 via a switch. In addition, the DC generation unit 122 has a function of outputting a DC voltage corresponding to the signal loss detection threshold described above in response to an instruction from the setting adjustment unit 123. Then, the setting adjustment unit 123 instructs the DC generation unit 122 to output the above-described DC voltage, for example, when the receiving device is installed, and controls the switch to input the DC generation unit 122 and the input buffer equalizer 124. The end can be connected.

  The input buffer equalizer 124 shown in FIG. 5 is obtained by adding functions equivalent to the input equalizer unit 111 to the input buffer 101 shown in FIG.

  FIG. 6 shows an embodiment of the input buffer equalizer. In FIG. 6, symbols in and inx indicate differential inputs, and symbols out and outx indicate differential outputs.

  The input buffer equalizer 124 shown in FIG. 6 includes a variable capacitance circuit including three capacitors and a switch for turning on / off the connection of these capacitors in accordance with an equalizer control signal. As the input buffer equalizer 124, another configuration that realizes a function of selectively amplifying a high frequency component may be employed. For example, the capacitance of each capacitor provided in the variable capacitance circuit, the number of capacitors, and the like can be appropriately selected according to the high frequency component to be amplified.

  As for this equalizer control signal, for example, the adaptive equalization control unit 125 provided in the signal processing unit 104 performs adaptive equalization control using a digital equalizer provided in the digital signal input via the demultiplexer 103. It can be generated in the process of performing.

  Next, the operation of the signal loss detection unit that detects signal loss based on the input signal with compensated transmission loss will be described.

  FIG. 7 is a flowchart showing the signal loss detection operation. 7 that are equivalent to the procedure shown in FIG. 4 are denoted by the same reference numerals and description thereof is omitted. In FIG. 7, the digital equalizer and the input buffer equalizer are abbreviated as D-EQ and input BFEQ, respectively.

  In the flowchart shown in FIG. 7, before the start of communication, the loss detection unit 112 sets a signal loss detection threshold to be compared with the output signal of the input buffer equalizer 124 (step 321). For example, the setting adjustment unit 123 illustrated in FIG. 5 controls the switch and the DC generation unit 122 at the time of installation of the receiving device, and applies a DC voltage corresponding to the signal loss detection threshold to the input terminal of the input buffer equalizer 124. Let them enter. At this time, the setting adjustment unit 123 can adjust the reference voltages ref and refx of the loss detection unit 112 based on the DC voltage corresponding to the signal loss detection threshold. In this way, an appropriate signal loss detection threshold can be set in the loss detection unit 112 for comparison with the output signal of the input buffer equalizer 124.

  Thereafter, the cancellation of the signal loss state is notified in response to reception of the test pattern at the start or restart of communication (steps 301 and 302), and power supply to the analog circuit unit and the digital circuit unit is started.

  Then, when the adaptive equalization control adjustment signal is received following the above-described test pattern for the low frequency signal (step 304), the adaptive equalization control unit 125 performs adaptive equalization from step 322 to step 324. Control processing is started.

  The adaptive equalization control unit 125 sets the coefficient of the digital equalizer (D-EQ) and the coefficient of the input buffer equalizer (BFEQ) 124 provided therein, and searches for the optimum value (step 322). . At this time, the adaptive equalization control unit 125 can generate an equalizer control signal corresponding to the coefficient for the input buffer equalizer 124, and can input this equalizer control signal to the input buffer equalizer 124.

  Then, corresponding to each combination, an error is calculated by a digital equalizer (step 323). These processes are repeated for all combinations, and when the processes for all the coefficient combinations are completed, the adaptive equalization control unit 125 determines that the search is completed (Yes determination in step 324). At this time, the application equalization control unit 125 sets the digital equalizer and the input buffer equalizer 124 according to the combination of coefficients that minimizes the error (step 325).

  In this way, the equalizer to be input to the input buffer equalizer 124 in parallel with the process of adjusting the digital equalizer provided in the signal processing unit 104 by the adaptive equalization control unit 125 provided in the signal processing unit 104. Control signals can be searched.

  In the signal loss detection unit configured as shown in FIG. 5, the function of the input buffer 101 and the function of the input equalizer unit 111 are performed by the input buffer equalizer 124. Further, in the process of adjusting the digital equalizer by the adaptive equalization control unit 125, an equalizer control signal to be input to the input buffer equalizer 124 is generated. Thereby, compared with the structure of FIG. 1 which newly provided the input equalizer part 111 and the amplification control part 113, the increase in the amount of hardware can be suppressed.

By the way, in the receiving device provided in the high-speed interface, a slicer can be provided as a quantization unit instead of the analog / digital conversion unit 102. Next, a signal loss detection unit that is suitable for a receiving apparatus configured to perform quantization using a slicer will be described.
(Embodiment 4)
FIG. 8 shows another embodiment of the receiving device. 8 that are the same as those shown in FIG. 5 are given the same reference numerals, and descriptions thereof are omitted.

  In the receiving apparatus illustrated in FIG. 8, the output of the input buffer equalizer 124 is passed to the demultiplexer 103 via the slicer 109. In the signal loss detection unit 120, the adaptive equalization control unit 126 performs adaptive equalization control based on the parallelized digital signal output from the demultiplexer 103 and the signal before determination by the slicer 109 described above. Process.

  The slicer 109 has a smaller amount of hardware than the analog / digital conversion unit 102, which is advantageous in reducing the size of the receiving apparatus.

Further, the conventional signal loss detection unit and the signal loss detection unit described in the third embodiment can be combined and applied to the reception apparatus. Next, a signal loss detection unit to which such a combination configuration is applied will be described.
(Embodiment 5)
FIG. 9 shows another embodiment of the receiving device. Note that, among the components shown in FIG. 9, components equivalent to those shown in FIGS. 1 and 5 are denoted by the same reference numerals, and description thereof is omitted.

The signal loss detection unit 130 illustrated in FIG. 9 includes an input buffer equalizer 124, an adaptive equalization control unit 125, two loss detection units 112 _L and 112 _H, and a signal generation unit 128. The loss detection section 112 _L, the received signal from the transmission line is input, while the loss detection unit 112 _H, the output signal of the input buffer equalizer 124 is input. Loss detection unit 112 _L corresponds to the second loss detection unit, whereas, the loss detecting unit 112 _H corresponds to the first loss detection unit.

The loss detection section 112 _L, as in the prior art, by comparing the reference voltage signals received from the transmission path, the transmission signal to detect a loss of signal for the interval that is the low-frequency signal. On the other hand, the loss detection unit 112 _H, by comparing the reference voltage output signal of the input buffer equalizer 124, the transmission signal to detect a loss of signal for the interval that is the high frequency signal.

The output signals of the two loss detection units 112 _L and 112 _H described above are input to the signal generation unit 128. For example, the signal generation unit 128 generates a signal loss detection signal indicating that the signal loss is detected when a signal indicating that the signal loss is detected is output by both of the two loss detection units 112 _L and 112 _H. can do.

In this configuration, the output of the loss detection unit 112 _H is not used for signal loss detection for section transmission signal is in the low-frequency signal. Therefore, the threshold setting unit 121 shown in FIG. 5 is not necessary, and the circuit of the signal loss detection unit can be downsized.

101 Input buffer (BF)
102 Analog / digital converter (ADC)
103 Demultiplexer (DMX)
104 signal processing unit 105 power control circuit 108 clock recovery unit (CDR)
109 slicer 110, 120, 130 signal loss detection unit 111 input equalizer 112, 112 _L, 112 _H loss detection unit 113 amplifies the control section 114 signal determining portion 115 amplitude detector 116 amplifies amount table 121 threshold setting memory 117 loss calculation section 118 Unit 122 DC generation unit 123 setting adjustment unit 124 input buffer equalizer 125, 126 adaptive equalization control unit 128 signal generation unit

Claims (5)

A quantization unit that quantizes an input signal input via a transmission line and generates a digital signal;
An input equalizer unit that generates a signal that emphasizes the first frequency component included in the input signal;
A loss detection unit that detects the loss of the input signal when the amplitude of the signal generated by the input equalizer unit falls below a first threshold;
An amplification control unit that controls an amplification amount of the first frequency component by the input equalizer unit based on a digital signal obtained by the quantization unit;
A receiving apparatus comprising: A quantization unit that quantizes an input signal to generate a digital signal;
An input equalizer unit that generates a signal in which the first frequency component included in the input signal input via the transmission path is emphasized, and is input to the quantization unit;
A loss detection unit that detects the loss of the input signal when the amplitude of the signal generated by the input equalizer unit falls below a first threshold;
An amplification control unit that controls an amplification amount of the first frequency component by the input equalizer unit based on a digital signal obtained by the quantization unit;
A threshold adjuster for adjusting the threshold used for comparison with the amplitude of the signal in the loss detector;
A receiving apparatus comprising: A quantization unit that quantizes an input signal to generate a digital signal;
A second loss detection unit that detects a loss of the second frequency component of the input signal when the amplitude of the input signal input via the transmission line falls below a second threshold;
An input equalizer unit that generates a signal that emphasizes the first frequency component included in the input signal and inputs the signal to the quantization unit;
A first loss detection unit that detects a loss of the first frequency component of the input signal when the amplitude of the signal generated by the input equalizer unit falls below a first threshold;
An amplification control unit that controls an amplification amount of the first frequency component by the input equalizer unit based on a digital signal obtained by the quantization unit;
A signal generation unit that generates a loss detection signal indicating that the input signal has been lost, based on outputs of the second loss detection unit and the first loss detection unit;
A receiving apparatus comprising: The receiving device according to claim 1,
The amplification controller is
Based on the digital signal generated by the quantization unit for the second frequency component signal and the first frequency component signal included in the test pattern reached via the transmission path at the start of communication, the transmission path A loss estimation unit for estimating transmission loss in
An amplification amount calculation unit for obtaining an amplification amount of the first frequency component by the input equalizer unit so as to compensate for the transmission loss estimated by the loss estimation unit;
A receiving apparatus comprising: The receiving device according to claim 4,
The loss estimator is
A signal discriminating unit for discriminating between a section in which the signal of the second frequency component included in the test pattern is input and a section in which the signal of the first frequency component is input;
Based on the output signal of the quantization unit corresponding to each section determined by the signal determination unit, the amplitude of each of the second frequency component signal and the first frequency component signal included in the test pattern An amplitude detector for detecting a value;
A loss calculating unit that calculates a transmission loss for the first frequency component based on the amplitude value of the signal of the second frequency component and the amplitude value of the signal of the first frequency component;
A receiving apparatus comprising:

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