JP2000332835A - Equalization amplification.identification recovery circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an adjustment time of a threshold voltage reaching an optimum point and to enhance the identification input sensitivity of an identification recovery circuit. SOLUTION: The equalization amplification.identification recovery circuit is provided with an equalization amplification section 16 that amplifies a high frequency signal to output an equalization signal, an identification recovery section 18 that uses a D flip-flop 3 to receive an equalization signal outputted from the equalization amplification section 16 and to recover the signal, and a waveform shaping section 17 that applies limit shaping to the equalization signal outputted from the equalization amplification section 16 and applies differentiation to an input to the D flip-flop of the identification recovery section 18. The waveform shaping section 17 consists of a slice amplifier 2 that applies waveform shaping to an equalization signal input, a peak rectifier circuit 6b that receives a noninverted signal and an inverted signal outputted from the slice amplifier 2 and given to the D flip-flop 3 as differential inputs and detects respective peaks of the noninverted signal and an inverted signal, and an offset compensation circuit 7b that cancels a DC level offset on the basis of the difference between the respective peaks.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to an IC (integrated circuit) using bipolar transistors, and furthermore, equalization amplification, identification and reproduction in an optical receiver for a digital optical communication system. Circuit.

[0002]

2. Description of the Related Art Generally, an optical receiver for a digital optical communication system is configured as shown in FIG. That is, a light receiving element 201 that converts an optical input signal into a current, a preamplifier circuit 202 that converts an output current of the light receiving element 201 into a voltage signal, and amplifies an output voltage signal of the preamplifier circuit 202 to a certain amplitude. Equalizing amplifier circuit 203 and equalizing amplifier circuit 2
A timing circuit 204 that extracts a timing component from the output signal of No. 03 to generate a clock signal, and an output signal of the equalization amplification circuit 203 is identified as “1” or “0” based on the output clock signal of the timing circuit 204. An identification reproduction circuit 205 is provided.

Here, the equalizing amplification circuit 203 and the identification reproduction circuit 205 are integrated on the same integrated circuit in order to suppress signal waveform deterioration at a connection point in each integrated circuit. The configuration of the equalizing amplification circuit 203 and the identification reproducing circuit 205 integrated on the same integrated circuit is equalized and amplified.
This is called an identification reproduction circuit. Examples of this type of system include, for example, Makoto Hatakeyama et al., “2.4 Gb / s Optical Communication S
i-BIP LSI chipset "There is a report of IEICE Technical Committee ICD91-90.

FIG. 8 is a configuration diagram of a conventional equalization amplification / identification reproduction circuit. 8 includes a signal source 315, an equalizing amplifier 316, and an identification reproducing unit 31.
8, an average value circuit 319 is included. In the conventional equalization amplification / identification reproduction circuit, the threshold voltage generated by the average value circuit 319 based on the output from the equalization amplification unit 316 is supplied to the identification reproduction unit 318 (D flip-flop 303). Is entered. The threshold voltage is adjusted to an optimum point of identification in the identification reproducing section 318 by an input from the external terminal 320 at a stage subsequent to the average value circuit 319.

[0005] The equalizing amplifier 316 has a gain control function and an offset compensation function. As shown in FIG. 8, the equalizing amplification section 316 is provided with a differential amplification amplifier 301. One input terminal of the differential amplifier 301 is connected to the signal source 315 via the capacitor C1. One input terminal of the differential amplifier 301 is terminated via a resistor R4 and a capacitor C2 connected by a bonding wire or a lead terminal (L1), and the other input terminal is connected by a resistor R5 and a bonding wire or a lead. Terminal (L
It is terminated via the capacitor C3 connected in 2).
The differential amplifier 301 amplifies a signal input in two systems and outputs the amplified signal to a peak rectifier circuit 305 connected to each channel.

[0006] The peak rectifier circuit 305 detects the peak value of each high-frequency signal and outputs detection signals po1 and po2. An average value circuit 313 is connected to two output terminals of the peak rectifier circuit 305. The average value circuit 313 includes a resistor R that connects two output terminals of the peak rectifier circuit 305 in series.
1, R2, and detects the average value of the detection signals po1 and po2 output from the peak rectification circuit 305 and outputs the average value to the gain control circuit 306. The gain control circuit 306
Detection signals po1 and po output from the average circuit 313
The difference between the average value of 2 and the reference voltage of the gain control circuit 306 is obtained, and the output is fed back to the control terminal of the differential amplifier 301. With this gain control function, the differential amplifier 3
01 changes the gain corresponding to the amplitude value of the input signal,
A constant amplitude signal is output to the equalization output terminals 308 and 309 of the equalization amplification unit 316 connected to the output terminal of the differential amplification amplifier 301, and the input amplitude of the identification reproduction unit 318 (D flip-flop 303) is fixed. To prevent the deterioration of the bit error rate.

[0007] An offset compensation circuit 307 is connected to two output terminals of the peak rectifier circuit 305. The offset compensation circuit 307 detects a difference between the detection signals po1 and po2 output from the peak rectification circuit 305, and outputs one of the outputs via the resistors R3 and R4 and the other via the resistor R5. The signal is fed back to the input terminal 301. The output of the offset compensation circuit 307 fed back to the input terminal of the differential amplifier 301 is used for offset compensation.

The averaging circuit 319 includes a differential amplifier 30
1 and the positive-phase output and the negative-phase output are connected to a resistor R6.
It is connected by R7, and generates a threshold voltage to be supplied to the identification reproducing unit 318.

The identification reproducing section 318 comprises a D flip-flop 303 and an output amplifier 304. The D flip-flop 303 receives the threshold voltage supplied from the averaging circuit 319 and outputs a “1” or “0” signal based on a clock signal input from the external terminal 312. The output amplifier 304 amplifies the output from the D flip-flop 303 and outputs it from the data signal output terminals 310 and 311 as output data (reproduction signal).

FIG. 6 is a diagram showing the relationship between the detection signals po1 and po2 in the peak rectifier circuit 305 of the equalizing amplifier 316. When there is no offset in the differential amplifier 301, the two detection signals po1 and po2 have different phases but the same value. However, when the differential amplifier 301 has an offset, the values of the detected detection signals po1 and po2 change. As a result, as shown by the broken lines in FIG. 6, the detection signals po1 and po2 differ from the actual signal peak values. Therefore, the offset compensation circuit 307 detects the difference between the detection signals po1 and po2, and feeds it back to the input stage of the differential amplifier 301 to perform offset compensation. With this offset compensation function, the identification reproducing unit 318
The input signal of the D flip-flop 303 is always set at the center with respect to the threshold voltage generated from the average of the positive-phase output and the negative-phase output of the differential amplifier 301, and becomes the optimum point of identification.

As another method of optimizing the threshold value of the identification reproducing circuit, there is a configuration of the identification reproducing circuit as shown in FIG. The identification reproducing circuit shown in FIG.
No. 46, which is disclosed in FIG.
By using one threshold voltage, the time for detecting a code error is reduced. In this discrimination reproduction circuit, an input signal from the light receiving unit (APD) 501 is supplied to the discrimination units 503 and 504 of the first and second discrimination reproduction circuits through the automatic gain adjustment amplifier 502. Identification unit 503
Is set to Vs, and the threshold of the identification unit 504 is set to a value Vm experimentally obtained so that the error pulse becomes a predetermined value at a certain low noise level. Identification unit 503,
The output of 504 is a D flip-flop DF / F1, DF / F of the reproducing unit according to the respective thresholds Vs and Vm.
2 and are compared by the exclusive logic circuit 505 through the second logic circuit 505. The comparison signal is input to the differential amplifier 508 via the pulse width extension circuit 506 and the low-pass filter 507. As a result, the threshold value V input to the discriminating unit 504 is inversely proportional to the magnitude of the noise, and a signal-to-noise ratio detection signal is extracted from a terminal 512. Based on this detection signal, a code error is detected and the threshold value Vs is adjusted to an optimum point.

[0012]

SUMMARY OF THE INVENTION
In the optical receiver including the discrimination reproduction circuit, it is important to reduce the degradation of the bit error rate of the reproduction reception signal.

In the conventional equalizing amplification / identification reproducing circuit shown in FIG. 8, a threshold value is set to a positive-phase signal of the output of the equalization amplification section 316,
And the average value of the negative-phase signals. in this case,
The optimum value of the threshold value fluctuates due to factors such as noise degradation or interference degradation in the optical input signal. Therefore, when the threshold value, which is a fixed set value, deviates from the optimum value, the code error rate of the reproduced signal in the identification reproducing unit 318 increases. In addition, a shift occurs in the threshold voltage due to fluctuations in the power supply voltage, the environmental temperature, and the like, and an external circuit for compensating the shift is required.

In the differential amplifier 301 of the conventional equalizing amplifier / identifying / reproducing circuit, since a feedback circuit for offset compensation and gain control is directly connected to the input stage of the differential amplifier 301, The frequency characteristics of the amplifier 301 are affected by circuit elements and the like externally connected to the feedback circuit.

The above is specifically described with reference to FIG. As shown in FIG. 8, the input stage of the differential amplifier 301 is terminated via resistors R3, R4, R5 and capacitors C2, C3 connected by bonding wires or lead terminals. By making the value of the resistor R4 equal to the value of the internal resistor R6 of the signal source 315, matching is performed so that reflection does not occur at the input stage of the differential amplifier 301. For example, when the internal resistance R6 of the signal source 315 is 50Ω, the resistance R4 is 50Ω.

The capacitors C2 and C3 are for adjusting the circuit time constant, but the impedance becomes lower as the input signal becomes higher in frequency. Therefore, the capacitor C
2, the impedance parasitic on a bonding wire or the like for connecting C3 affects the parasitic inductances L1 and L2 in the high frequency range of the input signal, and the resonance circuit is formed by the small input capacitance parasitic on the differential amplifier 301. Will be formed. That is, in the equalization amplification section 316, a resonance circuit is added to the input stage in the high frequency range, and the lift occurs in the high frequency range as shown in (1) in the frequency characteristic diagram of FIG.

Here, the influence of the frequency characteristic on the waveform response will be described. Generally, a pulse contains many frequency components, and can be represented by a superposition of a sine wave and a cosine wave having the frequency of each component. For example, a waveform g (t) having a repetition of a period T can be expanded into a Fourier series as shown in Expressions 1 and 2 when a period of −T / 2 ≦ t ≦ T / 2 is considered.

[0018]

(Equation 1) Here, each coefficient of Equation 1 is as shown in Equation 2.

(Equation 2)

In Equations 1 and 2, A0 is a DC component, A1 and B1 are fundamental wave components, and An and Bn (n ≧ 2) are n-th harmonic components.

Equalization amplifier 3 to which a random signal is input
In the case of No. 16, the gain in each frequency component of the input pulse sequence is different due to the lifting in the high frequency range described above, and a difference occurs in the output amplitude. For example, with respect to the waveform of the input signal wave shown in FIG.
A difference occurs in the output amplitude as seen in (2). Further, in a pulse sequence in which “1” or “0” continues, an overshoot accompanied by ringing occurs at a rising portion, and an undershoot occurs at a falling portion. This ringing is a peculiar phenomenon of a circuit including an inductance.

In general, due to a system having a finite frequency band or a frequency deviation such as lifting or unevenness in the equalizing amplification section 316, the pulse waveform is widened, adjacent pulses overlap with each other due to ringing or the like, and intersymbol interference occurs. Occurs. FIG. 4A shows an input signal, and FIG. 4B shows an eye pattern waveform of the equalizing amplifier 316. The eye pattern is used to grasp the magnitude of this intersymbol interference with respect to a random signal, and is obtained by superimposing and displaying all possible pulse waveforms in a predetermined signal cycle. is there.

A representative frequency characteristic R (f) in which there is no intersymbol interference has a cosine roll-off characteristic, which is given by Expression 3.

[0023]

(Equation 3)

FIG. 10 shows a frequency characteristic having a cosine roll-off characteristic, and FIG. 11 shows a waveform of a waveform response having a cosine roll-off characteristic.

The frequency characteristics of the equalizing amplifier 316 are
It is generally difficult to achieve the frequency characteristics shown in Equation 3 or FIG. 10 and an error occurs. As a result, intersymbol interference remains. The remaining intersymbol interference and intersymbol interference due to the deviation of the frequency characteristic will equivalently reduce the peak value of the signal in the discrimination determination in the discriminating / reproducing section 318, thereby deteriorating the error rate.

Further, as another method for optimizing the threshold value of the discrimination / reproduction circuit, as described in Japanese Patent Laid-Open No. 57-101446, the optimum value is determined by discrimination using a binary threshold voltage. There is a setting technique. In this case, in addition to the threshold adjustment function, the circuit size is increased by the binary identification circuit, so that the power consumption of the optical receiver circuit is increased, and the time for obtaining the experimental value Vm is reduced. This causes problems such as cost.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an equalizing amplification / identification reproducing circuit which can reduce the time required to adjust the threshold voltage to the optimum point and improve the identification input sensitivity of the identification reproduction circuit.

[0028]

According to a first aspect of the present invention, there is provided an equalizing amplification / identification / reproduction circuit for amplifying a high-frequency signal and outputting an equalized signal; Identification reproducing means for reproducing the signal by inputting the equalized signal output from the D flip-flop and a D flip-flop of the identification reproducing means after limit-shaping the equalized signal outputted from the equalizing amplifier means And a waveform shaping means for making the input differential.

Further, the waveform shaping means shapes the waveform of the equalized signal input, and differentially inputs a positive-phase signal and a negative-phase signal to the D flip-flop of the identification reproducing means; A peak detection circuit for detecting respective peak values of the positive-phase signal and the negative-phase signal; and offset compensation for canceling a DC potential offset based on a difference between the respective peak values detected by the peak detection circuit. And a circuit.

According to the above-described configuration, when the equalization amplification / identification circuit is realized by the semiconductor integrated circuit, the output signal of the equalization amplification unit is subjected to limit shaping, and then the input of the D flip-flop of the identification reproduction circuit is set to the differential. This eliminates the need for a threshold voltage adjustment circuit and achieves the object of reducing the time required to adjust the threshold voltage to the optimum point. Further, by compensating for the output offset of the equalizing amplifier and the waveform shaping unit, the identification input sensitivity can be improved.

The equalization amplification according to the second aspect of the present invention
An identification reproducing circuit cascades a differential amplifier for differentially amplifying a high-frequency signal and a differential output of a waveform shaping circuit for limiting an output signal of the differential amplifier to a D flip-flop, and an offset of the waveform shaping circuit. An offset compensating feedback circuit including an offset compensating circuit for detecting the amount, wherein the offset compensating feedback circuit converts an output signal of the offset compensating circuit into a signal for reducing the offset amount and supplies the signal to the waveform shaping circuit. It is characterized by returning.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration diagram showing an embodiment of the equalization amplification / identification reproduction circuit of the present invention.

The equalization amplification / identification reproduction circuit of the present embodiment
The differential output of the equalizing amplifier 16 is connected to the waveform shaping unit 17,
Further, a configuration is shown in which the differential output of the waveform shaping unit 17 is connected to the identification reproducing unit 18.

The equalizing amplifier 16 includes a differential amplifier 1, a peak rectifier circuit 5a, an average value circuit 13 of output signals of the peak rectifier circuit 5a, a gain control circuit 6, and an offset compensation circuit 7.
a, feedback resistors R3 and R5, time constant adjusting external capacitor C
2, C3 and an input signal source impedance matching resistor R4.

The equalizing amplifier 16 has a gain control function and an offset compensation function. As shown in FIG. 1, the equalizing amplifier 16 is provided with the differential amplifier 1. One input terminal of the differential amplifier 1 is connected to the signal source 15 via the capacitor C1. One input terminal of the differential amplifier 1 is terminated via a resistor R4 and a capacitor C2 connected by a bonding wire or a lead terminal (L1), and the other input terminal is connected by a resistor R5 and a bonding wire or a lead. It is terminated via a capacitor C3 connected at the terminal (L2). The differential amplifier 1
The signal input in the system is amplified and output to the peak rectifier circuit 5a connected to each channel.

The peak rectifier circuit 5a detects the peak value of each high-frequency signal and outputs detection signals po1 and po2.
The two output terminals of the peak rectifier circuit 5a have an average value circuit 1
3 are connected. The average value circuit 13 includes the peak rectifier circuit 5
The two output terminals are connected in series with resistors R1 and R2. The average value of the detection signals po1 and po2 output from the peak rectifier circuit 5a is detected and output to the gain control circuit 6. The gain control circuit 6 calculates the difference between the average value of the detection signals po1 and po2 output from the average value circuit 13 and the reference voltage of the gain control circuit 6, and feeds the output back to the control terminal of the differential amplifier 1. Let it. With this gain control function, the differential amplifier 1 changes the gain in accordance with the amplitude value of the input signal, and outputs the equalized signal output terminal of the equalizing amplifier 16 connected to the output terminal of the differential amplifier 1. Signals having a constant amplitude are output to 8 and 9, and the input amplitude of the discrimination / reproduction unit 18 (D flip-flop 3) is kept constant to prevent the code error rate from deteriorating.

An offset compensating circuit 7a is connected to two output terminals of the peak rectifying circuit 5a. The offset compensating circuit 7a detects a difference between the detection signals po1 and po2 output from the peak rectifier circuit 5a, and outputs one of the outputs via resistors R3 and R4 and the other via a resistor R5. 1 is fed back to the input terminal. Offset compensation circuit 7 fed back to the input terminal of differential amplifier 1
The output of a is used for offset compensation.

The waveform shaping section 17 comprises the slice amplifier 2, the peak rectifier 5b, and the offset compensator 7b.

The slice amplifier 2 shapes the waveform of the input of the equalized signal output from the differential amplifier 1 of the equalizing amplifier 16 and outputs the shaped signal. The slice amplifier 2 is composed of a high gain amplifier. The normal phase signal and the negative phase signal of the slice amplifier 2
8 to the D flip-flop 3.

Peak rectifier circuit 5b (peak detector circuit)
Detects the peak values of the positive-phase signal and the negative-phase signal of the slice amplifier 2, and outputs the detected signals SO1 and SO2 to the offset compensation circuit 7b.

The offset compensating circuit 7b cancels the DC potential offset based on the difference between the detected peak values based on the detection signals SO1 and SO2 from the peak rectifying circuit 5b. That is, the output signal of the offset compensating circuit 7 b is converted into a signal for reducing the offset amount of the slice amplifier 2 and is fed back to the slice amplifier 2.

The identification reproducing section 18 is provided with a D flip-flop 3
And an output amplifier 4, and a clock signal is input from an external terminal 12. The D flip-flop 3 inputs the differential signal after the output signal of the equalizing amplifier 16 is subjected to limit shaping by the waveform shaping unit 17, and outputs “1” based on the clock signal input from the external terminal 12. A signal of "0" or "0" is output. The output amplifier 4 amplifies the output from the D flip-flop 3 and outputs it from the data signal output terminals 10 and 11 as output data (reproduction signal).

Next, the operation of the equalization amplification / identification reproduction circuit in this embodiment will be described.

First, the input waveform shaping in the identification reproducing section 318 will be described.

FIG. 2 is a diagram comparing the frequency characteristics of each part of the equalization amplification / identification reproduction circuit according to the present embodiment. FIG.
(1) shows the frequency characteristics of the differential amplifier 1 according to the present embodiment, that is, the equalizing amplifier 16, and (2) shows the frequency characteristics of the slice amplifier 2, that is, the waveform shaping unit 17 according to the present embodiment. . As shown in FIG. 2 (2), the waveform shaping unit 17 of the present embodiment absorbs the lift in the high frequency range seen in the equalizing amplification unit 16.

FIG. 3 shows a waveform response corresponding to the frequency characteristic shown in FIG. 2, and FIG. 4 shows an eye pattern corresponding to the frequency characteristic shown in FIG. 3 and 4, (1) is an input signal, (2) is an equalizing amplifier 16,
(3) shows the waveform of the waveform shaping unit 17.

In the equalizing amplifier 16, as shown in FIG. 3 (2), a difference in amplitude occurs in each pulse train due to lifting in a high frequency range, and an overshoot and undershoot due to ringing causes a difference in FIG. As shown in the eye pattern of (1), jitter occurs at the top and bottom of the waveform, and at the rise and fall.

As shown in FIGS. 3 and 4 (3), the waveform shaping unit 17 suppresses the jitter at the top and bottom and reduces the rise time and fall time by the waveform shaping by the slice amplifier 2. The eye opening in the eye pattern is widened.

Next, the improvement of the identification input sensitivity realized by providing the waveform shaping section 17 will be described.

FIG. 5 shows an identification reproducing section 1 according to this embodiment.
8 (1) and (2) of FIG. 5 and the input waveform (FIG. 5 (3)) of the discriminating and reproducing unit 318 (FIG. 8) in the conventional equalizing amplification and discriminating and reproducing circuit. is there.

In the conventional identification reproducing section 318, since the input signal is identified by the threshold voltage VTH, the identification width for the input signals "1" and "0" is the threshold voltage VTH.
ΔV, which is the width from.

On the other hand, the identification reproducing section 18 of the present embodiment
Then, the input positive-phase signal (for example, DAT shown in FIG.
A), a signal having an opposite phase (for example, DAT shown in FIG.
AB), the positive-phase input signal “1”, “
The discrimination width for 0 ″ is 2ΔV, which is 2 μV of the conventional discrimination width.
Double. Therefore, identification errors are less likely to occur, and identification input sensitivity is improved.

Next, a description will be given of the need for adjusting the threshold voltage by providing the waveform shaping unit 17.

In the waveform shaping section 17 in the present embodiment,
The differential connection between the output of the slice amplifier 2 and the input of the D flip-flop 3 eliminates the need for a threshold voltage adjustment circuit. However, since the slice amplifier 2 is composed of a high-gain amplifier, if there is a small offset in the input, an offset of gain times occurs in the output, and the discrimination width decreases.

Therefore, in the present embodiment, the equalizing amplifier 16
The offset of the equalized output is compensated by the peak rectifying circuit 5a and the offset compensating circuit 7a. Similarly, the peak rectifying circuit 5b and the offset compensating circuit 7b of the waveform shaping unit 17 compensate for the offset of the limit shaping output.

The peak rectifier circuit 5a of the equalizing amplifier 16
The differential amplifier 1 is connected to each channel of the differential output and detects the peak value of each signal. When there is an offset in the output of the differential amplifier 1 as shown in FIG.
A potential difference is generated between the detection signals PO1 and PO2 by the peak rectification circuit 5a, and the output value of the offset compensation circuit 7a is fed back in a direction in which the detection signals PO1 and PO2 become equal. Similarly, the offset compensation circuit 7b also performs offset compensation on the detection signals SO1 and SO2 by the peak rectifier circuit 5b of the waveform shaping unit 17, and the respective detection signals SO1 and SO2
Feedback is applied in the direction in which By providing the waveform shaping unit 17 in this manner, the threshold voltage adjustment becomes unnecessary, and the time for adjusting the threshold voltage can be eliminated.

[0057]

As is apparent from the above description, according to the present invention, external adjustment of the threshold voltage of the discrimination / reproduction circuit becomes unnecessary, and the adjustment time of the threshold voltage is reduced. Also,
With the simple circuit configuration of the semiconductor integrated circuit, there is a unique effect that the offset of the equalized waveform and the limit shaping waveform is eliminated, and the identification input sensitivity of the identification reproducing circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of an equalization amplification / identification reproduction circuit according to an embodiment of the present invention.

FIG. 2 is a diagram comparing frequency characteristics of respective units of the embodiment.

FIG. 3 is a diagram comparing waveform responses according to time of respective units of the embodiment.

FIG. 4 is a diagram comparing waveform responses by eye patterns of respective units according to the embodiment.

FIG. 5 is a diagram showing an input waveform of an identification reproducing unit of the present embodiment in comparison with a conventional waveform.

FIG. 6 is a diagram illustrating detection signals po1 and po2 of the peak rectifier circuit.

FIG. 7 is a block diagram illustrating an optical receiving circuit.

FIG. 8 is a block diagram of a conventional equalization amplification / identification reproduction circuit.

FIG. 9 is a block diagram showing an example of a conventional signal-to-noise ratio detection circuit using a binary threshold voltage.

FIG. 10 is a diagram illustrating a frequency characteristic having a cosine roll-off characteristic.

FIG. 11 is a diagram showing a waveform response having a cosine roll-off characteristic.

[Explanation of symbols]

 Reference Signs List 1 Differential amplifier 2 Slice amplifier 3 D flip-flop 4 Output amplifier 5a, 5b Peak rectifier circuit 6 Gain control circuit 7a, 7b Offset compensation circuit 8, 9 Equalized signal output terminal 10, 11 Data signal output terminal 12 Clock signal input Terminal 13 Average circuit 15 Signal source of high-frequency signal 16 Equalization amplification unit 17 Waveform shaping unit 18 Identification reproduction unit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04B 10/06

Claims (3)

[Claims] 1. An equalizing amplifier for amplifying a high-frequency signal and outputting an equalized signal, and an identification reproducing unit for inputting the equalized signal output from the equalizing amplifier by a D flip-flop and reproducing the signal. And a waveform shaping means for subjecting the equalization signal output from the equalization amplification means to limit shaping, and then making the input of the D flip-flop of the identification and reproduction means differential. -Identification reproduction circuit. 2. A slice amplifier for waveform-shaping an equalized signal input and differentially inputting a positive-phase signal and a negative-phase signal to a D flip-flop of the discrimination / reproduction means; A peak detection circuit for detecting each peak value of the positive-phase signal and the negative-phase signal; and offset compensation for canceling a DC potential offset based on a difference between the respective peak values detected by the peak detection circuit. 2. The equalization amplification / identification reproduction circuit according to claim 1, comprising a circuit. 3. A differential amplifier circuit for differentially amplifying a high-frequency signal, and a differential output of a waveform shaping circuit for limiting an output signal of the differential amplifier circuit is cascaded to a D flip-flop, and an offset of the waveform shaping circuit is provided. An offset compensating feedback circuit including an offset compensating circuit for detecting an amount, wherein the offset compensating feedback circuit converts an output signal of the offset compensating circuit into a signal for reducing the offset amount, and supplies the signal to the waveform shaping circuit. An equalizing amplification / identification / reproduction circuit characterized by feedback.