JP2011228736A - Semiconductor device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control a threshold voltage using the stress of a thin film in an inverted staggered type TFT.SOLUTION: The threshold voltage is controlled by configuring a product of a stress of a first insulator layer provided on an electrode formed on a substrate and a layer thickness; a product of a stress of an active layer, which is constituted of a crystalline semiconductor film having a tensile stress, provided on the first insulator layer, and a layer thickness; and a product of a stress of a second insulator layer provided on the active layer and a layer thickness as appropriate magnitudes.

Description

  The present invention relates to a semiconductor device having an integrated circuit using a thin film transistor over a substrate. For example, the present invention relates to an electro-optical device typified by a liquid crystal display device and a configuration of an electronic apparatus equipped with the electro-optical device.

  A semiconductor device typified by an active matrix liquid crystal display device has been developed by arranging a large number of TFTs (thin film transistors) on a substrate. The TFT is formed by laminating at least an active layer made of an island-shaped semiconductor film, a first insulating layer provided on the substrate side of the active layer, and a second insulating layer provided on the opposite side of the active layer. Have a structure.

  A structure in which a gate electrode is provided so as to apply a predetermined voltage to the active layer through the first insulating layer is called an inverted stagger or bottom gate type. The present specification all relates to this inverted staggered structure.

  By the way, among several characteristic parameters representing TFT characteristics, field-effect mobility and threshold voltage are used as a standard for good characteristics.

  With the goal of realizing high field effect mobility, TFT structures and their manufacturing processes have been carefully studied from theoretical analysis and empirical aspects. Particularly important factors have been thought to be necessary to reduce the bulk defect density in the semiconductor layer and the interface potential density at the interface between the semiconductor layer and the insulating layer as much as possible.

  The type of device is distinguished by setting the threshold voltage, which is the most important parameter in device design. A TFT that needs to be applied with a gate voltage to be conductive is an enhancement type or a normally-off type TFT, and a TFT that needs to be applied with a gate voltage to be non-conductive is a depletion type. Alternatively, it is called a normally-on TFT.

  In general, threshold voltage, enhancement type TFT, and depletion type TFT are defined as follows. As shown in FIG. 1a, in the gate voltage-drain current characteristic curve, the intersection of the tangent line a in the square characteristic region of the characteristic curve and the horizontal axis (gate voltage axis) is defined as the threshold voltage. An enhancement type TFT is defined as an n-channel type TFT with a threshold voltage of zero or positive voltage, or a p-channel type TFT with a negative threshold voltage. Similarly, a depletion type TFT is defined as an n-channel TFT with a negative threshold voltage, or a p-channel TFT with a threshold voltage of zero or positive.

  As a method for controlling the threshold voltage, a channel doping method in which impurities are introduced into the semiconductor film on the gate insulating layer is generally used, such as an ion implantation method or a method of flowing an impurity gas when forming the semiconductor film.

In the enhancement type TFT, an impurity having a conductivity type different from that at the time of channel formation is added to the channel portion, and an impurity having the same conductivity type is introduced into the depletion type TFT. For example, a p-type impurity such as boron may be introduced to make an n-channel TFT an enhancement type TFT, and an n-type impurity such as phosphorus or arsenic may be introduced to make a depletion type.
The impurity concentration in the channel formation region exceeds the detection limit value of 1 × 10 ¹⁵ atoms / cm ³ in SIMS (Secondary Ion Mass Spectroscopy) analysis, and is about 2 V at 5 × 10 ¹⁷ atoms / cm ^3. However, if the concentration exceeds 5 × 10 ¹⁷ atoms / cm ³ , the mobility is significantly lowered due to the deterioration of crystallinity, so that the concentration does not exceed this is preferable.

  By the way, even in a TFT having a threshold voltage of 0V, the drain current is actually not 0 when the gate voltage is 0V. In order to reduce the drain current when the gate voltage is 0 V, this value is sufficiently close to 0 V using the gate voltage when the drain current value is lower than the reference value as an index rather than the threshold voltage. Better. In this specification, the gate when the drain current of 1 pA flows per 1 μm width of the channel formation region under the condition of the absolute value of the drain voltage of 1 V (specifically, the drain voltage is −1 V for the p-channel TFT and the drain voltage +1 V for the n-channel TFT) Consider that the voltage is a reference value and this value is controlled. (Figure 1b)

  Further, in this specification, the enhancement type TFT and the depletion type TFT are defined by the gate voltage value when the absolute value of the drain voltage is 1 V and the absolute value of the drain current per 1 μm width of the channel formation region is 1 pA. In other words, the enhancement type TFT is an n-channel type TFT with a drain voltage of +1 V and a drain current of 1 pA per 1 μm width of the channel formation region, or a p-channel type TFT with a drain voltage of zero or positive. It is defined as a TFT whose gate voltage is negative when the voltage is −1 V and the drain current is 1 pA per 1 μm width of the channel formation region. Similarly, the depletion type TFT is an n channel type TFT having a drain voltage of +1 V and a drain current of 1 pA per 1 μm width of the channel formation region, or a p channel type TFT having a drain voltage. It is defined as a TFT whose gate voltage is zero or positive when +1 V and a drain current of 1 pA per 1 μm width of the channel formation region.

  Further, when the gate voltage is sufficiently close to 0 V when the drain voltage is 1 V and the drain current is 1 pA per 1 μm width of the channel formation region with the absolute value of the drain voltage, the threshold voltage is also controlled to a certain voltage value. Therefore, in this specification, the gate voltage is sufficiently close to 0 V when the absolute value of the drain voltage is 1 V and the drain current is 1 pA per 1 μm width of the channel formation region, and the threshold voltage control has the same meaning. And

  When the channel doping method is used to control the threshold voltage, impurities are introduced into the active layer, which inevitably causes bulk crystal defects due to the impurities, or interface defects between the semiconductor layer and the insulating layer. End up. As a result, TFT characteristics, particularly field effect mobility, are deteriorated.

  It is important for the present inventor to control the threshold voltage without deteriorating the TFT characteristics. Therefore, the present inventor establishes a method for controlling the threshold voltage without using the channel doping method. Thought it was important. For this purpose, it was considered effective to control the stress of the thin film.

Consider the case where channel doping is not performed. In this case, the p-type or n-type impurity concentration in the channel formation region is less than the detection limit value of 1 × 10 ¹⁵ atoms / cm ³ in SIMS analysis.

  As a semiconductor film used for the TFT, it is considered that a crystalline semiconductor capable of obtaining a high field effect mobility, such as an amorphous semiconductor, is suitable. Here, the crystalline semiconductor includes a single crystal semiconductor, a polycrystalline semiconductor, or a microcrystalline semiconductor. The insulating layer is typically formed of a material such as silicon oxide, silicon nitride, or silicon nitride oxide.

  It is known that a thin film of the material manufactured by a known technique such as a CVD method (chemical vapor deposition method), a sputtering method, or a vacuum deposition method has an internal stress. Internal stress was further considered to be separated into intrinsic stress inherent to the thin film and thermal stress caused by the difference in thermal expansion coefficient between the thin film and the substrate. Thermal stress is generated in the heating process of the TFT fabrication process, and its influence can be ignored by setting the process temperature. On the other hand, the mechanism of the generation of intrinsic stress is not necessarily clarified, and it was considered that the phase change and composition change due to the growth process of the thin film and the subsequent heat treatment were complicatedly intertwined.

  In general, as shown in FIG. 2, when the thin film is contracted with respect to the substrate, the internal stress is influenced by the internal stress and is deformed with the thin film inside, and this is called tensile stress. On the other hand, when the thin film is stretched, the substrate is compressed and deformed with the thin film facing outward, and this is called compressive stress. Thus, for the sake of convenience, the definition of internal stress has been considered centering on the substrate. In this specification, the internal stress is described according to this definition. In this specification, the tensile stress is defined as having a positive sign, and the compressive stress is defined as having a negative sign.

It has been known that a crystalline semiconductor film produced from an amorphous semiconductor film by a method such as thermal crystallization or laser crystallization undergoes volume shrinkage during the crystallization process. Although the ratio depends on the state of the amorphous semiconductor film, it was supposed to be about 0.1 to 1%. As a result, tensile stress was generated in the crystalline semiconductor film, and the magnitude of the crystalline semiconductor film sometimes reached about 1 × 10 ⁹ Pa. In addition, it has been known that the internal stress of an insulating film such as a silicon oxide film, a silicon nitride film, and a silicon nitride oxide film varies in various ways from a compressive stress to a tensile stress depending on film forming conditions and subsequent heat treatment conditions.

  By the way, when the stress of the active layer semiconductor film and the insulating film on the substrate side in contact with the active layer semiconductor or on the opposite side of the substrate is changed, the threshold voltage changes. Although the detailed reason for this is not clear so far, for example, when the active layer semiconductor film tries to contract, if a stress acts in the direction of stretching the active layer semiconductor film, the crystal grain boundary is distorted. It is thought that the generation of interface defects accompanying the generation of crystal defects and unpaired bonds. It was well known that crystal defects and interface potentials affect the threshold voltage. Therefore, the threshold voltage can be changed by changing the stress. Alternatively, when stress is applied to the active layer semiconductor film, the lattice constant, that is, the distance between adjacent semiconductor atoms constituting the semiconductor film changes, and the energy band structure of the semiconductor film changes accordingly. The voltage is also expected to change.

  Therefore, the threshold voltage can be controlled by appropriately changing the stress applied to the active layer. By the way, it is the sum of the product of the stress and film thickness of the second insulating film and the product of the stress and film thickness of the active layer that has a direct correlation with the threshold voltage. The threshold voltage can also be controlled by changing the film thickness of either or both of the first and second insulating layers.

  FIG. 11 shows the sum of the product of the stress and film thickness of the second insulating layer and the product of the stress and film thickness of the active layer, and the drain current per 1 μm width of the channel formation region with the absolute value of 1V of the drain voltage of the TFT. It is a correlation curve of the gate voltage when the absolute value is 1 pA. However, the characteristic curve in the figure assumes that the p-channel TFT and the n-channel TFT have the same structure except for the impurity concentration of the active layer. Under this assumption, the X coordinate X0 at which the gate voltage becomes 0 V when the absolute value of the drain voltage is 1 V and the absolute value of the drain current per 1 μm width of the channel formation region is 1 pA is the same. Indicates that X0 is determined only by the amount of the sum of the product of the stress and film thickness of the second insulating film and the product of the stress and film thickness of the active layer. Further, the correlation curve is a straight line, and the sign of the inclination is the same between the n-channel TFT and the p-channel TFT, and therefore the distinction between the enhancement type and the depletion type is reversed for the same X coordinate. In the correlation curve, the absolute value of X0 and the slope of the correlation curve take arbitrary values depending on the product of the stress and the film thickness of the first insulating layer or the product of the stress and the film thickness of the active layer. By making the stress and film thickness of the second insulating layer appropriate, the gate voltage when the absolute value of the drain voltage is 1V and the absolute value of the drain current per 1 μm width of the channel forming region is 1 pA is close to 0V. Preferably, the absolute value can be 2 V or less.

  By the way, even when the channel doping method is used for controlling the threshold voltage, the gate voltage is close to 0 V when the drain voltage has an absolute value of 1 V and the drain current has an absolute value of 1 pA per 1 μm width of the channel formation region without channel doping. If the product of the stress and film thickness of the second insulating layer and the active layer is set to an appropriate value so that the voltage is preferably 2 V or less, the concentration of the impurity doped into the channel region can be reduced. This is effective because it can suppress the deterioration of the TFT characteristics.

  As described above, the threshold voltage of the TFT can be set without channel doping by setting the product of the stress and film thickness of the active layer or the product of the stress and film thickness of the second insulating film to an appropriate value. It is possible to control. As a result, a TFT having better electrical characteristics free from crystal defects caused by channel doping can be produced.

Definition diagram of enhancement type TFT and depletion type TFT. The figure explaining the definition of the internal stress of a thin film. FIG. 4 is a cross-sectional view of a TFT illustrating Embodiment 1; FIG. 6 is a cross-sectional view of a TFT illustrating Embodiment 2; Sectional drawing which shows the manufacturing process of TFT. Sectional drawing which shows the manufacturing process of TFT. Sectional drawing which shows the manufacturing process of TFT. Sectional drawing which shows the manufacturing process of TFT. The top view, sectional drawing, and circuit diagram of a CMOS circuit. The top view, sectional drawing, and circuit diagram of an E / DMOS circuit. The correlation figure of the gate voltage used as the reference | standard in this specification with the product of the stress of a 2nd insulating layer, and a film thickness. The TFT production experiment result of Example 1. FIG. 6 is a diagram illustrating Example 6; FIG. 6 is a diagram illustrating Example 6; FIG. 6 is a diagram illustrating Example 6; The figure explaining embodiment in the case of performing channel dope The top view, sectional drawing, and circuit diagram of a CMOS circuit manufactured by performing channel doping. The top view, sectional drawing, and circuit diagram of an E / DMOS circuit manufactured by channel doping.

[Embodiment Mode 1] An embodiment mode in which a channel doping method is not used will be described with reference to FIG. 3A and 3B, a gate electrode 302 is formed on a substrate 301 having an insulating surface, and a first insulating layer, which is a silicon nitride film 303a having tensile stress and compressive stress, is formed thereon. A silicon nitride oxide film 303b is stacked.

  The active layer 304 is a crystalline semiconductor film produced by a method such as laser crystallization or thermal crystallization of an amorphous semiconductor film, and is not limited to a detailed production method but necessarily has a tensile stress. is doing. A channel formation region 304c, an LDD region 304b, a source region 304a, and a drain region 304d are provided as necessary. The source electrode 306 and the drain electrode 307 are provided by forming contact holes in part of the second insulating layer 305.

In the channel formation region, the concentration of phosphorus or arsenic as n-type impurities or boron as p-type impurities is below the detection limit by SIMS analysis, and phosphorus or arsenic as n-type impurities or p-type in the source and drain regions. Boron as an impurity is implanted at a high concentration of 1 × 10 ¹⁹ atoms / cm ³ or more.

  In FIG. 3A, the second insulating layer is a silicon oxynitride film having a compressive stress. The threshold voltage is controlled by the stress and the film thickness.

  As shown in FIG. 3B, the second insulating layer may be formed by stacking a plurality of insulating films. In FIG. 3B, the second insulating layer 305a is a silicon oxynitride film having a compressive stress, and a silicon oxide film, which is the second insulating layer 305b having a compressive stress, is stacked thereon. Stress was controlled.

Since the product of the absolute value of the stress and the film thickness in the first insulating layer is sufficiently smaller than the product of the absolute value of the stress and the film thickness in the second insulating layer, the second insulating layer to the threshold voltage The product of stress and film thickness was dominant. The sum of the product of the stress [Pa] and the film thickness [m] in the second insulating layer and the product of the stress [Pa] and the film thickness [m] in the active layer is −8.0 × 10 ¹ to −1. a 2 × 10 ^2, the absolute value of the gate voltage when the absolute value 1pA the drain current per width 1μm of the channel formation region in absolute value 1V of the drain voltage was controlled below 2V.

The n-channel TFT manufactured through the above steps is a depletion type TFT, and the p-channel TFT is an enhancement type TFT.

[Embodiment 2] In a CMOS circuit, both an n-channel TFT and a p-channel TFT are manufactured on the same substrate. For the n-channel TFT and the p-channel TFT, an enhancement type circuit configuration is often used. Therefore, in this embodiment, a method of obtaining a desired TFT by controlling the threshold voltage by appropriately setting the product of the stress and the film thickness in the second insulating layer without using the channel doping method is shown. 4 will be described.

  By the way, as described in the detailed description of the invention, in the n-channel TFT and the p-channel TFT which are not channel doped, the distinction between the enhancement type and the depletion type is made between the second insulating film and the active layer. If the product of stress and film thickness is the same, they are of the opposite type. Therefore, in order to fabricate only one of the enhancement type and the depletion type TFTs in the same substrate, it is necessary to change the structure of the second insulating layer to make a difference in the product of stress and film thickness.

  In FIG. 4, a gate electrode 402 is formed on a substrate 401 having an insulating surface, and a silicon nitride film 403a having tensile stress and a silicon nitride oxide film 403b having compressive stress, which are first insulating layers, are stacked thereon. ing.

  On the n-channel TFT side, the active layer 404 is a semiconductor layer having a tensile stress, and a channel formation region 404c, an LDD region 404b, a source region 404a, and a drain region 404d are provided as necessary. The active layer 405 on the p-channel TFT side is a semiconductor layer having tensile stress, and is provided with a channel formation region 405c, a source region 405a, and a drain region 405d. The source electrodes 406 and 408 and the drain electrodes 407 and 409 are provided by forming contact holes in part of the second insulating layer 410.

The concentration of phosphorus or arsenic as n-type impurities or boron as p-type impurities is 1 × 10 ¹⁵ atoms / cm ³ or less in the active layer channel formation region, and phosphorus as n-type impurities in the active layer source and drain regions. , Arsenic, or boron, which is a p-type impurity, is implanted at a high concentration of 1 × 10 ¹⁹ atoms / cm ³ or more.

  By the way, in FIG. 4, what is stacked between the second insulating layer 410 and the active layer 404 of the n-channel TFT is an active layer protective film and a mask used at the time of impurity doping of the n-channel TFT. The insulating film is left without being etched after the impurity doping, so that the product of the film thickness and stress of the second insulating layer is different from that of the p-channel TFT.

As the stress applied to the n-channel TFT, the product of the stress [Pa] and the film thickness [m] of the protective film of the active layer used at the time of doping #, the second insulating layer, the mask insulating film, and the stress [Pa] of the active layer ] the sum of the product of the film thickness [m] is set to n in channel ^{TFT -1.2 × 10 2 ~-1.4} × 10 2, whereas the p-channel type TFT in the -8.0 × 10 ¹ to 1 , 2 × 10 ² , both n-channel TFTs and p-channel TFTs can be enhanced TFTs. The absolute value of the gate voltage is controlled to 2 V or less when the absolute value of the drain voltage is 1 V and the drain current has an absolute value of 1 pA per 1 μm width of the channel formation region.

[Embodiment 3] An embodiment in which the channel top method of the present invention is used will be described with reference to FIG. In a CMOS circuit, both an n-channel TFT and a p-channel TFT are formed in the same substrate, and the threshold voltage is controlled so that both become enhancement-type TFTs. However, when the channel doping is not performed, the stress and the film thickness of the second insulating layer and the active layer are made the same in the n-channel TFT and the p-channel TFT. As described above, when the absolute value of the drain voltage is 1 V and the absolute value of the drain current per 1 μm width of the channel formation region is 1 pA, the absolute value of the gate voltage can be controlled to be close to 0 V, but only the enhancement type TFT In addition, a depletion type TFT is also produced. In this case, it is effective to perform channel doping on the active layer of the depletion type TFT among the n-channel type TFT or the p-channel type TFT and control the threshold voltage so as to become an enhancement type TFT. is there.

  In FIG. 16, a gate electrode 402 is formed on a substrate 401 having an insulating surface, and a silicon nitride film 403a having tensile stress and a silicon nitride oxide film 403b having compressive stress, which are first insulating layers, are stacked thereon. ing.

  On the n-channel TFT side, the active layer 404 is a semiconductor layer having a tensile stress, and a channel formation region 404c, an LDD region 404b, a source region 404a, and a drain region 404d are provided as necessary. The active layer 405 on the p-channel TFT side is a semiconductor layer having tensile stress, and is provided with a channel formation region 405c, a source region 405a, and a drain region 405d. The source electrodes 406 and 408 and the drain electrodes 407 and 409 are provided by forming contact holes in part of the second insulating layer 410.

Here, the active layers 404 and 405 are semiconductor films having the same film thickness and stress formed simultaneously, and the second insulating layers 410 and 411 are formed simultaneously and have the same film thickness and film quality. It is an insulating film. For example, when the thickness and stress of the second insulating layer and the active layer are set so that the p-channel TFT in FIG. 16 is an enhancement type, boron or the like is formed in the active layer channel formation region 404 of the n-channel TFT. The channel is doped with p-type impurities to control the threshold value to the enhancement type. Thereby, an enhancement type n-channel TFT and a p-channel TFT can be formed in the same substrate.

In the above method, since the n-channel TFT is not channel-doped, the active layer has good crystallinity free from crystal defects and interface defects caused by channel doping. Further, although channel doping is performed on the p-channel TFT, the impurity concentration in the channel doping is 5 × 10 ¹⁷ atoms / cm ³ because it is formed in consideration of the stress of the second insulating layer and the active layer. Since the threshold voltage can be controlled by a sufficiently small amount as described below, a TFT having an active layer with good crystallinity is obtained.

The present embodiment will be described with reference to FIGS. First, a glass substrate such as a # 1737 substrate manufactured by Corning was prepared as the substrate 601. A gate electrode 602 was formed over the substrate 601. Here, tantalum (Ta) is used by sputtering.
A film was formed by sputtering to a thickness of 200 nm. The gate electrode 602 may have a two-layer structure of a tantalum nitride film (film thickness 50 nm) and a tantalum film (film thickness 250 nm).

Then, the first insulating layer 603 and the amorphous semiconductor layer 604 were successively formed without being sequentially opened to the atmosphere. The first insulating layer was formed of a nitrogen-rich silicon nitride oxide film 603a (film thickness 50 nm) and a silicon nitride oxide film (film thickness 125 nm). The nitrogen-rich silicon oxynitride film 603a was formed by a plasma CVD method using a mixed gas of SiH ₄ , N ₂ O, and NH ₃ . The amorphous semiconductor layer 604 was also formed to a thickness of 20 to 100 nm, preferably 30 to 75 nm, using a plasma CVD method. (Fig. 5 (B))

And the heat processing for 1 hour were performed at 450-550 degreeC. By this heat treatment, hydrogen was released from the first insulating layer 603 and the amorphous semiconductor layer 604, and tensile stress could be applied. Thereafter, a crystallization process was performed on the amorphous semiconductor layer 604 to form a crystalline semiconductor layer 605. For the crystallization step here, a laser crystallization method or a thermal crystallization method may be used. In the laser crystallization method, for example, XeCl excimer laser light (wavelength 308 nm) is used to form a linear beam, the oscillation pulse frequency is 30 Hz, the laser energy density is 100 to 500 mJ / cm ² , and the linear beam overlap rate is 96. The amorphous semiconductor layer was crystallized as%. Here, as the amorphous semiconductor layer crystallized, volume shrinkage occurred, and the tensile stress of the formed crystalline semiconductor layer 605 increased. (Fig. 5 (C))

Here, in the case of performing channel doping, after forming an insulating layer in contact with the crystalline semiconductor layer 605, channel doping is selectively performed only on the TFT that performs channel doping using a resist mask. After the channel doping, the resist mask is peeled off and the insulating layer covering the active layer is implanted with impurities at the time of channel doping, and the impurities in this insulating layer can diffuse into the active layer in a later step. Therefore, it is selectively removed using a hydrofluoric acid-based etchant.

Next, an insulating film 606 was formed in contact with the crystalline semiconductor layer 605 thus formed. Here, a silicon oxynitride film was formed to a thickness of 200 nm. Thereafter, a resist mask 607 in contact with the insulating film 606 was formed by a patterning method using exposure from the back surface. Here, the resist mask 607 can be formed in a self-aligning manner using the gate electrode 602 as a mask. As shown in the figure, the size of the resist mask was slightly smaller than the width of the gate electrode due to the wraparound of light. (FIG. 5D) Then, the insulating film 606 was etched using the resist mask 607 to form the channel protective film 608, and then the resist mask 607 was removed. Through this step, the surface of the crystalline semiconductor layer 605 other than the region in contact with the channel protective film 608 was exposed. This channel protective film 608 served to prevent impurities from being added to the channel region in the subsequent impurity addition step.
(Fig. 5 (E))

Next, a resist mask 609 that covers a part of the n-channel TFT and the p-channel TFT region is formed by patterning using a photomask, and the n-type region is exposed in the region where the surface of the crystalline semiconductor layer 605 is exposed. A step of adding an impurity element to be imparted was performed. A first impurity region (n ⁺ type region) 610a was formed. In this embodiment, since phosphorus is used as an impurity element imparting n-type, phosphine (PH ₃ ) is used in the ion doping method, the dose is 5 × 10 ¹⁴ atoms / cm ² , and the acceleration voltage is 10 kV. The pattern of the resist mask 609 was determined by the practitioner to determine the width of the n ⁺ -type region, and an n ⁻ -type region having a desired width and a channel formation region could be easily obtained. . (Fig. 6 (A))

  After removing the resist mask 609, a mask insulating film 611 was formed. Here, a silicon oxynitride film (film thickness: 50 nm) was formed by a plasma CVD method. The silicon nitride oxide film had compressive stress. (Fig. 6 (B))

Next, a step of adding an impurity element imparting n-type conductivity to the crystalline semiconductor layer provided with the mask insulating film 611 on the surface was performed, so that a second impurity region (n ⁻ -type region) 612 was formed. However, in order to add impurities to the underlying crystalline semiconductor layer through the mask insulating film 611, it is necessary to set appropriate conditions in consideration of the thickness of the mask insulating film 611. Here, the dose is 3 × 10 ¹³ atoms / cm ² and the acceleration voltage is 60 kV. The second impurity region 612 thus formed functions as an LDD region. (Fig. 6 (C))

Next, a resist mask 614 covering the n-channel TFT was formed, and a step of adding an impurity element imparting P-type to a region where the p-channel TFT was formed was performed. Here, diborane (B ₂ H ₆ ) was used by ion doping, and boron (B) was added. The dose was 4 × 10 ¹⁵ atoms / cm ² and the acceleration voltage was 30 kV. (Fig. 6 (D))

  By the way, after the addition of the p-type impurity, the resist mask covering the n-channel TFT is not peeled off, and the mask insulating film 611 and the channel protective film 608 covering the active layer of the p-channel TFT are formed with a fluorine-based etching solution. The threshold voltage may be controlled by selectively removing the difference in the stress applied to the active layer by changing the structure of the second insulating layer in the n-channel TFT and the p-type TFT. (Fig. 8 (A))

  Also, for example, in the case where both enhancement type and depletion type TFTs are formed among n-channel type TFTs on the same substrate, after the impurity addition process, the TFT other than the depletion type is covered with a resist mask, The mask insulating film and the channel protective film may be selectively removed with a fluorine-based etchant solution.

  Then, after performing an impurity element activation process by laser annealing or thermal annealing, heat treatment (300 to 450 ° C., 1 hour) was performed in a hydrogen atmosphere to hydrogenate the whole (FIGS. 7 and 8A). . Alternatively, hydrogenation may be performed with plasma hydrogen. Thereafter, the channel protective film 608 and the mask insulating film 611 were selectively removed with a hydrofluoric acid-based etchant, and the crystalline semiconductor layer was etched into a desired shape by a known patterning technique. (Figs. 7 and 8 (B))

Through the above steps, the source region 615, the drain region 616, the LDD regions 617 and 618, and the channel formation region 619 of the n-channel TFT are formed, and the source region 621, the drain region 622, and the channel formation region 620 of the p-channel TFT. Formed. Next, a second insulating layer was formed to cover the n-channel TFT and the p-channel TFT. As the second insulating layer, a silicon oxide film having a compressive stress of −8.1 × 10 ⁸ Pa was formed to a thickness of 1000 nm. (Fig. 7, 8 (C))

  Then, contact holes were formed, and source electrodes 624 and 627 and drain electrodes 625 and 627 were formed. Further, as a second insulating layer, a silicon nitride oxide film 623 was formed over the insulating film 623 made of a silicon oxide film so as to cover the source electrodes 624 and 627 and the drain electrodes 625 and 627. After obtaining the states shown in FIGS. 7 and 8D, heat treatment was finally performed in a hydrogen atmosphere, and the whole was hydrogenated to complete an n-channel TFT and a p-channel TFT. The hydrogenation process could also be realized by exposure to a plasma hydrogen atmosphere.

  Stress dependence of the absolute value of the gate voltage when the absolute value of the drain voltage is 1 V and the absolute value of the drain current per 1 μm of the width of the channel formation region by the TFT manufactured by the above-described process is The product of the stress and film thickness of the insulating layer 2 and the sum of the product of the stress and film thickness of the active layer) are as shown in FIGS. 12 (A) and 12 (B). Here, the value of the product of the three types of stress and film thickness shown in FIG. 12 was obtained by the second insulating layer structure shown in Table 1.

FIG. 12A shows the dependency of the threshold value of the n-channel TFT manufactured by the TFT manufacturing method and the second insulating layer stress × film thickness. Assuming that the actual measurement data is on a straight line, the straight-line (line segment) with the least error from the actual measurement data was obtained using the least square method, and the Fitting-Curve in FIG. The predicted curve is an extrapolation of Fitting-Curve. From the fitting curve and the expected curve, the sum of the product of the stress [Pa] and the film thickness [m] of the second insulating layer and the product of the stress [Pa] and the film thickness [m] of the active layer is about -7.5. × when in between 10 ¹ ~-1.1 × 10 ^1, the absolute value of the gate voltage when the absolute value 1pA the drain current per width 1μm of the channel formation region in the drain voltage + 1V becomes less than 2V I found out. It was also found that both enhancement type TFTs and depletion type TFTs can be manufactured by setting the sum of the product of the stress and film thickness of the second insulating layer and the product of the stress and film thickness of the active layer to appropriate values. .
Similarly, FIG. 12B shows the result of an experiment for fabricating a p-channel TFT. Again, the product of the insulating layer stress [Pa] and the film thickness [m] of 2 and the stress [Pa] and the film thickness [m] of the active layer. when the sum of the product of is between approximately ^{-8.5 × 10 1 ~-1.1 ×} 10 1 , when the absolute value 1pA the drain current per width 1μm of the channel forming region is -1V drain voltage It was found that the absolute value of the gate voltage was 2 V or less, and that both enhancement type TFTs and depletion type TFTs could be produced.

An example of a semiconductor device including an n-channel TFT and a p-channel TFT using the manufacturing process of Embodiment 1 without channel doping will be described with reference to FIG.
FIG. 9 shows an inverter circuit which is a basic configuration of a CMOS circuit. By combining such inverter circuits, a basic circuit such as a NAND circuit or a NOR circuit can be formed, or a more complicated shift register circuit or buffer circuit can be formed. FIG. 9A is a view corresponding to a top view of the CMOS circuit, and FIG. 9B shows a cross-sectional structure view taken along a dotted line AA ′ in FIG. 9A.

In FIG. 9B, both the n-channel TFT and the p-channel TFT are formed over the same substrate. In the p-channel TFT, a gate electrode 902 is formed, and a nitrogen-rich silicon nitride oxide film 903 having a tensile stress and a silicon nitride oxide film 904 are provided thereon as a first insulating layer. An active layer made of a crystalline semiconductor film is formed in contact with the first insulating layer, and p ⁺ regions 912 (drain regions) and 915 (source regions) and a channel formation region 914 are provided. A second insulating layer 917 is provided in contact with the semiconductor layer, and a silicon oxide film 919 is formed here. A source electrode 920 and a drain electrode 918 are formed through contact holes provided in the silicon oxide film. On the other hand, in the active layer of the n-channel type TFT, the n ⁺ -type region 905 (source region), 911 (the drain region) and the channel forming region 909, between the n ⁺ -type region and the channel forming region n ^- type An area is provided. Then, the mask insulating film 921 and the active layer protective film 922 used in the dope process are left on the active layer without being removed, thereby receiving a larger stress than the p-channel TFT, and a threshold value. The voltage is controlled. Further, like the p-channel TFT, a contact hole is formed in the second insulating layer 917, and a source electrode 916 and a drain electrode 918 are provided.

  Such a CMOS circuit can be applied to a peripheral drive circuit of an active matrix liquid crystal display device, a drive circuit of an EL (ElectroLuminescence) display device, a reading circuit of a contact image sensor, or the like.

  An example of a semiconductor device provided with an n-channel TFT using the manufacturing process of Embodiment 1 without channel doping will be described with reference to FIGS. FIG. 10 shows an E / D MOS (enhancement / depletion) inverter circuit which is a basic configuration of an NMOS circuit. A feature of the E / D MOS inverter is that both enhancement type and depletion type TFTs are included in one circuit. By combining such inverter circuits, basic circuits such as NAND circuits and NOR circuits It is the same as that of the CMOS inverter circuit of the second embodiment in that it is possible to construct a more complicated shift register circuit or buffer circuit. FIG. 10A is a view corresponding to a top view of the E / D MOS inverter circuit. FIG. 10B shows a cross-sectional structural view taken along the dotted line AA ′ in FIG. C) shows a circuit diagram.

In FIG. 10B, enhancement type and depletion type TFTs are formed on the same substrate. In the depletion type TFT, a gate electrode 902 is formed, and a nitrogen-rich silicon nitride oxide film 903 having tensile stress and a silicon nitride oxide film 904 are provided thereon as a first insulating layer. Then, an active layer made of a crystalline semiconductor film is formed in contact with the first insulating layer, and n ⁺ regions 911 (drain regions) and 915 (source regions) and a channel formation region 914 are provided. An n − -type region is provided between the drain region and the channel formation region as necessary. A second insulating layer 917 is provided in contact with the semiconductor layer, and a silicon oxide film 919 is formed here. A drain electrode 920 is formed through a contact hole provided in the silicon oxide film. On the other hand, the active layer of the enhancement type TFT includes n ⁺ type regions 905 (source region) and 911 (drain region), a channel formation region 909, and an n ⁻ type region between the n ⁺ type region and the channel formation region. Is provided. Then, on the active layer, the mask insulating film 921 and the protective film 922 for the active layer used in the doping process are left without being removed, thereby receiving a larger stress than the depletion type TFT, and a threshold value. The voltage is controlled. Further, like the depletion type TFT, a contact hole is formed in the second insulating layer 917, and a source electrode 916 is provided.

  Such an E / D MOS circuit, like the CMOS circuit of the second embodiment, is a peripheral drive circuit for an active matrix liquid crystal display device, a drive circuit for an EL (Electroluminescence) display device, a reading circuit for a contact image sensor, etc. It can be applied to.

  An example of a semiconductor device having an n-channel TFT and a p-channel TFT, which are enhancement-type TFTs, on the same substrate, in which channel doping is performed in the channel formation region of either TFT, with reference to FIG. explain. FIG. 17 shows an inverter circuit which is a basic configuration of a CMOS circuit. By combining such inverter circuits, a basic circuit such as a NAND circuit or a NOR circuit can be formed, or a more complicated shift register circuit or buffer circuit can be formed. FIG. 17A is a diagram corresponding to a top view of the CMOS circuit, and FIG. 17B shows a cross-sectional structure view taken along a dotted line AA ′ in FIG.

In FIG. 17B, both the n-channel TFT and the p-channel TFT are formed over the same substrate. In the p-channel TFT, a gate electrode 902 is formed, and a nitrogen-rich silicon nitride oxide film 903 having a tensile stress and a silicon nitride oxide film 904 are provided thereon as a first insulating layer. Then, an active layer made of a crystalline semiconductor film is formed in contact with the first insulating layer, and the p ⁺ region 912 (drain region) and 915 (source region) and the p-type or n-type impurity concentration is 1 × 10 ¹⁵ atoms. A channel formation region 914 that is less than / cm ³ is provided. A second insulating layer 917 is provided in contact with the semiconductor layer, and a silicon oxide film 919 is formed here. A source electrode 920 and a drain electrode 918 are formed through contact holes provided in the silicon oxide film. On the other hand, in the active layer of the n-channel type TFT, the n ⁺ -type region 905 (source region), 911 (the drain region) and the channel forming region 909, between the n ⁺ -type region and the channel forming region n ^- type An area is provided. Then, p-type impurities such as B are channel-doped at a low concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less in the active layer channel formation region 909, so that the drain voltage is + 1V. The gate voltage when the absolute value of the drain current per 1 μm width of the channel formation region is 1 pA is controlled to the plus side. Further, like the p-channel TFT, a contact hole is formed in the second insulating layer 917, and a source electrode 916 and a drain electrode 918 are provided. The above is an example in which channel doping is performed on an n-channel TFT. However, channel doping may be performed on a p-channel TFT depending on the thickness and stress settings of the second insulating layer and the active layer.

  Such a CMOS circuit can be applied to a peripheral drive circuit of an active matrix liquid crystal display device, a drive circuit of an EL (ElectroLuminescence) display device, a reading circuit of a contact image sensor, or the like.

FIG. 18 shows a semiconductor device that includes both a first n-channel TFT that is an enhancement-type TFT and a second n-channel TFT that is a depletion-type TFT on the same substrate, and channel doping is performed on one of them. It explains using.
FIG. 18 shows an E / D MOS (enhancement / depletion) inverter circuit which is a basic configuration of an NMOS circuit. A feature of the E / D MOS inverter is that both enhancement type and depletion type TFTs are included in one circuit. By combining such inverter circuits, basic circuits such as NAND circuits and NOR circuits It is the same as that of the CMOS inverter circuit of the second embodiment in that it is possible to construct a more complicated shift register circuit or buffer circuit. FIG. 18A is a view corresponding to a top view of the E / D MOS inverter circuit. FIG. 18B shows a cross-sectional structure diagram along a dotted line AA ′ in FIG. C) shows a circuit diagram.

In FIG. 18B, enhancement type and depletion type TFTs are formed on the same substrate. In the depletion type TFT, a gate electrode 902 is formed, and a nitrogen-rich silicon nitride oxide film 903 having tensile stress and a silicon nitride oxide film 904 are provided thereon as a first insulating layer. Then, an active layer made of a crystalline semiconductor film is formed in contact with the first insulating layer, and the n ⁺ regions 911 (drain regions) and 915 (source regions) and the p-type or n-type impurity concentration is 1 × 10 ¹⁵ atoms. A channel formation region 914 that is less than / cm 3 is provided, and an n − -type region is provided between the source and drain regions and the channel formation region as necessary. A second insulating layer 917 is provided in contact with the semiconductor layer, and a silicon oxide film 919 is formed here. A drain electrode 920 is formed through a contact hole provided in the silicon oxide film. On the other hand, the active layer of the enhancement type TFT includes n ⁺ type regions 905 (source region) and 911 (drain region), a channel formation region 909, and an n ⁻ type region between the n ⁺ type region and the channel formation region. Is provided. Then, p-type impurities such as B are channel-doped at a low concentration of 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less in the active layer channel formation region 909, so that the drain voltage is + 1V. The gate voltage when the absolute value of the drain current per 1 μm width of the channel formation region is 1 pA is controlled to the plus side. Further, like the depletion type TFT, a contact hole is formed in the second insulating layer 917, and a source electrode 916 is provided. The above is an example in which the enhancement type TFT is channel-doped, but the depletion type TFT may be channel-doped depending on the settings of the film thickness and stress of the second insulating layer and the active layer.

  Such an E / D MOS circuit, like the CMOS circuit of the second embodiment, is a peripheral drive circuit for an active matrix liquid crystal display device, a drive circuit for an EL (Electroluminescence) display device, a reading circuit for a contact image sensor, etc. It can be applied to.

  In this embodiment, a semiconductor device incorporating an active matrix liquid crystal display device using a TFT circuit of the present invention will be described with reference to FIGS.

  Examples of such a semiconductor device include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a still camera, a personal computer, a television, and the like. Examples of these are shown in FIGS.

  FIG. 13A illustrates a mobile phone, which includes a main body 9001, an audio output portion 9002, an audio input portion 9003, a display device 9004, operation switches 9005, and an antenna 9006. The present invention can be applied to an audio output unit 9002, an audio input unit 9003, and a display unit 9004 including an active matrix substrate.

  FIG. 13B illustrates a video camera which includes a main body 9101, a display portion 9102, an audio input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 9106. The present invention can be applied to the audio input portion 9103, the display device 9102 including the active matrix substrate, and the image receiving portion 9106.

  FIG. 13C illustrates a mobile computer or a portable information terminal, which includes a main body 9201, a camera portion 9202, an image receiving portion 9203, operation switches 9204, and a display device 9205. The present invention can be applied to an image receiving portion 9203 and a display device 9205 including an active matrix substrate.

  FIG. 13D illustrates a head mounted display which includes a main body 9301, a display portion 9302, and an arm portion 9303. The present invention can be applied to the display device 9302. Although not shown, it can also be used for other signal control circuits.

  FIG. 13E illustrates a television set including a main body 9401, speakers 9402, a display portion 9403, a receiving device 9404, an amplifying device 9405, and the like. A liquid crystal display device or an EL display device can be applied to the display portion 9403.

  FIG. 13F illustrates a portable book, which includes a main body 9501, display portions 9502 and 9503, a storage medium 9504, an operation switch 9505, and an antenna 9506, and data stored in a minidisc (MD) or DVD, The data received by the antenna is displayed. The display portions 9502 and 9503 are direct-view display devices, and the present invention can be applied to this display portion.

  FIG. 14A illustrates a personal computer, which includes a main body 9601, an image input portion 9602, a display portion 9603, and a keyboard 9604.

  FIG. 14B shows a player that uses a recording medium (hereinafter referred to as a recording medium) in which a program is recorded, and includes a main body 9701, a display device 9702, a speaker unit 9703, a recording medium 9704, and operation switches 9705. This apparatus uses a DVD (Digital Versatile Disc), CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet.

  FIG. 14C illustrates a digital camera, which includes a main body 9801, a display portion 9802, an eyepiece portion 9803, operation switches 9804, and an image receiving portion (not shown).

  FIG. 15A illustrates a front type projector which includes a display device 3601 and a screen 3602. The present invention can be applied to display devices and other signal control circuits.

  FIG. 15B shows a rear projector, which includes a main body 3701, a projection device 3702, a mirror 3703, and a screen 3704. The present invention can be applied to display devices and other signal control circuits.

  FIG. 15C is a diagram showing an example of the structure of the projection devices 3601 and 3702 in FIGS. 15A and 15B. The projection devices 3601 and 3702 include a light source optical system 3801, mirrors 3802 and 3804 to 3806, a dichroic mirror 3803, a prism 3807, a liquid crystal display device 3808, a phase difference plate 3809, and a projection optical system 3810. The projection optical system 3810 is composed of an optical system including a projection lens. Although the present embodiment shows a three-plate type example, it is not particularly limited, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the optical path indicated by an arrow in FIG. Good.

  FIG. 15D illustrates an example of the structure of the light source optical system 3801 in FIG. In this embodiment, the light source optical system 3801 includes a reflector 3811, a light source 3812, lens arrays 3813 and 3814, a polarization conversion element 3815, and a condenser lens 3816. Note that the light source optical system illustrated in FIG. 15D is an example and is not particularly limited. For example, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, or an IR film in the light source optical system.

  In addition, the present invention can also be applied to image sensors and EL display elements. Thus, the applicable range of the present invention is extremely wide and can be applied to electronic devices in all fields.

Claims (14)

A semiconductor device having a first semiconductor layer that is not channel doped and a second semiconductor layer that is not channel doped,
A first gate electrode provided in the first semiconductor layer;
A second gate electrode provided in the second semiconductor layer;
A first insulating layer provided in contact with the first semiconductor layer and the second semiconductor layer;
A second insulating layer provided on the opposite side of the one surface of the first semiconductor layer provided with the first insulating layer;
The second insulating layer and the third insulating layer provided on the opposite side of the one surface of the second semiconductor layer provided with the first insulating layer,
Stress is applied to the first semiconductor layer by the second insulating layer, and stress is applied to the second semiconductor layer by the second insulating layer and the third insulating layer. The semiconductor device is characterized in that stress applied to the semiconductor layer and the second semiconductor layer are different. A semiconductor device having a first semiconductor layer that is not channel doped and a second semiconductor layer that is not channel doped,
A first gate electrode provided in the first semiconductor layer;
A second gate electrode provided in the second semiconductor layer;
A first insulating layer provided in contact with the first semiconductor layer and the second semiconductor layer;
A second insulating layer provided on the opposite side of the one surface of the first semiconductor layer provided with the first insulating layer;
The second insulating layer and the third insulating layer provided on the opposite side of the one surface of the second semiconductor layer provided with the first insulating layer,
The third insulating layer does not overlap the first semiconductor layer;
Stress is applied to the first semiconductor layer by the second insulating layer, and stress is applied to the second semiconductor layer by the second insulating layer and the third insulating layer. The semiconductor device is characterized in that stress applied to the semiconductor layer and the second semiconductor layer are different. A semiconductor device having a first semiconductor layer that is not channel doped and a second semiconductor layer that is not channel doped,
A first gate electrode provided in the first semiconductor layer;
A second gate electrode provided in the second semiconductor layer;
A first insulating layer provided in contact with the first semiconductor layer and the second semiconductor layer;
A second insulating layer provided on the opposite side of the one surface of the first semiconductor layer provided with the first insulating layer;
The second insulating layer and the third insulating layer provided on the opposite side of the one surface of the second semiconductor layer provided with the first insulating layer,
The third insulating layer does not overlap the first semiconductor layer;
Stress is applied to the first semiconductor layer by the second insulating layer, and stress is applied to the second semiconductor layer by the second insulating layer and the third insulating layer. The stress applied to the semiconductor layer and the second semiconductor layer is different,
The semiconductor device, wherein the first semiconductor layer and the second semiconductor layer are single crystal semiconductors. A first gate electrode provided in the first semiconductor layer;
A second gate electrode provided in the second semiconductor layer;
A first insulating layer provided in contact with the first semiconductor layer and the second semiconductor layer;
A second insulating layer provided on the opposite side of the one surface of the first semiconductor layer provided with the first insulating layer;
The second insulating layer and the third insulating layer provided on the opposite side of the one surface of the second semiconductor layer provided with the first insulating layer,
Stress is applied to the first semiconductor layer by the second insulating layer, and stress is applied to the second semiconductor layer by the second insulating layer and the third insulating layer. The semiconductor device is characterized in that stress applied to the semiconductor layer and the second semiconductor layer are different. In any one of Claims 1 thru | or 4,
A semiconductor device, wherein stress is applied to the first semiconductor layer and the second semiconductor layer, and strain is generated in the first semiconductor layer and the second semiconductor layer. In any one of Claims 1 thru | or 5,
The semiconductor device, wherein the second insulating layer is in contact with the first semiconductor layer and the second semiconductor layer. In any one of Claims 1 thru | or 6,
The semiconductor device, wherein the third insulating layer is provided on the second insulating layer. In any one of Claims 1 thru | or 7,
The product of stress and film thickness of the second insulating layer in contact with the first semiconductor layer is different from the product of stress and film thickness of the second insulating layer in contact with the second semiconductor layer. A semiconductor device characterized by the above. In any one of Claims 1 thru | or 5,
On the second insulating layer, a source electrode and a drain electrode that are electrically connected to the first semiconductor layer through a contact hole are provided.
A source device and a drain electrode that are electrically connected to the second semiconductor layer through contact holes are provided on the second insulating film and the third insulating film. . In claim 9,
The semiconductor device, wherein the third insulating layer is provided between the second insulating layer and the second semiconductor layer. In claim 9 or 10,
A silicon oxide film is provided on the source electrode and the drain electrode electrically connected to the first semiconductor layer, and on the source electrode and the drain electrode electrically connected to the second semiconductor layer. Semiconductor device. In any one of Claims 1 thru | or 11,
The n-type or p-type impurity concentration in the channel formation region of the first semiconductor layer is less than a detection limit value in SIMS analysis, and the n-type or p-type impurity concentration in the channel formation region of the second semiconductor layer is A semiconductor device characterized by being less than a detection limit value in SIMS analysis. In any one of Claims 1 thru | or 12,
The first TFT having the first semiconductor layer and the second TFT having the second semiconductor layer are enhancement type TFTs.   An electronic apparatus comprising the semiconductor device according to claim 1 and an operation switch.

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