JP2011223243A - Electronic circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic circuit device that is capable of reducing deterministic jitter resulted from impedance mismatch by adjusting the delay time of a signal.SOLUTION: A typical constitution is an electronic circuit device 100 that transmits signals from a driver 104 to a receiver 108 through a transmission path 106 via high-speed serial transmission, comprising: an inductor 112, an LC circuit 114, or an LCR circuit that constitutes a delay circuit with capacitance of an impedance mismatch point near the upstream side or the downstream side of the impedance mismatch point on the transmission path 106.

Description

  The present invention relates to an electronic circuit device that transmits a signal from a driver to a receiver through a transmission line by high-speed serial transmission.

  The recent development of information communication technology is remarkable, and the speed of data communication has been increasing. For example, in high-speed digital serial communications represented by serial ATA, Fiber Channel, PCI Express, etc., the bit rate is several Gbps (Gigabit per second) or more, and a gigahertz (GHz) band. Are being transmitted.

  In the electric signal transmission line, if there is an impedance mismatch, the efficiency of the transmitted power is lowered. Further, when high frequency is transmitted as in high-speed serial transmission, reflection occurs at impedance mismatch points and is superimposed on the original signal as noise. Due to such noise, the rise and fall of the signal fluctuate in the time axis direction, and so-called deterministic jitter (hereinafter abbreviated as jitter) occurs. Therefore, impedance matching is extremely important in high-speed serial transmission, and is usually designed so that the output impedance of the driver, the characteristic impedance of the transmission line, and the input impedance of the receiver match.

  However, there are parasitic capacitances in protective diodes and transistors included in LSIs such as drivers and receivers. In general, the influence of parasitic capacitance increases as the signal becomes higher in frequency. Similarly, in a low frequency range, parasitic capacitance is generated in a connector or a circuit pattern in which parasitic capacitance is not a problem, and a parasitic capacitance is generated when the signal frequency is increased, which becomes an impedance mismatch point. As the frequency is further increased in the high-speed serial communication, it is virtually impossible to perfectly match the impedance.

  Further, the characteristic impedance of the transmission line changes depending on the line length. Therefore, when considering impedance matching, the line length is naturally set, but due to restrictions such as the placement of elements and LSIs that increase with higher functionality and the size reduction of the substrate due to miniaturization, it is excessive. It is difficult to set the desired line length without a shortage.

  Therefore, various techniques for reducing jitter have been proposed. In Patent Document 1, in an in-vehicle device mounted on an automobile or the like, a reflected wave that delays a traveling wave of a signal by λ / 4 time with a minimum pulse width on the upstream side of a transmission path in which a relay connector is interposed in a twisted pair wire. A technique for providing a delay means is disclosed. In Patent Literature 1, even if a part of the traveling wave is reflected by using the relay connector as an impedance mismatch point with the above configuration, the phase (half cycle) of the traveling wave and the reflected wave can be matched, and jitter can be reduced. .

JP 2008-54100 A

  In the technique of Patent Document 1, it is assumed that only the relay connector is an impedance mismatch point. However, in high-speed serial transmission, the influence of parasitic capacitance increases, so there is a possibility that drivers and receivers become impedance mismatch points.

  When there are a plurality of impedance mismatch points, even if the traveling wave of the signal is delayed by λ / 4 time of the minimum pulse width as in Patent Document 1, the jitter is not necessarily reduced. In other words, Patent Document 1 is effective only with an ideal model in which only the relay connector is an impedance mismatch point, as disclosed in the specification. Moreover, Patent Document 1 does not disclose how to provide a reflected wave delay means (inductor) for delaying λ / 4 time with the minimum pulse width.

  The present invention has been made in view of the above problems, and provides an electronic circuit device capable of reducing deterministic jitter caused by impedance mismatch by adjusting a delay time of a signal. For the purpose.

  In order to solve the above-mentioned problems, the present inventors have intensively studied and found that in high-speed serial transmission, jitter periodically increases / decreases with respect to changes in the transmission line length. That is, although parasitic capacitance occurs at various locations, the inventors have finally found the possibility of comprehensively controlling the increase / decrease in jitter using the line length as a parameter. However, as described above, it is difficult to set the line length to a desired length due to various restrictions. Thus, the present invention has been completed by adjusting the signal delay time to shift the jitter increase / decrease period and further researching how the delay time can be adjusted easily and reliably.

  That is, a representative configuration of the present invention is an electronic circuit device that transmits a signal from a driver to a receiver through a transmission line by high-speed serial transmission, and is located upstream or downstream of an impedance mismatch point on the transmission line. An inductor, an LC circuit, or an LCR circuit constituting a delay circuit is provided between the impedance mismatch point and the capacitance.

  According to such a configuration, it is possible to adjust the jitter increase / decrease period dip with respect to an arbitrary (actual) line length by changing the value (combination) of the elements constituting the delay circuit. . Therefore, jitter can be reduced.

  In addition, depending on the configuration of the LC circuit or the LCR circuit, a circuit that also operates as an impedance matching circuit can be configured. In other words, it is possible to adjust the jitter to increase or decrease with respect to an arbitrary (actual) line length while performing impedance matching. Thereby, since the reflection of the signal itself can be reduced, a higher jitter reduction effect can be obtained.

  The delay circuit may be provided at a distance of 1/8 or less of the fundamental wavelength λ of the signal transmitted from the impedance mismatch point. Here, it is assumed that the relationship of fundamental wave wavelength λ = v · 2 / BR (v is the speed at which the signal propagates through the transmission path, BR is the bit rate of the signal) is satisfied. As a result, an element (such as an LSI or a connector) existing at an impedance mismatch point and an inductor, an LC circuit, or an LCR circuit inserted in the transmission line can be regarded as an integrated circuit. It can be prevented from becoming a matching point (reflection point).

  In order to solve the above problems, another typical configuration of the present invention is an electronic circuit device that transmits a signal from a driver to a receiver through a transmission line by high-speed serial transmission, and is upstream of an impedance mismatch point on the transmission line. The inductor, the LC circuit or the LCR circuit constituting the delay circuit between the impedance mismatch point and the capacitance at the impedance side or the downstream side is provided, and at least the signal bit rate, the inductor, and the LC circuit are determined by simulator analysis. Alternatively, the signal flowing through the transmission line is delayed by the delay circuit using the value of the element of the LCR circuit, the capacitance of the impedance mismatch point, the line length of the transmission line, and the characteristic impedance of the transmission line. Jitter that periodically increases and decreases with changes in length is small in the line length of this transmission line. So as to, characterized in that calculated values of the element.

  According to such a configuration, it is possible to appropriately calculate the values of the elements constituting the delay circuit capable of shifting the increase / decrease period so as to be a jitter dip at an arbitrary (actual) line length. Thereby, it is possible to suitably and reliably reduce jitter.

  ADVANTAGE OF THE INVENTION According to this invention, the electronic circuit apparatus which can reduce the deterministic jitter which generate | occur | produces by impedance mismatching by adjusting the delay time of a signal can be provided.

It is a figure which illustrates 1st Embodiment of the electronic circuit apparatus concerning this invention. It is a figure explaining the characteristic of a jitter. It is a figure which illustrates the receiver input waveform of the transmission line of 105 mm of line length, and the receiver input waveform after adjustment by inductor insertion. It is a figure which illustrates 2nd Embodiment of the electronic circuit apparatus concerning this invention. It is a figure which illustrates 3rd Embodiment of the electronic circuit apparatus concerning this invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in the embodiments are merely examples for facilitating understanding of the invention, and do not limit the present invention unless otherwise specified. In the present specification and drawings, elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted, and elements not directly related to the present invention are illustrated. Omitted.

[First embodiment]
FIG. 1 is a diagram illustrating a first embodiment of an electronic circuit device according to the invention. FIG. 1A is a schematic diagram showing a configuration of an electronic circuit device, and FIG. 1B is a schematic diagram of FIG. 1A after adjustment by inserting an inductor. The electronic circuit device 100 transmits a signal at a constant bit rate by high-speed serial transmission.

  As illustrated in FIG. 1A, the electronic circuit device 100 has a differential configuration. That is, the signals generated by the waveform generation circuit 102 and applied to the driver 104 are output in opposite phases from the pair of differential driver output terminals 104a. Then, the signals are applied to the receiver 108 from the pair of differential receiver input terminals 108a through the two transmission lines 106, and the difference between them is combined.

  When the output impedance of the driver 104 and the input impedance of the receiver 108 do not match the characteristic impedance of the transmission line 106, a part of the signal is reflected there to become a reflected wave. Such reflected waves cause deterministic jitter.

  In this embodiment, an inductor 112 that constitutes a delay circuit between the impedance mismatch point and the capacitance is inserted in the vicinity of the impedance mismatch point on the transmission line 106 upstream or downstream. Thereby, it is possible to reduce the jitter by adjusting the delay time of the signal.

  Specifically, as illustrated in FIG. 1B, an inductor 112 having a predetermined inductance is mounted on an element mounting portion 110b formed so that an additional element can be inserted. Here, the inductor 112 is mounted on the element mounting portion 110b formed upstream of the receiver 108, but the inductor 112 may be mounted on the element mounting portion 110a formed downstream of the driver 104. That is, the insertion position of the inductor 112 may be in the vicinity of the impedance mismatch point, and may be inserted in both the element mounting portions 110a and 110b. When no inductor is mounted on the element mounting portions 110a and 110b, the transmission path 106 can be simply short-circuited.

  The element mounting portions 110a and 110b are preferably provided at a distance of 1/8 or less of the fundamental wavelength λ of the transmitted signal from the driver 104 or the receiver 108 (impedance mismatch point). In other words, the distance from the impedance mismatch point to the end of the delay circuit is preferably a distance that is 1/8 or less of the fundamental wavelength λ. As a result, the driver 104 and the receiver 108 and the mounted inductor 112 can be regarded as an integrated circuit, and each can be prevented from independently becoming a reflection point.

  FIG. 2 is a diagram for explaining the characteristics of jitter. 2A illustrates the jitter value with respect to the line length of the transmission line of the electronic circuit device of FIG. 1A, and FIG. 2B illustrates the jitter value of FIG. 1B after adjustment by inserting an inductor. Is illustrated.

  As illustrated in FIG. 2A, in the electronic circuit device 100, the jitter periodically increases / decreases as the line length of the transmission path 106 changes. Here, the jitter peak (maximum value) occurs when the line length is about 101 mm, about 105 mm, and about 109 mm, and the jitter dip (minimum value) occurs when the line length is about 103 mm and about 107 mm.

  The jitter increase / decrease period depends on the signal delay time in the transmission path 106 when the bit rate is constant. That is, the jitter increase / decrease period changes with the fluctuation of the inductance of the inductor 112 inserted in the transmission line 106. Assuming only the case where a part of the signal reflected by the receiver 108 is reflected by the driver 104 without back-matching and interferes with the traveling wave (both ends are reflection points), the jitter peak to dip are assumed. The interval is λ / 8. The interval (increase / decrease period) from the peak of jitter to the next peak is λ / 4.

  As illustrated in FIG. 2B, when the inductor 112 is mounted on the element mounting portion 110b, the jitter increase / decrease period is shifted with respect to the line length based on the inductance value of the inductor 112. From this, a simulator analysis is performed, and it is calculated how large the inductor 112 having an inductance can be inserted to the transmission line 106 so that the increase / decrease period can be shifted so as to be a jitter dip at an arbitrary line length.

In the simulator analysis, at least the bit rate BR of the transmitted signal, the inductance L of the inductor 112, the capacitance C _txi (C _txo ) of the impedance mismatch point, the line length M of the transmission path 106, and the transmission path 106 Characteristic impedance Z ₀ is used. For example, a data table as exemplified in Table 1 may be created, and the magnitude of the inductance of the inductor 112 may be calculated so that the jitter becomes small at an arbitrary line length x by inputting each numerical value.

  Table 1 is an example, and it is not always necessary to use all of these parameters for the simulator analysis. Of course, other parameters may be adopted for simulator analysis. Other parameters include the rising frequency of the edge of the signal that affects the increase or decrease of jitter.

  For example, referring to FIG. 2A, when the line length of the transmission path 106 becomes 105 mm due to restrictions on element arrangement or the like, the jitter peaks. However, the above-described simulator analysis can calculate the inductance (here, 0.6 nH) of the inductor 112 that shifts the jitter increase / decrease period so that the jitter dip comes when the line length is 105 mm. As a result, the 0.6 nH inductor 112 is mounted on the element mounting portion 110b, and the jitter can be suitably and reliably reduced. Here, the jitter value can be reduced from 13 ps_pp to 5 ps_pp (see FIG. 2B).

  In addition, the element mounting part 110b can be formed as a component pad to which the inductor 112 formed on, for example, a printed board can be added. Of course, the element mounting part 110b may be one in which the inductor 112 is inserted into the transmission line 106 by wire bonding.

  FIG. 3 is a diagram illustrating a receiver input waveform of a transmission line having a line length of 105 mm and a receiver input waveform after adjustment by inserting an inductor. FIG. 3A illustrates the receiver input waveform of the electronic circuit device of FIG. 1A having a line length of 105 mm. FIG. 3B illustrates a receiver input waveform of the electronic circuit device of FIG. 1B in which a 0.6 nH inductor is inserted in the transmission line.

  Comparing FIG. 3 (a) and FIG. 3 (b), it can be seen that the zero cross points of the receiver input waveform are clearly aligned in FIG. 3 (b). Therefore, it has been proved that the insertion of the inductor 112 based on the simulator analysis reduces the jitter and improves the bit error rate.

  As described above, according to the electronic circuit device 100 according to the present embodiment, the jitter peak and dip position can be changed by changing the value of the inductance of the inductor 112 constituting the delay circuit. It is possible to adjust so that the jitter becomes a dip with respect to the length. Therefore, even if the parasitic capacitance generated in various parts of the circuit is not accurately grasped and the line length of the transmission line 106 cannot be set to a desired length, the jitter can be reduced by adjusting the inductance appropriately. it can.

[Second Embodiment]
FIG. 4 is a diagram illustrating a second embodiment of the electronic circuit device according to the invention. In the second embodiment, elements having substantially the same functions and configurations as those of the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  In the first embodiment, the inductor 112 is inserted into the transmission line 106, and the delay circuit that adjusts the signal delay time is configured by the capacitance at the impedance mismatch point and the inductor 112. On the other hand, in the second embodiment, the LC circuit 114 is inserted into the transmission line 106, and the capacitance at the impedance mismatch point and the LC circuit 114 constitute a delay circuit that adjusts the signal delay time.

  That is, as illustrated in FIG. 4, the inductor 112 and the capacitor 116 are mounted on the element mounting portion 110 b formed so that additional elements can be inserted, and the LC circuit 114 is inserted into the transmission path 106. As a matter of course, these may be mounted on the element mounting portion 110a on the downstream side of the driver 104, or may be mounted on both the element mounting portion 110b on the upstream side of the receiver 108.

  As one of the features of this embodiment, the LC circuit 114 can be operated as an impedance matching circuit. That is, it is possible to determine the combination of the inductor 112 and the capacitor 116 by which the impedance is matched and the increase / decrease period is shifted so as to be a jitter dip at an arbitrary line length by simulator analysis. Thereby, since the reflection of the signal itself can be reduced, a higher jitter reduction effect can be obtained.

  The impedance matching by the LC circuit 114 is to match the impedance of a known element in a calculation formula. Therefore, it is practically impossible to completely eliminate the reflected wave in high-speed serial transmission in which the influence of parasitic capacitance is a problem. In addition, in the impedance matching, when the cut-off frequency of the LC circuit 114 is lower than the signal frequency, there is a problem that the impedance is not actually matched even if the impedance matching is performed according to the calculation formula. Thus, even if impedance matching is incomplete, the jitter can be extremely effectively reduced by shifting the increase / decrease period so that the jitter dip occurs at an arbitrary line length as in the present invention.

  The electronic circuit device 100 according to the present embodiment has been described above. In the above description, the case where the LC circuit 114 is inserted into the transmission path 106 has been described in detail. However, instead of this, an LCR circuit may be inserted into the transmission path 106. Naturally, the LCR circuit can be operated as an impedance matching circuit by combining the elements, and the increase / decrease period can be shifted so that the jitter dip occurs at an arbitrary line length.

[Third Embodiment]
FIG. 5 is a diagram illustrating a third embodiment of the electronic circuit device according to the invention. Note that in the third embodiment, elements having substantially the same functions and configurations as those of the first embodiment are denoted by the same reference numerals, and redundant description is omitted.

  As illustrated in FIG. 5, the present invention can be applied even when the relay connector 118 serving as an impedance mismatch point exists in the transmission line 106. That is, an inductor 112 having a predetermined inductance can be mounted on the element mounting portions 110c and 110d in the vicinity of the relay connector 118 formed so that an additional element can be inserted, thereby reducing jitter.

  Although not shown, the inductor 112 may be mounted not only in the vicinity of the relay connector 118 but also in the element mounting portions 110a and 110b in the vicinity of the driver 104 and the receiver 108. That is, it is preferable to configure a delay circuit that delays so that the jitter becomes a dip for each impedance mismatch point, in other words, for each location where a reflected wave is generated. Further, even if the LC circuit 114 or the LCR circuit is inserted into the transmission line 106 instead of the inductor 112, the same effect can be obtained.

  The preferred embodiments of the present invention have been described above with reference to the accompanying drawings. According to the electronic circuit device 100 described above, the inductor 112, the LC circuit 114, or the LCR circuit can be connected later even when the line length of the transmission line 106 is equivalent to the jitter peak due to manufacturing variations or the like. In addition, jitter can be reduced. Therefore, this is particularly effective when a shift in the line length is assumed in advance or when the signal delay time per unit length of the transmission path 106 does not become the design value.

  Needless to say, the present invention is not limited to such examples. That is, in the above-described embodiment, the electronic circuit device 100 having the differential configuration is illustrated, but a single-ended configuration is also encompassed by the present invention. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  The present invention is applicable to an electronic circuit device that transmits a signal from a driver to a receiver through a transmission line by high-speed serial transmission.

DESCRIPTION OF SYMBOLS 100 ... Electronic circuit apparatus 102 ... Waveform generation circuit 104 ... Driver 104a ... Differential driver output terminal 106 ... Transmission path 108 ... Receiver 108a ... Differential receiver input terminal 110a-110d ... Element mounting part 112 ... Inductor 114 ... LC circuit 116 ... Capacitor 118 ... Relay connector

Claims (3)

An electronic circuit device for transmitting a signal from a driver to a receiver through a transmission line by high-speed serial transmission,
An inductor, an LC circuit, or an LCR circuit that constitutes a delay circuit between the impedance mismatch point and the capacitance at the impedance mismatch point on the transmission line is provided in the vicinity of the upstream or downstream side of the impedance mismatch point. Electronic circuit device.   2. The electronic circuit device according to claim 1, wherein the delay circuit is provided at a distance of 1/8 or less of a fundamental wavelength λ of a signal transmitted from the impedance mismatch point. An electronic circuit device for transmitting a signal from a driver to a receiver through a transmission line by high-speed serial transmission,
An inductor, an LC circuit, or an LCR circuit that forms a delay circuit with the capacitance of the impedance mismatch point in the vicinity of the upstream side or downstream side of the impedance mismatch point on the transmission line;
By simulator analysis, at least
The bit rate of the signal;
The value of the inductor, LC circuit or LCR circuit element;
A capacitance of the impedance mismatch point;
A line length of the transmission line;
Using the characteristic impedance of the transmission line,
The value of the element was calculated so that the jitter that periodically increases / decreases with respect to the change in line length is reduced in the line length of the transmission line by the signal flowing through the transmission line being delayed by the delay circuit. An electronic circuit device.

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