JP2011217102A - Receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve digital signal processing performance while suppressing increase in circuit scale, in a receiver provided in a high-speed interface.SOLUTION: The receiver includes: a digital/analog conversion part which converts voltage change of an analog signal to be input into a series of digital data; a parallelization part which parallelizes the series of the digital data; an equalizer part which performs waveform generation processing on parallelized digital signals; a delay addition part which branches an analog signal into a plurality of lines to give different delays to the plurality of lines of analog signals, respectively; and a gain control part which controls a gain of an amplifier in which the analog signals of each line delayed by the delay addition part are input by bias current of the amplifier.

Description

  The present invention relates to a receiving device provided in a wired interface for high-speed data communication.

  Wired interfaces for high-speed data communication are used for LSI intra-chip communication, short-distance communication between chips on the same substrate, and medium-distance communication between cards via a backplane. In such a high-speed interface receiver, for example, an analog / digital converter (ADC) may be arranged after the input amplifier, and the subsequent signal processing may be realized by a digital circuit. In this case, the digital signal obtained by the ADC is parallelized by the demultiplexer and then output through the equalizer (see Patent Document 1).

  Therefore, in the equalizer provided in the high-speed interface receiver, the signal waveform is processed for each signal parallelized by the demultiplexer. Waveform shaping in the equalizer is realized, for example, by a circuit that sequentially delays an input signal using i flip-flops (FFs), amplifies the output of each FF with a corresponding amplifier, and feeds back to the input signal.

JP 2006-262395 A

  In the above-described conventional high-speed interface receiver, for example, when the number of ADC bits is increased from m bits to m + 1 bits, the number of signals to be equalized by the equalizer is changed from m × n to (m + 1) ×. increase to n. Here, the numerical value n is the number of parallel data series generated by the demultiplexer from each bit of the ADC output. Then, corresponding to each of the increased signal lines, the equalizer is provided with FFs and amplifiers corresponding to the number of feedback loops.

  As described above, in the conventional high-speed interface receiver, the scale of the equalizer circuit greatly increases as the number of bits of the ADC increases in order to improve digital signal processing performance including equalization processing. The overall circuit scale is increased. Also, when the number of feedback loops is increased with the aim of improving the waveform equalization accuracy by the equalizer, the circuit scale similarly increases. In other words, it has been difficult for a conventional high-speed interface receiver to achieve both reduction in circuit scale and improvement in digital signal processing performance.

  An object of the present disclosure is to provide a receiving device that is provided in a high-speed interface, and that can improve digital signal processing performance while reducing the circuit scale.

  The above-described object can be achieved by the receiving device disclosed below.

  A receiving apparatus according to one aspect includes an analog / digital conversion unit that converts a voltage change of an input analog signal into a digital data sequence, a parallelization unit that parallelizes the digital data sequence, and a parallel digital signal An equalizer unit that performs waveform generation processing, a delay adding unit that branches analog signals into a plurality of systems and gives different delays to the plurality of analog signals, and an analog signal of each system that is delayed by the delay adding unit are input. And a gain control unit for controlling the gain of the amplifier according to the bias current of the amplifier.

  According to the device of the present disclosure, it is possible to improve the digital signal processing performance while suppressing the circuit scale of the receiving device provided in the high-speed interface.

It is a figure which shows one Embodiment of a receiver. It is explanatory drawing of an input equalizer part. It is a figure which shows embodiment of a variable gain amplifier. It is a figure which shows another embodiment of an input equalizer part. It is a timing diagram explaining an equalizing action. It is a figure which shows one Embodiment of a gain control part. It is a figure which shows one Embodiment of an equalizer circuit. It is a flowchart showing a gain setting operation. It is a figure which shows another embodiment of a receiver. It is a figure which shows another embodiment of an equalizer circuit. It is a figure which shows another embodiment of a receiver.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 shows an embodiment of a receiving device.

  The receiving apparatus illustrated in FIG. 1 receives a high-speed serial signal transmitted from the transmitting apparatus 100 via a transmission path. An analog / digital conversion unit (A / D) 101 shown in FIG. 1 converts an input analog signal into, for example, k-bit digital data. The parallelizing unit 102 provided in the receiving device is, for example, a 1: n demultiplexer. The output of the analog / digital conversion unit 101 is divided into n pieces of parallel data by the parallelization unit 102 and output through the equalizer 103.

  The receiving apparatus illustrated in FIG. 1 includes an input equalizer unit 110 on the input side of the analog / digital conversion unit 101. The input equalizer unit 110 includes a delay adding unit 111, a variable amplifier 112, a gain control unit 113, and an adder 114.

  The delay adding unit 111 branches the input analog signal into a plurality of systems, and adds different delays to each system. For example, the delay adding unit 111 illustrated in FIG. 1 generates analog signals having different delays in the number n + 1 of delay elements using delay elements τ connected in series.

The variable amplifier 112 includes variable gain amplifiers AMP _{1 to} AMP _{n + 1} corresponding to a plurality of analog signals generated by the delay adding unit 111. The bias currents of these variable gain amplifiers AMP _{1 to} AMP _{n + 1} are variably controlled by the gain control unit 113. The outputs of these variable gain amplifiers AMP _{1 to} AMP _{n + 1} are added by the adder 114 and input to the analog / digital conversion unit 101.

  FIG. 2 is an explanatory diagram of the input equalizer unit. In the example shown in FIG. 2, a delay τ is given to one of the two systems of analog signals, which are input to the adder 114 via the amplifier 1 and the amplifier 2, respectively.

In the amplifier 1 shown in FIG. 2, voltage values X _n−2 , X _n−1 , X _n , X _{n + 1} , X _{n + 2} , and X _{n + 3 obtained} by sampling the received waveform at time intervals corresponding to the delay τ are sequentially input. Is done. The output multiplied by the gain C ₀ is sequentially output from the amplifier 1. Similarly, sampling the voltage value that is delayed in the amplifier 2 is input, the output value obtained by multiplying the gain C ₁ in response to these inputs are output. Therefore, the output Y of the adder 114 that adds the outputs of the amplifiers 1 and 2 is expressed as shown in Expression (1).

_{Y n = C 0 × X n} + C 1 × X n-1 ··· (1)
In the equalizer configured as described above, by setting the gains C ₀ and C ₁ of the amplifiers 1 and 2 to appropriate values, a dull received waveform as indicated by the symbol X (t) in FIG. , And an equalized waveform as shown with a symbol Y (t) can be obtained. For example, the gain control unit 113 can set a gain C ₀ larger than the numerical value 1 for the amplifier 1 and a gain C ₁ having a negative value for the amplifier 2. The gains of the amplifiers 1 and 2 can be set to desired values by adjusting the bias currents of the amplifiers 1 and 2, for example.

  FIG. 3 shows an embodiment of a variable gain amplifier. In the variable gain amplifier shown in FIG. 3, the gate voltages of the two MOS transistors connected to the current source of the Gilbert cell amplifier are controlled by two bias current values ibias + and ibias−. In the variable gain amplifier configured as described above, positive and negative gains can be realized by adjusting the bias current values ibias + and ibias−.

  In a receiving apparatus in which such an input equalizer unit 110 is arranged on the front side of the analog / digital conversion unit 101, the waveform of the received signal deteriorated due to loss in the transmission path is shaped prior to A / D conversion. Therefore, a highly accurate A / D conversion result can be obtained. Therefore, the performance of the receiving apparatus can be improved without increasing the number of bits of the analog / digital conversion unit 101 or the number of taps in the equalizer 103 at the subsequent stage. That is, in a receiving device for a high-speed interface, it is possible to improve digital signal processing performance while reducing the circuit scale.

  In addition, since the received signal waveform input to the analog / digital conversion unit 101 is shaped by the input equalizer unit 110 described above, the performance of the receiving apparatus is maintained even if the number of bits of the analog / digital conversion unit 101 is reduced. can do. For example, when the number of bits of the analog / digital conversion unit 101 shown in FIG. 1 is reduced from k bits to k−1 bits, the parallelization unit 102 makes the reduced 1 bit n parallel. Circuit to be reduced. Similarly, in the equalizer 103, the number of circuits that perform waveform shaping processing on the n signal lines reduced by the parallelizing unit 102 is reduced. The scale of these circuits to be reduced is larger than the circuit scale added as the input equalizer unit 110. Therefore, by applying the input equalizer unit 110 as described above, it is possible to greatly reduce the circuit scale while maintaining the performance of the receiving device.

As shown in FIG. 1, instead of using a plurality of delay elements, it is also possible to generate a plurality of systems of analog signals to be input to a plurality of variable amplifiers using clock signals whose phases are shifted. In the following embodiments, waveform equalization processing for a plurality of analog signals generated using a plurality of sample and hold units will be described.
(Embodiment 2)
FIG. 4 shows another embodiment of the input equalizer unit. 4 that are the same as those shown in FIGS. 1 and 2 are given the same reference numerals, and descriptions thereof are omitted.

In the delay adding unit 111 of the input equalizer unit shown in FIG. 4, the clock signals CLK are input to the two sample-and-hold units 115 ₁ and 115 ₂ in opposite phases, whereby two systems of input signals din (0) and din (180) is generated. The input signals din (0) and din (180) are added by the adder 114 via the amplifier P1 and the amplifier P2, respectively.

The gain control unit 113 shown in FIG. 4 switches the gains gm ₁ and gm ₂ of the amplifiers P1 and P2 in synchronization with the clock signal. For example, in the first half of the clock signal cycle, the gain control unit 113 sets the gains gm ₁ and gm ₂ of the amplifiers P1 and P2 to values corresponding to the gains C ₀ and C ₁ of the amplifiers 1 and 2 shown in FIG. Set. In the second half of the cycle of the clock signal, conversely, the gain gm _{2 of the} amplifier P2 is set to a value corresponding to the gain C ₀ of the amplifier 1 shown in FIG. 2, and the gain gm _{1 of the} amplifier P1 is shown in FIG. A value corresponding to the gain C ₁ of the amplifier 2 is set.

  That is, in the configuration shown in FIG. 4, the amplifier P1 functions as the amplifier 1 that amplifies an input signal that is not delayed in the input equalizer unit 110 shown in FIG. At this time, the amplifier P2 of FIG. 4 fulfills the function of the amplifier 2 that amplifies the input signal delayed in the input equalizer unit 110 shown in FIG.

  On the other hand, in the second half of the cycle of the clock signal, the functions of the amplifiers P1 and P2 of the input equalizer section shown in FIG. 4 are reversed. That is, the function of the amplifier 2 that amplifies the input signal delayed in the input equalizer unit 110 shown in FIG. 2 is performed by the amplifier P1. The amplifier P2 performs the function of the amplifier 1 that amplifies the input signal that is not delayed in the input equalizer unit 110 shown in FIG.

FIG. 5 is a timing chart for explaining the equalizing operation. FIG. 5A shows the received signal waveform, and FIG. 5B shows the clock signal CLK. In the example shown in FIG. 5, in synchronization with the rising edge of the clock signal CLK, the sample point Xn-1, Xn + 1, Xn + 3, Xn + 5 are held in sequence in the sample-and-hold unit 115 ₁ is input to the amplifier P1 (FIG. 5 ( d)). Further, in synchronization with the falling edge of the clock signal CLK, the sample point Xn, Xn + 2, Xn + 4 are held in sequence in the sample-and-hold unit 115 _2, are input to the amplifier P2 (see FIG. 5 (g)).

FIGS. 5C and 5F show how the gains gm ₁ and gm ₂ set in the amplifiers P1 and P2 are switched in synchronization with the clock signal CLK. FIGS. 5E and 5H show changes in the outputs of the amplifiers P1 and P2 in response to the above-described gain switching.

For example, at the rising edge of the clock signal indicated by reference numeral (1) in FIG. 5 (b), the sample point Xn-1 is held by the sample-and-hold unit 115 ₁ is maintained one period of the clock signal. In this period, the output gm ₁ × din (0) of the amplifier P1 is a value obtained by multiplying the sample value Xn−1 by the gain C ₀ in accordance with the switching of the gain gm ₁ as shown in FIG. from changes to the gain C ₁ to multiplied value to the sample value Xn-1. On the other hand, for example, at the falling edge of the clock signal indicated by reference numeral (2) in FIG. 5 (b), the sample point Xn is held in the sample hold unit 115 ₂ is maintained one period of the clock signal. In this period, the output gm ₂ × din amplifier P2 (180), as shown in FIG. 5 (h), in accordance with the switching of the gain gm _2, the gain _{C 0} from a value obtained by multiplying the sample value Xn, changes to a value obtained by multiplying the gain C ₁ to the sample value Xn. Therefore, in the second half of the cycle of the clock signal including the falling edge of the symbol (2) in FIG. 5B, the outputs of the two amplifiers P1 and P2 have values C ₁ × Xn−1 and C ₀ × Xn, respectively. . Then, in the first half of the next cycle, the outputs of the two amplifiers P1 and P2 have values C ₀ × Xn + 1 and C ₁ × Xn, respectively (see FIGS. 5E and 5H).

In this way, as the result of adding the outputs gm ₁ × din (0) and gm ₂ × din (180) of the amplifiers P1 and P2 by the adder 114, an addition result similar to the above equation (1) is obtained. Can do. That is, as shown in FIG. 4, by controlling the two sample hold units 115 ₁ and 115 ₂ and the two amplifiers P1 and P2 in synchronization with the clock signal, the input equalizer unit 110 shown in FIG. An equivalent waveform shaping action can be realized.

As described above, in the input equalizer unit configured by including the _two sample hold units 115 ₁ and 115 ₂ , it is easy to design the transmission path lengths of the two branched paths equally. Thereby, a highly accurate waveform shaping operation can be realized.

Next, the gain control unit 112 that performs the switching control described above will be described.
FIG. 6 shows an embodiment of the gain control unit. The gain control unit shown in FIG. 6 includes a conversion table circuit 116, a selector circuit 117, a digital / analog conversion unit (D / A) 118, and a coefficient setting processing unit 119.

The conversion table circuit 116 holds a plurality of sets of coefficients corresponding to the gain sets C ₀ and C ₁ that are alternately set in the two amplifiers P 1 and P 2 described above. The conversion table circuit 116 shown in FIG. 6 has coefficients having three different values corresponding to the gain C ₁ corresponding to the coefficients α ₁ , α ₂ , and α ₃ having three different values corresponding to the gain C _0. β ₁ , β ₂ and β ₃ are retained. The conversion table circuit 116 outputs a set of coefficients designated by an instruction from the coefficient setting processing unit 119.

The two coefficients output from the conversion table circuit 116 are respectively input to the input terminals D ₁ and D ₂ of the _two selectors S1 and S2 of the selector circuit 117. Clock signals are inputted in opposite phases to the clock terminals of the selectors S1 and S2. Therefore, the selectors S1 and S2 switch the above-described two coefficients between the first half and the second half of the clock signal cycle and alternately output them.

  The outputs of the selectors S1 and S2 are input to the two input terminals G1 and G2 of the digital / analog converter 118. The digital / analog conversion unit 118 generates control signals cont1 + and cont1- according to the coefficient input to the input terminal G1. The coefficient input to the input terminal G2 of the digital / analog conversion unit 118 is converted into control signals cont2 + and cont2-. The digital / analog converter 118 generates a bias current that realizes a gain corresponding to the coefficient input by the variable gain amplifier shown in FIG. 3, for example, as the control signals cont1 +, cont1- and the control signals cont2 +, cont2-. be able to.

  Also, the coefficient setting processing unit 119 is prepared for the conversion table circuit 116 based on, for example, the characteristics of a high-speed interface including the receiving device including the input equalizer unit illustrated in FIG. One of a set of coefficients can be selected.

  On the other hand, for example, in the test stage of the high-speed interface, the coefficient set selected from the conversion table circuit 116 may be optimized based on the result of evaluating the received signal when the receiving device receives the training signal. Is possible. As an evaluation result of the received signal at this time, for example, an error signal error used for controlling the waveform equalization process can be used in the equalizer 103 shown in FIG.

  FIG. 7 shows an embodiment of the equalizer circuit. The equalizer circuit shown in FIG. 7 is provided corresponding to each signal parallelized by the parallelization unit 102. That is, the equalizer 103 shown in FIG. 1 includes an equalizer circuit corresponding to all the parallel signals.

  The equalizer circuit shown in FIG. 7 includes j flip-flops (FF) and variable amplifiers corresponding to these flip-flops. Then, based on the error signal error corresponding to the difference between the addition result of the output of these variable amplifiers and the input signal din and the result obtained by binarizing the input signal din, each variable is selected by the coefficient selection circuit. The gain of the amplifier is controlled. In the equalizer circuit shown in FIG. 7, the number of taps can be reduced as compared with the conventional equalizer circuit that performs the waveform shaping process using only the equalizer after parallelization.

  Next, a method for controlling the gain of the variable gain amplifier provided in the input equalizer unit using the error signal error will be described.

  FIG. 8 is a flowchart showing the gain setting operation. In the example shown in FIG. 8, a plurality of sets of coefficients are prepared in the conversion table circuit 116 in advance, and one of the sets is selected. Thereafter, the coefficients of the selected set are fixedly set. Input to the selector circuit 117.

  The coefficient setting processing unit 119 starts coefficient selection processing in response to the input of the training signal (step 301). Then, the coefficient setting processing unit 119 sequentially selects a plurality of sets of coefficients prepared in the conversion table circuit 116 (step 302), and a control signal corresponding to the selected coefficient set is shown in FIG. This is used for the gain switching control of the two amplifiers P1 and P2.

For example, when a set of coefficients α ₁ and β ₁ is selected, gains C ₀₁ and C ₁₁ corresponding to the coefficients α ₁ and β ₁ are alternately set in the two amplifiers P 1 and P 2, and FIG. Waveform shaping processing as described with reference to this is performed.

  The waveform shaping processing result is input to the equalizer 103 via the analog / digital conversion unit 101 and the parallelizing unit 102. In response to this, the error signal error is calculated by an equalizer circuit as shown in FIG. 7 (step 303).

  The coefficient setting processing unit 119 repeats the process of selecting all coefficient sets prepared in the conversion table 116, and calculates an error signal error corresponding to these coefficient sets. When error signals error are obtained for all coefficient sets, the process proceeds to step 305 as an affirmative determination in step 304.

  In step 305, for example, the coefficient setting processing unit 119 detects a coefficient set given an error signal error indicating the minimum error, and sets the conversion table circuit 116 so as to select the coefficient set in a fixed manner. Exit.

  In this way, the input equalizer unit shown in FIG. 4 is optimized so as to switch the gains of the two amplifiers P1 and P2 shown in FIG. 4 according to the optimum coefficient set selected from the plurality of coefficient sets. be able to.

Such optimization control can also be applied to the input equalizer 110 as shown in FIG. For example, the combination of gains of AMP _{1 to} AMP _{n + 1} provided in the variable amplifier 112 can be changed, and the optimum combination of gains can be searched based on the error signal obtained by the equalizer 103 at that time. .

  It is also possible to operate three or more sample-and-hold units in synchronization with clock signals having different phases, and switch and control the gain of the variable amplifier corresponding to each sample-and-hold unit based on these clock signals. is there. As a result, a waveform shaping function corresponding to an equalizer having three or more taps can be realized.

On the other hand, as a variable amplifier provided in the input equalizer unit, an amplifier provided in the analog / digital conversion unit 102 may be used. Hereinafter, an embodiment in which the amplifier provided in the analog / digital conversion unit 102 is made into a variable amplifier will be described.
(Embodiment 3)
FIG. 9 shows another embodiment of the receiving device. Note that among the constituent elements shown in FIG. 9, the same constituent elements as those shown in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

The receiving apparatus shown in FIG. 9 includes two flash analog / digital converters (A / D) 210 ₁ and 210 ₂ corresponding to the _two sample and hold units 115 ₁ and 115 ₂ . These analog / digital converters 210 ₁ and 210 _{2 each} include a comparator that compares the input signal voltage with a reference voltage of ^2k steps. The outputs of these comparators are binarized by 2 ^k slicers. Also, the coders 211 ₁ and 211 ₂ provided in the analog / digital conversion units 210 ₁ and 210 ₂ respectively correspond to the input signal voltage based on the output signals of 2 ^k slicers provided therein. Bit digital data is output.

In the analog / digital converters 210 ₁ and 210 ₂ shown in FIG. 9, the Gilbert cell variable gain amplifier shown in FIG. 3 is used as an amplifier related to amplification of input signal voltages included in 2 ^k comparators. be able to. Then, the ^{2 k-number} of the variable gain amplifier provided to an analog / digital converter 210 _1, above control signal cont1 +, to enter the cont1- as a bias current. Similarly, the ^{2 k-number} of the variable gain amplifier provided to an analog / digital converter 210 _2, above control signals cont2 +, cont2- is input as a bias current.

As a result, the gains of these variable gain amplifiers provided in the analog / digital conversion units 210 ₁ and 210 ₂ are alternately switched in synchronization with the clock signal as described with reference to FIG. Therefore, the k-bit digital data obtained by the analog / digital conversion units 210 ₁ and 210 ₂ is converted into the input signal voltage values held in the corresponding sample hold units 115 ₁ and 115 ₂ in the first half and second half of the clock cycle. It is a value with different weighting.

The demultiplexer (DEMUX) 212 illustrated in FIG. 9 divides each bit of the k-bit digital data obtained by the analog / digital conversion units 210 ₁ and 210 ₂ into n parts for parallelization. The demultiplexer 212 corresponds to the parallelizing unit 102 shown in FIG.

Further, the equalizer 213 shown in FIG. 9 adds one line of parallel data obtained by the two analog / digital conversion units 210 ₁ and 210 ₂ to each other, thereby shaping one line of parallel data. Is generated. The equalizer 213 corresponds to the equalizer 103 shown in FIG.

The equalizer 213 may, for example, the signal and corresponding signal included in the parallel data lines corresponding to the analog / digital converter 210 ₂ included in the parallel data lines corresponding to the analog / digital converter 210 ₁ Is included.

  FIG. 10 shows another embodiment of the equalizer circuit. Note that, among the components shown in FIG. 10, components equivalent to those shown in FIG. 9 are denoted by the same reference numerals, and description thereof is omitted.

The equalizer 213 shown in FIG. 10 has the number of equalizer circuits 214 _{11 to} 214 corresponding to the product of the number of bits k of the digital data obtained by the analog / digital converters 210 ₁ and 210 ₂ and the number n of demultiplexers in parallel. _kn . These equalizer circuits 214 _{11 to} 214 _kn have the same configuration. 10 shows the internal structure only for the equalizer circuit 214 _11, it is omitted internal illustration of another equalizer circuit 214.

The equalizer circuit 214 ₁₁ shown in FIG. 10 includes an adder that adds two input signals, a slicer that binarizes the output of the adder, and a subtractor that calculates an error signal from signals before and after the slicer. And. In the example shown in FIG. 10, the two input signals input to each equalizer circuit 214 are shown separately with reference numerals din (0) and din (180). In the example of FIG. 10, an input signal code din (0) is attached, is one of the parallel signal digital data generated by the analog / digital converter 210 _2. Then, the input signal code din (180) is attached, is one of the parallel signal digital data generated by the analog / digital converter 210 _1.

  As described above, in the receiving apparatus configured as illustrated in FIGS. 9 and 10, a function corresponding to the adder 114 of the input equalizer unit 110 is performed by the adder included in the equalizer 213 arranged after the demultiplexer 212. Is fulfilled. Further, the two input signals added by the adder of the equalizer circuit 214 shown in FIG. 10 correspond to signals fed back through the flip-flop and the variable amplifier in the equalizer circuit shown in FIG.

  Therefore, the equalizer circuit 214 shown in FIG. 10 does not require a feedback loop including a flip-flop and a variable amplifier as provided in the equalizer circuit shown in FIG. As a result, the amount of hardware provided for realizing the equalization function in the receiving apparatus can be greatly reduced.

The digital data weighted by the analog / digital conversion units 210 ₁ and 210 ₂ may be added and then subjected to parallel processing by the parallel processing unit 102.

  FIG. 11 shows another embodiment of the receiving device. 11 that are the same as those shown in FIGS. 1 and 9 are given the same reference numerals, and descriptions thereof are omitted.

In the configuration shown in FIG. 11, the digital data obtained by the analog / digital converters 210 ₁ and 210 ₂ are added by the adder 114. Then, the addition result by the adder 114 is parallelized by the parallelizing unit 102 and is subjected to waveform shaping processing by the equalizer 103.

100 Transmitters 101, 210 ₁ , 210 ₂ Analog / digital converter (A / D)
102 Parallelizing units 103, 213 Equalizer 110 Input equalizer unit 111 Delay adding unit 112 Variable amplifier 113 Gain control unit 114 Adder 115 ₁ , 115 ₂ Sample hold unit 116 Conversion table circuit 117 Selector circuit 118 Digital / analog conversion unit (D / A)
119 Coefficient setting processing units 211 ₁ , 211 ₂ coder 212 demultiplexer (DEMUX)
214 _{11 to} 214 _kn equalizer circuit

Claims (5)

An analog / digital converter that converts a voltage change of an input analog signal into a digital data sequence;
A parallelization unit for parallelizing the digital data series;
An equalizer for performing waveform generation processing on the parallel digital signals;
A delay adding unit for branching the analog signal into a plurality of systems and giving different delays to the analog signals of the plurality of systems;
A receiving apparatus comprising: a gain control unit that controls a gain of the amplifier by a bias current of the amplifier to which an analog signal of each system delayed by the delay adding unit is input. The receiving device according to claim 1,
The delay adding unit includes:
A branching section for branching the analog signal into N systems;
A sample-and-hold unit that samples and holds the N-system analog signals according to a clock signal having a corresponding phase, and
The gain control unit applies the amplifier gain of the N systems to each input by temporally changing the bias current of the amplifier to which the output of the N system sample and hold units is input based on the clock signal. A receiving device, wherein switching control is performed so as to correspond to a given delay amount. The receiving device according to claim 1,
The analog / digital conversion unit includes comparators that respectively compare with a predetermined number of reference voltages corresponding to the analog signals of the plurality of systems.
The gain control unit controls a gain of an amplifier included in a comparator corresponding to the analog signal of each system. The receiving apparatus according to claim 3,
The analog / digital converter outputs digital data corresponding to the analog signals of the plurality of systems,
The receiving device, wherein the equalizer unit includes an adding unit that adds digital signals representing digital data corresponding to the analog signals of the plurality of systems and outputs the addition result as an equalization result. The receiving device according to claim 1,
Provided with an input amplifier that amplifies a plurality of analog signals that are pre-arranged on the input side of the analog / digital conversion unit and branched by the delay adding unit,
The gain control unit controls gains of the plurality of input amplifiers.

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