KR20150025571A - A/d conversion apparatus with adaptive reference and data receiver including it - Google Patents

A/d conversion apparatus with adaptive reference and data receiver including it Download PDF

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KR20150025571A
KR20150025571A KR20130103217A KR20130103217A KR20150025571A KR 20150025571 A KR20150025571 A KR 20150025571A KR 20130103217 A KR20130103217 A KR 20130103217A KR 20130103217 A KR20130103217 A KR 20130103217A KR 20150025571 A KR20150025571 A KR 20150025571A
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signal
reference voltage
output
voltage level
value
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KR102032325B1 (en
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전세준
배현민
이현배
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에스케이하이닉스 주식회사
한국과학기술원
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging
    • H03M1/181—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
    • H03M1/182—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values the feedback signal controlling the reference levels of the analogue/digital converter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values

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  • Theoretical Computer Science (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)

Abstract

According to the invention, a bit error rate can be directly optimized by adaptively allocating reference levels for analog to digital converters (ADCs), and the bit error rate can be optimized by allocating reference levels for the ADCs allocated in a plurality of equalizers to be independent of one another. The ADC device according to the present invention comprises a clock generator which uses an external clock applied from outside to output first and second clocks with difference phases; a sampling holding unit which performs sampling at first and second phases within a half period of a distorted digital input signal received from outside, and holds the sampled result; a first input stage equalizer which is configured to be synchronized with the first clock whose state is shifted at the first phase, receive a first hold signal held at the first phase, and reduce an error between a digital signal outputted from a transmitter and an equalization signal by using an applied weight; a second input stage equalizer which is configured to be synchronized with the second clock whose state is shifted at the second phase, receive a second hold signal held at the second phase, and reduce an error between a digital signal outputted from the transmitter and the equalization signal by using an applied weight; an error generating unit which sums outputs from the first and second stage equalizers to generate the equalization signal, and subtracts the equalization signal from the digital signal outputted from the transmitter to output an error signal; and a slicer which slices the equalization signal to generate a sliced output signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion apparatus having an adaptive reference value, and a data receiving apparatus including the A / D conversion apparatus. 2. Description of the Related Art [0002]

The present invention relates to a data receiving apparatus, and more particularly, to an A / D converting apparatus for converting an analog signal input to a data receiving apparatus into a digital signal.

As the traffic volume explosively increases, the data rate in the communication system is increasing. This increases the operating frequency on the communication circuit and increases the skin effect and dielectric loss. To compensate for this, the size of the analog equalizer is increased, but the stability of the analog equalizer is not better than the stability of the digital equalizer.

In addition, efforts are being made to increase the spectral efficiency within a limited bandwidth through complicated modulation such as pulse amplitude modulation (PAM4), PAM8, and PAM16 because the bandwidth per pin of an integrated circuit interface is limited in a communication system.

In addition, since an A / D converter is required in such a communication system, a receiver based on an ADC-equalizer has recently attracted attention.

On the other hand, the bit error rate (BER) is a final performance index of the communication system and directly affects the accuracy of the system. That is, efficiency is improved by using FFE (Feed Forward Equalizer) and DFE (Decision Forward Equalizer). However, this method has a limitation in that it is an indirect method that directly correlates with BER but can not optimize BER directly.

The present invention provides an A / D conversion device capable of directly optimizing a bit error rate by adaptively arranging an ADC reference level and a data receiving device including the same.

Also, the present invention provides an A / D conversion device capable of optimizing a bit error rate by disposing reference voltage levels of ADCs arranged in a plurality of equalizers independently of each other, and a data reception device including the A / D conversion device.

The A / D converter according to the present invention includes: a clock generator for outputting first and second clocks having the same period and different phases using an external clock applied from the outside; A sample hold section for sampling and holding the first and second phases, respectively, in a half period of a distorted digital input signal received from the outside; A first hold signal that is held in the first phase in synchronization with a first clock that transits from the first phase to the first phase is received, and an error between the digital signal output from the transmitter and the equalized signal is reduced Gt; equalizer; And a second hold signal synchronized with a second clock that transitions from the second phase to the second phase and held at the second phase, and calculates an error rate between the digital signal output from the transmitter and the equalization signal using the weight A second input stage equalizer configured to reduce the second input stage equalizer; An error generator for generating the equalization signal by adding the outputs of the first and second input stage equalizers, subtracting the equalization signal from the digital signal output from the transmitter, and outputting an error signal; And a slicer for slicing the equalization signal to generate a sliced output signal.

Advantageously, the first input stage equalizer and the second input stage equalizer operate independently of each other.

The apparatus may further include an output stage equalizer configured to receive the sliced output signal and to reduce an error rate between the output signal and the digital signal output from the transmitter using the weight, And adds the output of the output stage equalizer to the signal.

Preferably, the first input stage equalizer adjusts the reference voltage level using the reference voltage level adjusting signal in the analog state, compares the reference voltage level with the hold signal, and outputs a representative value selecting signal, ; A first encoder for outputting a plurality of representative values using a representative value adjustment signal, and being controlled by the representative value selection signal to select any one of the plurality of representative values; A first weight adjusting unit for generating a reference voltage level adjusting signal of the representative value adjusting signal and the digital value using the weight value; And a first DAC converting a reference voltage level adjustment signal of the digital value into a reference voltage level adjustment signal of an analog value.

Preferably, the first encoder includes: a code conversion unit for outputting a plurality of updated representative values using the representative value adjustment signal; And a multiplexer controlled by the representative value selection signal to select any one of the plurality of updated representative values.

Preferably, the first weight adjusting unit includes: a unit delay element connected in series so as to sequentially delay the representative value output from the first encoder; A variable weight unit which multiplies a representative value involved in delay at the input and output ends of the unit delay elements by using the weights and a weight that varies independently of each other; And an adding unit for adding the output of the variable weight unit which is matched and output.

Preferably, the first weight adjusting unit outputs the reference value adjusting signal, updates the reference value, and outputs the reference voltage level adjusting signal to adjust the reference voltage level of the first ADC to a median value of a neighboring reference value do.

Preferably, the first input stage equalizer adjusts the reference voltage level using the reference voltage level adjusting signal in the analog state, compares the reference voltage level with the hold signal, and outputs a representative value selecting signal, ; A first encoder controlled by a representative value selection signal to select any one of the plurality of representative values; A first weight adjuster for generating a plurality of reference values and a reference voltage level adjusting signal of a digital value using the weight; And a first DAC converting a reference voltage level adjustment signal of the digital value into a reference voltage level adjustment signal of an analog value.

The present invention can directly optimize the bit error rate by adaptively arranging the ADC reference level and optimize the bit error rate by disposing the reference voltage levels of the ADCs disposed in the plurality of equalizers independently of each other.

1 is a block diagram of an A / D converter according to an embodiment of the present invention;
2 is a sampling timing diagram for an input signal according to an embodiment of the present invention,
3 is a block diagram of a first input stage equalizer 120 according to an embodiment of the present invention,
4 is a detailed configuration diagram of an ADC and an encoder according to an embodiment of the present invention,
5 is a diagram illustrating an example of a representative value adjustment according to an exemplary embodiment of the present invention,
6 is a block diagram of an output stage equalizer 140 according to an embodiment of the present invention.
FIG. 7A is an exemplary diagram illustrating an A / D conversion device according to an exemplary embodiment of the present invention,
7B is an exemplary diagram illustrating an A / D conversion device according to another embodiment of the present invention, and FIG.
FIG. 8 is a diagram illustrating an A / D converter according to another embodiment of the present invention. Referring to FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, terms and words used in the present specification and claims should not be construed as limited to ordinary or dictionary terms, and the inventor should appropriately interpret the concepts of the terms appropriately It should be interpreted in accordance with the meaning and concept consistent with the technical idea of the present invention based on the principle that it can be defined. Therefore, the embodiments described in this specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention and do not represent all the technical ideas of the present invention. Therefore, It is to be understood that equivalents and modifications are possible.

1 is a block diagram of an A / D converter according to an embodiment of the present invention. The A / D converter includes a sample hold unit 110, a first input stage equalizer 120, a second input stage equalizer 130, an output stage equalizer 140, A weight generating unit 150, a slicer 160, and a clock generator 170. [

Although not shown, the transmitter outputs a digital signal of +1 or -1, but the digital signal output from the transmitter as it passes through the channel disposed between the transmitter and the receiver is distorted to the analog state.

Referring to the sampling timing diagram of FIG. 2, the sample hold section 110 receives a first phase (" 1 ") signal for half a period of the distorted digital input signal T received from the transmitter via the channel

Figure pat00001
1) and the second phase (
Figure pat00002
2), respectively.

The first input stage equalizer 120 includes a first phase

Figure pat00003
1), a first clock (CLK_
Figure pat00004
1) < / RTI >
Figure pat00005
(D_Tx) output from the transmitter using an applied weight (= error signal e [n]) * step size (u)) and an equalization signal 0.0 > Y) < / RTI > Here, the step size u means the size of a unit step for updating.

The second input stage equalizer 130 operates independently of the first input stage equalizer 120 and the second phase

Figure pat00006
2), the second clock (CLK_
Figure pat00007
2) < / RTI >
Figure pat00008
2 and is configured to reduce an error between the digital signal D_Tx output from the transmitter and the equalization signal Y using an applied weight. Here, it is assumed that there is no delay time between the sample hold unit 110 and the first and second input stage equalizers 120 and 130.

The output stage equalizer 140 is configured to receive the output signal A and to reduce the error between the digital signal D_Tx output from the transmitter and the equalization signal Y using the applied weights. Here, a digital signal (D_Tx) output from the transmitter passes through a channel disposed between the transmitter and the receiver, causing a delay, which can be synchronized using a delay locked loop (not shown) And will be omitted because it is self-evident to a person having ordinary skill in the art.

The weight generator 150 includes a first adder 151 for adding the outputs of the input first and second input stage equalizers, and an adder 151 for adding the output of the first adder and the output of the output stage equalizer to obtain an equalization signal Y [n] A subtractor 155 for subtracting the equalized signal Y [n] from the digital signal D_Tx [n] output from the transmitter and outputting an error signal e [n] And a multiplier 157 for multiplying the error signal e [n] by the step size u.

Figure pat00009

The slicer 160 slices the equalization signal Y [n] to generate an output signal A [n]. Here, slicing the equalization signal Y [n] means outputting +1 if the equalization signal Y [n] is greater than 0, and decreasing -1 if the equalization signal Y [n] .

The clock generator 170 receives the external clock CLK of a predetermined period from the outside and outputs the first and second clocks CLK_

Figure pat00010
1, CLK_
Figure pat00011
2).

FIG. 3 is a block diagram of a first input stage equalizer 120 according to an embodiment of the present invention. The first input stage equalizer 120 includes a first ADC 310, a first encoder 320, (330), and a first DAC (340). 4 is a detailed configuration diagram of a first ADC 310 and a first encoder 320 according to an embodiment of the present invention.

The first ADC 310 receives the first clock CLK_

Figure pat00012
The reference DAC 240 adjusts the reference voltage level using the reference voltage level adjustment signal refa in the analog state and outputs the hold signal TH as the reference voltage levels ref1, ref2, ref3) and outputs a representative value selection signal in the form of a thermometer code. That is, the first ADC 310 outputs a representative value selection signal of a thermometer code of one of 000, 001, 011, and 111.

The first DAC 340 converts the reference voltage level adjustment signal refd in the digital state into a reference voltage level adjustment signal refa in the analog state and outputs the reference voltage level adjustment signal refd.

According to an embodiment of the present invention, the first encoder 320 includes a code conversion unit 321 and a multiplexer 323, and the code conversion unit 321 uses the representative value adjustment signal Cont_code of Equation (2) And the multiplexer 323 outputs the four updated representative values c [n + 1], which are controlled by the representative value selection signal output from the first ADC 310, And outputs the selected one.

Figure pat00013

Figure pat00014

Here, uc is an arbitrary value in the size of a unit step for updating a representative value, and I is an indicator function, and becomes 1 only when an error occurs.

According to another embodiment of the present invention, the first weight adjusting unit 330 outputs the four updated representative values as shown in Equation (3) using the representative value adjusting signal Cont_code. The first encoder 320 including the multiplexer 323 is controlled by the representative value selection signal output from the first ADC 310 and outputs the four updated representative values c [n + 1 ]) And outputs it.

The first weight adjusting unit 330 includes a unit delay unit 331, a variable weight unit 333, and an adding unit 335.

The unit delay unit 331 is composed of unit delay elements connected in series so as to sequentially delay the inputted representative value. The variable weight unit 333 multiplies all the representative values to be delayed or delayed in the unit delay unit 331 by a weight that is variable by using a weight. The addition section 335 adds the output of the variable weight section 333.

The first weight adjusting unit 330 adjusts the reference value adjusting signal Cont_code and the reference voltage level of the digital state by using the weight value applied from the weight generating unit 150 and the representative value outputted from the first encoder 320 within one cycle, And generates and outputs a signal refd.

First, the first weight adjusting unit 330 outputs a representative value adjusting signal cont_code and the first encoder 320 updates the representative value code using the representative value adjusting signal cont_code, as shown in Equation (3) Adapt the code.

Secondarily, the first weight adjusting unit 330 outputs the reference voltage level adjusting signal refd so as to adjust the levels of the reference voltages ref1, ref2 and ref3 of the first ADC 310 to the intermediate values of the adjacent neighboring reference values (See FIG. 5).

Figure pat00015

On the other hand, the equalizer weight W in the first weight adjusting unit 330 is equal to the error e [n] and the representative value X (n) to be delayed or delayed in the unit delay unit 331, as shown in Equations 5 and 6 (n [n]: X1, X2, ...) and is updated in a direction decreasing the error e [n] between the transmission signal D_Tx and the equalization signal Y. Here, X1 is a representative value (code) input to the unit delay unit 331, X2 is a representative value in which X1 is delayed by one time unit time, and X3 is a representative value delayed by twice the unit time.

Figure pat00016

Figure pat00017

Here, uw is the size of the unit step for updating the weight and is an arbitrary value.

The cost function for updating the representative code in the first weight adjuster 330 is expressed by Equation 7 using the error e [n] and a series of input window weight W [j ]).

Figure pat00018

Meanwhile, according to an embodiment of the present invention, since the output of the code conversion unit 321 is 2 bits, the first ADC 310 uses three comparators, but the scope of the present invention is not limited thereto. For example, if the output of the code conversion unit is 3 bits, eight comparators may be used in the first ADC.

The digital block, such as the weight adjuster, can be synthesized using Synopsys' IC compiler program, Cadence's NC-sim program or NC-verilog program, which is familiar to those skilled in the art, A description thereof will be omitted.

5 is a diagram illustrating an example of a representative value adjustment according to an exemplary embodiment of the present invention.

When the third reference value code2_old is adjusted in the direction of reducing the error rate of the output signal A with respect to the transmission signal D_Tx and adjusted to the third new reference value code2_new, The third reference voltage level ref3 is adjusted to an intermediate value between the third new reference value code2_new and the fourth reference value code3 and the third reference voltage level ref3 is adjusted to an intermediate value between the reference value code1 and the third new reference value code2_new. At this time, it is assumed that the first reference value code 0, the second reference value code 1, and the fourth reference value code 3 do not change.

The second input stage equalizer 130 includes a second ADC, a second encoder, a second weight adjuster, and a second DAC, similar to the first input stage equalizer 120.

According to an embodiment of the present invention, the coefficients w1, w2, ... in the first weight adjusting unit 330 and the coefficients w21, w22, ... in the second weight adjusting unit are matched to the same value .

According to another embodiment of the present invention, the coefficients w1, w2, ... in the first weight adjusting unit 330 and the coefficients w21, w22, ... in the second weight adjusting unit are mutually independent values And the inner coefficients may be mutually independent. For example, w1 and w21 are mutually independent, and w1 and w2 may also be mutually independent. Accordingly, the arrangement of the reference voltage level of the ADC in the first input stage equalizer and the arrangement of the reference voltage level of the ADC in the second input stage equalizer are independently performed to optimize the BER (Bit Error Rate).

FIG. 6 is a block diagram of an output stage equalizer 140 according to an embodiment of the present invention. Referring to FIG. 6, an error rate between a digital signal D_Tx output from a transmitter and an equalization signal Y using an applied weight is reduced . The coefficients w31, w32,... In the weight adjusting section of the output stage equalizer are independent of the coefficients in the first and second weight adjusting sections, and the coefficients in the inner stages are mutually independent.

The A / D converter 100 according to the present invention can be disposed between the data transmission device 710 and the data reception device 720, as shown in FIG. 7A. Alternatively, as shown in FIG. 7B, the A / D converter 100 according to the present invention can be disposed in the data receiving device 725. [

The data receiving apparatus may be a chip, a card, an MCU, a DRAM, a flash memory, a backplane link, a serial interface, an Ethernet Communications, data centers, and the like.

8, according to another embodiment of the present invention, a plurality of A / D conversion apparatuses 100 # 1, 100 # 2, and 100 # are provided between the data transmission apparatus 710 and the data reception apparatus 720, ..., 100 # n) can be connected in parallel to process data.

7 and 8, the data transmission apparatus 710 outputs a digital signal, and the digital signal output from the data transmission apparatus 710 is converted into an analog signal as it passes through the channel, It will be apparent to those skilled in the art that a detailed description thereof will be omitted.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It is to be understood that various changes and modifications may be made without departing from the scope of the appended claims.

110: Sample hold section
120: first input stage equalizer
130: second input stage equalizer
140: Output stage equalizer
150: Error generating unit
160: Slicer
170: Clock generator
310: first ADC
320: first encoder
330: first weight adjusting section
340: first DAC

Claims (13)

A clock generator for outputting a first clock and a second clock having the same period and different phases using an external clock applied from the outside;
A sample hold section for sampling and holding the first and second phases, respectively, in a half period of a distorted digital input signal received from the outside;
A first hold signal that is held in the first phase in synchronization with a first clock that transits from the first phase to the first phase is received, and an error between the digital signal output from the transmitter and the equalized signal is reduced Gt; equalizer;
And a second hold signal synchronized with a second clock that transitions from the second phase to the second phase and held at the second phase, and calculates an error rate between the digital signal output from the transmitter and the equalization signal using the weight A second input stage equalizer configured to reduce the second input stage equalizer;
An error generator for generating the equalization signal by adding the outputs of the first and second input stage equalizers, subtracting the equalization signal from the digital signal output from the transmitter, and outputting an error signal; And
A slicer for slicing the equalization signal to generate a sliced output signal,
And an A / D converter.
The method according to claim 1,
Wherein the first input stage equalizer and the second input stage equalizer operate independently of each other.
3. The method of claim 2,
Further comprising an output stage equalizer configured to receive the sliced output signal and to reduce an error rate between the output signal and the digital signal output from the transmitter using the weight,
Wherein the error generator adds the output of the output stage equalizer to the equalization signal.
The apparatus of claim 3, wherein the first input stage equalizer comprises:
A first ADC that adjusts a reference voltage level using the reference voltage level adjustment signal in the analog state, compares the reference voltage level with the hold signal, and outputs a representative value selection signal;
A first encoder for outputting a plurality of representative values using a representative value adjustment signal, and being controlled by the representative value selection signal to select any one of the plurality of representative values;
A first weight adjusting unit for generating a reference voltage level adjusting signal of the representative value adjusting signal and the digital value using the weight value; And
A first DAC for converting the reference voltage level adjustment signal of the digital value into a reference voltage level adjustment signal of an analog value,
And an A / D converter.
5. The apparatus of claim 4, wherein the first encoder comprises:
A code conversion unit for outputting a plurality of updated representative values using the representative value adjustment signal; And
A multiplexer for selecting one of the plurality of updated representative values controlled by the representative value selection signal,
And an A / D converter.
5. The apparatus of claim 4, wherein the first weight adjusting unit comprises:
A unit delay element serially connected to sequentially delay the representative value output from the first encoder;
A variable weight unit which multiplies a representative value involved in delay at the input and output ends of the unit delay elements by using the weights and a weight that varies independently of each other; And
And an adder for adding the output of the variable weight unit,
And an A / D converter.
5. The apparatus of claim 4, wherein the first weight adjusting unit comprises:
And an A / D converter for outputting the reference voltage adjustment signal to update the reference voltage value, and to adjust the reference voltage level of the first ADC to an intermediate value of a neighboring reference voltage value.
The apparatus of claim 3, wherein the first input stage equalizer comprises:
A first ADC that adjusts a reference voltage level using the reference voltage level adjustment signal in the analog state, compares the reference voltage level with the hold signal, and outputs a representative value selection signal;
A first encoder controlled by a representative value selection signal to select any one of the plurality of representative values;
A first weight adjuster for generating a plurality of reference values and a reference voltage level adjusting signal of a digital value using the weight; And
A first DAC for converting the reference voltage level adjustment signal of the digital value into a reference voltage level adjustment signal of an analog value,
And an A / D converter.
5. The method of claim 4,
Wherein the representative value adjustment signal is calculated using the following equation.
[Mathematical Expression]
Figure pat00019

Where uc is the size of the unit step for updating the reference value, and I is an indicator function, which is 1 when an error occurs.
The data processing system according to any one of claims 1 to 9, wherein the A / D conversion device is disposed between the data transmission device and the data reception device.
A data receiving apparatus comprising an A / D converter according to any one of claims 1 to 9.
The data processing system according to any one of claims 1 to 9, wherein a plurality of A / D conversion devices are arranged in parallel between the data transmission device and the data reception device.
A data receiving apparatus comprising a plurality of A / D converters according to any one of claims 1 to 9 arranged in parallel.
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US11003205B2 (en) 2019-02-04 2021-05-11 Sigmasense, Llc. Receive analog to digital circuit of a low voltage drive circuit data communication system
US10884967B2 (en) 2019-01-14 2021-01-05 Sigmasense, Llc. Low voltage drive circuit with variable frequency characteristics and methods for use therewith
US10915483B2 (en) 2019-01-14 2021-02-09 Sigmasense, Llc. Low voltage drive circuit with variable oscillating characteristics and methods for use therewith
US10826747B2 (en) 2019-01-14 2020-11-03 Sigmasense, Llc. Low voltage drive circuit with digital to digital conversion and methods for use therewith
US11327917B2 (en) 2019-01-14 2022-05-10 Sigmasense, Llc. Low voltage drive circuit and communication system
US10831226B2 (en) 2019-01-14 2020-11-10 Sigmasense, Llc Low voltage drive circuit with variable oscillating frequencies and methods for use therewith
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US11221980B2 (en) 2019-10-31 2022-01-11 Sigmasense, Llc. Low voltage drive circuit operable to convey data via a bus

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KR19990056135A (en) * 1997-12-29 1999-07-15 윤종용 Holdover Control Circuit in Digital Phase Synchronizer

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