JP2011215178A - Electro-optical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the driving capability of a unit shift registers for relief and to make its operation fast with respect to a scanning line-driving circuit of the electro-optical device.SOLUTION: The unit register SRBfor relief is arranged on the opposite side from a normal unit shift register SR across a liquid crystal array portion 10. The unit register SRBfor relief receives a gate line driving signal Gfor a gate line two rows ahead thereof, and activates a gate line driving signal Gk that the unit register SRBfor relief itself outputs, in synchronism with a clock signal for activation two horizontal periods after the activation.

Description

  The present invention relates to defect relief of a scanning line driving circuit used in an electro-optical device such as an image display device or an image sensor, and more particularly, as a scanning line driving circuit configured using only field effect transistors of the same conductivity type. The present invention relates to defective relief of the shift register circuit.

  An electro-optical device including a scanning line driving circuit that scans pixels connected to a scanning line is widely known. For example, in an image display device such as a liquid crystal display device (hereinafter “display device”), a gate line is provided for each pixel row (pixel line) of a display unit (display panel) in which a plurality of pixels are arranged in a matrix (matrix shape). (Scanning lines) are provided, and the display image is updated by sequentially selecting and driving the gate lines in a cycle of one horizontal scanning period of the display signal. As such a gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving pixel lines, that is, gate lines, a multistage shift register that performs a shift operation that makes a round in one frame period of a display signal is used. Can do. Hereinafter, each stage of the multistage shift register is referred to as a “unit shift register”.

  The pixels of the image sensor used in the imaging device are also arranged in a matrix, and the image data captured by scanning these pixels by the gate line driving circuit is extracted. A shift register can also be used for the gate line driver circuit of the imaging device.

  By integrally forming the gate line driver circuit and the pixel over the same substrate, the manufacturing cost of the electro-optical device can be reduced. On the other hand, if the gate line driving circuit and the pixel are integrally formed, when a manufacturing defect occurs in the gate line driving circuit, the defect rate of the electro-optical device increases, which may rather cause an increase in cost. Various proposals have been made to solve this problem (for example, Patent Documents 1 and 2).

JP 2007-140512 A JP 58-219595 A

  In Patent Document 1, a dummy unit shift register (relief unit shift register) for repair is provided in the gate line driving circuit in addition to a regular unit shift register disposed at one end of each gate line, and a regular unit shift is performed. When a malfunction of the register occurs, it is replaced with a repair unit shift register to repair the defect of the electro-optical device.

  In order to enable such replacement, an input wiring for supplying a predetermined input signal to the repair unit shift register and an output signal (gate line drive signal) of the repair unit shift register are supplied to the gate line. It is necessary to provide an output wiring for this purpose. If the unit shift registers for relief are arranged at both ends of the gate line driving circuit, and an operation failure due to a defect occurs in a normal unit shift register located near the center, the wiring length becomes long, and the gate line A delay occurs in the drive signal, which causes a reduction in the operation margin of the gate line drive circuit.

  In Patent Document 2, as shown in FIG. 6, two shift registers (31, 32) are provided so as to sandwich the pixel portion (1). If an operation failure due to a defect occurs in the unit shift register of the first shift register that is one of them, the defective unit shift register is replaced with that of the second shift register that is the other one as shown in FIG. By replacing the corresponding unit shift register stage, defective repair of the electro-optical device is performed.

  FIG. 2 of the same document shows a shift register circuit. Each unit shift register (5) has an output pull-up transistor (8) for activating the output signal (D). This output pull-up transistor (8) is connected between the output terminal of the output signal (D) and the clock terminal to which the clock signal (φ1 or φ2) is supplied, and responds to the activation of the output signal in the previous stage. The gate electrode is turned on when charged. That is, in each unit shift register (5), the output pull-up transistor (8) is turned on in response to the activation of the output signal of the previous stage, and the clock signal (φ1 or φ2) is transmitted to the output terminal, thereby outputting the output signal. (D) is activated.

  Here, there is a defect in the third stage unit shift register of the first shift register (31), and it is repaired by replacing it with the third stage unit shift register of the second shift register (32). think of. In this case, the third-stage output pull-up transistor (8) of the second shift register (relief side) activates the second-stage output signal (D2) of the first shift register (defective side). Is turned on in response to this, and the output signal (D3) of the third stage on the relief side is activated.

Here, since the defective side and the relief side are disposed with the pixel portion (1) interposed therebetween, the second-stage output signal (D2) on the defective side is the second-row gate line (G _2). ) Through the third stage on the rescue side. Therefore, the second-stage output signal (D2) on the defective side is affected by the resistance component and the capacitance component of the gate line (G ₂ ), and the rising speed is slow (the rising speed of the signal is the resistance component of the wiring). Slow in proportion to the time constant based on the product of the sum and the sum of the capacitive components).

  For this reason, the charging speed of the gate electrode of the third-stage output pull-up transistor (8) on the relief side is slow. Therefore, when the shift register is operated at high speed, there is a concern that the gate electrode of the third-stage output pull-up transistor (8) on the rescue side becomes insufficiently charged. Then, in the third stage on the relief side, the on-resistance of the output pull-up transistor (8) becomes high, so that its driving capability (ability to flow current) decreases. This causes a decrease in the rising speed of the third-stage output signal on the relief side, resulting in a decrease in the operation margin of the electro-optical device.

  SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has an object to improve the driving capability of a repair unit shift register and increase the operation speed in a scanning line driving circuit of an electro-optical device. To do.

  The electro-optical device according to the first aspect of the present invention includes a plurality of scanning lines, a plurality of signal lines orthogonal to the plurality of scanning lines, and a vicinity of an intersection of the plurality of scanning lines and the plurality of signal lines. A plurality of formed pixels; a scanning line driving circuit including a normal unit shift register disposed on a first end side of each of the plurality of scanning lines; and a second end side of each of the plurality of scanning lines. An electro-optical device including a relief unit shift register disposed, wherein each of the relief unit shift registers includes a first input terminal, a second input terminal, an output terminal, a clock terminal, and a clock terminal. A first transistor for supplying an input first clock signal to an output terminal; a second transistor for charging a first node connected to a control electrode of the first transistor; and a first transistor input to the first input terminal. input A charging circuit for charging a second node to which the control electrode of the second transistor is connected in response to activation of the signal, and a second input signal input to the second input terminal is connected to the charged second node. And a booster circuit that boosts the voltage in response to activation.

  An electro-optical device according to a second aspect of the present invention includes a plurality of scanning lines, a plurality of signal lines orthogonal to the plurality of scanning lines, and in the vicinity of an intersection of the plurality of scanning lines and the plurality of signal lines. A plurality of formed pixels; a scanning line driving circuit including a normal unit shift register disposed on a first end side of each of the plurality of scanning lines; and a second end side of each of the plurality of scanning lines. An electro-optical device including a relief unit shift register disposed, wherein each of the relief unit shift registers includes a first input terminal, a second input terminal, an output terminal, a clock terminal, and a clock terminal. A first transistor for supplying an input first clock signal to an output terminal; a second transistor connected between the second input terminal and a first node to which a control electrode of the first transistor is connected; First The second node connected to the control electrode of the second transistor is charged according to the activation of the first input signal input to the power terminal, and the second node is charged according to the charging of the first node. A charge / discharge circuit for discharging, and the output terminal and the corresponding scanning line are connected by a defect relief process.

  An electro-optical device according to a third aspect of the present invention includes a plurality of scanning lines, a plurality of signal lines orthogonal to the plurality of scanning lines, and in the vicinity of intersections of the plurality of scanning lines and the plurality of signal lines. A plurality of pixels formed, and a scanning line driving circuit including normal unit shift registers respectively disposed on the first end side of odd lines and the second end side of even lines in the plurality of scanning lines; And a repair unit shift register disposed on each of the second end side of the odd lines and the first end side of the even lines in the plurality of scanning lines.

  According to the electro-optical device according to the first and second aspects of the present invention, in the relief unit shift register, when the control electrode (first node) of the first transistor is charged (precharged) by the second transistor. The control electrode of the second transistor is boosted in response to the activation of the second input signal. Therefore, the second transistor operates in the non-saturated region and can charge the first node at high speed. Therefore, even when the first input signal is input through the scanning line and the first input signal is delayed, the first node can be sufficiently precharged. Therefore, it is possible to prevent the on-resistance of the first transistor from increasing, and it is possible to suppress a decrease in the driving capability of the repair unit shift register.

  According to the shift register circuit of the third aspect of the present invention, since the normal unit shift register and the repair unit shift register are arranged in a staggered manner, the repair unit shift register when repair is performed includes An output signal of an adjacent normal unit shift register can be supplied. Since the input signal of the relief unit shift register does not pass through the scanning line, it is not affected by the resistance component or the capacitance component. Therefore, it is possible to prevent a reduction in driving capability of the repair unit shift register.

It is a schematic block diagram which shows the structure of the liquid crystal display device which concerns on this invention. FIG. 3 is a block diagram showing a configuration of a gate line driving circuit and a relief gate line driving circuit according to the first embodiment. FIG. 3 is a circuit diagram of a unit shift register according to the first embodiment. FIG. 3 is a circuit diagram of a repair unit shift register according to the first embodiment. FIG. 6 is a timing diagram illustrating an operation of the unit shift register according to the first embodiment. 4 is a circuit diagram of a gate line driving circuit and a relief gate line driving circuit according to the first embodiment. FIG. 5 is a circuit diagram of a gate line driving circuit and a relief gate line driving circuit according to a first modification of the first embodiment. FIG. FIG. 10 is a diagram for explaining a defect repairing method in a second modification of the first embodiment. FIG. 10 is a circuit diagram of a gate line driving circuit and a relief gate line driving circuit according to a third modification of the first embodiment. 12 is a circuit diagram of a repair unit shift register according to a fourth modification of the first embodiment. FIG. FIG. 10 is a circuit diagram of a repair unit shift register according to a fifth modification of the first embodiment. 12 is a circuit diagram of a repair unit shift register according to a sixth modification of the first embodiment. FIG. FIG. 16 is a circuit diagram of a repair unit shift register according to a seventh modification example of the first embodiment. FIG. 5 is a block diagram showing a configuration of a gate line driving circuit and a relief gate line driving circuit according to a second embodiment. FIG. 6 is a circuit diagram of a repair unit shift register according to a second embodiment. FIG. 6 is a circuit diagram of a gate line driving circuit and a relief gate line driving circuit according to a second embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, in order to avoid duplication and redundant description, elements having the same or corresponding functions are denoted by the same reference symbols in the respective drawings.

  The transistor used in each embodiment is an insulated gate field effect transistor. In the insulated gate field effect transistor, the electric conductivity between the drain region and the source region in the semiconductor layer is controlled by the electric field in the gate insulating film. As a material of the semiconductor layer in which the drain region and the source region are formed, an organic semiconductor such as polysilicon, amorphous silicon, or pentacene, an oxide semiconductor such as single crystal silicon or IGZO (In-Ga-Zn-O), or the like is used. be able to.

  As is well known, each transistor has a control electrode (gate (electrode) in the narrow sense), one current electrode (drain (electrode) or source (electrode) in the narrow sense)), and the other current electrode (in the narrow sense, the drain (electrode) or the source (electrode)). In a narrow sense, it is an element having at least three electrodes including a source (electrode) or a drain (electrode). The transistor functions as a switching element in which a channel is formed between the drain and the source by applying a predetermined voltage to the gate. The drain and source of the transistor have basically the same structure, and their names are interchanged depending on the applied voltage condition. For example, in the case of an N-type transistor, an electrode having a relatively high potential (hereinafter also referred to as “level”) is called a drain, and a low electrode is called a source (in the case of a P-type transistor, the opposite is true).

  Unless otherwise specified, these transistors may be formed on a semiconductor substrate, or may be a thin film transistor (TFT) formed on an insulating substrate such as glass. The substrate over which the transistor is formed may be a single crystal substrate or an insulating substrate such as SOI, glass, or resin.

  The gate line driving circuit of the present invention is configured using only a single conductivity type transistor. For example, an N-type transistor becomes active (on state, conductive state) when the gate-source voltage becomes H (high) level higher than the threshold voltage of the transistor, and L ( At a low level, it becomes inactive (off state, non-conductive state). Therefore, in a circuit using an N-type transistor, the H level of the signal is “active level” and the L level is “inactive level”. In addition, each node of a circuit configured using an N-type transistor is charged to become an H level, thereby causing a change from an inactive level to an active level, and being discharged to an L level. A change from to inactive level occurs.

  Conversely, a P-type transistor becomes active (on state, conductive state) when the gate-source voltage becomes L level lower than the threshold voltage of the transistor (a negative value with respect to the source). It becomes inactive (OFF state, non-conducting state) at an H level higher than the voltage. Therefore, in a circuit using a P-type transistor, the L level of the signal is “active level” and the H level is “inactive level”. In addition, each node of the circuit configured using the P-type transistor has a charge / discharge relationship opposite to that in the case of the N-type transistor, and is charged to the L level, so that the inactive level changes from the inactive level to the active level. When the change occurs and is discharged to the H level, a change from the active level to the inactive level occurs.

  In this specification, the change from the inactive level to the active level is defined as “pull-up”, and the change from the active level to the inactive level is defined as “pull-down”. That is, in a circuit using an N-type transistor, a change from the L level to the H level is defined as “pull-up”, and a change from the H level to the L level is defined as “pull-down”. A change from the level to the L level is defined as “pull-up”, and a change from the L level to the H level is defined as “pull-down”.

  In this specification, “connection” between two elements, between two nodes, or between one element and one node is a connection through other elements (elements, switches, etc.). In the following description, it is assumed to include a state that is substantially equivalent to a direct connection. For example, even if two elements are connected via a switch, if they can function in the same way as when they are directly connected, the two elements are “connected”. Express.

  In the present invention, clock signals (multiphase clock signals) having different phases are used. In the following, for the sake of simplicity, a certain interval is provided between the active period of one clock signal and the active period of the clock signal to be activated next (Δt in FIG. 5). However, in the present invention, it is sufficient that the active periods of the clock signals do not substantially overlap, and the above-described interval may not be provided. For example, if the activation level is H level, the timing of the fall of one clock signal (change from H level to L level) and the timing of the rise of the clock signal activated next (change from L level to H level) May be simultaneous.

<Embodiment 1>
FIG. 1 is a schematic block diagram showing a configuration of an electro-optical device according to the present invention, and shows an overall configuration of a liquid crystal display device as a representative example of the electro-optical device. Note that the present invention is not limited to application to a liquid crystal display device, and is an electroluminescence (EL), an organic EL, a plasma display, an electronic paper, or the like, which is a display device that converts an electrical signal into light luminance. The present invention is widely applicable to electro-optical devices such as an imaging device (image sensor) that converts light intensity into an electric signal.

  The liquid crystal display device 100 includes a liquid crystal array unit 10, a regular gate line driving circuit (scanning line driving circuit) 30a, a relief gate line driving circuit 30b, and a source driver 40.

The liquid crystal array unit 10 includes a plurality of pixels 15 arranged in a matrix. Each of the pixel rows (hereinafter also referred to as “pixel lines”) is provided with gate lines GL ₁ , GL ₂ ... (Generically referred to as “gate lines GL”), and each pixel row (hereinafter also referred to as “pixel column”). Are respectively provided with data lines DL ₁ , DL ₂ ... (Generic name “data line DL”). FIG. 1 shows the first and second columns of the first row and the pixels 15 of the first and second columns of the second row, and the corresponding gate lines GL ₁ and GL ₂ and data lines DL ₁ , DL ₂ is representatively shown.

  Each pixel 15 includes a pixel switch element 16 provided between the corresponding data line DL and the pixel node Np, a capacitor 17 and a liquid crystal display element 18 connected in parallel between the pixel node Np and the common electrode node Nc. have. The orientation of the liquid crystal in the liquid crystal display element 18 changes according to the voltage difference between the pixel node Np and the common electrode node Nc, and the display brightness of the liquid crystal display element 18 changes in response to this. Thereby, the luminance of each pixel can be controlled by the display voltage transmitted to the pixel node Np via the data line DL and the pixel switch element 16. That is, by applying an intermediate voltage difference between the voltage difference corresponding to the maximum luminance and the voltage difference corresponding to the minimum luminance between the pixel node Np and the common electrode node Nc, the intermediate luminance is reduced. Obtainable. Therefore, gradation brightness can be obtained by setting the display voltage stepwise.

  The gate line driving circuit 30a (scanning line driving circuit) is composed of a multistage shift register, and sequentially selects and activates the gate lines GL based on a predetermined scanning period. The relief gate line drive circuit 30b is disposed on the opposite side of the gate line drive circuit 30a with the liquid crystal array section 10 interposed therebetween, and is a relief that can be replaced with a unit shift register that constitutes a multistage shift register of the gate line drive circuit 30a. The unit shift register is used. Each of the relief unit shift registers of the relief gate line drive circuit 30b has the ability to drive the gate line GL in the same manner as the unit shift register of the gate line drive circuit 30a.

  The gate electrodes of the pixel switch elements 16 are connected to the corresponding gate lines GL. While a specific gate line GL is selected (activated), in each pixel connected thereto, the pixel switch element 16 becomes conductive, and the pixel node Np is connected to the corresponding data line DL. The display voltage transmitted to the pixel node Np is held by the capacitor 17. In general, the pixel switch element 16 is composed of a TFT formed on the same insulator substrate (glass substrate, resin substrate, etc.) as the liquid crystal display element 18.

The source driver 40 is for outputting a display voltage, which is set stepwise by a display signal SIG that is an N-bit digital signal, to the data line DL. Here, as an example, the display signal SIG is a 6-bit signal and is composed of display signal bits DB0 to DB5. Based on the 6-bit display signal SIG, 2 ⁶ = 64 gradation display is possible in each pixel. Furthermore, if one color display unit is formed by three pixels of R (Red), G (Green), and B (Blue), approximately 260,000 colors can be displayed.

  As shown in FIG. 1, the source driver 40 includes a shift register 50, data latch circuits 52 and 54, a gradation voltage generation circuit 60, a decode circuit 70, and an analog amplifier 80.

  In the display signal SIG, display signal bits DB0 to DB5 corresponding to the display luminance of each pixel 15 are serially generated. In other words, the display signal bits DB0 to DB5 at each timing indicate the display luminance in any one pixel 15 in the liquid crystal array unit 10.

  The shift register 50 instructs the data latch circuit 52 to take in the display signal bits DB0 to DB5 at a timing synchronized with the cycle at which the setting of the display signal SIG is switched. The data latch circuit 52 sequentially takes in the serially generated display signal SIG and holds the display signal SIG for one pixel line.

  The latch signal LT input to the data latch circuit 54 is activated at the timing when the display signal SIG for one pixel line is taken into the data latch circuit 52. In response thereto, the data latch circuit 54 takes in the display signal SIG for one pixel line held in the data latch circuit 52 at that time.

  The gradation voltage generation circuit 60 is composed of 63 voltage dividing resistors connected in series between the high voltage VDH and the low voltage VDL, and generates 64 gradation voltages V1 to V64, respectively.

The decode circuit 70 decodes the display signal SIG held in the data latch circuit 54 and outputs a voltage to each decode output node Nd ₁ , Nd ₂ ... (Generic name “decode output node Nd”) based on the decode result. Are selected from the gradation voltages V1 to V64 and output.

As a result, at the decode output node Nd, a display voltage (one of the gradation voltages V1 to V64) corresponding to the display signal SIG for one pixel line held in the data latch circuit 54 is simultaneously (in parallel). ) Is output. In FIG. 1, the decode output nodes Nd ₁ and Nd ₂ corresponding to the data lines DL ₁ and DL ₂ in the first column and the second column are representatively shown.

The analog amplifier 80 amplifies the analog voltage corresponding to each display voltage output from the decode circuit 70 to the decode output nodes Nd ₁ , Nd ₂ ... And outputs them to the data lines DL ₁ , DL ₂ .

The source driver 40 repeatedly outputs a display voltage corresponding to a series of display signals SIG to the data lines DL for each pixel line based on a predetermined scanning cycle, and the gate line driving circuit 30a is synchronized with the scanning cycle. By sequentially driving the gate lines GL ₁ , GL ₂ ..., An image is displayed on the liquid crystal array unit 10 based on the display signal SIG.

  1 illustrates the configuration of the liquid crystal display device 100 in which the gate line driving circuit 30a, the relief gate line driving circuit 30b, and the source driver 40 are integrally formed with the liquid crystal array unit 10, but the gate line driving is illustrated. The circuit 30a, the relief gate line driving circuit 30b, and the liquid crystal array unit 10 may be integrally formed, and the source driver 40 may be provided as an external circuit of the liquid crystal array unit 10.

FIG. 2 is a diagram showing the configuration of the gate line drive circuit 30a and the relief gate line drive circuit 30b according to the first embodiment. The gate line driving circuit 30a includes a multi-stage shift register composed of a plurality of unit shift registers SR ₁ , SR ₂ , SR ₃ , SR ₄ ... Connected in cascade (cascade connection) (hereinafter referred to as unit shift register SR). ₁ , SR ₂ ... Are collectively referred to as “unit shift register SR”). The unit shift register SR is provided for each pixel line, that is, for each gate line GL.

The relief gate line driving circuit 30b is formed from a multistage shift register composed of a plurality of cascaded relief unit shift registers SRB ₁ , SRB ₂ , SRB ₃ , SRB ₄ (shown by bold lines in FIG. 2). (Hereinafter, the shift register circuits SRB ₁ , SRB ₂ ... Are collectively referred to as “relief unit shift register SRB”). Each relief unit shift register SRB is provided at the opposite end to which the unit shift register SR is connected to each gate line GL.

  However, when the unit shift register SR of the gate line driving circuit 30a is not defective, the output terminal OUT of the repair gate line driving circuit 30b and the gate line GL are not electrically connected. Only when a defect is found in the unit shift register SR and defect repair processing is performed to replace it with the repair unit shift register SRB, the repair unit shift register SRB and the gate line GL are electrically connected.

  In the drawings shown below, the positions where the wiring is connected and disconnected by the defect repairing process are indicated by squares. The black squares indicate the locations where the wires are connected (or locations before being cut), and the white squares indicate the locations where the wires are not connected (or locations after being disconnected). For example, in FIG. 2, the output terminal OUT of each unit shift register SR and the gate line GL are connected, but can be disconnected by the defect relief process. Further, the output terminal OUT of each relief unit shift register SRB and the gate line GL are not connected but can be connected by defect relief processing.

  As a method for connecting and disconnecting the wiring in the defect relief processing, wiring processing by laser irradiation can be applied. In wiring processing by laser irradiation, as well as cutting the wiring, if two wirings are preliminarily intersected (intersecting at different heights), the two wirings can be connected by laser irradiation at the intersection. it can.

  The clock signal generator 31 generates three-phase clock signals CLK1, CLK2, and CLK3 having different phases (active periods do not overlap). The clock signals CLK1 to CLK3 are supplied to the unit shift register SR of the gate line drive circuit 30a and the unit shift register SRB for repair of the repair gate line drive circuit 30b. The clock signals CLK1 to CLK3 are controlled by the clock signal generator 31 so that the clock signals CLK1 to CLK3 are activated repeatedly in sequence (that is, in the order of CLK1, CLK2, CLK3, CLK1,...) At a timing synchronized with the scanning cycle of the display device. (See FIG. 5).

  Each unit shift register SR has a first input terminal IN1, a second input terminal IN2, an output terminal OUT, a clock terminal CK, and a reset terminal RST. As shown in FIG. 2, a predetermined one of the clock signals CLK1 to CLK3 is supplied to the clock terminal CK of each unit shift register SR.

Specifically, the clock signal CLK1 is supplied to the unit shift registers SR ₁ , SR ₄ , SR ₇ ... Driving the [3m-2] -th row (m is a natural number, the same applies hereinafter) gate line GL _3m-2. Is done. The clock signal CLK2 is supplied to unit shift registers SR ₂ , SR ₅ , SR ₈ ... Driving the [3m−1] -th gate line GL _3m−1 . The clock signal CLK3 is supplied to the unit shift registers SR ₃ , SR ₆ , SR ₉ ... Driving the [3m] -th gate line GL _3m . Since the clock signals CLK1, CLK2, and CLK3 are repeatedly activated in this order, the clock terminals CK of the shift registers SR ₁ , SR ₂ , SR ₃ ... Are activated in that order.

Since the number of scanning lines of a general display device is not a multiple of 3, three-phase in the shift register controlled by the clock signal CLK1 to CLK3, the n-th row of the unit shift register SR _n of the final line The clock signal supplied to the clock terminal CK varies depending on the number of scanning lines of the display device. In the example of FIG. 2, the clock signal CLK3 is supplied to a clock terminal CK of the unit shift register SR _n.

  A gate line GL is connected to the output terminal OUT of each unit shift register SR. That is, the output signal G of each unit shift register SR becomes a “gate line drive signal” for driving the corresponding gate line GL. Note that the output terminal OUT of the unit shift register SR and the gate line GL can be disconnected by defect repair processing.

The first and second input terminals IN1, IN2 of the unit shift register SR ₁ of the first row, the first and second start pulses respectively SP1, SP2 is input. Both the first and second start pulses SP1 and SP2 are signals activated (become H level) at a timing corresponding to the head of each frame period of the image signal, but the second start pulse SP2 is the first start pulse. The phase is delayed by one horizontal scanning period (1H), that is, by one line scanning period from SP1.

  Therefore, the first start pulse SP1 becomes H level at a timing earlier than the second start pulse SP2, and the second start pulse SP2 is controlled to transition to H level after the first start pulse SP1 returns to L level. . Here, it is assumed that the first start pulse SP1 is in phase with the clock signal CLK2, and the second start pulse SP2 is in phase with the clock signal CLK3 (see FIG. 5).

In the unit shift register SR ₂ of the second row, the second start pulse SP2 described above is inputted to the first input terminal IN1. The second input terminal IN2 is activated between the active period of the second start pulse SP2 and the active period of the clock signal CLK2 input to the clock terminal CK (with a delay of one horizontal scanning period from the second start pulse SP2). The clock signal CLK1 is activated.

In the unit shift registers SR _k (k ≧ 3) on and after the third row, the first input terminal IN1 is connected to the gate line GL _k−2 before two rows. That is, the gate line drive signal G _{k-2 of the} previous row is input to the first input terminal IN1. The second input terminal IN2 is connected between the signal of the first input terminal IN1 (the gate line driving signal G _{k-2 of the} previous two rows), the active period, and the active period of the clock signal input to the clock terminal CK. A clock signal to be activated (that is, in phase with the gate line driving signal G _{k−1 of the} previous row) is supplied. That is, the same clock signal as that of the clock terminal CK of the unit shift register SR _k-1 of the previous row is supplied to the second input terminal IN2.

On the other hand, the gate line drive signal G _{k + 1} after one row is input to the reset terminal RST of the unit shift register SR _k (1 ≦ k ≦ n−1) except the last stage. The reset terminal RST of the unit shift register SR _n of the last stage, and inputs the clock signal CLK1 activating delayed by one horizontal scanning period from the gate line driving signal G _n of the unit shift register SR _n outputs.

Incidentally, if the driven using the clock signal CLK1~CLK3 three-phase gate line driving circuit 30a as in this embodiment, the gate line after two lines to the reset terminal RST of each unit shift register SR _k The drive signal G _{k + 2} may be input. If a four-phase clock signal is used, the gate line drive signal G _{k + 3} after the third row may be input to the reset terminal RST of each unit shift register SR _k .

Although details will be described later, each of the unit shift registers SR _k constituting the gate line driving circuit 30a receives a signal (start pulse SP1, SP2 or the gate line driving signal G _k one row before) input to the first input terminal IN1. _-1 ) is shifted in time by two horizontal scanning periods, and is transmitted to the corresponding gate line GL _{k and} the unit shift register SR _{k + 2} after two rows. The second start pulse SP2 inputted to the unit shift register SR ₂ of the second row, the first start pulse SP1 from one horizontal scanning period the phase to be input to the unit shift register SR ₁ of the first row is delayed As a result, the gate line drive signal G is activated in the order of G ₁ , G ₂ , G ₃ . Thereby, the gate line driving circuit 30a can sequentially activate the gate lines GL ₁ , GL ₂ , GL ₃ , GL ₄ ... At a timing based on a predetermined scanning cycle.

FIG. 3 is a circuit diagram showing a configuration of the unit shift register SR according to the first embodiment. The configuration of each unit shift register SR of the gate line driving circuit 30a are the same: essentially, are representatively shown unit shift register SR _k of the k-th row. The transistors constituting the unit shift register SR _k of this embodiment are all field effect transistors of the same conductivity type, in the form and variations and examples below shall all be N-type TFT.

The unit shift register SR _k shown in FIG. 3 has a low potential side power supply potential (low side power supply potential) in addition to the first and second input terminals IN1 and IN2, the output terminal OUT, the clock terminal CK and the reset terminal RST shown in FIG. The first power supply terminal S1 to which the potential (VSS) is supplied, and the second and third power supply terminals S2 and S3 to which the high potential side power supply potential (high side power supply potential) VDD1 and VDD2 are supplied, respectively.

  The high-side power supply potentials VDD1 and VDD2 may be at the same level. In the following description, the low-side power supply potential VSS is described as the circuit reference potential (VSS = 0 V). However, in actual use, the reference potential is set based on the voltage of data written to the pixel. VDD1 and VDD2 are set to 17V, and the low-side power supply potential VSS is set to -12V.

The unit shift register SR _k includes an output circuit 20, a pull-up drive circuit 21, and a pull-down drive circuit 22. The output circuit 20 activates and deactivates the gate line drive signal G _k output from the unit shift register SR _k , and activates the gate line drive signal G _k during the selection period of the gate line GL _k. Transistor Q1 (output pull-up transistor) to be set to (H level) and transistor Q2 (output pull-down transistor) for maintaining the gate line drive signal G _k in the inactive state (L level) during the non-selection period of the gate line GL _k ).

Transistor Q1 is connected between the output terminal OUT and the clock terminal CK, activate the gate line driving signal G _k by supplying the clock signal input to the clock terminal CK to the output terminal OUT. The transistor Q2 is connected between the output terminal OUT and the first power supply terminal S1, and maintains the gate line driving signal _Gk at an inactive level by discharging the output terminal OUT to the potential VSS. . Here, a node to which the gate (control electrode) of the transistor Q1 is connected is defined as “node N1”, and a node to which the gate of the transistor Q2 is connected is defined as “node N2”.

  A capacitive element C1 is provided between the gate and source of the transistor Q1 (that is, between the output terminal OUT and the node N1). The capacitive element C1 is for capacitively coupling between the output terminal OUT and the node N1 to enhance the boosting effect of the node N1 accompanying the increase in the level of the output terminal OUT. However, the capacitor C1 can be replaced if the gate-channel capacitance of the transistor Q1 is sufficiently large, and may be omitted in such a case.

  Usually, in one semiconductor integrated circuit, the thickness of the insulating film serving as the dielectric layer of the capacitive element is the same as the thickness of the gate insulating film of the transistor, so that the capacitive element is replaced with the gate capacitance of the transistor. Can be replaced with a transistor having the same gate area as the capacitor. Therefore, when the capacitor C1 in FIG. 3 is replaced with the gate-channel capacitance of the transistor Q1, the gate width of the transistor Q1 may be increased by a considerable amount.

Pull-up driving circuit 21 is a circuit for driving the transistor Q1 (output pull-up transistor), a transistor Q1, the selection period of the gate line GL _k is turned on, the non-selection period operates to turn off. Specifically, the pull-up drive circuit 21 receives the gate line drive signal G _k-2 (or the first or second start pulse SP1, SP2) two rows before input to the first input terminal IN1 and the second input. The node N1 (the gate of the transistor Q1) is charged in response to the activation of the clock signal (CLK1, CLK2, or CLK3) input to the input terminal IN2. Then, the node N1 is discharged in response to the activation of the gate line drive signal G _{k + 1} (or the clock signal CLK1) after one row as the reset signal supplied to the reset terminal RST.

  The pull-up drive circuit 21 includes the following transistors Q3 to Q5 and Q8 to Q10. The transistor Q3 is connected between the node N1 and the second power supply terminal S2, and supplies the potential of the second power supply terminal S2 to the node N1. Here, a node to which the gate of the transistor Q3 is connected is defined as “node N3”.

  The transistor Q4 is connected between the node N1 and the first power supply terminal S1, and its gate is connected to the node N2. The transistor Q8 is connected between the node N3 and the second power supply terminal S2, and the gate is connected to the first input terminal IN1.

  The transistor Q10 has a gate connected to the node N3, and two current electrodes (source and drain) both connected to the second input terminal IN2. In a field effect transistor, when a voltage higher than a threshold voltage is applied to a gate electrode, the drain-source is electrically connected by a conductive channel formed directly under the gate electrode through a gate insulating film in a semiconductor substrate. It is an element that conducts when connected to. Therefore, the conductive field effect transistor has a certain capacitance (gate-channel capacitance) between the gate and the channel. That is, it can also function as a capacitor element in which the channel and the gate electrode are both terminals and the gate insulating film is a dielectric layer. Accordingly, the transistor Q10 selectively functions as a capacitor depending on the voltage between the node N3 and the second input terminal IN2 (functions as a capacitor only when the node N3 is at the H level).

Since the second start pulse SP2 supplied to the second input terminal IN2 of the unit shift register SR ₁ of the first row is only activated once per frame period, there is no need to act as a selectively capacitive element (Always function as a capacitor). Therefore, a normal capacitive element may be used in the unit shift register SR ₁ instead of the MOS capacitive element (transistor Q10).

  The transistor Q5 is connected between the node N3 and the first power supply terminal S1, and the gate is connected to the reset terminal RST. The transistor Q9 is connected between the node N3 and the first power supply terminal S1, and has a gate connected to the node N2.

On the other hand, the pull-down drive circuit 22 is a circuit for driving the transistor Q2 (output pull-down transistor), and has the node N3 as an input end and the node N2 (the gate of the transistor Q2) as an output end. That is, the pull-down drive circuit 22 charges and discharges the node N2 according to the level change of the node N3. Specifically, when the node N3 becomes H level, the node N2 is discharged, and when the node N3 becomes L level, the node N2 is charged. Whereby the transistor Q2 is turned off in the selection period of the gate line GL _k, turn on the non-selection period. As described above, the gates of the transistors Q4 and Q9 of the pull-up drive circuit 21 are also connected to the node N2 which is the output terminal of the pull-down drive circuit 22.

  The pull-down drive circuit 22 includes transistors Q6 and Q7 connected in series between the third power supply terminal S3 and the first power supply terminal S1. The transistor Q6 is connected between the node N2 and the third power supply terminal S3, and its gate is connected to the third power supply terminal S3 (that is, the transistor Q6 is diode-connected). The transistor Q7 is connected between the node N2 and the first power supply terminal S1, and its gate is connected to the node N3.

  The transistor Q7 is set to have a sufficiently smaller on-resistance than the transistor Q6 (that is, the driving capability is large). Therefore, when the gate (node N3) of the transistor Q7 becomes H level and the transistor Q7 is turned on, the node N2 is discharged and becomes L level. Conversely, when the node N3 becomes L level and the transistor Q7 is turned off, the node N2 becomes H level. become.

  That is, the pull-down drive circuit 22 constitutes a ratio type inverter whose operation is defined by the ratio of the on-resistance values of the transistors Q6 and Q7. In the inverter, the transistor Q6 functions as a load element and the transistor Q7 functions as a drive element.

Hereinafter, a specific operation of the unit shift register SR according to the present embodiment will be described. Here, as an example, the operation of the unit shift register SR _k in the k-th row will be described. In the unit shift register SR _k , it is assumed that the clock signal CLK1 is input to the clock terminal CK (for example, 3m-2 stage unit shift registers SR ₁ , SR ₄ ... In FIG. 2 correspond to this).

  For the sake of simplicity, it is assumed that the H level potentials of the clock signals CLK1 to CLK3 and the first and second start pulses SP1 and SP2 are all equal and the level is VDD unless otherwise specified. Further, it is assumed that VDD is equal to the levels of the high-side power supply potentials VDD1 and VDD2 (that is, VDD = VDD1 = VDD2). The L level potentials of the clock signals CLK1 to CLK3 and the first and second start pulses SP1 and SP2 are equal to the low-side power supply potential VSS, and the potential is set to 0 V (VSS = 0). Further, it is assumed that the threshold voltages of the transistors are all equal, and the value is Vth. As shown in FIG. 5, the clock signals CLK1 to CLK3 are repetitive signals having a phase difference of one horizontal scanning period (1H).

FIG. 5 is a timing diagram for explaining the operation of the unit shift register SR according to the first embodiment. The operation of the unit shift register SR _k will be described with reference to FIG.

First, as an initial state, it is assumed that the nodes N1 and N3 are at an L level (VSS) and the node N2 is at an H level (VDD-Vth) (hereinafter, this state is referred to as a “reset state”). In addition, the first input terminal IN1 (gate line drive signal G _k−2 before two rows), the second input terminal IN2 (clock signal CLK3), the clock terminal CK (clock signal CLK1), and the reset terminal RST (gate after one row) The line drive signals G _{k + 1} ) are all at L level.

In the reset state, the transistor Q1 is off (cut-off state) and the transistor Q2 is on (conduction state). Therefore, regardless of the level of the clock terminal CK (clock signal CLK1), the output terminal OUT (gate line drive signal G _k ). Is kept at L level. That is, in this initial state, the gate line GL _k corresponding to the unit shift register SR _k is in a non-selected state.

From this state, when the gate line drive signal G _{k-2 of the} previous row at time t ₁ (first start pulse SP1 in the case of the unit shift register SR ₁ in the first row) becomes H level, the unit shift is performed. transistor Q8 is turned on in the register SR _k. At this time, since the node N2 is at the H level, the transistor Q9 is also turned on, but the on-resistance of the transistor Q8 is set sufficiently lower than that of the transistor Q9, and the node N3 is charged by the charge supplied through the transistor Q8. Rises. That is, the transistor Q8 functions as a charging circuit that charges the node N3 to which the gate of the transistor Q3 is connected based on the signal input to the first input terminal IN1.

  When the level of the node N3 rises, the transistor Q7 starts to conduct and the level of the node N2 falls. As a result, the resistance of the transistor Q9 increases, and the level of the node N3 rises rapidly. In response, transistor Q7 is fully turned on. As a result, the node N2 becomes L level (VSS), the transistor Q9 is turned off, and the node N3 becomes H level (VDD-Vth).

  In order to raise the level of the node N3, it is necessary to charge the gate-channel capacitance (gate capacitance) of the transistor Q10 and the transistor Q3, and the capacitance value thereof is about 1 of the transistor Q1 and the capacitance element C1 of the output circuit 20. The node N3 can be charged at high speed because it is as small as / 5 to 1/10.

  When node N3 becomes H level, transistor Q3 is turned on accordingly. At this time, since the node N2 is at the L level, the transistor Q4 is turned off, and the level of the node N1 rises.

In order to increase the level of the node N1, it is necessary to charge the gate capacitances of the capacitive element C1 and the transistor Q1, but since the capacitance values thereof are relatively large as described above, it is difficult to charge the node N1 at high speed. . Furthermore, since the transistor Q3 operates in the source follower mode, it is difficult to raise the level of the node N1 to the theoretical value (VDD−2 × Vth) in a short time. Therefore, if the pulse width of the gate line drive signal G _k-2 of the previous two rows is not sufficiently wide, the level of the node N1 at this time rises only to a level lower than the theoretical value.

At time t _2, 2 lines before the gate line drive signal G _k-2 is returned to L level when the transistor Q8 is turned off but the node N1, N3 becomes a floating state and the transistors Q7, Q9 is flip-flop works Therefore, the levels of the nodes N1 and N3 are maintained.

When the clock signal CLK3 at time t ₃ (in the case of a unit shift register SR ₁ of the first row and the second start pulse SP2) becomes H level, the second input terminal IN2 of the unit shift register SR _k is the H level Become. At this time, since the node N3 is at the H level, a channel is formed on the source / drain side (IN2 side) of the transistor Q10. Therefore, the transistor Q10 functions as a capacitive element, and the node N3 is boosted by capacitive coupling through the transistor Q10. That is, the transistor Q10 functions as a booster circuit that boosts the charged node N3 based on a signal input to the first input terminal IN1.

  Assuming that the parasitic capacitance of the node N3 is sufficiently small compared to the capacitance value of the transistor Q10 as a MOS capacitor, the node N3 after boosting by the transistor Q10 increases from the potential before boosting by the amplitude VDD of the clock signal CLK3. . That is, the potential of the node N3 after boosting is 2 × VDD−Vth. In addition, since the voltage is boosted according to the clock signal CLK3 which is an external signal having a fast rising speed, the rising speed of the potential of the node N3 is as high as the rising speed of the clock signal CLK3.

  When the node N3 is boosted, the voltage between the gate (node N3) and the source (node N1) of the transistor Q3 becomes sufficiently high, so that the transistor Q3 operates in the non-saturated region and charges the node N1. Therefore, the node N1 is charged at high speed, and the node N1 reaches the potential VDD without loss of the threshold voltage (Vth) of the transistor Q3. Thus, when the nodes N1 and N3 are at the H level and the node N2 is at the L level (hereinafter, this state is referred to as “set state”), the transistor Q1 is turned on and the transistor Q2 is turned off.

When the clock signal CLK3 is returned to L level at time t _4, the transistor Q10 as a MOS capacitor element, the potential of the node N3 is pulled down, the flow returns to the step-up prior to VDD-Vth. At this time, since the node N1 is at the potential VDD, the transistor Q3 is turned off, but the node N1 is maintained at the potential VDD in a floating state. Accordingly, the set state of the unit shift register SR _k is maintained.

When the clock signal CLK1 at time t ₅ becomes H level, the potential change is transmitted to the output terminal OUT through the transistor Q1 in the ON state, the level of the gate line drive signal G _k is increased. At this time, the level of the node N1 is boosted by a specific voltage due to capacitive coupling via the capacitive element C1 and the gate capacitance of the transistor Q1.

Therefore, even in the process of the level of the gate line drive signal G _k is increased, the gate-source voltage of the transistor Q1 is kept large, the transistor Q1 operates in the non-saturation region. Accordingly, the output terminal OUT is charged to a high speed, the level of the gate line drive signal G _k rises quickly following the rise of the clock signal CLK1. As a result, the level of the gate line drive signal G _k is without loss of the threshold voltage Vth of the transistor Q1, it reaches the same VDD and the clock signal CLK1.

Note that assuming that the parasitic capacitance value of the node N1 is sufficiently small compared to the sum of the capacitance value of the gate capacitance of the transistor Q1 and the capacitance element C1, the step-up width of the node N1 at this time is the clock signal CLK1 and the gate line drive. the same VDD and the amplitude of the signal G _k. Therefore, the potential of the node N1 after boosting is 2 × VDD.

Then while the clock signal CLK1 is at H level (time t ₅ ~t _6), the gate line drive signal G _k is maintained at H level. Therefore, during that time, the gate line GL _k is activated to be in a selected state.

When the clock signal CLK1 at time t ₆ returns to the L level, the output terminal OUT is discharged through the transistor Q1, the gate line drive signal G _k becomes L level. Thus the gate line GL _k is deactivated, returning to a non-selected state. At this time, the level of the node N1 also returns to VDD before boosting.

Since the unit shift register SR k _{+ 1} this time is shifted to the set state, followed by the clock signal CLK2 at time t ₇ becomes H level, the gate line drive signal G _{k + 1} after one row H level become.

Therefore, in the unit shift register SR _k , the transistor Q5 is turned on. As a result, the node N3 is discharged to the L level, whereby the transistor Q7 is turned off, so that the node N2 becomes the H level. Accordingly, the transistors Q4 and Q9 are turned on, and the node N1 becomes L level. That is, the unit shift register SR _k returns to the reset state, and the transistor Q1 is turned off and the transistor Q2 is turned on.

Thereafter, at time t ₈ , the clock signal CLK2 becomes L level, and the gate line drive signal G _{k + 1} after one row becomes L level. In response, the transistor Q5 of the unit shift register SR _k is turned off.

After time t _8, the transistors Q7, Q9 to maintain the node N2 by the action of flip-flop H level, the node N3 to L level. The period node N3 to L level, the transistor Q10 does not function as a capacitive element without a channel is formed, the node N3 also the clock signal CLK3 is activated the second input terminal IN2 after time t ₈ is not boosted At L level. Therefore, the unit shift register SR _k is maintained in the reset state until the gate line driving signal G _{k-2 of the} previous two rows is activated in the next frame period.

In summary, the unit shift register SR _k is in a reset state until the signal of the first input terminal IN1 is activated, and maintains the gate line drive signal G _k at the L level. When the signal at the first input terminal IN1 becomes H level, the node N3 is charged, so that the transistor Q3 is turned on to charge the node N1, and the unit shift register SR _k shifts to the set state. Subsequently, when the signal at the second input terminal IN2 becomes H level, the node N3 is boosted, and the transistor Q3 operates in the non-saturated region, so that the potential of the node N1 rises to VDD. Subsequently, when the signal at the clock terminal CK becomes H level, the output terminal OUT is charged through the transistor Q1 in the on state, and the gate line driving signal _Gk is activated. When the signal at the reset terminal RST becomes H level, the unit shift register SR _k returns to the reset state, and again maintains the gate line drive signal G _k at L level.

When the gate line driving circuit 30a is configured by connecting the unit shift registers SR _k operating in this way as shown in FIG. 2, each unit shift register SR _k is activated by the gate line driving signal G _k-2 of the previous two rows. As a result, the potential of the node N1 is increased to VDD after one horizontal scanning period, and the gate line driving signal _Gk is activated after two horizontal scanning periods. That is, each unit shift register SR _k operates so as to activate its own gate line driving signal G _k with a delay of two horizontal scanning periods with respect to the gate line driving signal G _{k-2 of the} previous row.

Accordingly, the odd-numbered unit shift register SR _k triggers the activation of the first start pulse SP1 input to the unit shift register SR ₁ , and the odd-numbered gate line drive signals G ₁ , G ₂ , G ₃ , G ₅ ... Are activated sequentially. On the other hand, the unit shift register SR _k of the even row, the activation of the second start pulse SP2 inputted to the unit shift register SR ₂ a trigger, two horizontal scanning periods gate line drive signal G ₂ of the even rows for each, G ₄ , G ₆ ... Are activated sequentially.

Since the second start pulse SP2 has only the phase is delayed one horizontal scanning period to the first start pulse SP1, the unit shift register SR ₂ starts delayed by operating one horizontal scanning period than the unit shift register SR _1. In the entire gate line driving circuit 30a, following activation of the first and second start pulses SP1, SP2, the gate line driving signals G ₁ , G ₂ , G ₃ , G ₄ . The gate lines GL ₁ , GL ₂ , GL ₃ , GL ₄ ... Are sequentially selected.

Next, the repair unit shift register SRB will be described. FIG. 4 is a circuit diagram showing a configuration of repair unit shift register SRB according to the first embodiment. The configuration of the relief unit shift register SRB relief gate line drive circuit 30b are the same: essentially, are representatively shown in the k-th row relief unit shift register SRB _k of.

As shown in FIG. 4, the repair unit shift register SRB _k of the present embodiment has the same circuit configuration as that of FIG. Further, the connection destinations of the first input terminal IN1, the second input terminal IN2, the output terminal OUT, the clock terminal CK, and the reset terminal RST of the repair unit shift register SRB _k are also common to the unit shift registers SR _{k in the} same row. Yes.

However, between the output terminal OUT and the corresponding gate line GL _k , as well as the first input terminal IN1 and the gate line GL _k-2 two rows before (in the relief unit shift register SRB ₁ , the first start pulse SP1 wire, between the wire) of the relief unit shift register SRB ₂ in the second start pulse SP2 are respectively connected by failure repair process. That is, as can be connected by the laser irradiation, and a gate line GL _k and the corresponding connected to the output terminal OUT line is crossing, as well, wiring and two lines before the gate line connected to the first input terminal IN1 GL _k-2 is crossed three-dimensionally.

  In the present embodiment, in the repair unit shift register SRB before the defect repair process, the first input terminal IN1 is connected to the low-side power supply potential VSS. Thereby, transistor Q8 of repair unit shift register SRB is maintained in the off state, and repair unit shift register SRB is maintained in the reset state. If the current of the transistor Q1 is acceptable or if the level of the node N3 does not increase even when the first input terminal IN is open (floating state), the first input terminal IN is open. It may be.

A defect repair method for the gate line drive circuit 30a using the repair gate line drive circuit 30b will be described. Here as an example, be described as the operation failure occurs in the third row unit shift register SR ₃ in. If the unit shift register SR ₃ is operating normally, all of the fourth and subsequent rows of the pixel line for the unit shift register SR of the fourth and subsequent rows does not operate correctly is poor display. As a cause of the malfunction, for example, disconnection due to a mixed foreign matter during the manufacturing process can be considered.

FIG. 6 is a circuit diagram of the gate line driving circuit 30a and the relief gate line driving circuit 30b. This figure shows an example in which a defect repair process is performed in which a defect occurs in the unit shift register SR ₃ and is replaced with the repair unit shift register SRB ₃ in the same row. This replacement can be performed by the following procedure.

First, the output terminal OUT of the unit shift register SR ₃ and the gate line GL ₃ are cut by laser irradiation, and the two are electrically separated. In the relief unit shift register SRB ₃ , the wiring between the first input terminal IN1 and the low-side power supply VSS is cut by laser irradiation, and the wiring connected to the first input terminal IN1 and the gate line GL two rows before ₁ and electrically connects the first input terminal IN1 and the laser irradiation and the gate lines GL ₁ an intersection. Further, the intersection of the wiring connected to the output terminal OUT of the repair unit shift register SRB and the gate line GL ₃ is irradiated with laser to electrically connect the output terminal OUT and the gate line GL ₃ .

As a result, the unit shift register SR ₃ is replaced with the repair unit shift register SRB ₃ . That is relief unit shift register SRB ₃ acts on behalf of the unit shift register SR _3, thereby outputting the gate line driving signal G ₃ to the gate line GL _3. As a result, in the gate line driving circuit 30a, the unit shift registers SR on and after the fourth row operate normally, and the gate line driving circuit 30a is restored.

The gate line driving signals G ₁ to be inputted to the first input terminal IN1 of the unit shift register SR _3, since being input through the gate line driving signals G _1, the resistance component of the gate line driving signals G ₁ and It has a delay due to the influence of the capacitive component. Thus the charging of the relief unit shift register SRB ₃ of node N3 is correspondingly will be delayed. However, the potential of the node N3 is boosted when the non-delayed clock signal CLK2 input to the second input terminal IN2 is activated, and the transistor Q3 operates in the non-saturated region. It does not affect. Therefore, in the repair unit shift register SRB ₃ , a reduction in the operation margin due to the signal delay of the gate line drive signal G ₁ is suppressed.

In the above, an example in which the unit shift register SR (FIG. 3) and the relief unit shift register SRB _k (FIG. 4) are each operated using a three-phase clock signal has been shown. It can also be used and operated.

  In this embodiment, the unit shift register SR and the repair unit shift register SRB have the same circuit configuration, but the unit shift register SR may use a circuit having another configuration. For example, a unit shift register SR that can operate even with a two-phase clock signal as shown in FIG. 3 of Japanese Patent Laid-Open No. 2007-207411 may be used. In this case, only the unit shift register SR may be operated using a two-phase clock signal, but for this purpose, a two-phase clock signal generator is required. As in the present embodiment, it is preferable from the viewpoint of simplification of the device configuration to supply clock signals of three or more phases in common to the unit shift register SR and the relief unit shift register SRB.

[First change example]
FIG. 7 is a circuit diagram showing configurations of the gate line driving circuit 30a and the relief gate line driving circuit 30b according to the first modification of the first embodiment. In the same figure, an example in which the unit shift register SR ₃ in the third row is replaced with the unit shift register SRB ₃ for repair in the same row is shown.

In this modification, the first input terminal IN1 of each repair unit shift register SRB is connected to the gate line GLk _-2 two rows before from the beginning (before the defect repair process). In this case, as wiring processing for replacing the unit shift register SR _k with the repair unit shift register SRB _k , disconnection between the output terminal OUT of the unit shift register SR _k and the gate line GL _k , repair unit shift It is only necessary to connect the output terminal OUT of the register SRB _k and the gate line GL _k . That is, defect repair can be performed more easily than in FIG.

  However, it should be noted that since all of the repair unit shift registers SRB operate in the same manner as the normal unit shift register SR, power consumption increases.

[Second modification]
In the present modification example, a repair process will be described in the case where a failure occurs due to disconnection of the gate line drive signal G in the liquid crystal array unit 10 instead of a failure of the unit shift register SR.

For example, as shown in FIG. 8, it is assumed that the disconnection occurs in the gate line GL ₃ in the third row. In the third row where the disconnection has occurred, the pixels from the unit shift register SR ₃ to the disconnection portion perform normal display, but the display defect occurs in the pixels from there to the repair unit shift register SRB ₃ .

In this case, only the wiring on the relief unit shift register SRB ₃ side is performed without cutting between the output terminal OUT of the unit shift register SR ₃ and the gate line GL ₃ . That is, in the relief unit shift register SRB ₃ , disconnection between the first input terminal IN1 and the low-side power supply VSS, connection between the first input terminal IN1 and the gate line GL _k-2 of the previous two rows, and output terminal OUT Only the connection with the gate line GL ₃ is performed.

As a result, the pixels from the unit shift register SR ₃ to broken point, is driven by a unit shift register SR _3, pixels from the broken portion to the relief unit shift register SRB ₃ is driven by a relief unit shift register SRB ₃ Will be. Therefore, all the pixels in the third row can display normally.

[Third Modification]
FIG. 9 is a circuit diagram showing configurations of the gate line driving circuit 30a and the relief gate line driving circuit 30b according to the third modification of the first embodiment. In this modification example, in each of the relief unit shift registers SRB, the second input terminal IN2 and the gate line GL _k-2 (the wiring of the second start pulse SP2 in the relief unit shift register SRB ₁ ) two rows before And between the clock terminal CK and the wiring of the clock signal (any one of the signals CLK1 to CLK3) are not initially connected (before the defect relief process) but can be connected by the defect relief process ( Two wires are crossed in three dimensions).

  In the configurations shown in FIGS. 6, 7, and 8, one of the clock signals CLK1 to CLK3 is input to the first and second input terminals IN1 and IN2 of all the repair unit shift registers SRB. Wasteful power is consumed (this power consumption is mainly caused by charging / discharging of the gate-drain capacitance of the transistor Q1). In the configuration of FIG. 9, since the clock signals CLK1 to CLK3 are not input to the repair unit shift register SRB that is not subjected to the defect repair processing, power consumption can be reduced.

  In the repair unit shift register SRB of FIG. 9, the second input terminal IN2 is connected to the low-side power supply potential VSS, and is cut off during the repair process. This is because if the second input terminal IN2 is in an open state (floating state), the potential of the node N3 becomes unstable due to the influence of noise or the like, and there is a concern that current flows through the transistor Q3. When the current of the transistor Q3 is acceptable, the second input terminal IN2 may be in an open state.

For example, when an operation failure occurs in the unit shift register SR ₃ as shown in FIG. 9 and is replaced with the repair unit shift register SRB ₃ , the following wiring processing by laser irradiation is performed as the failure repair processing.

First, the output terminal OUT of the unit shift register SR ₃ and the gate line GL ₃ are disconnected. In the relief unit shift register SRB ₃ , the second input terminal IN 2 is disconnected from the low-side power source VSS and connected to the wiring of the clock signal CLK 2, and the clock terminal CK and the wiring of the clock signal CLK 3 are connected. Further, the first input terminal IN1 of the relief unit shift register SRB ₃ is disconnected from the low-side power supply VSS and connected to the gate line GL ₁ (the input terminal IN is connected to the gate line GL ₁ from the beginning as shown in FIG. 7). If this is the case, this step is not necessary). As a result, the unit shift register SR ₃ is replaced with the repair unit shift register SRB ₃ .

[Fourth modification]
FIG. 10 is a circuit diagram of repair unit shift register SRB _{k according} to the fourth modification of the first embodiment. The relief unit shift register SRB _k is _obtained by connecting the drain of the transistor Q8 to the first input terminal IN1 in the configuration of FIG. According to this structure, wirings for supplying a high power supply potential VDD to the transistor Q8 of the relief unit shift register SRB _k becomes unnecessary, thereby facilitating the layout design of the circuit.

  The circuit of FIG. 10 may of course be used as a regular unit shift register SR.

[Fifth Modification]
FIG. 11 is a circuit diagram of repair unit shift register SRB _{k according} to the fifth modification of the first embodiment. The relief unit shift register SRB _k is different from the configuration shown in FIG. 10 in that the gate of the transistor Q8 has a clock signal in phase with the gate line drive signal G _k-2 two rows before (that is, the unit shift register SR two rows before). to the second clock terminal CK1 supplied to the clock terminal CK of _k-2 ).

The clock signals CLK <b> 1 to CLK <b> 3 supplied from the clock signal generator 31 have a higher level rising rate than the gate line drive signal G. Therefore, in the circuit of FIG. 11, when the transistor Q8 starts to charge the node N3 in response to the activation of the gate line drive signal G _k-2 of the previous row (the level of the gate line drive signal G _k-2 is sufficiently high). Until it rises), transistor Q8 operates in the non-saturated region. Therefore, the charging of the node N3 can be speeded up, and the operation margin of the repair unit shift register SRB can be increased.

  However, it should be noted that wiring is required to supply a predetermined clock signal to the transistor Q8, and that the power consumption of the clock signal generator 31 is increased.

  The circuit of FIG. 11 may of course be used as a regular unit shift register SR.

[Sixth Modification]
FIG. 12 is a circuit diagram of repair unit shift register SRB _{k according} to the sixth modification of the first embodiment. The repair unit shift register SRB _k is provided with a charge / discharge circuit that charges and discharges the gate of the transistor Q8 at a predetermined timing in the configuration of FIG.

  The charge / discharge circuit includes a first inverter having a node N2 as an input terminal, a second inverter having a node N4 as an output terminal of the first inverter as an input terminal, and a node as an output terminal of the second inverter The transistor Q15 is interposed between N5 and a node N6 to which the gate of the transistor Q8 is connected. The gate of the transistor Q15 is connected to the third power supply terminal S3.

  The first inverter is a push-pull inverter composed of transistors Q11 and Q12. The transistor Q11 has a gate connected to the first input terminal IN1, and is connected between the node N4 and the third power supply terminal S3. The transistor Q12 has a gate connected to the node N2, and is connected between the node N4 and the first power supply terminal S1.

  The second inverter is a ratio type inverter composed of transistors Q13 and Q14. The transistor Q13 has a gate connected to the third power supply terminal S3, and is connected between the node N5 and the third power supply terminal S3. The transistor Q14 has a gate connected to the node N4, and is connected between the node N5 and the first power supply terminal S1. The on-resistance of the transistor Q14 is set to be sufficiently smaller than that of the transistor Q13.

Here, it is assumed that the first input terminal IN1 of the repair unit shift register SRB _k is connected to the gate line GL _k-2 two rows before by the defect repair processing, and the repair unit shift register of FIG. The operation of SRB _k will be described.

The basic operation of the unit shift register SR _{k in} FIG. 12 is almost the same as the operation of the unit shift register SRB _k for repair in FIG. 4 (that is, almost the same as the operation of the unit shift register SR shown in FIG. 5). ). However, since the transistor Q8 operates in the non-saturated region to charge the node N6 when the gate line drive signal G _{k-2 of the} previous row is activated, the charging speed of the node N3 is higher than that of the circuit of FIG. Speeded up.

In the non-selection period of the repair unit shift register SRB _k, the repair unit shift register SRB _k is in the reset state, and its node N2 is at the H level. Therefore, since the transistor Q12 is on, the node N4 is at L level (VSS), and since the transistor Q14 is off, the node N5 is at H level (VDD-Vth). Since the gate potential of the transistor Q15 is fixed to the high-side power supply potential VDD, if the node N5 is at the H level (VDD−Vth), the node N6 is also charged to the H level (VDD−Vth). Therefore, the transistor Q8 is on.

Therefore, when the gate line drive signal G _{k-2 of the} previous two rows becomes H level, the node N3 is charged and becomes H level. At this time, the node N6 is boosted by coupling through the gate capacitance (gate-channel capacitance, gate-drain capacitance, and gate-source capacitance) of the transistor Q8. As a result, transistor Q8 operates in the non-saturated region and charges node N3 at high speed.

When the charging of the node N3 proceeds and becomes H level, the transistor Q7 is turned on and the node N2 becomes L level. Responsively, transistor Q12 is turned off, and node N4 is charged through transistor Q11 and becomes H level. Thereby, transistor Q14 is turned on, and node N5 changes to L level. Then, the node N6 is discharged through the transistors Q15 and Q14 and becomes L level (VSS), and the transistor Q8 is turned off accordingly. Since the transistor Q8 is turned off, the node N3 is maintained at the H level even when the gate line driving signal G _{k-2 of the} previous two rows returns to the L level thereafter, and the repair unit shift register SRB _k. Can operate in the same manner as the circuit of FIG.

In other words, the charging / discharging circuit including the transistors Q11 to Q15 charges the node N6 prior to the activation of the gate line driving signal G _k-2 of the previous row, and the gate line driving signal G _{k of the} previous row. _{After -2} is activated, it operates to discharge node N6 before it deactivates. Note that the interval between the activation timing of the gate line drive signal G _k-2 two rows before and the discharge timing of the node N6 is determined by the time required for charging the node N4 and discharging the node N5.

In the circuit of FIG. 12, a through current flows through the transistors Q13 and Q14 when the gate line drive signal G _{k-2 of the} previous two rows becomes H level. However, the transistor Q13 only needs to have a driving capability capable of charging the node N6 to the H level during the period when the repair unit shift register SRB is in the reset state, and the on-resistance can be set high. By doing so, an increase in power consumption due to the through current can be suppressed.

  Further, it should be noted that the circuit formation area increases because the number of transistors used is larger than that in the configuration of FIG. In the circuit of FIG. 12, the transistor Q15 may be omitted (the gate of the transistor Q8 may be directly connected to the node N5). The transistor Q15 is turned off when the node N6 is boosted, and serves to separate the nodes N5 and N6. With this function, the parasitic capacitance of the node N6 when the node N6 is boosted can be reduced, and the node N6 can be boosted more greatly.

  The circuit of FIG. 12 may of course be used as a regular unit shift register SR.

[Seventh Modification]
For example, in the repair unit shift register SRB of FIG. 3, the transistor Q10 (MOS capacitive element) is used as the boosting element for boosting the node N3. However, since a relatively large capacitance value is required, it is necessary to secure a large formation area. There is. Therefore, in this modification, an example in which the gate capacitance of the transistor Q3 is used as the boosting element that boosts the node N3 without using the transistor Q10.

Figure 13 is a circuit diagram of a seventh relief unit shift register SRB _k according to a modification of the first embodiment. In the repair unit shift register SRB _k , the output circuit 20 has a gate connected to a node N7, which will be described later, and a transistor connected between the output terminal OUT and the first power supply terminal S1 in the configuration of FIG. Q16 is provided.

  The pull-up drive circuit 21 includes the following transistors Q3, Q4, and Q17 to Q22. The transistor Q3 is connected between the node N1 (the gate of the transistor Q1) and the second input terminal IN2. The transistor Q4 has a control electrode connected to the node N2 (the output terminal of the pull-up drive circuit 21), and is connected between the node N1 and the first power supply terminal S1.

  The transistor Q17 has a gate connected to the second power supply terminal S2, and is connected between the gate (node N3) of the transistor Q3 and a predetermined node N7. The transistor Q18 is connected between the node N7 and the first power supply terminal S1, and its gate is connected to the node N2. The transistor Q19 has a gate connected to the first input terminal IN1, and is connected between the node N7 and the first input terminal IN1. The transistor Q20 is connected between the node N7 and the first power supply terminal S1. A node to which the gate of the transistor Q20 is connected is defined as “node N8”.

  The transistor Q21 has a gate connected to the node N1, and is connected between the node N8 and the second power supply terminal S2. The transistor Q22 has a gate connected to the node N2, and is connected between the node N8 and the first power supply terminal S1.

  The pull-down drive circuit 22 includes an inverter having the node N2 as an output terminal, and an input circuit that controls the level of the node N9 that is an input terminal of the inverter.

  The inverter is composed of transistors Q6 and Q7. The transistor Q6 has a gate connected to the second power supply terminal S2, and is connected between the node N2 and the third power supply terminal S3. The transistor Q7 has a gate connected to the node N9, and is connected between the node N2 and the first power supply terminal S1.

  The input circuit includes transistors Q23 to Q25. The transistor Q23 has a gate connected to the first input terminal IN1, and is connected between the node N9 and the third power supply terminal S3. The transistor Q24 has a gate connected to the reset terminal RST, and is connected between the node N9 and the first power supply terminal S1. The transistor Q25 has a gate connected to the node N2, and is connected between the node N9 and the first power supply terminal S1. The on-resistance of the transistor Q25 is set larger than that of the transistor Q23.

This input / output circuit sets the node N9 (inverter input terminal) to the H level in response to the activation of the signal of the first input terminal IN1 (the gate line driving signal G _{k-2 of the} previous two rows), and the reset terminal RST. In response to the activation of the signal (the gate line drive signal G _{k + 1} after one row), the node N9 operates so as to be at the L level. The transistor Q25, when the unit for the repair shift register SRB _k is reset (when the node N2 is at the H level), functions to maintain the node N9 to the L level.

Here, it is assumed that the first input terminal IN1 of the repair unit shift register SRB _k is connected to the gate line GL _k-2 two rows before by the defect repair process, and the repair unit shift register of FIG. The operation of SRB _k will be described. For convenience of explanation, a clock terminal CK of the relief unit shift register SRB _k clock signal CLK1, the second input terminal IN2 is assumed that the clock signal CLK3 is input.

In the non-selection period of the repair unit shift register SRB _k , the unit shift register SR _k is in a reset state in which the node N1 is at the L level and the node N2 is at the H level. At this time, since the transistor Q1 is off and the transistor Q2 is on, the output terminal OUT (gate line drive signal G _k ) is at low level with low impedance. The transistors Q18, Q22, and Q25 are on, and the nodes N7, N8, and N9 are also at a low impedance L level.

  Since the node N7 is at the L level, the transistor Q17 whose gate potential is fixed at VDD is in the on state, and the node N3 is at the L level. Therefore, the transistor Q3 is in an off state, and the node N1 is maintained at the L level even when the clock signal CLK3 is activated.

When the gate line drive signal G _{k-2 of the} previous two rows becomes H level at a predetermined timing, the transistor Q23 is turned on and the node N9 is charged and becomes H level. Responsively, transistor Q7 is turned on, and node N2 is discharged to L level. Therefore, the transistors Q2, Q4, Q18, Q22, and Q25 are turned off. At this time, the transistor Q19 is turned on, and the node N7 is charged and becomes H level (VDD-Vth). Then, the node N3 is charged through the transistor Q17 and becomes H level (VDD-Vth), and the transistor Q3 is turned on.

  Note that the transistor Q2 is turned off when the node N2 becomes L level, but the node N7 becomes H level and the transistor Q16 is turned on almost simultaneously, so that the output terminal OUT is maintained at the L level with low impedance.

Thereafter, the gate line drive signal G _k-2 of the previous two rows returns to the L level, but the diode-connected transistor Q19 is turned off, so that the node N7 is maintained at the H level.

Subsequently, when the clock signal CLK3 becomes H level (VDD), the node N1 is charged through the transistor Q3 in the on state and becomes H level. At this time, the node N3 is boosted by coupling via the gate capacitance (gate-channel capacitance, gate-source capacitance, gate-channel capacitance) of the transistor Q3, and the transistor Q3 operates in the non-saturated region to charge the node N1. To do. Therefore, the node N1 is charged at high speed, and its H level potential becomes VDD. That unit shift register SRB _k for relief, the node N1 is at the H level, the node N2 is set at L level.

  When the node N1 becomes H level, the transistor Q21 is turned on, the node N8 is charged and becomes H level. Responsively, transistor Q20 is turned on, and node N7 is discharged to L level (VSS). Then, the node N3 is discharged through the transistors Q17 and Q20 and becomes L level (VSS), and the transistor Q3 is turned off accordingly. Therefore, even when the clock signal CLK3 returns to the L level, the node N1 is maintained at the H level. Since the node N7 becomes L level, the transistor Q16 is also turned off.

Thereafter, when the clock signal CLK1 becomes H level, the output terminal OUT is charged through the transistor Q1 in the on state, and the gate line driving signal _Gk becomes H level. At this time, the node N1 is boosted by the coupling through the gate capacitance of the transistor Q1, and the transistor Q1 operates in the non-saturated region. Therefore H-level potential of the gate line drive signal G _k becomes VDD.

When the clock signal CLK1 becomes the L level, the output terminal OUT is discharged by the transistor Q1, the gate line drive signal G _k is returned to L level.

Thereafter, when the gate line drive signal G _{k + 1} after one row becomes H level, the transistor Q24 is turned on and the node N9 becomes L level. Responsively, transistor Q7 is turned off and node N2 goes to H level. Therefore, the transistors Q2, Q4, Q18, Q22, and Q25 are turned on, and the nodes N1, N3, N7, and N8 and the output terminal OUT are set to L level with low impedance. That is, the repair unit shift register SRB _k returns to the reset state.

Thereafter, the half latch circuit composed of the transistors Q6, Q7, and Q25 maintains the node N2 at the H level until the gate line drive signal _{Gk-2 of the} previous two rows is activated. The unit shift register SRB _k is maintained in the reset state.

As can be seen from the above operation, the circuit formed by the transistors Q17~Q22 is previously charges the node N3 in response to activation of the gate line drive signal G _k-2 two lines before, the node N1 is charged It functions as a charging / discharging circuit that discharges the node N3 in response. In this charge / discharge circuit, the transistor Q17 may be omitted (the gate of the transistor Q3 may be directly connected to the node N7). The transistor Q17 is turned off when the node N3 is boosted, and serves to separate the nodes N3 and N7. With this function, the parasitic capacitance of the node N3 when the node N3 is boosted can be reduced, and the node N3 can be boosted more greatly.

<Embodiment 2>
FIG. 14 is a block diagram showing a configuration of the gate line driving circuit 30a and the relief gate line driving circuit 30b according to the second embodiment of the present invention. In the present embodiment, the unit shift registers SR constituting the gate line driving circuit 30a and the relief unit shift registers SRB constituting the relief gate line driving circuit 30b are arranged in a staggered manner with the liquid crystal array unit 10 interposed therebetween. Is done.

  That is, as shown in FIG. 14, the unit shift register SR of the gate line driving circuit 30a is arranged on the left end side of the odd-numbered gate lines GL and on the right end side of the even-numbered gate lines GL. The relief unit shift register SRB of the relief gate line driving circuit 30b is disposed on the right end side of the odd-numbered gate lines GL and on the left end side of the even-numbered gate lines GL.

  The unit shift register SR of the gate line driving circuit 30a may have any configuration as long as it can be arranged in a staggered manner with the liquid crystal array unit 10 interposed therebetween. However, in order to avoid the influence of the signal delay due to the gate line GL, each unit shift register SR receives the gate line drive signal G two rows before, and the gate line output by itself after a two horizontal scanning period after its activation. It is preferable to use one that activates the drive signal G, for example, one having the configuration shown in FIGS. 3 and 10 to 12.

  On the other hand, the relief unit shift register SRB of the relief gate line drive circuit 30b receives the gate line drive signal G of the previous row and outputs the gate line drive signal output by itself with a delay of one horizontal scanning period from its activation. Those that activate G are used. The gate line drive signal G one row before as viewed from each of the repair unit shift registers SRB is output from the unit shift register SR disposed on the same side with respect to the liquid crystal array unit 10, so that the defect repair processing is performed. Is not affected by the signal delay caused by the gate line GL. In this embodiment, the circuit shown in FIG. 15 is used as the repair unit shift register SRB.

FIG. 15 is a circuit diagram of the repair unit shift register SRB _{k according to} the present embodiment. The repair unit shift register SRB _k shown in the first embodiment has a configuration having two input terminals (first and second input terminals IN1 and IN2), but the repair unit shift register of the present embodiment. The SRB _k has only one input terminal IN to which the gate line driving signal G _{k−1 of the} previous row (the second start pulse SP2 in the _first unit relief unit shift register SRB ₁ ) is input.

In the repair unit shift register SRB _k of FIG. 15, the output circuit 20 has the same configuration as that of FIG. The pull-down drive circuit 22 has the same configuration as that shown in FIG. 13, but the gate of the transistor Q23 is connected to the input terminal IN.

  The pull-up drive circuit 21 includes a transistor Q30 connected between the node N1 (gate of the transistor Q1) and the input terminal IN, a gate of the transistor Q30 (defined as “node N30”), and a node N2 (pull-down drive circuit 22). The transistor Q31 is connected to the output terminal of the transistor Q31. The gate of the transistor Q31 is connected to the second power supply terminal S2.

Here, the failure repair process, assuming the input terminal IN of the relief unit shift register SRB _k is connected to the gate line GL _k-1 of the preceding row, the relief unit shift register SRB _k in FIG. 15 The operation of will be described. For convenience of explanation, a clock terminal CK of the relief unit shift register SRB _k it is assumed that the clock signal CLK1 is input.

First, in the non-selection period of the repair unit shift register SRB _k , the unit shift register SR _k is in a reset state in which the node N1 is at the L level and the node N2 is at the H level. At this time, since the transistor Q1 is off and the transistor Q2 is on, the output terminal OUT (gate line drive signal G _k ) is at low level with low impedance. The transistor Q25 is on, and the node N4 (the gate of the transistor Q7) is also at a low impedance and at the L level.

  Since the node N2 is at the H level (VDD−Vth), the node N30 is charged through the transistor Q31 whose gate potential is fixed at VDD and is at the H level (VDD−Vth), and the transistor Q30 is in the on state. .

When the gate line drive signal G _{k-1 of the} previous row becomes H level at a predetermined timing, the node N1 is charged through the transistor Q30 in the on state and becomes H level. At this time, the node N30 is boosted by coupling via the gate capacitance (gate-channel capacitance, gate-source capacitance, gate-channel capacitance) of the transistor Q30, and the transistor Q30 operates in the non-saturated region to charge the node N1. To do. Therefore, the node N1 is charged at high speed, and its H level potential becomes VDD. Therefore, the transistor Q1 is turned on.

  On the other hand, in the pull-down drive circuit 22, the transistor Q23 is turned on, and the node N4 is charged and becomes H level. Responsively, transistor Q7 is turned on and node N2 is discharged to L level (VSS). At this time, the transistors Q2 and Q25 are turned off.

When node N2 becomes L level, transistor Q31 is turned on, so that node N30 is discharged through transistors Q31 and Q7 and becomes L level. Therefore, transistor Q30 is turned off. Therefore, after this, the gate line drive signal G _{k-1 of the} previous row becomes L level, but the node N1 is maintained at H level (VDD).

Subsequently, when the clock signal CLK1 becomes H level, the output terminal OUT is charged through the transistor Q1 in the on state, and the gate line driving signal _Gk becomes H level. At this time, the node N1 is boosted by the coupling through the gate capacitance of the transistor Q1, and the transistor Q1 operates in the non-saturated region. Therefore H-level potential of the gate line drive signal G _k becomes VDD.

When the clock signal CLK1 becomes the L level, the output terminal OUT is discharged by the transistor Q1, the gate line drive signal G _k is returned to L level.

Thereafter, when the gate line drive signal G _{k + 1} after one row becomes H level, the transistor Q24 is turned on and the node N4 becomes L level. Accordingly, the transistor Q7 is turned off, and the node N2 becomes H level (VDD-Vth). Therefore, the transistors Q2 and Q25 are turned on. Further, the node N30 is charged through the transistor Q31 and becomes H level (VDD-Vth), and the transistor Q30 is turned on, so that the node N1 is discharged and becomes L level. That is, the repair unit shift register SRB _k returns to the reset state.

Thereafter, the half latch circuit composed of the transistors Q6, Q7, and Q25 maintains the node N2 at the H level until the gate line drive signal G _{k-1 of the} previous row is activated next. The unit shift register SRB _k is maintained in the reset state.

As can be seen from the above operation, the circuit composed of the pull-down drive circuit 22 and the transistor Q31 charges the node N30 before the activation of the gate line drive signal G _k-1 of the previous row, and After the gate line drive signal G _k-1 is activated, it functions as a charge / discharge circuit that discharges the node N30 before it is deactivated. Note that the interval between the activation timing of the gate line drive signal G _k-1 of the previous row and the discharge timing of the node N30 is defined by the time required for charging the node N4 and discharging the node N2.

  In this charge / discharge circuit, the transistor Q31 may be omitted (the gate of the transistor Q30 may be directly connected to the node N2). The transistor Q31 is turned off when the node N30 is boosted, and functions to separate the nodes N30 and N2. By this function, the parasitic capacitance of the node N30 when the node N30 is boosted can be reduced, and the node N30 can be boosted more greatly.

FIG. 16 is a circuit diagram of the gate line driving circuit 30a and the relief gate line driving circuit 30b according to the present embodiment. This figure shows an example in which a defect repair process is performed in which a defect occurs in the unit shift register SR ₃ and is replaced with the repair unit shift register SRB ₃ in the same row. This replacement can be performed by the following procedure.

First, the output terminal OUT of the unit shift register SR ₃ and the gate line GL ₃ are cut by laser irradiation, and the two are electrically separated. In the relief unit shift register SRB ₃ , the wiring between the input terminal IN and the low-side power supply VSS is cut by laser irradiation, and the intersection of the wiring connected to the input terminal IN and the gate line GL _{2 in the} previous row is cut. thereby electrically connecting the input terminal iN and the gate line GL ₂ the laser irradiation. Further, the intersection of the wiring connected to the output terminal OUT of the repair unit shift register SRB and the gate line GL ₃ is irradiated with laser to electrically connect the output terminal OUT and the gate line GL ₃ .

As a result, the unit shift register SR ₃ is replaced with the repair unit shift register SRB ₃ . That is relief unit shift register SRB ₃ acts on behalf of the unit shift register SR _3, thereby outputting the gate line driving signal G ₃ to the gate line GL _3. As a result, in the gate line driving circuit 30a, the unit shift registers SR on and after the fourth row operate normally, and the gate line driving circuit 30a is restored.

Note that the first to third modifications of the first embodiment can also be applied to the repair gate line driving circuit 30b of the present embodiment. For example, the first modification example may be applied to connect the input terminal IN and the previous gate line GL _k−1 in each of the repair unit shift registers SRB _k from the beginning. Further, when the disconnection of the gate line GL _k is repaired, the unit shift register SR _k and the gate line GL _k are connected to each other and the repair unit shift register SRB _{k is} defective as in the second modification. Relief processing may be performed. Further, the third modification is applied, and in each of the repair unit shift registers SRB _k , defective repair is performed without initially connecting (three-dimensionally intersecting) the clock terminal CK and the wiring that supplies the clock signal thereto. You may make it connect by a process.

  10 liquid crystal array unit, 100 liquid crystal display device, 15 pixels, 20 output circuit, 21 pull-up drive circuit, 22 pull-down drive circuit, 30b relief gate line drive circuit, 30a gate line drive circuit, 31 clock signal generator, 32 start Signal generator, GL gate line, SR unit shift register, SRB relief unit shift register.

Claims (32)

A plurality of scan lines;
A plurality of signal lines orthogonal to the plurality of scanning lines;
A plurality of pixels formed in the vicinity of intersections of the plurality of scanning lines and the plurality of signal lines;
A scanning line driving circuit comprising a normal unit shift register disposed on the first end side of each of the plurality of scanning lines;
An electro-optical device comprising a relief unit shift register disposed on a second end side of each of the plurality of scanning lines,
Each of the relief unit shift registers includes:
A first input terminal, a second input terminal, an output terminal and a clock terminal;
A first transistor for supplying a first clock signal input to the clock terminal to an output terminal;
A second transistor for charging a first node to which the control electrode of the first transistor is connected;
A charging circuit that charges a second node to which a control electrode of the second transistor is connected in response to activation of a first input signal input to the first input terminal;
An electro-optical device comprising: a boosting circuit that boosts the charged second node in response to activation of a second input signal input to the second input terminal. The booster circuit includes:
2. The electro-optical device according to claim 1, wherein the electro-optical device is a MOS (Metal Oxide Semiconductor) capacitive element that capacitively couples between the second node and the second input terminal. The charging circuit is
3. The electro-optical device according to claim 1, wherein the electro-optical device is a third transistor that has a control electrode connected to the first input terminal and charges the second node. The charging circuit is
2. The third transistor having a control electrode to which a second clock signal having the same phase as the first input signal is supplied and connected between the first input terminal and the second node. 3. The electro-optical device according to 2. The charging circuit is
A third transistor connected between the first input terminal and the second node;
A charge / discharge circuit that charges the fifth node connected to the control electrode of the third transistor prior to the activation of the first input signal and discharges the fifth node prior to the deactivation of the first input signal. The electro-optical device according to claim 1, further comprising: The charge / discharge circuit is
6. The electro-optical device according to claim 5, wherein the electro-optical device is connected to the fifth node via a fifth transistor having a control electrode connected to an active level power source. The electro-optical device according to claim 1, wherein the first input signal is a drive signal for a scanning line adjacent to two lines. 8. The electricity according to claim 1, wherein the second input signal is a third clock signal that is activated between an active period of the first input signal and an active period of the first clock signal. 9. Optical device. The electro-optical device according to claim 1, wherein the output terminal and the scanning line are connected by defect repair processing. The electro-optical device according to claim 1, wherein the first input terminal and a wiring that supplies the first input signal to the first input terminal are connected by defect repair processing. The electro-optical device according to claim 1, wherein the second input terminal and a wiring that supplies the second input signal thereto are connected by defect repair processing. The electro-optical device according to claim 1, wherein the clock terminal and a wiring that supplies the first clock signal to the clock terminal are connected by defect repair processing. The electro-optical device according to claim 1, wherein the defect repairing process is a wiring processing process by laser irradiation. A plurality of scan lines;
A plurality of signal lines orthogonal to the plurality of scanning lines;
A plurality of pixels formed in the vicinity of intersections of the plurality of scanning lines and the plurality of signal lines;
A scanning line driving circuit comprising a normal unit shift register disposed on the first end side of each of the plurality of scanning lines;
An electro-optical device comprising a relief unit shift register disposed on a second end side of each of the plurality of scanning lines,
Each of the relief unit shift registers includes:
A first input terminal, a second input terminal, an output terminal and a clock terminal;
A first transistor for supplying a first clock signal input to the clock terminal to an output terminal;
A second transistor connected between the second input terminal and a first node to which a control electrode of the first transistor is connected;
The second node connected to the control electrode of the second transistor is charged in response to the activation of the first input signal input to the first input terminal, and the first node is charged in response to the first node being charged. A charge / discharge circuit for discharging two nodes;
An electro-optical device, wherein the output terminal and a corresponding scanning line are connected by defect repair processing. The charge / discharge circuit is
15. The electro-optical device according to claim 14, wherein the electro-optical device is connected to the second node through a third transistor having a control electrode connected to an active level power source. 16. The electro-optical device according to claim 14, wherein the first input signal is a driving signal for a scanning line adjacent to two lines. The second input signal input to the second input terminal is a second clock signal that is activated between an active period of the first input signal and an active period of the first clock signal. The electro-optical device according to claim 16. The electro-optical device according to claim 14, wherein the output terminal and the scanning line are connected by defect repair processing. 19. The electro-optical device according to claim 14, wherein the first input terminal and a wiring that supplies the first input signal to the first input terminal are connected by defect repair processing. 20. The electro-optical device according to claim 14, wherein the second input terminal and a wiring that supplies the second input signal to the second input terminal are connected by defect relief processing. 21. The electro-optical device according to claim 14, wherein the clock terminal and a wiring that supplies the first clock signal to the clock terminal are connected by defect repair processing. The electro-optical device according to any one of claims 14 to 21, wherein the defect relief processing is wiring processing by laser irradiation. A plurality of scan lines;
A plurality of signal lines orthogonal to the plurality of scanning lines;
A plurality of pixels formed in the vicinity of intersections of the plurality of scanning lines and the plurality of signal lines;
A scanning line driving circuit composed of normal unit shift registers respectively disposed on the first end side of odd lines and the second end side of even lines in the plurality of scanning lines;
An electro-optical device comprising: a relief unit shift register disposed on each of a second end side of odd lines and a first end side of even lines in the plurality of scanning lines. The electro-optical device according to claim 23, wherein
Each of the normal unit shift registers receives a driving signal for a scanning line adjacent to two lines, and activates a driving signal for the corresponding scanning line after a scanning period of two lines from the activation.
Each of the relief unit shift registers receives a driving signal for a scanning line of an adjacent line, and activates the driving signal for the corresponding scanning line after a scanning period of one line from the activation. An electro-optical device. The electro-optical device according to claim 23, wherein
Each of the relief unit shift registers includes:
Input terminal, output terminal and clock terminal;
A first transistor for supplying a clock signal input to the clock terminal to an output terminal;
A second transistor connected between a first node to which a control electrode of the first transistor is connected and the input terminal;
Prior to activation of the input signal input to the input terminal, the second node to which the control electrode of the second transistor is connected is charged, and prior to deactivation of the input signal, the second node is discharged. Charge and discharge circuit,
An electro-optical device, wherein the output terminal and the scanning line are connected by a defect relief process. The electro-optical device according to claim 25,
Each of the relief unit shift registers includes:
A third transistor for discharging the output terminal;
The charge / discharge circuit is
An electro-optical device having a control electrode connected to a power supply of an active level, and a fourth transistor connected between the third node connected to the control electrode of the third transistor and the second node . 27. The electro-optical device according to claim 25, wherein the input signal is a driving signal for a scanning line of an adjacent line. 28. The electro-optical device according to claim 25, wherein the output terminal and the scanning line are connected by defect relief processing. 30. The electro-optical device according to claim 25, wherein the input terminal and a wiring that supplies the input signal to the input terminal are connected by defect relief processing. 30. The electro-optical device according to claim 25, wherein the clock terminal and a wiring that supplies the clock signal thereto are connected by defect repair processing. 31. The electro-optical device according to claim 25, wherein the defect relief process is a wiring processing process by laser irradiation. 26. Each of the normal unit shift registers receives a driving signal for a scanning line adjacent to two lines, and activates the driving signal for the corresponding scanning line after a scanning period of two lines from the activation. 31. The electro-optical device according to any one of 31.

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