JP5094757B2 - Initial reset signal generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an initialization signal generation circuit (initial reset signal generation circuit) configured using only the same conductivity type transistors. <P>SOLUTION: The initial reset signal generation circuit 110, which generates an initial reset signal IRS for initializing a shift register, comprises a pull-up circuit 11 and a pull-down circuit 12. The pull-up circuit 11 activates the initial reset signal IRS in response of casting power. The pull-down circuit 12 deactivates the initial reset signal IRS in response to activation of a start signal ST for starting the operation of the shift register. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a scanning line driving circuit, and in particular, a control signal generating circuit (initial reset signal) for initializing a scanning line driving circuit used in an electro-optical device such as an image display device or an image sensor. Generation circuit).

  In an image display device such as a liquid crystal display device (hereinafter “display device”), a gate line (scanning line) is provided for each pixel row (pixel line) of a display panel in which a plurality of pixels are arranged in a matrix, and a display signal is displayed. The display image is updated by sequentially selecting and driving the gate lines in one horizontal period (1H period). As such a gate line driving circuit (scanning line driving circuit) for sequentially selecting and driving pixel lines, that is, gate lines, a shift register that performs a shift operation that makes a round in one frame period of a display signal can be used. .

  A shift register as a gate line driving circuit is configured by cascading a plurality of shift register circuits provided for each pixel line, that is, for each gate line. In this specification, each of the plurality of shift register circuits constituting the gate line driving circuit is referred to as a “unit shift register”. In other words, the output terminals of the individual unit shift registers constituting the gate line driving circuit are connected not only to the corresponding gate lines but also to the input terminals of the next stage or subsequent stage unit shift registers.

  The shift register used in the gate line driver circuit is preferably configured using only field effect transistors of the same conductivity type in order to reduce the number of steps in the manufacturing process of the display device. For this reason, various shift registers configured using only N-type or P-type field effect transistors and display devices on which the shift registers are mounted have been proposed (for example, Patent Documents 1-6 below).

JP 2007-35188 A JP 2006-60225 A JP 2004-157508 A JP 2006-24350 A JP 2004-295126 A JP 2002-133890 A JP 2007-250052 A

  FIG. 6 of Patent Document 1 shows a circuit diagram of a conventional unit shift register configured using only P-type MOS transistors. The output signal (OUT) of the unit shift register is supplied with the clock signal (C1) to the output terminal through a transistor (T2) (hereinafter referred to as “pull-up transistor”) that sets the output to an active level (here, L (Low) level). Is activated. In particular, since a unit shift register used in a gate line driving circuit drives a gate line having a large load capacity using an output signal, the pull-up transistor is required to have a large driving capability (capability of flowing current). Therefore, the on-resistance of the pull-up transistor is set very low.

  In the normal operation of the shift register (signal shift operation), the pull-up transistors at each stage are turned on in order so that output signals of a plurality of cascaded unit shift registers are sequentially activated one by one. However, when the potential of each node of the circuit is indefinite, for example, immediately after the power is turned on, the pull-up transistors of a plurality of unit shift registers may be turned on. An excessive current flows through a plurality of low pull-up transistors, which is not preferable.

  In the unit shift register of FIG. That is, in the unit shift register, the transistor (T7a) controlled by the initialization signal (SHUT) between the gate of the pull-up transistor and the power source (VDD) of the inactive level (here, H (High) level). (Hereinafter referred to as “initializing transistor”). Prior to normal operation, initialization transistors of all unit shift registers are temporarily turned on using an initialization signal. As a result, in all the unit shift registers, the gate potential of the pull-up transistor is initialized to the inactive level, and is released from the indefinite state. As a result, since all the pull-up transistors are turned off, even if the clock signal is activated, an excessive current does not flow through the plurality of pull-up transistors.

  On the other hand, when an initialization signal is input from the outside as in the unit shift register of FIG. 6 of Patent Document 1, it is necessary to provide an initialization signal generation circuit as an external circuit, leading to an increase in manufacturing cost. There is.

  SUMMARY An advantage of some aspects of the invention is that it provides an initialization signal generation circuit (initial reset signal generation circuit) that can be configured using only transistors of the same conductivity type. .

An initial reset signal generation circuit according to a first aspect of the present invention is formed using only transistors of the same conductivity type, and receives an input terminal that receives a start signal for starting the operation of a shift register, and an initial reset signal is output. An output terminal that is activated, a pull-up circuit that activates the initial reset signal in response to power-on, and a pull-down circuit that deactivates the initial reset signal in response to activation of the start signal. is there.

An initial reset signal generation circuit according to a second aspect of the present invention is formed using only transistors having the same conductivity type, and receives a plurality of clock signals having different phases for defining the operation of the shift register. A clock terminal, an output terminal from which an initial reset signal is output, a pull-up circuit that activates the initial reset signal in response to power-on, and the activation in response to activation of any of the plurality of clock signals And a pull-down circuit for inactivating the initial reset signal.

An initial reset signal generation circuit according to a third aspect of the present invention is formed using only transistors of the same conductivity type, receives an input terminal for starting a shift register operation, and an operation of the shift register A plurality of clock terminals for receiving a plurality of clock signals having different phases, an output terminal for outputting an initial reset signal, and a pull-up for activating the initial reset signal upon power-on A circuit, and a pull-down circuit that deactivates the initial reset signal in response to activation of the start signal, and further sets the output terminal to an inactive level with a low impedance according to activation of each of the plurality of clock signals. It is to be prepared.

An initial reset signal generation circuit according to a fourth aspect of the present invention is formed using only transistors of the same conductivity type, and receives first and second control signals complementary to each other and supplied to a shift register, respectively. A second input terminal, an output terminal for outputting an initial reset signal, a pull-up circuit for activating the initial reset signal in response to power-on, and in response to activation of the first or second control signal And a pull-down circuit for inactivating the initial reset signal.

  Since the initial reset signal generation circuit according to the present invention can be configured using only transistors having the same conductivity type, the increase in the number of manufacturing steps can be suppressed by aligning the conductivity type with the transistors used in the shift register. However, it can be formed on the same substrate as the shift register. Accordingly, this can contribute to a reduction in manufacturing cost of a display device including a gate line driver circuit using a shift register.

It is a figure which shows the structural example of the display apparatus with which this invention is applied. 1 is a block diagram showing an initial reset signal generation circuit and its peripheral circuits according to the present invention. It is a figure which shows the structural example of the gate line drive circuit combinable with the initial stage reset signal generation circuit which concerns on this invention. It is a circuit diagram which shows the example of the unit shift register which comprises a gate line drive circuit. It is a signal waveform diagram showing the operation of the gate line drive circuit. 3 is a circuit diagram of an initial reset signal generation circuit according to the first embodiment. FIG. FIG. 4 is a signal waveform diagram illustrating an operation of the initial reset signal generation circuit according to the first embodiment. 6 is a circuit diagram of an initial reset signal generation circuit according to a first modification of the first embodiment. FIG. 6 is a circuit diagram of an initial reset signal generation circuit according to a second modification of the first embodiment. FIG. FIG. 10 is a circuit diagram of an initial reset signal generation circuit according to a third modification of the first embodiment. FIG. 6 is a circuit diagram of an initial reset signal generation circuit according to a second embodiment. FIG. 10 is a signal waveform diagram illustrating an operation of the initial reset signal generation circuit according to the second embodiment. FIG. 10 is a signal waveform diagram illustrating an operation of an initial reset signal generation circuit according to a first modification example of the second embodiment. FIG. 10 is a diagram illustrating a configuration example of a configuration of a gate line driving circuit according to a first modification example of the second embodiment. FIG. 10 is a circuit diagram of an initial reset signal generation circuit according to a second modification of the second embodiment. FIG. 10 is a signal waveform diagram illustrating an operation of an initial reset signal generation circuit according to a second modification of the second embodiment. 10 is a circuit diagram of an initial reset signal generation circuit according to a third modification of the second embodiment. FIG. FIG. 10 is a circuit diagram of an initial reset signal generation circuit according to a fourth modification example of the second embodiment. FIG. 20 is a circuit diagram of an initial reset signal generation circuit according to a fifth modification example of the second embodiment. FIG. 12 is a signal waveform diagram for illustrating the operation of the fifth modification example of the second embodiment. FIG. 20 is a circuit diagram of an initial reset signal generation circuit according to a sixth modification of the second embodiment. FIG. 6 is a circuit diagram of an initial reset signal generation circuit according to a third embodiment. FIG. 10 is a signal waveform diagram illustrating an operation of the initial reset signal generation circuit according to the third embodiment.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, in order to avoid duplication and redundant description, elements having the same or corresponding functions are denoted by the same reference symbols in the respective drawings.

  The transistor used in each embodiment is an insulated gate field effect transistor. In the insulated gate field effect transistor, the electric conductivity between the drain region and the source region in the semiconductor layer is controlled by the electric field in the gate insulating film. As a material of the semiconductor layer in which the drain region and the source region are formed, an organic semiconductor such as polysilicon, amorphous silicon, or pentacene, an oxide semiconductor such as single crystal silicon or IGZO (In-Ga-Zn-O), or the like is used. be able to.

  As is well known, each transistor has a control electrode (gate (electrode) in the narrow sense), one current electrode (drain (electrode) or source (electrode) in the narrow sense)), and the other current electrode (in the narrow sense, the drain (electrode) or the source (electrode)). In a narrow sense, it is an element having at least three electrodes including a source (electrode) or a drain (electrode). The transistor functions as a switching element in which a channel is formed between the drain and the source by applying a predetermined voltage to the gate. The drain and source of the transistor have basically the same structure, and their names are interchanged depending on the applied voltage condition. For example, in the case of an N-type transistor, an electrode having a relatively high potential is referred to as a drain, and a low electrode is referred to as a source (in the case of a P-type transistor, the opposite is true).

  Unless otherwise specified, these transistors may be formed on a semiconductor substrate, or may be a thin film transistor (TFT) formed on an insulating substrate such as glass. The substrate over which the transistor is formed may be a single crystal substrate or an insulating substrate such as SOI, glass, or resin.

  The initialization circuit (initial reset signal generation circuit) of the present invention is configured using only a single conductivity type transistor. For example, an N-type transistor becomes active (on state, conductive state) when the gate-source voltage becomes H (high) level higher than the threshold voltage of the transistor, and L ( At a low level, it becomes inactive (off state, non-conductive state). Therefore, in a circuit using an N-type transistor, the H level of the signal is “active level” and the L level is “inactive level”. In addition, each node of a circuit configured using an N-type transistor is charged to become an H level, thereby causing a change from an inactive level to an active level, and being discharged to an L level. A change from to inactive level occurs.

  Conversely, a P-type transistor becomes active (on state, conductive state) when the gate-source voltage becomes L level lower than the threshold voltage of the transistor (a negative value with respect to the source). It becomes inactive (OFF state, non-conducting state) at an H level higher than the voltage. Therefore, in a circuit using a P-type transistor, the L level of the signal is “active level” and the H level is “inactive level”. In addition, each node of the circuit configured using the P-type transistor has a charge / discharge relationship opposite to that in the case of the N-type transistor, and is charged to the L level, so that the inactive level changes from the inactive level to the active level. When the change occurs and is discharged to the H level, a change from the active level to the inactive level occurs.

  In this specification, the change from the inactive level to the active level is defined as “pull-up”, and the change from the active level to the inactive level is defined as “pull-down”. That is, in a circuit using an N-type transistor, a change from the L level to the H level is defined as “pull-up”, and a change from the H level to the L level is defined as “pull-down”. A change from the level to the L level is defined as “pull-up”, and a change from the L level to the H level is defined as “pull-down”.

  In this specification, “connection” between two elements, between two nodes, or between one element and one node is a connection through other elements (elements, switches, etc.). In the following description, it is assumed to include a state that is substantially equivalent to a direct connection. For example, even if two elements are connected via a switch, if they can function in the same way as when they are directly connected, the two elements are “connected”. Express.

  In the present invention, clock signals having different phases (multiphase clock signals) are used. In the following, for the sake of simplicity, a certain interval is provided between the active period of one clock signal and the active period of the clock signal to be activated next (for example, the interval Δt in FIG. 5). However, in the present invention, it is sufficient that the active periods of the clock signals do not substantially overlap, and the above-described interval may not be provided. For example, if the activation level is H level, the falling timing of one clock signal and the rising timing of the clock signal to be activated next may be simultaneous.

<Embodiment 1>
FIG. 1 is a schematic block diagram showing a configuration of a display device according to Embodiment 1 of the present invention, and shows an overall configuration of a liquid crystal display device 100 as a representative example of the display device. Note that the gate line driving circuit including the initial reset signal generating circuit of the present invention is not limited to application to a liquid crystal display device, and electroluminescence (EL) including a gate line driving circuit configured by a single conductivity type transistor, The present invention can also be applied to electro-optical devices such as organic EL, plasma display, electronic paper, and image sensor.

  The liquid crystal display device 100 includes a liquid crystal array unit 10, a gate line driving circuit (scanning line driving circuit) 30, and a source driver 40. As will be apparent from the following description, the initial reset signal generation circuit according to the embodiment of the present invention supplies an initial reset signal to the gate line driving circuit 30 (in FIG. 1, the initial reset signal generation circuit is illustrated). Is omitted).

The liquid crystal array unit 10 includes a plurality of pixels 15 arranged in a matrix. Each of the pixel rows (hereinafter also referred to as “pixel lines”) is provided with gate lines GL ₁ , GL ₂ ... (Generically referred to as “gate lines GL”), and each pixel row (hereinafter also referred to as “pixel column”). Are respectively provided with data lines DL ₁ , DL ₂ ... (Generic name “data line DL”). FIG. 1 representatively shows the pixels 15 in the first and second columns of the first row, and the corresponding gate lines GL ₁ and data lines DL ₁ and DL ₂ .

  Each pixel 15 includes a pixel switch element 16 provided between the corresponding data line DL and the pixel node Np, a capacitor 17 and a liquid crystal display element 18 connected in parallel between the pixel node Np and the common electrode node NC. have. The orientation of the liquid crystal in the liquid crystal display element 18 changes according to the voltage difference between the pixel node Np and the common electrode node NC, and the display brightness of the liquid crystal display element 18 changes in response to this. Thus, the luminance of each pixel can be controlled by the display voltage transmitted to the pixel node Np via the data line DL and the pixel switch element 16. That is, by applying an intermediate voltage difference between the voltage difference corresponding to the maximum luminance and the voltage difference corresponding to the minimum luminance between the pixel node Np and the common electrode node NC, the intermediate luminance is reduced. Can be obtained. Therefore, gradation brightness can be obtained by setting the display voltage stepwise.

  The gate line driving circuit 30 sequentially selects and drives the gate lines GL based on a predetermined scanning cycle. The gate electrodes of the pixel switch elements 16 are connected to the corresponding gate lines GL. While a specific gate line GL is selected, the pixel switch element 16 is in a conductive state in each pixel connected to the gate line GL, and the pixel node Np is connected to the corresponding data line DL. The display voltage transmitted to the pixel node Np is held by the capacitor 17. In general, the pixel switch element 16 is composed of a TFT formed on the same insulator substrate (glass substrate, resin substrate, etc.) as the liquid crystal display element 18.

The source driver 40 is for outputting a display voltage, which is set stepwise by a display signal SIG that is an N-bit digital signal, to the data line DL. Here, as an example, the display signal SIG is a 6-bit signal and is composed of display signal bits DB0 to DB5. Based on the 6-bit display signal SIG, 2 ⁶ = 64 gradation display is possible in each pixel. Furthermore, if one color display unit is formed by three pixels of R (Red), G (Green), and B (Blue), approximately 260,000 colors can be displayed.

  As shown in FIG. 1, the source driver 40 includes a shift register 50, data latch circuits 52 and 54, a gradation voltage generation circuit 60, a decode circuit 70, and an analog amplifier 80.

  In the display signal SIG, display signal bits DB0 to DB5 corresponding to the display luminance of each pixel 15 are serially generated. In other words, the display signal bits DB0 to DB5 at each timing indicate the display luminance in any one pixel 15 in the liquid crystal array unit 10.

  The shift register 50 instructs the data latch circuit 52 to take in the display signal bits DB0 to DB5 at a timing synchronized with the cycle at which the setting of the display signal SIG is switched. The data latch circuit 52 sequentially takes in the serially generated display signal SIG and holds the display signal SIG for one pixel line.

  The latch signal LT input to the data latch circuit 54 is activated at the timing when the display signal SIG for one pixel line is taken into the data latch circuit 52. In response thereto, the data latch circuit 54 takes in the display signal SIG for one pixel line held in the data latch circuit 52 at that time.

  The gradation voltage generation circuit 60 is composed of 63 voltage dividing resistors connected in series between the high voltage VDH and the low voltage VDL, and generates 64 gradation voltages V1 to V64, respectively.

The decode circuit 70 decodes the display signal SIG held in the data latch circuit 54 and outputs a voltage to each decode output node Nd ₁ , Nd ₂ ... (Generic name “decode output node Nd”) based on the decode result. Are selected from the gradation voltages V1 to V64 and output.

As a result, at the decode output node Nd, a display voltage (one of the gradation voltages V1 to V64) corresponding to the display signal SIG for one pixel line held in the data latch circuit 54 is simultaneously (in parallel). ) Is output. In FIG. 1, the decode output nodes Nd ₁ and Nd ₂ corresponding to the data lines DL ₁ and DL ₂ in the first column and the second column are representatively shown.

The analog amplifier 80 amplifies the analog voltage corresponding to each display voltage output from the decode circuit 70 to the decode output nodes Nd ₁ , Nd ₂ ... And outputs them to the data lines DL ₁ , DL ₂ .

The source driver 40 repeatedly outputs a display voltage corresponding to a series of display signals SIG to the data line DL for each pixel line based on a predetermined scanning cycle, and the gate line driving circuit 30 is synchronized with the scanning cycle. By sequentially driving the gate lines GL ₁ , GL ₂ ..., An image is displayed on the liquid crystal array unit 10 based on the display signal SIG.

  1 illustrates the configuration of the liquid crystal display device 100 in which the gate line driving circuit 30 and the source driver 40 are integrally formed with the liquid crystal array unit 10, but the gate line driving circuit 30, the liquid crystal array unit 10, and the like. The source driver 40 can be provided as an external circuit of the liquid crystal array unit 10, or the gate line driving circuit 30 and the source driver 40 can be provided as an external circuit of the liquid crystal array unit 10.

  FIG. 2 is a block diagram showing a configuration of a peripheral circuit that supplies power and various control signals to the gate line driving circuit 30.

  The initial reset signal generation circuit 110 generates an initial reset signal IRS for initializing the gate line driving circuit 30. The initial reset signal generation circuit 110 according to the present invention can be configured only by transistors having the same conductivity type as the transistors constituting the gate line driving circuit 30, and is formed on the same substrate (display device substrate) as the gate line driving circuit 30. It is formed.

  On the other hand, the control circuit 120, the high-potential-side power supply 130, the low-potential-side power supply 140, and the level shifter 150 are external control circuits that are externally connected to the display device substrate, and are all semiconductor integrated circuits formed on the single crystal silicon substrate. It is.

  The control circuit 120 generates a start signal st for defining the operation timing of the gate line driving circuit 30 and two-phase clock signals clk and / clk. The level shifter 150 adjusts the levels of the start signal st and the clock signals clk, / clk, and the start signal ST at a level that can be used by the circuits (gate line driving circuit 30 and initial reset signal generation circuit 110) on the display device substrate. Also, the signal is converted into clock signals CLK and / CLK.

  The high potential side power supply 130 and the low potential side power supply 140 are connected to the gate line driving circuit 30, the initial reset signal generation circuit 110, and the level shifter 150, respectively, by a high potential side power supply potential (hereinafter referred to as “high side power supply potential”) VDD and a low potential. A side power supply potential (hereinafter referred to as “low side power supply potential”) VSS is supplied. More specifically, each of the high-potential-side power supply 130 and the low-potential-side power supply 140 is configured by a charge pump circuit that operates by receiving a drive signal from the control circuit 120, for example.

  Normally, the start signal st and the clock signals clk, / clk generated by the control circuit 120 have a small amplitude, and the level shifter 150 functions to amplify them into the start signal ST and the clock signals CLK, / CLK having a large amplitude. In the following description, it is assumed that the start signal ST and the clock signals CLK, / CLK output from the level shifter 150 have an L level potential equal to the low side power supply potential VSS and an H level potential equal to the high side power supply potential VDD. .

  The values of the high-side power supply potential VDD and the low-side power supply potential VSS in actual use are set such that the high-side power supply potential VDD is 17V, the low-side power supply potential VSS is −12V, for example, with reference to the ground level (GND = 0V). The

  Clock signals CLK and / CLK (and clock signals clk and / clk) are two-phase clock signals having different phases (the active periods do not overlap). The clock signals CLK and / CLK are controlled to be activated alternately at a timing synchronized with the scanning period of the display device. The start signal ST (and the start signal st) is for causing the gate line driving circuit 30 to start the shift operation of the gate line selection signal, and is activated at a timing corresponding to the head of each frame period of the image signal. Pulse signal. Therefore, the cycle of the start signal ST becomes the operation cycle of the gate line driving circuit 30.

  In the above description, it is assumed that the high-potential-side power supply 130, the low-potential-side power supply 140, and the level shifter 150 are semiconductor integrated circuits formed on a single crystal silicon substrate, like the control circuit 120. However, if the transistors of the gate line driving circuit 30 are formed of low temperature polysilicon or oxide semiconductor having a relatively large charge carrier mobility, these are indicated by the gate line driving circuit on the display device substrate. 30 may be formed integrally.

FIG. 3 is a diagram showing a configuration example of the gate line driving circuit 30 to which the initial reset signal generation circuit 110 according to the present invention is applied. The gate line driving circuit 30 includes a shift register composed of a plurality of unit shift registers SR ₁ , SR ₂ , SR ₃ , SR ₄ ... Connected in cascade (cascade connection) (for convenience of explanation, the shift register circuit SR). ₁ , SR ₂ ... Are collectively referred to as “unit shift register SR”). The unit shift register SR is provided for each pixel line, that is, for each gate line GL.

An example of the unit shift register SR constituting the gate line driving circuit 30 of FIG. 3 is shown in FIG. Since all the unit shift registers SR constituting the gate line driving circuit 30 have the same configuration, FIG. 4 representatively shows the k-th stage unit shift register SR _k .

In the gate line driving circuit 30 of FIG. 3, a dummy unit shift register SRD (hereinafter referred to as “dummy stage”) that is not connected to the gate line is provided further to the next stage of the last unit shift register SR _n . Basically, the dummy stage SRD also has the same configuration as the other unit shift registers SR.

  The unit shift register SR of FIG. 4 includes transistors Q51 to Q58, which are N-type TFTs, and a capacitive element C51, and includes an input terminal IN, an output terminal OUT, a clock terminal CKT, a reset terminal RST, an initial reset terminal IRT, 1 power supply terminal S1 and 2nd power supply terminal S2 are included (in FIG. 3, illustration of 1st and 2nd power supply terminal S1, S2 is abbreviate | omitted). The low power supply potential VSS generated by the low potential power supply 140 is supplied to the first power supply terminal S1, and the high power supply potential VDD generated by the high potential power supply 130 is supplied to the second power supply terminal S2.

  A transistor Q51 is connected between the clock terminal CKT and the output terminal OUT, and a transistor Q52 is connected between the output terminal OUT and the first power supply terminal S1. A node to which the gate of the transistor Q51 is connected is defined as “node N51”, and a node to which the gate of the transistor Q52 is connected is defined as “node N52”. The capacitive element C51 is connected between the output terminal OUT and the node N51.

  The transistor Q53 has a gate connected to the input terminal IN, and is connected between the node N51 and the second power supply terminal S2. The transistor Q54 has a gate connected to the reset terminal RST, and is connected between the node N51 and the first power supply terminal S1.

  The transistor Q56 is connected between the node N52 and the second power supply terminal S2, and the gate is connected to the second power supply terminal S2 (that is, the transistor Q56 is diode-connected between the second power supply terminal S2 and the node N52). ing). Transistor Q57 is connected between node N52 and first power supply terminal S1, and has its gate connected to node N51. The transistor Q57 is set to have an on-resistance sufficiently smaller than that of the transistor Q56, and these transistors Q56 and Q57 constitute a ratio type inverter having the node N51 as an input terminal and the node N52 as an output terminal.

  4 includes a transistor Q58 having a gate connected to the initial reset terminal IRT and connected between the node N51 and the first power supply terminal S1. The transistor Q58 is for initializing the nodes N51 and N52 to a specific level based on the initial reset signal IRS output from the initial reset signal generation circuit 110.

Referring again to FIG. 3, one of the clock signals CLK and / CLK is input to the clock terminal CKT of each unit shift register SR. Specifically, the clock signal CLK is supplied to the odd-numbered unit shift registers SR ₁ , SR ₃ , SR ₅ ..., And the clock signal / CLK is supplied to the even-numbered unit shift registers SR ₂ , SR ₄ , SR ₆ . Is done.

In the example of Figure 3 the unit shift register SR _n of the n-th stage is the last stage (stage n) and even-numbered stages, the unit shift register SR _n, the clock signal / CLK is supplied. Therefore, the dummy stage SRD is an odd number stage, and the clock signal CLK is supplied to the clock terminal CK.

The input terminal IN of the unit shift register SR ₁ is a first stage (first stage), the start signal ST is input. The input terminal IN of each unit shift register SR after the second stage is connected to the output terminal OUT of the preceding stage.

The reset terminal RST of each unit shift register SR is connected to the output terminal OUT at the next stage. However, the reset terminal RST of the unit shift register SR _n of the last stage, the output signal GD of the dummy stage SRD is input. A clock signal / CLK having a phase different from that of the clock signal CLK input to the clock terminal CK is input to the reset terminal RST of the dummy stage SRD.

That is, the output signal G _k output from the output terminal OUT of the _k-th unit shift register SR _k is supplied to the corresponding gate line GL _k as a vertical (or horizontal) scanning pulse, and at the next stage. The signal is supplied to an input terminal IN of a certain unit shift register SR _{k + 1} and a reset terminal RST of the unit shift register SR _k-1 which is the preceding stage.

  FIG. 5 is a signal waveform diagram for explaining the operation of the unit shift register SR of FIG. The operation of the unit shift register SR will be described with reference to FIG. For simplicity of explanation, it is assumed that the threshold voltages of all the transistors are equal and the value is Vth.

In FIG. 5, time t ₀ is when the power to the gate line driving circuit 30 is turned on. That is, at time t ₀ , the output potential of the high potential side power supply 130 changes to VDD and the output potential of the low potential side power supply 140 changes to VSS. At this time, the control circuit 120 and the level shifter 150 are also turned on.

Until time t ₀ , the level of the node N51 (gate of the transistor Q51) of each unit shift register SR is indefinite. If the node N51 is at the H level in the plurality of unit shift registers SR, the transistors Q51 are simultaneously turned on. Therefore, when the clock signals CLK and / CLK are activated as they are, the plurality of transistors having low on-resistances. Since an excessive current flows through Q51, it is not preferable.

The initial reset signal generation circuit 110 according to the present invention activates the initial reset terminal IRT when the power is turned on at time t ₀ (details will be described later). When the initial reset signal IRS is activated, the transistors Q58 are turned on in all the unit shift registers SR, and the node N51 is initialized to the L level (VSS). Responsively, transistor Q57 is turned off, and node N52 is charged by the current flowing through transistor Q56, and initialized to H level (VDD-Vth).

  By this initialization operation, in all the unit shift registers SR, the node N51 becomes L level, the node N52 becomes H level, the transistor Q51 is turned off, and the transistor Q52 is turned on (this state is referred to as “reset state”). ). Therefore, the output signals G of all the unit shift registers SR are initialized to L level. Further, after the initialization operation, even if the clock signals CLK and / CLK are activated, the transistors Q51 of all the unit shift registers SR are turned off, so that no excessive current flows through the plurality of transistors Q51.

  This state is maintained even when the initial reset signal IRS returns to the inactive level (L level). This is because the transistors Q55, Q56, and Q57 of each unit shift register SR constitute a half latch circuit, whereby the levels of the nodes N51 and N52 are held.

  Thereafter, when the control circuit 120 activates the start signal ST and the clock signals CLK and / CLK through the level shifter 150, each unit shift register SR starts a normal operation (shift operation of the gate line selection signal). When the unit shift register SR performs a normal operation, the initial reset signal generation circuit 110 fixes the initial reset signal IRS at an inactive level. Hereinafter, the normal operation of the unit shift register SR will be described.

Referring to FIG. 5, at time t _1, the initial reset signal IRS becomes L level, the transistor Q58 of all the unit shift register SR is turned off. At this time, the start signal ST becomes the active level (H level).

Then the unit shift register SR ₁ of the first stage, the transistor Q53 is turned on. At this time, the transistor Q55 is also in the on state, but the transistor Q53 is set to have a sufficiently lower on-resistance than the transistor Q55, and the node N51 is at the H level (VDD-Vth). Since the transistor Q57 is turned on when the node N51 becomes H level, the node N52 becomes L level (hereinafter, this state is referred to as “set state”).

In the set state, the transistor Q51 is turned on, becomes a transistor Q52, Q55 is off, since at this point the clock signal CLK is inactive level (L level), the output signal G ₁ remains at the L level (VSS) is there.

When the start signal ST goes to L level at time t _2, the although the unit shift register SR ₁ in the transistor Q53 is turned off, the transistor Q55, Q58 is also turned off, the node N51 is a high impedance state (floating state) H Maintained at level. Therefore, transistor Q57 is maintained in the on state, and node N52 is maintained at the L level. That is, the set state of the unit shift register SR ₁ is maintained.

When the clock signal CLK changes to H level (VDD) at time t ₃ , the level change is transmitted to the output terminal OUT through the transistor Q51 in the on state, and the output signal G ₁ becomes H level. As a result, the gate line GL ₁ is selected.

When the level of the output terminal OUT (output signal G ₁ ) rises, the potential change is transmitted to the node N51 by coupling via the capacitive element C1, and the level of the node N51 rises. Due to the boosting effect of the node N51, the transistor Q51 can operate in the non-saturated region. Therefore, the H level potential of the output signal G ₁ rises to the same VDD as the H level of the clock signal CLK.

Thereafter, when the clock signal CLK changes to L level (VSS) at time t ₄ , the output terminal OUT is discharged through the transistor Q51 in the on state in the unit shift register SR ₁ . Therefore, the output signal G ₁ becomes L level.

Here, since the output signal G ₁ is supplied to the input terminal IN of the second stage unit shift register SR ₂ , when the output signal G ₁ becomes H level at the time t ₃ , the unit shift register. SR ₂ is in the set state.

Therefore, when the clock signal / CLK becomes H level at time t ₅ , the second-stage output signal G ₂ becomes H level. Since the output signal G ₂ is supplied to the reset terminal RST of the unit shift register SR _1, the unit shift register SR _1, the transistor Q54 is turned on, the L-level node N51 is discharged. Accordingly, transistor Q57 is turned off, so that node N52 is charged by transistor Q56 and becomes H level. That is, the unit shift register SR ₁ returns to the reset state, the transistor Q51 of the unit shift register SR ₁ is turned off, and the transistor Q52 is turned on.

Thereafter, the unit shift register SR ₁ is maintained in the reset state until the start signal ST becomes H level in the next frame period. This is because the half latch circuit composed of transistors Q55, Q56, and Q57 holds the levels of nodes N51 and N52. Meanwhile, since the transistor Q52 is on, the output terminal OUT is maintained at the L level with low impedance.

The operation of the first stage unit shift register SR ₁ has been described above. In the gate line driving circuit 30 of FIG. 2, the second and subsequent unit shift registers SR and dummy stage SRD operate in the same manner.

That is, the second and subsequent unit shift registers SR _k enter the set state in response to the activation of the output signal G _{k-1 in} the previous stage, and at that time, the unit shift register SR _k self activates the output signal G _k of, then, to maintain the output signal G _k returns to the reset state in response to activation of the next stage output signal G _{k + 1} to L level. Incidentally, the unit shift register SR _n of the last stage, is in a reset state in response to activation of the output signal GD of the dummy stage SRD, dummy stage SRD is in a reset state in response to activation of the clock signal / CLK.

Therefore, in the gate line drive circuit 30, and the activation of the start signal ST is input to the unit shift register SR ₁ a trigger, the clock signal CLK, / output signal at a timing synchronized with the _{CLK G 1, G 2, G} 3 ... are activated sequentially. Accordingly, the gate line driving circuit 30 can sequentially drive the gate lines GL ₁ , GL ₂ , GL ₃ ... With a predetermined scanning cycle.

  Note that the unit shift register SR to which the initial reset signal generation circuit 110 according to the present invention can be applied is not limited to that shown in FIG. 4, and performs an initialization operation according to a predetermined pulse signal (initial reset signal IRS). If it is.

  FIG. 6 is a circuit diagram of the initial reset signal generation circuit 110 according to the first embodiment of the present invention. As described above, the initial reset signal generation circuit 110 is configured using a transistor having the same conductivity type as that of the gate line driving circuit 30. In this embodiment, it is assumed that the unit shift register SR of the gate line driving circuit 30 is configured using N-type TFTs as shown in FIG. 4, and the initial reset signal generation circuit 110 is also configured by N-type TFTs. It will be described as a thing. Here again, it is assumed that the threshold voltages of the transistors are all equal, and the value is Vth.

  As shown in FIG. 6, the initial reset signal generation circuit 110 includes a pull-up circuit 11 and a pull-down circuit 12. The pull-up circuit 11 activates the initial reset signal IRS, and the pull-down circuit 12 deactivates the initial reset signal IRS and maintains the inactive level thereafter.

  The pull-up circuit 11 includes a transistor Q1 and a capacitive element C1. The transistor Q1 is connected between the output terminal IOUT of the initial reset signal IRS and the second power supply terminal S2 to which the high-side power supply potential VDD is supplied. Here, a node to which the gate (control electrode) of the transistor Q1 is connected is defined as “node N1”.

  The capacitive element C1 is connected between the node N1 and the second power supply terminal S2. The capacitive element C1 has a function of capacitively coupling between the node N1 and the second power supply terminal S2, and transmitting a potential change at the rising of the high-side power supply potential VDD (output of the high-potential side power supply 130) to the node N1. To do.

  The pull-down circuit 12 is composed of transistors Q2 to Q7. The transistor Q2 is connected between the output terminal IOUT and the first power supply terminal S1, and its gate is connected to the start signal input terminal SIN that receives the start signal ST. The transistor Q3 has a gate connected to the start signal input terminal SIN, and is connected between the node N1 and the first power supply terminal S1.

  The transistors Q6 and Q7 are connected in series between the second power supply terminal S2 and the first power supply terminal S1. When a connection node between the transistors Q6 and Q7 is defined as “node N2,” the transistor Q6 is connected between the node N2 and the second power supply terminal S2, and the gate is connected to the second power supply terminal S2 (that is, the transistor Q6). Is diode-connected between the second power supply terminal S2 and the node N2). Transistor Q7 is connected between node N2 and first power supply terminal S1, and has its gate connected to node N1.

  The transistor Q7 has an on-resistance set sufficiently lower than that of the transistor Q6, and these transistors Q6 and Q7 constitute a ratio type inverter having the node N1 as an input terminal and the node N2 as an output terminal. The transistor Q6 only needs to prevent the level of the node N2 from being lowered due to a leakage current generated in the transistor Q7 when the transistor Q7 is turned off, and its current driving capability may be low (ON resistance may be high).

  In the inverter, the transistor Q6 functions as a load element and the transistor Q7 functions as a drive element. The load element of the inverter may be a current driving element, and for example, a resistance element or a constant current element may be used instead of the transistor Q6. The same applies to the following modified examples.

  The transistor Q4 is connected between the output terminal IOUT and the first power supply terminal S1, and the gate is connected to the node N2. The transistor Q5 is connected between the node N1 and the first power supply terminal S1, and the gate is connected to the node N2.

  FIG. 7 is a signal waveform diagram for explaining the operation of the initial reset signal generation circuit 110 according to the present embodiment. Note that the times shown in FIG. 7 correspond to those shown in FIG. Hereinafter, the operation of the initial reset signal generation circuit 110 will be described with reference to FIG.

During a period prior to the time t _{0 when the} power is turned on (period when the power is shut off), the output of the high potential side power supply 130 (high potential side power supply output) and the output of the low potential side power supply 140 (low potential side) The potentials of the power supply output), the start signal ST and the clock signals CLK and / CLK are set to the ground level (GND = 0V).

When the power is turned on at time t ₀ , the output of the high potential side power supply 130 rises from the ground level to the potential VDD, and the output of the low potential side power supply 140 falls from the ground level to the potential VSS. As a result, the power supply potentials VDD and VSS are also supplied to the level shifter 140, the initial reset signal generation circuit 110, and the gate line driving circuit 30.

  When the power is turned on, the control circuit 120 sets the start signal st and the clock signals clk and / clk to the L level, so that the start signal ST and the clock signals CLK and / CLK output through the level shifter 150 become the potential VSS.

  Therefore, in the initial reset signal generation circuit 110, the start signal input terminal SIN is at L level (VSS), and the transistors Q2 and Q3 are turned off. Therefore, when the output of the high-potential-side power supply 130 supplied to the second power supply terminal S2 rises to the potential VDD, the node N1 is boosted to the H level due to the coupling through the capacitive element C1. Accordingly, transistors Q1 and Q7 are turned on.

  On the other hand, when the potential of the second power supply terminal S2 becomes VDD, the transistor Q6 is also turned on. However, since the on-resistance of the transistor Q7 is set to be sufficiently smaller than that of the transistor Q6, the node N2 becomes L level. Accordingly, transistors Q5 and Q4 are turned off.

Incidentally, rise in the potential of the node N1 at time t ₀ (step-up amount) is determined by the ratio of the parasitic capacitance values of the node N1 of the capacitor C1. If the capacitance value of the capacitive element C1 is set sufficiently larger than the parasitic capacitance value of the node N1, the boosting amount of the node N1 becomes almost the same as the level change amount of the second power supply terminal S2, and the level of the node N1 is almost equal to the potential VDD. To rise. The potential of the node N2 is determined by the on-resistance ratio of the transistors Q6 and Q7. If the on-resistance of the transistor Q7 is sufficiently small, the potential of the node N2 is almost equal to the potential VSS.

Thus, at time t ₀ , the transistor Q1 is turned on and the transistors Q2 and Q4 are turned off, so that the output terminal IOUT is charged by the transistor Q1 and becomes H level (VDD−Vth). That is, the initial reset signal IRS is activated. By the activation of the initial reset signal IRS, the above-described initialization operation of each unit shift register SR is performed in the gate line driving circuit 30, and an excessive current flows through the transistors Q51 of the plurality of unit shift registers SR. Is prevented.

Thereafter, when the start signal ST becomes H level (VDD) at time t _1, the transistors Q2, Q3 are turned on. Node N1 is discharged through transistor Q3 and goes to L level, thereby turning off transistor Q1. Further, the output terminal IOUT is discharged through the transistor Q2 and becomes L level, and the initial reset signal IRS is deactivated.

Here, the turn-on of the transistor Q2 is almost the same as the turn-on of the transistor Q3, but the turn-off of the transistor Q1 is delayed by the time required for discharging the node N1. Therefore, at time t ₁ , a through current flowing from the second power supply terminal S2 to the first power supply terminal S1 through the transistors Q1 and Q2 is transiently generated. However, the through current does not occur in the steady state after the transistor Q1 is turned off.

  When the node N1 becomes L level, the transistor Q7 is turned off, and the node N2 is charged by the transistor Q6 and becomes H level (VDD-Vth). Accordingly, transistors Q4 and Q5 are turned on. Since the output terminal IOUT and the node N1 are already at the L level when the transistors Q2 and Q3 are turned on, the level of the output terminal IOUT and the node N1 is not changed when the transistors Q4 and Q5 are turned on.

When the start signal ST becomes L level (VSS) at time t _2, the transistors Q2, Q3 are turned off. However, since the node N2 does not change from the H level, the transistors Q4 and Q5 are kept on. Therefore, the output terminal IOUT and the node N1 are maintained at the L level (VSS) with low impedance.

  Thereafter, the transistors Q2 and Q3 are turned on every time the start signal ST is activated for each frame period, but the levels of the output terminal IOUT and the nodes N1 and N2 are not changed. Therefore, the initial reset signal IRS is maintained at the L level while the gate line driving circuit 30 performs the normal operation. This state continues until the display device is powered off.

Note that the clock signals CLK and / CLK are not output until the initialization operation of the unit shift register SR is completed, that is, from the time when the power is turned on (time t ₀ ) until the end of the active period of the initial reset signal IRS (time t ₁ ). It is preferably maintained at an activity level. By doing so, it is possible to prevent a malfunction caused by the unit shift register SR in an unstable state before initialization and an excessive current from flowing through the transistors Q1 of the plurality of unit shift registers SR in an unstable state.

  As described above, since the initial reset signal generation circuit 110 according to the present embodiment is configured using only N-type transistors, the unit shift register SR (for example, similarly configured only with N-type transistors) (for example, 6), the gate line driving circuit 30 can be easily formed on the same substrate. That is, the initial reset signal generation circuit 110 can be formed on the same substrate as the gate line driving circuit 30 while suppressing an increase in the number of manufacturing steps, which can contribute to a reduction in manufacturing cost.

[First change example]
FIG. 8 is a circuit diagram of the initial reset signal generation circuit 110 according to the first modification of the first embodiment. The initial reset signal generation circuit 110 is different from the circuit of FIG. 6 in that the transistors Q2 and Q3 are omitted and a transistor Q8 is connected between the node N2 and the second power supply terminal S2. The gate of the transistor Q8 is connected to the start signal input terminal SIN. The transistor Q8 is set to have a sufficiently smaller on-resistance than the transistor Q7.

The operation of the initial reset signal generation circuit 110 in FIG. 8 is basically the same as the circuit in FIG. 6, and the level transition of each node is also the same as in FIG. However, in the initial reset signal generation circuit 110 of this modification example, the operation during the period from time t ₁ to t ₂ when the start signal ST is activated is as follows.

That is, when the start signal ST becomes H level at time t _1, the transistor Q8 is turned on. At this time, the transistor Q7 is also on, but the on-resistance value of the transistor Q8 is sufficiently smaller than that of the transistor Q7, so that the node N2 is at the H level (VDD-Vth). Responsively, transistors Q4 and Q5 are turned on, and output terminal IOUT and node N1 attain L level. Therefore, the transistor Q7 is turned off.

When the At time t ₂ the start signal ST returns to the L level (VSS), the transistor Q8 is turned off, the transistor Q7 is turned off, the node N2 by the transistor Q6 in the on state is maintained at the H level . Thus also the time t ₂ after transistor Q4, Q5 is kept turned on, the output terminal IOUT, and the node N1 is kept at the L level (VSS) with low impedance.

  Thereafter, every time the start signal ST is activated for each frame period, the start signal input terminal SIN becomes H level (VDD) (at this time, the gate-source voltage of the transistor Q8 becomes the threshold voltage Vth). Therefore, the transistor Q8 is in an on / off boundary state), and there is no level change in the output terminal IOUT and the nodes N1 and N2. Therefore, the initial reset signal IRS is maintained at the L level until the power of the display device is shut off.

  According to this modification, the initial reset signal generation circuit 110 can be configured with fewer transistors than the circuit of FIG. Note that the drain of the transistor Q8 may be connected to the start signal input terminal SIN together with the gate. That is, the transistor Q8 may be diode-connected between the start signal input terminal SIN and the node N2.

[Second modification]
FIG. 9 is a circuit diagram of the initial reset signal generation circuit 110 according to the second modification of the first embodiment. The initial reset signal generation circuit 110 is different from the circuit of FIG. 8 in that a transistor Q3 having a gate connected to the start signal input terminal SIN is provided between the node N1 and the first power supply terminal S1. In other words, the initial reset signal generation circuit 110 in FIG. 9 is different from the circuit in FIG. 6 in that only the transistor Q2 is omitted and a transistor Q8 is provided. However, as will be described later, in this modification, the transistor Q8 does not need to be set to have a smaller on-resistance than the transistor Q7.

The operation of the initial reset signal generation circuit 110 of FIG. 9 is almost the same as that of the circuit of FIG. 8, but when the start signal ST becomes H level (time t ₁ ), the transistor Q3 is turned on and the node N1 is L level. Therefore, the transistor Q7 is turned off at that time. Therefore, the node N2 is at the H level regardless of the on resistance of the transistors Q7 and Q8.

  That is, in this modified example, the on-resistance value of the transistor Q7 may be set regardless of the on-resistance value of the transistor Q8. Further, since the on-resistance of the transistor Q8 may be high, the gate width can be reduced, which can contribute to the reduction of the area occupied by the circuit.

When the start signal ST becomes H level (time t ₁ ), the transistor Q3 is turned on in the non-saturated region, whereas the transistor Q8 is turned on in the saturated region. Therefore, the discharging speed of node N1 by transistor Q3 is faster than the charging speed of node N2 by transistor Q8. As a result, the turn-on of the transistor Q2 and the turn-off of the transistor Q1 become almost simultaneous, and the through current flowing through the transistors Q1 and Q4 is reduced.

  In this modified example, the drain of the transistor Q8 may be connected to the start signal input terminal SIN together with the gate.

[Third Modification]
In actual use, the display device may be turned on and off at relatively short intervals. For example, when the display device is performing a normal operation, the power is cut off for some reason, and the power is turned on again immediately thereafter.

  In the circuit of FIG. 6, when the power supply is cut off, the node N2 enters a high impedance state, so that it does not immediately return to the ground level, and the H level (VDD-Vth) of the node N2 is maintained for a certain period thereafter. If the power is turned on again in this state, boosting of the node N1 by the capacitive element C1 is started with the transistor Q5 turned on. Therefore, the charge of the node N1 is discharged through the transistor Q5 during the boosting process, and the node N1 cannot be set to a sufficiently high level. As a result, the driving capability of the initial reset signal IRS is lowered, and the H level potential of the initial reset signal IRS is lowered, so that there is a concern that each unit shift register SR cannot perform a normal initialization operation.

  FIG. 10 is a circuit diagram of an initial reset signal generation circuit 110 according to a third modification of the first embodiment. The initial reset signal generation circuit 110 is obtained by connecting a transistor Q9 whose gate is connected to the node N2 between the node N2 and the second power supply terminal S2 to the circuit of FIG. That is, the transistor Q9 is diode-connected so that the node N2 side is an anode and the second power supply terminal S2 side is a cathode, and functions as a unidirectional element whose forward direction is from the node N2 to the second power supply terminal S2. .

  In the circuit of FIG. 10, when the power supply is cut off and the second power supply terminal S2 becomes the ground level (GND = 0V), the transistor Q9 immediately discharges the node N2, and the potential of the node N2 becomes GND + Vth = Vth. Even when the power is turned on in this state, the transistor Q5 is hardly turned on, and the node N1 rises to the potential VDD when boosted by the capacitive element C1. Therefore, the above problem can be avoided.

  The transistor Q9 can also be applied to the circuits of the first and second modified examples (FIGS. 8 and 9), and the same effect as described above can be obtained.

<Embodiment 2>
FIG. 11 is a circuit diagram of the initial reset signal generation circuit 110 according to the second embodiment of the present invention. In the initial reset signal generation circuit 110, the pull-down circuit 12 is driven by the clock signals CLK and / CLK.

  That is, the pull-down circuit 12 of the present embodiment includes transistors Q2A, Q2B, Q3A, and Q3B controlled by the clock signals CLK and / CLK. Note that the configuration of the pull-up circuit 11 is the same as that of the first embodiment (FIG. 6).

  As shown in FIG. 11, the transistors Q2A and Q2B are respectively connected between the output terminal IOUT and the first power supply terminal S1, and the transistors Q3A and Q3B are respectively connected to the node N1 (the gate of the transistor Q1) and the first power supply terminal S1. Connected between. The gates of the transistors Q2A and Q3A are connected to the first clock terminal CK1 to which the clock signal CLK is supplied, and the gates of the transistors Q2B and Q3B are connected to the second clock terminal CK2 to which the clock signal / CLK is supplied.

  FIG. 12 is a signal waveform diagram for explaining the operation of the initial reset signal generation circuit 110 according to the present embodiment. Hereinafter, the operation of the initial reset signal generation circuit 110 in FIG. 11 will be described with reference to FIG.

When power is turned on at time t ₀ , the clock signals CLK and / CLK are at the L level (VSS), so that the transistors Q2A, Q2B, Q3A, and Q3B are all off. At this time, since the output of the high potential side power supply 130 (high potential side power supply output) changes from the ground level (GND) to the potential VDD, the level of the node N1 becomes approximately VDD due to the coupling through the capacitive element C1. Accordingly, the transistor Q1 is turned on, and the output terminal IOUT is charged and becomes H level (VDD-Vth), whereby the initial reset signal IRS is activated.

When the clock signal / CLK becomes H level at time t _1, the transistors Q2B, since Q3B is turned on, the node N1 and the output terminal IOUT is formed by discharged to L level (VSS). Therefore, the initial reset signal IRS is deactivated.

A transistor Q2B time t _1, the result of Q3B is turned on, the node N1 and the output terminal IOUT becomes L level with low impedance. Thereafter, the node N1 and the output terminal IOUT is at time t ₂ when the clock signal / CLK becomes L level, the transistor Q2B, Q3B but becomes L level temporarily high impedance to OFF, the clock signal CLK at time t ₃ When H becomes H level, the transistors Q2A and Q3A are turned on, so that the level immediately returns to L level with low impedance. Further the node N1 and the output terminal IOUT is the clock signal CLK becomes L level at time t ₄ when the transistors Q2A, Q3A but becomes L level of high impedance to off, at time t ₅ to the clock signal / CLK is at H level Then, since the transistors Q2B and Q3B are turned on, the low impedance L level is restored.

  Thereafter, the node N1 and the output terminal IOUT are in a low impedance state during the active period of the clock signals CLK and / CLK, and are in a high impedance state during the active period of the clock signals CLK and / CLK (interval Δt in FIG. 5). It remains at the L level. For example, the gate line driving circuit 30 can be normally operated except for an exceptional case where the output terminal IOUT changes to H level due to the influence of noise when the output terminal IOUT enters a high impedance state.

  Incidentally, an amorphous silicon (a-Si) TFT is known as a thin film transistor (TFT) constituting the gate line driving circuit 30. When the initial reset signal generation circuit 110 is formed on the same substrate as the gate line driving circuit 30 configured by a-Si TFTs, the initial reset signal generation circuit 110 is also generally configured by a-Si.

  The a-Si TFT tends to shift the threshold voltage when the gate is continuously (directly) biased with respect to the source. For example, when the gate of an N-type a-Si TFT is continuously positively biased, the threshold voltage is shifted in the positive direction, and the driving capability of the TFT is reduced (ON resistance is increased).

  In the initial reset signal generation circuit 110 (FIG. 6) of the first embodiment, once the initial reset signal IRS is activated when the power is turned on, the node N2 continues to be at the H level until the power is turned off, so that the transistor Q4 , Q5 are a-Si TFTs, their threshold voltages are shifted in the positive direction, and the on-resistances of the transistors Q4, Q5 are increased. Then, during normal operation of the gate line driving circuit 30, the output terminal IOUT and the node N1 of the initial reset signal generation circuit 110 are in a high impedance state, and an erroneous signal of the initial reset signal IRS is likely to occur due to the influence of noise or the like. It becomes a problem.

  On the other hand, in the initial reset signal generation circuit 110 of FIG. 11, the gates of all the transistors Q2A, Q2B, Q3A, and Q3B constituting the pull-down circuit 12 are AC-driven by the clock signals CLK and / CLK having a duty ratio of about 50%. Biased. For this reason, the shift of the threshold voltage can be suppressed, and an increase in on-resistance can be suppressed.

  Since the transistor Q1 of the pull-up circuit 11 operates as a source follower when charging the output terminal IOUT, its gate-source voltage is biased only to the same extent as its threshold voltage Vth. Therefore, even if the transistor Q1 is an a-Si TFT, the threshold voltage does not shift.

  As described above, the initial reset signal generation circuit 110 in FIG. 11 can suppress the shift of the threshold voltage of each transistor of the pull-down circuit 12 even when the initial reset signal generation circuit 110 is configured using the a-Si TFT. Therefore, it becomes easy to form the initial reset signal generation circuit 110 on the same substrate as the gate line driving circuit 30 configured by a-Si TFTs.

[First change example]
In the example shown in FIG. 12, the first active period of the clock signal / CLK is made the same as the active period of the start signal ST, but one pulse of the clock signal / CLK does not affect the operation of the gate line driving circuit 30. The first active period of the clock signal / CLK may be delayed by one period (two horizontal periods). FIG. 13 is a signal waveform diagram showing an operation of initial reset signal generation circuit 110 in FIG. 11 when the first active period of clock signal / CLK is delayed by one cycle.

When the initial reset signal generation circuit 110 of FIG. 11 is used, if the initial activation period of the clock signal / CLK is delayed by one cycle, the timing at which the initial reset signal IRS is deactivated is the transistors Q2A and Q3A are turned on first. That is, when the clock signal CLK is first activated (time t ₃ ). That is, the timing at which the initial reset signal IRS is deactivated is delayed by one horizontal period compared to the case of FIG.

When the level of the initial reset signal IRS changes as shown in FIG. 13, for example, in the gate line driving circuit 30 configured as shown in FIG. 3 using the unit shift register SR shown in FIG. In the unit shift register SR ₁ , both transistors Q53 and Q58 are turned on. Therefore not charged node N51 is sufficiently unit shift register SR _1, the problem that the driving capability of the transistor Q51 is lowered.

In order to use the initial reset signal IRS having the waveform as shown in FIG. 13 without causing this problem, the initial reset signal IRS is not supplied to the first stage unit shift register SR ₁ as shown in FIG. The gate line driving circuit 30 may be configured. In this case, the unit shift register SR ₁ does not perform the initialization operation based on the initial reset signal IRS. However, prior to the first activation of the clock signal CLK, the unit shift register SR ₁ does not respond to the start signal ST. It is not a problem because it goes out of a stable state (becomes a set state).

[Second modification]
The clock signals CLK and / CLK used for driving the pull-down circuit 12 in FIG. 11 (each of which has a period of two horizontal periods) are the start signals ST (cycles) used for driving the pull-down circuit 12 of the first embodiment (FIG. 6). 11 has a higher frequency than (one frame period), the power consumption of the initial reset signal generation circuit 110 in FIG. 11 is relatively large.

  The two signals for driving the pull-down circuit 12 of the initial reset signal generation circuit 110 in FIG. 11 are not necessarily the clock signals CLK and / CLK, and may be alternating signals complementary to each other. Therefore, power consumption can be reduced by using complementary signals having a frequency lower than that of the clock signals CLK and / CLK.

  For example, in the unit shift register SR of FIG. 7 of Patent Document 7 invented by the present inventor, the signals are alternated every frame (that is, every operation cycle of the gate line driving circuit 30) to control the operation, and signals complementary to each other. Certain first and second control signals VFR, / VFR are used (see FIG. 8 of Patent Document 7). If such a signal is used for driving the pull-down circuit 12, power consumption can be greatly reduced.

  FIG. 15 shows an example in which the first and second control signals VFR and / VFR are used as signals for driving the pull-down circuit 12 with respect to the initial reset signal generation circuit 110 of the circuit of FIG. In FIG. 15, terminals CTA and CTB are first and second input terminals for receiving first and second control signals VFR and / VFR, respectively.

  FIG. 16 is a signal waveform diagram showing the operation of the initial reset signal generation circuit 110 of FIG. The operation of the initial reset signal generation circuit 110 of FIG. 15 is the same as that of the circuit of FIG. 11 except that the transistors Q2A and Q3A and the transistors Q2B and Q3B are switched on and off every frame.

  FIG. 16 shows an example in which the activation timing of the second control signal / VFR is the same as the first activation timing of the clock signal / CLK, but the activation of the second control signal / VFR is thereby May be early. For example, in the example of FIG. 16, the activation timing of the second control signal / VFR may be earlier than the activation timing of the start signal ST. If the activation timing of the second control signal / VFR is advanced, the pulse width of the initial reset signal IRS becomes narrow, but it is necessary to ensure a pulse width that allows the unit shift register SR to perform the reset operation.

Further, as shown in FIG. 13, in the case where the first activation timing of the clock signal / CLK is delayed by one cycle (two horizontal periods) with respect to FIG. 16, the activation timing of the second control signal / VFR is It may be earlier than the first activation timing of the clock signal CLK. However, if the activation timing of the second control signal / VFR is later than the activation timing of the start signal ST, the activation period of the start signal ST and the activation period of the initial reset signal IRS are overlapped. There is a problem that both the transistors Q53 and Q58 are turned on in the first-stage unit shift register SR ₁ (FIG. 4) (see the first modification of the second embodiment). Therefore, in that case, the gate line driver circuit 30 having the configuration shown in FIG. 14 may be used.

[Third Modification]
The shift register constituting the gate line driver circuit is not always controlled using a two-phase clock signal. For example, the shift register of Patent Document 6 is controlled using a three-phase clock signal.

  FIG. 17 is a circuit diagram of the initial reset signal generation circuit 110 according to the third modification of the second embodiment. The pull-down circuit 12 has three phases of clock signals CLK1 to CLK1 that have different phases (the active periods do not overlap). This is an example of driving using CLK3.

  17, the initial reset signal generation circuit 110 includes a transistor Q2C connected between the output terminal IOUT and the first power supply terminal S1, a node N1, and the first power supply terminal S1 with respect to the circuit of FIG. A transistor Q3C connected between them is provided. A clock signal CLK1 is supplied to the first clock terminal CK1 to which the gates of the transistors Q2A and Q3A are connected. A clock signal CLK2 is supplied to the second clock terminal CK2 to which the gates of the transistors Q2B and Q3B are connected. The clock signal CLK3 is supplied to the third clock terminal CK3 to which the gate of Q3C is connected.

  The operation of the initial reset signal generation circuit 110 of FIG. 17 is basically the same as that of the circuit of FIG. However, the node N1 and the output terminal IOUT are sequentially connected to the transistors Q2A and Q3A, the transistors Q2B and Q3B, and the transistors Q2C and Q3C according to the activation of the clock signals CLK1 to CLK3 while the gate line driving circuit 30 performs the normal operation. By being turned on, it is maintained at the L level.

  In the case where the pull-down circuit 12 is driven using clock signals of four or more phases, an additional transistor for discharging the node N1 and the output terminal IOUT may be provided according to the number of phases. That is, when an n-phase clock signal is used, a transistor in which different clock signals are supplied to the gates between the output terminal IOUT and the start signal ST and between the input terminal IN and the first power supply terminal S1. N may be connected.

  According to this modification, the initial reset signal generation circuit 110 can be applied to a shift register (gate line driving circuit 30) controlled using a multiphase clock signal of three or more phases.

[Fourth modification]
FIG. 18 is a circuit diagram of the initial reset signal generation circuit 110 according to the fourth modification example of the second embodiment. The initial reset signal generation circuit 110 is obtained by supplying a clock signal having a phase different from that supplied to the gate of each of the transistors Q2A, Q2B, Q3A, and Q3B to the circuit of FIG. .

  That is, the sources of the transistors Q2A and Q3A to which the clock signal CLK is supplied to the gates are connected to the second clock terminal CK2 to which the clock signal / CLK is supplied. The sources of the transistors Q2B and Q3B to which the clock signal / CLK is supplied to the gate are connected to the first clock terminal CK1 to which the clock signal CLK is supplied. Therefore, it is not necessary to supply the low-side power supply potential VSS to the initial reset signal generation circuit 110.

  When the transistors Q2A, Q2B, Q3A, and Q3B are turned on, their sources are at L level, so that they can set the node N1 and the output terminal IOUT to L level with low impedance as in the case of FIG. Therefore, the initial reset signal generation circuit 110 in FIG. 18 can perform the same operation as the circuit in FIG.

  According to this modification, the wiring for supplying the low-side power supply potential VSS to the initial reset signal generation circuit 110 is not necessary, so that the area occupied by the circuit can be reduced.

[Fifth Modification]
FIG. 19 is a circuit diagram of an initial reset signal generation circuit 110 according to a fifth modification of the second embodiment. The initial reset signal generation circuit 110 inputs the clock signal / CLK to the gates of the transistors Q2A and Q3A via the first inverter composed of the transistors Q10 and Q11, and the gates of the transistors Q2B and Q3B. The clock signal CLK is inputted through a second inverter composed of transistors Q12 and Q13.

  However, in the example of FIG. 19, the clock signal CLK is supplied as the power source of the first inverter, and the clock signal / CLK is supplied as the power source of the second inverter. That is, the output of the first inverter does not change to the active level (H level) unless it is the active period of the clock signal CLK, and the output of the second inverter does not change to the active level unless it is the active period of the clock signal / CLK.

  The first inverter is a ratioless inverter having the transistor Q10 as a load element and the transistor Q11 as a drive element. When a node to which the gates of the transistors Q2A and Q3A are connected is defined as “node N3”, in the first inverter, the second clock terminal CK2 is an input terminal, the node N3 is an output terminal, and the first clock terminal CK1 is a power supply node. .

  The transistor Q10 is connected between the node N3 and the first clock terminal CK1, and its gate is connected to the first clock terminal CK1 (ie, the transistor Q10 is diode-connected). The transistor Q11 is connected between the node N3 and the first power supply terminal S1, and its gate is connected to the second clock terminal CK2.

  The second inverter is a ratioless inverter having the transistor Q12 as a load element and the transistor Q13 as a drive element. When a node to which the gates of the transistors Q2B and Q3B are connected is defined as “node N4”, in the second inverter, the first clock terminal CK1 is an input terminal, the node N4 is an output terminal, and the second clock terminal CK2 is a power supply node. .

  The transistor Q12 is connected between the node N4 and the second clock terminal CK2, and its gate is connected to the second clock terminal CK2 (that is, the transistor Q12 is diode-connected). The transistor Q13 is connected between the node N4 and the first power supply terminal S1, and its gate is connected to the first clock terminal CK1.

  The operation of the initial reset signal generation circuit 110 in FIG. 19 is substantially the same as the operation of the circuit in FIG. 11 (FIG. 12), but the gates of the transistors Q2A and Q3A (node N3) and the gates of the transistors Q2B and Q3B (node N4). The waveform of the signal supplied to () is slightly different.

  FIG. 20 is a signal waveform diagram showing operations of the first and second inverters. As shown in the figure, the node N3 that is the output terminal of the first inverter changes to H level when the clock signal CLK rises, and changes to L level when the clock signal / CLK rises. On the other hand, the node N4, which is the output terminal of the second inverter, changes to H level when the clock signal / CLK rises, and changes to L level when the clock signal CLK rises.

  As can be seen from FIG. 20, there is an interval Δt between the active period of the clock signal CLK and the active period of the clock signal / CLK, but the period when the node N3 is at the H level and the period when the node N4 is at the H level. There is no interval between.

  Therefore, after the initial reset signal IRS is deactivated, one of the transistors Q2A and Q3A or the transistors Q2B and Q3B is always turned on while the clock signals CLK and / CLK are alternately activated. The node N1 and the output terminal IOUT can always be at a low impedance L level. Accordingly, since there is no period in which the node N1 and the output terminal IOUT are in a high impedance state, it is possible to prevent an erroneous signal of the initial reset signal IRS from being generated due to the influence of noise or the like.

  In FIG. 19, the clock signals CLK and / CLK are supplied as the power sources of the first and second inverters, respectively, but the high-side power supply potential VDD may be supplied as in the case of a general inverter (ie, the transistors Q10 and Q10). The drain of Q12 may be connected to the second power supply terminal S2.)

  Further, the source of the transistor Q11 may be connected to the first clock terminal CK1, and the source of the transistor Q13 may be connected to the second clock terminal CK2. Since the active periods of the clock signals CLK and / CLK do not overlap, the transistors Q11 and Q13 can discharge the nodes N3 and N4 during the active periods of the clock signals / CLK and CLK, respectively. Therefore, in this case, the same operation as the circuit of FIG. 19 is possible.

[Sixth Modification]
In the a-Si TFT, a threshold voltage shift occurs when the gate is biased. As described above, since the pull-down circuit 12 is driven by the clock signals CLK and / CLK in the circuit of FIG. 11, even if the transistors Q2A, Q2B, Q3A, and Q3B constituting the pull-down circuit 12 are a-Si TFTs. The threshold voltage shift is suppressed.

  However, when the driving time is long, it is inevitable that the transistors Q2A, Q2B, Q3A, and Q3B shift at a constant level, and their on-resistances are somewhat increased. Since the transistors Q2A, Q2B, Q3A, and Q3B do not need to pass a large current while the node N1 and the output terminal IOUT are maintained at the low impedance L level after the initial reset signal IRS is deactivated, The increase in the on-resistance of is not a problem.

  However, when inactivating the initial reset signal IRS at the active level, it is necessary to pass a certain amount of current. If the on-resistance is high at this time, the falling speed of the initial reset signal IRS (discharge of the output terminal IOUT) (Speed) becomes slow. As a result, an overlap occurs between the active period of the start signal ST and the active period of the initial reset signal IRS.

For example, when the gate line driving circuit 30 is configured by the unit shift register SR of FIG. 4, if there is an overlap in the active period of the start signal ST and the initial reset signal IRS, the transistor in the first stage unit shift register SR ₁ Both Q53 and Q58 are turned on. Therefore not charged node N51 is sufficiently unit shift register SR _1, the problem that the driving capability of the transistor Q51 is lowered. Here, the example of a change which took the measure is shown.

  FIG. 21 is a circuit diagram of the initial reset signal generation circuit 110 according to the sixth modification of the second embodiment. The initial reset signal generation circuit 110 is provided with transistors Q14A and Q14B that discharge the output terminal IOUT and the node N1 in response to the activation of the start signal ST, respectively, in the circuit of FIG.

  As shown in FIG. 21, the transistor Q14A is connected between the output terminal IOUT and the first power supply terminal S1, and the transistor Q14B is connected between the node N1 and the first power supply terminal S1. The gates of the transistors Q14A and Q14B are both connected to the start signal input terminal SIN.

The operation of the initial reset signal generation circuit 110 in FIG. 21 is almost the same as the operation of the circuit in FIG. 11 (FIG. 12), but the node N1 and the output when the initial reset signal IRS is deactivated (time t ₁ ). The terminal IOUT is discharged mainly by the transistors Q14A and Q14B in response to the activation of the start signal ST.

  Since the start signal ST is activated only once in one frame period, the frequency with which the gates of the transistors Q14A and Q14B are biased is significantly smaller than that of the gates of the transistors Q2A, Q2B, Q3A, and Q3B. Therefore, even if the driving time of the pull-down circuit 12 is increased, only a slight threshold voltage shift occurs in the transistors Q14A and Q14B, and the increase in on-resistance is small. Therefore, the fall rate of the initial reset signal IRS hardly decreases, and the above problem does not occur.

  21 shows an example in which the transistors Q14A and Q14B are provided in the pull-down circuit 12 driven by the two-phase clock signals CLK and / CLK. Of course, the transistors Q14A and Q14B are driven by a multiphase clock signal having three or more phases. Transistors Q14A and Q14B may be provided for the pull-down circuit 12 (for example, FIG. 17), and the same effect can be obtained. The present invention is also applicable to the initial reset signal generation circuit 110 having the configuration described in the modification examples 4 and 5.

<Embodiment 3>
In the third embodiment, an initial reset signal generation circuit 110 according to the present invention configured using P-type transistors will be described.

  FIG. 22 is a diagram illustrating a configuration of the initial reset signal generation circuit 110 according to the third embodiment. The initial reset signal generation circuit 110 is an example in which a circuit that functions similarly to the circuit of FIG. 6 is realized by a P-type transistor. That is, the circuit of FIG. 22 uses a P-type transistor instead of an N-type transistor, and reverses the polarity of the power supply voltage (the high-side power supply potential is supplied to the first power supply terminal S1 of FIG. The low power supply potential is supplied to the second power supply terminal S2, and the voltage polarity of each signal is reversed (the active level is set to L level and the inactive level is set to H level). In FIG. 22, elements corresponding to those shown in the initial reset signal generation circuit 110 in FIG. 6 are denoted by the same reference numerals with “p” suffixes.

  As shown in FIG. 23, the initial reset signal generation circuit 110 according to the present embodiment is configured to activate the initial reset signal IRS, deactivate the initial reset signal IRS, and maintain the inactive level thereafter. And a pull-down circuit 12p for performing.

  The pull-up circuit 11p includes a transistor Q1p and a capacitive element C1p. The transistor Q1p is connected between the output terminal IOUT of the initial reset signal IRS and the second power supply terminal S2p to which the low-side power supply potential VSS is supplied. Here, a node to which the gate of the transistor Q1p is connected is defined as “node N1p”. The capacitive element C1p is connected between the node N1p and the second power supply terminal S2p.

  The pull-down circuit 12p is configured by transistors Q2p to Q7p. The transistor Q2p is connected between the output terminal IOUT and the first power supply terminal S1p to which the high-side power supply potential VDD is supplied, and its gate is connected to the start signal input terminal SIN that receives the start signal ST. The transistor Q3p has a gate connected to the start signal input terminal SIN, and is connected between the node N1p and the first power supply terminal S1p.

  The transistors Q6p and Q7p are connected in series between the second power supply terminal S2p and the first power supply terminal S1p. When a connection node between the transistors Q6p and Q7p is defined as “node N2p”, the transistor Q6p is connected between the node N2p and the second power supply terminal S2p, and the gate is connected to the second power supply terminal S2p. The transistor Q7p is connected between the node N2p and the first power supply terminal S1p, and the gate is connected to the node N1p.

  The transistor Q7p has an on-resistance set sufficiently lower than that of the transistor Q6p, and these transistors Q6p and Q7p constitute a ratio type inverter having the node N1p as an input terminal and the node N2p as an output terminal. In the inverter, the transistor Q6p functions as a load element, and the transistor Q7p functions as a drive element. Note that the load element of the inverter may be a current driving element, and for example, a resistance element or a constant current element may be used instead of the transistor Q6p.

  The transistor Q4p is connected between the output terminal IOUT and the first power supply terminal S1p, and the gate is connected to the node N2p. The transistor Q5p is connected between the node N1p and the first power supply terminal S1p, and the gate is connected to the node N2p.

  FIG. 23 is a signal waveform diagram for explaining the operation of the initial reset signal generation circuit 110 according to the present embodiment. Normally, the signal level of the data line DL is the same regardless of the conductivity type of the pixel switch element 16 shown in FIG. 1, so the levels of the high-side power supply potential VDD and the low-side power supply potential VSS are substantially the same as those in FIG. However, since the pixel switch element 16 is P-type, it is shifted slightly to the negative side than in the case of FIG.

  In the present embodiment, the high-side power supply potential VDD becomes the reference potential of the circuit, and negative pulses are input as the clock signals CLK and / CLK and the start signal ST. Further, the threshold voltage of each transistor also becomes a negative value. Here, it is assumed that the threshold voltages of the transistors are all equal, and the value is Vthp (negative voltage).

  Further, as described above, each node of the circuit configured using the P-type transistor has the charge / discharge relationship opposite to that of the N-type transistor. Therefore, in the following description, the flow of current that changes each node from H level (inactive level) to L level (active level) is referred to as “charging” of the node, and each node is changed from L level to H level. The current flow is referred to as “discharge” of the node.

Hereinafter, the operation of the initial reset signal generation circuit 110 will be described with reference to FIG. During a period prior to time t _{0 when the} power is turned on (a period when the power is shut off), the high-potential side power output, the low-potential side power output, the start signal ST, and the clock signals CLK and / CLK are grounded The level (GND = 0V) is set.

When power is turned on at time t ₀ , the high-potential-side power supply output rises from the ground level to the potential VDD, and the low-potential-side power supply output falls from the ground level to the potential VSS. Further, the start signal ST and the clock signals CLK and / CLK become inactive levels (potential VDD).

  Therefore, in the initial reset signal generation circuit 110, the transistors Q2p and Q3p are turned off. Therefore, when the potential of the second power supply terminal S2p falls to VSS, the potential of the node N1p is lowered to the L level due to the coupling through the capacitive element C1p. Accordingly, the transistors Q1p and Q7p are turned on.

  On the other hand, when the potential of the second power supply terminal S2p becomes VSS, the transistor Q6p is also turned on. However, since the on-resistance of the transistor Q7p is set to be sufficiently smaller than that of the transistor Q6p, the node N2p becomes H level. Accordingly, the transistors Q5p and Q4p are turned off.

Note that lowering the width of the potential of the node N1p at time t ₀ is determined by the ratio of the parasitic capacitance values of the node N1p capacitive element C1p. If the capacitance value of the capacitive element C1p is set to be sufficiently larger than the parasitic capacitance value of the node N1p, the level of the node N1p decreases to almost the potential VSS. Further, the potential of the node N2p is determined by the on-resistance ratio of the transistors Q6p and Q7p. If the on-resistance of the transistor Q7p is sufficiently small, the potential becomes almost the potential VDD.

Thus, at time t ₀ , the transistor Q1p is turned on and the transistors Q2p and Q4p are turned on, so that the output terminal IOUT is charged by the transistor Q1p and becomes L level (VSS + | Vthp |). That is, the initial reset signal IRS is activated.

Thereafter, when the start signal ST at time t ₁ becomes L level (VSS) activated, the transistors Q2p, Q3p is turned on. Node N1p is discharged through transistor Q3p to H level, thereby turning off transistor Q1p. Therefore, the output terminal IOUT is discharged through the transistor Q2p and becomes H level, and the initial reset signal IRS is deactivated.

  When the node N1p becomes H level, the transistor Q7p is turned off, and the node N2p is charged by the transistor Q6p and becomes L level (VSS + | Vthp |). Accordingly, the transistors Q4p and Q5p are turned on.

When the At time t ₂ the start signal ST becomes H level (VDD), the transistor Q2p, Q3p is turned off. However, since the transistors Q4p and Q5p are kept on, the output terminal IOUT and the node N1p are kept at the H level (VDD) with low impedance.

  Thereafter, when the start signal ST is activated for each frame period, the transistors Q2p and Q3p are turned on, but the levels of the output terminal IOUT and the nodes N1p and N2p are not changed. Therefore, the initial reset signal IRS is maintained at the H level until the power supply of the display device is cut off.

  As described above, the initial reset signal generation circuit 110 according to the present invention can also be configured using P-type transistors. Therefore, the present invention can also be applied to an image display device including the gate line driving circuit 30 configured using P-type transistors.

  FIG. 23 shows an example in which the initial reset signal generation circuit 110 having the same function as that of the circuit of FIG. 6 is configured using a P-type transistor. However, the initial reset of the first and second embodiments and their modifications are shown. Similarly, the signal generation circuit 110 can be configured using P-type transistors.

  That is, for each initial reset signal generation circuit 110 of the first and second embodiments, a P-type transistor is used instead of an N-type transistor, the polarity of the power supply voltage is reversed, and the voltage polarity of each signal is reversed (active If the level is set to L level and the inactive level is set to H level, a driver circuit having the same function as those circuits can be configured using P-type transistors (not shown).

  110 Initial reset signal generation circuit, 120 control circuit, 130 high potential side power supply, 140 low potential side power supply, 150 level shifter, 11 pull-up circuit, 12 pull-down circuit.

Claims (22)

An initial reset signal generation circuit that generates an initial reset signal for initializing a shift register , formed using only transistors of the same conductivity type ,
An input terminal for receiving a start signal for starting the operation of the shift register;
An output terminal from which the initial reset signal is output;
A pull-up circuit that activates the initial reset signal in response to power-on;
An initial reset signal generation circuit comprising: a pull-down circuit that deactivates the initial reset signal in response to activation of the start signal. The initial reset signal generation circuit according to claim 1,
The pull-up circuit is
A first power supply terminal to which a first power supply of an active level is supplied;
A first transistor connected between the first power supply terminal and the output terminal;
An initial reset signal generation circuit comprising a first capacitor connected between the first power supply terminal and a control electrode of the first transistor. The initial reset signal generation circuit according to claim 2,
The pull-down circuit is
A second power supply terminal to which a second power supply having an inactive level is supplied;
A second transistor connected between the second power supply terminal and the output terminal and having a control electrode connected to the input terminal;
A third transistor connected between the second power supply terminal and the control electrode of the first transistor and having a control electrode connected to the input terminal;
An inverter that operates using the first and second power sources as power sources and has a control electrode of the first transistor as an input end;
A fourth transistor having a control electrode connected between the second power supply terminal and the output terminal and connected to the output terminal of the inverter;
An initial reset signal generating circuit comprising: a fifth transistor having a control electrode connected between the second power supply terminal and the control electrode of the first transistor and connected to an output terminal of the inverter. The initial reset signal generation circuit according to claim 2,
The pull-down circuit is
A second power supply terminal to which a second power supply having an inactive level is supplied;
An inverter that operates using the first power source and the second power source as power sources, and has a control electrode of the first transistor as an input end;
A fourth transistor having a control electrode connected between the second power supply terminal and the output terminal and connected to the output terminal of the inverter;
A fifth transistor having a control electrode connected between the second power supply terminal and the control electrode of the first transistor and connected to an output terminal of the inverter;
An initial reset signal generation circuit, further comprising a sixth transistor connected between the first power supply terminal and an output terminal of the inverter and having a control electrode connected to the input terminal. The initial reset signal generation circuit according to claim 4,
The pull-down circuit is
An initial reset signal generation circuit, further comprising a third transistor connected between the second power supply terminal and the control electrode of the first transistor and having a control electrode connected to the input terminal. An initial reset signal generation circuit according to any one of claims 3 to 5,
The pull-down circuit is
An initial stage further comprising a unidirectional element connected between the output terminal of the inverter and the first power supply terminal and having a forward direction from the output terminal of the inverter to the first power supply terminal. Reset signal generation circuit. An initial reset signal generation circuit that generates an initial reset signal for initializing a shift register , formed using only transistors of the same conductivity type ,
A plurality of clock terminals for receiving each of a plurality of clock signals having different phases to define the operation of the shift register;
An output terminal from which the initial reset signal is output;
A pull-up circuit that activates the initial reset signal in response to power-on;
An initial reset signal generation circuit comprising: a pull-down circuit that deactivates the initial reset signal in response to activation of any of the plurality of clock signals. The initial reset signal generation circuit according to claim 7,
The pull-down circuit further includes
An initial reset signal generation circuit, wherein the output terminal is set to an inactive level with a low impedance according to activation of each of the plurality of clock signals. An initial reset signal generation circuit according to claim 7 or 8,
The pull-up circuit is
A first power supply terminal to which a first power supply of an active level is supplied;
A first transistor connected between the first power supply terminal and the output terminal;
An initial reset signal generation circuit comprising a first capacitor connected between the first power supply terminal and a control electrode of the first transistor. An initial reset signal generation circuit according to claim 9,
The pull-down circuit is
A second power supply terminal to which a second power supply having an inactive level is supplied;
A plurality of second transistors connected between the second power supply terminal and the output terminal, each having a control electrode connected to a different clock terminal;
An initial reset signal generation circuit comprising: a plurality of third transistors connected between the second power supply terminal and the control electrode of the first transistor, each having a control electrode connected to a different clock terminal. . An initial reset signal generation circuit according to claim 9,
The pull-down circuit is
A second power supply terminal to which a second power supply having an inactive level is supplied;
A plurality of second transistors each having a control electrode connected to one of the current terminals connected to the output terminal and connected to the different clock terminals;
A plurality of third transistors each having a control electrode connected between one of the current electrodes and the control electrode of the first transistor and connected to each of the different clock terminals;
In each of the plurality of second transistors,
The other current electrode is connected to a clock terminal different from the control electrode,
In each of the plurality of third transistors,
2. The initial reset signal generation circuit according to claim 1, wherein the other current electrode is connected to a clock terminal different from the control electrode. The initial reset signal generation circuit according to claim 10,
In each of the plurality of second transistors,
Between the control electrode and the clock terminal connected thereto, an inverter having the clock terminal as an input end and the control electrode as an output end is interposed,
In each of the plurality of third transistors,
An initial reset signal generating circuit, wherein an inverter having the clock terminal as an input end and the control electrode as an output end is interposed between the control electrode and the clock terminal connected thereto. An initial reset signal generation circuit that generates an initial reset signal for initializing a shift register , formed using only transistors of the same conductivity type ,
An input terminal for receiving a start signal for starting the operation of the shift register;
A plurality of clock terminals for receiving each of a plurality of clock signals having different phases to define the operation of the shift register;
An output terminal from which the initial reset signal is output;
A pull-up circuit that activates the initial reset signal in response to power-on;
A pull-down circuit that inactivates the initial reset signal in response to activation of the start signal and further sets the output terminal to an inactive level with a low impedance according to activation of each of the plurality of clock signals. An initial reset signal generation circuit as a feature. An initial reset signal generation circuit according to claim 13,
The pull-up circuit is
A first power supply terminal to which a first power supply of an active level is supplied;
A first transistor connected between the first power supply terminal and the output terminal;
An initial reset signal generation circuit comprising a first capacitor connected between the first power supply terminal and a control electrode of the first transistor. The initial reset signal generation circuit according to claim 14,
The pull-down circuit is
A second power supply terminal to which a second power supply having an inactive level is supplied;
A plurality of second transistors connected between the second power supply terminal and the output terminal, each having a control electrode connected to a different clock terminal;
A plurality of third transistors connected between the second power supply terminal and the control electrode of the first transistor, each having a control electrode connected to a different clock terminal;
A fourth transistor connected between the second power supply terminal and the output terminal and having a control electrode connected to the input terminal;
An initial reset signal generation circuit comprising: a fifth transistor having a control electrode connected between the second power supply terminal and the control electrode of the first transistor and connected to the input terminal. The initial reset signal generation circuit according to claim 14,
The pull-down circuit is
A second power supply terminal to which a second power supply having an inactive level is supplied;
A plurality of second transistors each having a control electrode connected to one of the current terminals connected to the output terminal and connected to the different clock terminals;
A plurality of third transistors having one control electrode connected between the control electrode of the first transistor and one of the control electrodes connected to the different clock terminals;
A fourth transistor connected between the second power supply terminal and the output terminal and having a control electrode connected to the input terminal;
A fifth transistor connected between the second power supply terminal and the control electrode of the first transistor and having a control electrode connected to the input terminal;
In each of the plurality of second transistors,
The other current electrode is connected to a clock terminal different from the control electrode,
In each of the plurality of third transistors,
2. The initial reset signal generation circuit according to claim 1, wherein the other current electrode is connected to a clock terminal different from the control electrode. The initial reset signal generation circuit according to claim 15,
In each of the plurality of second transistors,
Between the control electrode and the clock terminal connected thereto, an inverter having the clock terminal as an input end and the control electrode as an output end is interposed,
In each of the plurality of third transistors,
An initial reset signal generating circuit, wherein an inverter having the clock terminal as an input end and the control electrode as an output end is interposed between the control electrode and the clock terminal connected thereto. An initial reset signal generation circuit that generates an initial reset signal for initializing a shift register , formed using only transistors of the same conductivity type ,
First and second input terminals respectively receiving first and second complementary control signals supplied to the shift register;
An output terminal from which the initial reset signal is output;
A pull-up circuit that activates the initial reset signal in response to power-on;
An initial reset signal generation circuit comprising: a pull-down circuit that deactivates the initial reset signal in response to activation of the first or second control signal. The initial reset signal generation circuit according to claim 18,
The pull-down circuit further includes
An initial reset signal generation circuit, wherein the output terminal is set to an inactive level with a low impedance according to activation of each of the first and second control signals. An initial reset signal generation circuit according to claim 18 or 19,
The first and second control signals are:
An initial reset signal generation circuit, wherein the shift register alternates at least every one operation cycle. An initial reset signal generation circuit according to any one of claims 18 to 20,
The pull-up circuit is
A first power supply terminal to which a first power supply of an active level is supplied;
A first transistor connected between the first power supply terminal and the output terminal;
An initial reset signal generation circuit comprising a first capacitor connected between the first power supply terminal and a control electrode of the first transistor. The initial reset signal generation circuit according to claim 21,
The pull-down circuit is
A second power supply terminal to which a second power supply having an inactive level is supplied;
A plurality of second transistors connected between the second power supply terminal and the output terminal and having a control electrode connected to the first input terminal;
A plurality of third transistors connected between the second power supply terminal and the control electrode of the first transistor and having a control electrode connected to the first input terminal;
A plurality of fourth transistors connected between the second power supply terminal and the output terminal and having a control electrode connected to the second input terminal;
An initial reset signal generation circuit comprising a plurality of fifth transistors connected between the second power supply terminal and a control electrode of the first transistor and having a control electrode connected to the second input terminal. .

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