JP2011205235A - Solid-state imaging apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce characteristic dispersion of a sensor output even when there is the dispersion in the characteristics of an amplifier for amplifying the sensor output.SOLUTION: A photoelectric conversion part 13 and outputting parts 14 and 15 are formed on a sensor chip 12, the outputting part 14 outputs a sensor signal OS read from the photoelectric conversion part 13 to a main substrate 1, and the outputting part 15 outputs a reference signal DOS that does not respond to light as a reference potential VREF of the sensor signal OS output from the outputting part 14 to the main substrate 1.

Description

  The present invention relates to a solid-state imaging device, and is particularly suitable for application to a method for setting a reference potential for sensor output.

  In a conventional solid-state imaging device, a black level is made common between pixels and chips by applying a reference potential from the outside to a CMOS sensor and an external substrate.

  Further, for example, Patent Document 1 discloses a CDS circuit in which the amplification factors of the first programmable gain amplifier and the second programmable gain amplifier are switched to a plurality of predetermined values, and the pixel signals are equal between different amplification factors. And a method of finding an offset voltage of the first programmable gain amplifier and setting the offset voltage in the CDS circuit and the first programmable gain amplifier.

  However, in the method of applying the reference potential from the outside, when a plurality of amplifiers that amplify the sensor output are provided in the chip, when there is a difference in amplifier characteristics between chips, or when noise is applied to a specific pixel, etc. There is a problem in that output characteristics vary from pixel to pixel.

JP 2002-199283 A

  An object of the present invention is to provide a solid-state imaging device capable of reducing variations in sensor output characteristics even when there are variations in the characteristics of an amplifier that amplifies the sensor output.

  According to one aspect of the present invention, a sensor chip in which a photoelectric conversion unit is formed, a first output unit that is formed in the sensor chip and outputs a signal read from the photoelectric conversion unit, and the sensor chip And a second output unit that outputs a signal that does not react to light as a reference potential of a signal output from the first output unit.

  According to the present invention, it is possible to reduce variations in sensor output characteristics even when there are variations in the characteristics of an amplifier that amplifies the sensor output.

FIG. 1 is a block diagram showing a schematic configuration of the solid-state imaging device according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating an example of an output level of the solid-state imaging device of FIG. FIG. 3 is a block diagram showing a schematic configuration of the sensor module of FIG. 4A is a circuit diagram illustrating a configuration of a pixel portion when one amplifier is shared by four pixels in the sensor chip of FIG. 3, and FIG. 4B is an amplifier that amplifies a signal that does not react to light. It is a circuit diagram which shows the example of a structure. FIG. 5 is a diagram illustrating an example of an output level of the solid-state imaging device according to the second embodiment of the present invention.

  Hereinafter, a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of the solid-state imaging device according to the first embodiment of the present invention.
In FIG. 1, a sensor chip 12 that performs imaging is mounted on the sensor module 11. The number of sensor chips 12 mounted on the sensor module 11 may be one or plural.

  The sensor chip 12 includes a photoelectric conversion unit 13 and output units 14 and 15. Here, the output unit 14 can output the sensor signal OS read from the photoelectric conversion unit 13 to the main board 1. The output unit 14 may be provided for each pixel formed on the sensor chip 12, for example, or one output unit 14 may be assigned to a plurality of pixels.

  The output unit 15 can output a reference signal DOS that does not react to light as the reference potential VREF of the sensor signal OS output from the output unit 14 to the main board 1. Note that the output unit 15 may be provided for each pixel formed in the sensor chip 12, may be provided for each output unit 14, or may be provided for each sensor chip 12.

  On the main board 1, a DC / DC converter 2, capacitors 3, 4 and an analog front end circuit 5 are mounted. Here, the output terminal of the DC / DC converter 2 is grounded via the capacitors 3 and 4, and the power supply voltage VOD is supplied from the DC / DC converter 2 to each part of the main board 1. For example, the value of the power supply voltage VOD can be set to 3.3V.

  The analog front end circuit 5 is provided with an offset DA converter 6, an adder 7, a subtracter 8, a gain adjuster 9, and an AD converter 10. Here, the offset DA converter 6 can generate an offset signal so that the sensor signal OS falls within the input range of the analog front end circuit 5. The adder 7 can add the offset signal generated by the offset DA converter 6 to the sensor signal OS. The subtractor 8 can calculate the difference between the value obtained by adding the offset signal to the sensor signal OS and the reference potential VREF. The gain adjuster 9 can amplify the difference between the value obtained by adding the offset signal to the sensor signal OS and the reference potential VREF. The AD converter 10 can digitize the signal amplified by the gain adjuster 9.

FIG. 2 is a diagram illustrating an example of an output level of the solid-state imaging device of FIG.
In FIG. 2, it is assumed that the dark output of the sensor signal OS is VOS and the saturation output is VSAT. For example, the value of the dark output VOS can be set to 1.0V. When the line start pulse TR is input to the sensor chip 12, the sensor signal OS is output from the output unit 14 to the adder 7 in FIG. 1, and the reference signal DOS is output from the output unit 15 to the subtracter 8 in FIG. Is output. For example, the value of the reference signal DOS can be set to about 1.1V.

  When the output unit 15 is provided for each pixel, the reference signal DOS output from the output unit 15 can be switched corresponding to the pixel from which the sensor signal OS is output. When the output unit 15 is provided for each output unit 14, the reference signal DOS output from the output unit 15 can be switched corresponding to the output unit 14 from which the sensor signal OS is output. When the output unit 15 is provided for each sensor chip 12, the reference signal DOS output from the output unit 15 can be switched for each sensor chip 12 to which the sensor signal OS is output.

  Then, after the offset signal is added to the sensor signal OS in the adder 7, the reference signal DOS is subtracted in the subtracter 8 and output to the gain adjuster 9. Then, after gain adjustment is performed by the gain adjuster 9, it is digitized by the AD converter 10.

Here, by providing the output unit 15 that outputs the reference signal DOS on the sensor chip 12 side, the characteristic variation of the output unit 14 and the characteristic variation of the output unit 15 can be matched, and the characteristic variation of the output unit 14 can be reduced. It can be canceled by the characteristic variation of the output unit 15.
Therefore, even when a plurality of output units 14 are provided in the sensor chip 12 or when there is a difference in the characteristics of the output unit 14 between the sensor chips 12, it is possible to reduce variations in the output characteristics of the sensor signal OS. It becomes possible, and the image quality can be improved.

  Further, since the difference between the sensor signal OS and the reference signal DOS can be input to the gain adjuster 9, variation in offset voltage between chips can be reduced. Therefore, the operating point of the gain adjuster 9 can be prevented from changing, and the linearity characteristic difference can be reduced.

FIG. 3 is a block diagram showing a schematic configuration of the sensor module of FIG.
In FIG. 3, the sensor module 11 of FIG. 1 is provided with N (N is a positive integer) sensor chips 12-1 to 12 -N as sensor chips 12. For example, when the sensor module 12 is used as a linear sensor that reads an A4 size image, N = 12.

  Here, for example, in the sensor chip 12-1, a photodiode 21 that performs photoelectric conversion, a storage 22 that holds charges photoelectrically converted by the photodiode 21, and switching that reads out the charges accumulated in the storage 22 for each pixel. Amplified by a logic circuit 24 that controls the gate 23, the switching gate 23, etc., an amplifier 25 that amplifies a signal read from the photodiode 21, an amplifier 26 that amplifies a signal that does not react to light, and amplifiers 25 and 26, respectively. An output buffer 27 is provided for outputting the detected signal as a sensor signal OS and a reference signal DOS to the outside.

  The photodiode 21 can be provided for each pixel of the sensor chip 12-1. Further, the amplifier 25 can be provided in the output unit 14 in FIG. 1, and the amplifier 26 can be provided in the output unit 15 in FIG. Further, the photodiode 21, the storage 22, and the switching gate 23 can be provided in the photoelectric conversion unit 13 in FIG.

  The sensor chip 12-1 is supplied with the power supply voltage VOD from the DC / DC converter 2 of FIG. When reading the sensor signal OS from the sensor chip 12-1, the chip start pulse TIN is input to the logic circuit 24. When the line start pulse TR is input to the logic circuit 24, the charges photoelectrically converted by the photodiode 21 are read out for each pixel via the storage 22, amplified by the amplifier 25, and then output buffer. 27 is output as a sensor signal OS. A signal that does not react to light is amplified by an amplifier 26 and then output as a reference signal DOS via an output buffer 27.

  When the output of the sensor signal OS and the reference signal DOS from the sensor chip 12-1 is completed, the output of the sensor signal OS and the reference signal DOS from the sensor chips 12-2 to 12-N is sequentially performed.

4A is a circuit diagram illustrating a configuration of a pixel portion when one amplifier is shared by four pixels in the sensor chip of FIG. 3, and FIG. 4B is an amplifier that amplifies a signal that does not react to light. It is a circuit diagram which shows the example of a structure.
4A, the sensor chip 12-1 is provided with photodiodes PD1 to PD4 for each pixel, and the photodiodes PD1 to PD4 are connected to the floating diffusion FD via read transistors M1 to M4, respectively. . The source of the reset transistor M5 and the gate of the amplifier transistor M6 are connected to the floating diffusion FD, the gate of the reset transistor M5 is connected to the reset line RL, and the source of the amplifier transistor M6 is connected to the vertical signal line VL1. The drain of M5 and the drain of the amplifier transistor M6 are connected to the power supply potential VDD. The gates of the read transistors M1 to M4 are connected to the read signal lines HL1 to HL4, respectively.

  The drain of the load transistor TL1 is connected to the vertical signal line VL1, and the bias signal VB is input to the gate of the load transistor TL1. The load transistor TL1 constitutes a source follower and can perform a constant current operation.

  Then, when the reset signal RS becomes high level, the reset transistor M5 is turned on, and the charge of the floating diffusion FD is reset. Then, when the read signal CK1 becomes high level, the read transistor M1 is turned on, the charge accumulated in the photodiode PD1 is transferred to the floating diffusion FD, and the potential corresponding to the charge transferred to the floating diffusion FD is amplified. Applied to the gate of transistor M6.

  Here, since the source follower is configured by the amplifier transistor M6 and the load transistor TL1, the voltage of the vertical signal line VL1 follows the voltage applied to the gate of the amplifier transistor M6, and is output as the sensor signal OS. it can.

  When the reading from the photodiode PD1 is completed, the sensor signal OS for four pixels can be output by sequentially repeating the reset operation of the floating diffusion FD and the reading operation for one piece from the photodiodes PD2 to PD4. .

  In FIG. 4B, an amplifier transistor M11 is provided in the sensor chip 12-1. The amplifier transistor M11 can be provided corresponding to four pixels provided with the photodiodes PD1 to PD4. Further, it is preferable that the amplifier transistor M11 has the same size as the amplifier transistor M6 and is disposed in the vicinity of the amplifier transistor M6 so that the characteristic variation of the amplifier transistor M11 matches the characteristic variation of the amplifier transistor M6.

  The source of the amplifier transistor M11 is connected to the vertical signal line VL2, the drain of the amplifier transistor M11 is connected to the power supply potential VDD, and the gate of the amplifier transistor M11 is grounded. A fixed potential may be applied to the gate of the amplifier transistor M11.

  The drain of the load transistor TL2 is connected to the vertical signal line VL2, and the bias signal VB is input to the gate of the load transistor TL2. The load transistor TL2 constitutes a source follower and can perform a constant current operation.

  Here, since the amplifier transistor M11 and the load transistor TL2 form a source follower, the voltage of the vertical signal line VL2 follows the voltage applied to the gate of the amplifier transistor M11, and is output as the reference signal DOS. it can.

  Also, by grounding the gate of the amplifier transistor M11, a signal that does not react to light can be output from the amplifier transistor M11, and the reference signal DOS output from the amplifier transistor M11 is used as the reference potential VREF of the sensor signal OS. Is possible.

(Second Embodiment)
FIG. 5 is a diagram illustrating an example of an output level of the solid-state imaging device according to the second embodiment of the present invention.
In FIG. 5, in the example of FIG. 2, the level of the sensor signal OS is higher than the value of the dark output VOS at the time of light output. In the second embodiment, the sensor signal OS is output at the time of light output. The operation can be performed in the same manner as in the first embodiment except that the level is lower than the value of the dark output VOS.

  When the level of the sensor signal OS is lower than the value of the dark output VOS during the light output, for example, the value of the dark output VOS can be set to 1.7 V, and the value of the reference signal DOS is 1. It can be set to about 6V.

  1 main board, 2 DC / DC converter, 3 4 capacitor, 5 analog front end circuit, 6 offset DA converter, 7 adder, 8 subtractor, 9 gain adjuster, 10 AD converter, 11 sensor module, 12, 12 -1 to 12-N sensor chip, 13 photoelectric conversion unit, 14, 15 output unit, 21 photodiode, 22 storage, 23 switching gate, 24 logic circuit, 25, 26 amplifier, 27 output buffer, FD floating diffusion, PD1 PD4 photodiode, M1 to M4 readout transistor, M5 reset transistor, M6, M11 amplifier transistor, VL1, VL2 vertical signal line, TL1, TL2 load transistor

Claims (7)

A sensor chip on which a photoelectric conversion unit is formed;
A first output unit formed on the sensor chip and outputting a signal read from the photoelectric conversion unit;
A solid-state imaging device comprising: a second output unit that is formed on the sensor chip and outputs a signal that does not react to light as a reference potential of a signal output from the first output unit. The first output unit includes a first amplifier that amplifies a signal read from the photoelectric conversion unit,
The solid-state imaging device according to claim 1, wherein the second output unit includes a second amplifier that amplifies a signal that does not react to the light.   The solid-state imaging device according to claim 1, further comprising an analog front end circuit that adjusts a black level based on a reference potential output from the second output unit. The analog front-end circuit is
A subtractor that calculates a difference between the signal output from the first output unit and the reference potential output from the second output unit;
The solid-state imaging device according to claim 1, further comprising: a gain adjuster that amplifies the output of the subtracter.   5. The solid-state imaging device according to claim 1, wherein the second output unit is provided for each pixel formed in the sensor chip. 6.   5. The solid-state imaging device according to claim 1, wherein the second output unit is provided for each first output unit formed in the sensor chip. 6.   The solid-state imaging device according to claim 1, wherein the second output unit is provided for each sensor chip.

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