JP2011204191A - Electric power saving multi-cpu system, and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a strong electric power saving multi-CPU system restraining properly electric power consumption, by stopping only internal clocks of one part of the CPUs, without stopping erroneously the internal clocks of all the CPU, and to provide an image forming apparatus.SOLUTION: The electric power saving multi-CPU system includes: a plurality of CPUs 10, 11 which operate by receiving a clock signal; signal supply control parts 12-15 controlled by the respective CPUs and supplying and supply-blocking the clock signal to/from other CPU other than the CPUs; a monitoring part 16 monitoring the supply of the clock signal to each CPU, and for determining whether all the supplies of the clock signals to the respective CPUs are blocked or not; and a blocking release control part 17 for restarting up the supply of the clock signal to any of the respective CPUs, by the signal supply control parts 12-15, when all the supplies of the clock signals to the respective CPUs are determined to be blocked by the monitoring part 16.

Description

  The present invention relates to a power saving multi-CPU system and an image forming apparatus.

  In recent years, it has been desired to improve the control performance of the control unit as the functionality of electronic devices increases. Therefore, the control unit is often provided with a plurality of CPU cores. Thus, by providing a plurality of CPU cores, the control performance of the control unit is improved.

  On the other hand, in recent years, it has been desired to suppress power consumption of electronic devices, and various technologies for power saving have been developed for electronic devices provided with a plurality of CPU cores of this type. .

  Patent Document 1 describes a power saving control system capable of saving power in an electronic device provided with a plurality of CPU cores of this type. In the power saving control system described in Patent Document 1, each of the two CPU cores can execute a normal operation mode and a low power consumption operation mode.

  This power saving control system operates as follows in order to save power. That is, one CPU core operates at a clock frequency smaller than that in the normal operation mode, monitors the presence or absence of a return event, and the other CPU core operates in an operation mode in which the internal clock is almost stopped. Run the mode.

JP 2007-47966 A

  However, in the power saving control system described in Patent Document 1, although the low power consumption operation mode is executed to save power, there is some internal clock of the other CPU core, and the internal clock is It is not completely stopped. Therefore, it is desired that the internal clock of the other CPU core is completely stopped for further power saving.

  By the way, when the internal clocks of all the CPU cores are stopped, a so-called deadlock state occurs, and the control unit cannot execute subsequent processing. In addition, it is difficult to restore the internal clock of any one of the CPU cores to release such a deadlock state because the internal clocks of all the CPU cores are stopped.

  Therefore, it is desirable to stop only the internal clocks of some CPU cores without erroneously stopping the internal clocks of all the CPU cores.

  The present invention is proposed in order to solve the above-mentioned problem, and by appropriately stopping the internal clocks of some CPUs without erroneously stopping the internal clocks of all the CPUs, the power consumption is appropriately reduced. An object of the present invention is to provide a robust and power-saving multi-CPU system and an image forming apparatus that can be suppressed.

  A power-saving multi-CPU system according to an aspect of the present invention includes a plurality of CPUs (Central Processing Units) that operate by receiving a clock signal, and the clock signals for other CPUs other than the CPU that are controlled by the CPUs. A signal supply control unit that performs supply and cutoff of the supply, and monitoring that determines whether all of the supply of the clock signal to each CPU is blocked by monitoring the supply of the clock signal to each CPU. And the monitoring unit determine that all of the supply of the clock signal to the CPUs is interrupted, the signal supply control unit supplies the clock signal to any one of the CPUs. And a shut-off release control unit for resuming the supply of the power supply (claim 1).

  According to this configuration, each CPU controls the signal supply control unit to supply the clock signal to other CPUs other than the CPU and to block the supply.

  Thus, each CPU can block the supply of the clock signal to other CPUs by the signal supply control unit.

  In addition, when each CPU has cut off the supply of clock signals to other CPUs by the signal supply control unit, when the supply of clock signals to all CPUs is cut off, this state is detected by the monitoring unit. To be judged. At this time, supply of the clock signal to any one of the CPUs is resumed by the shut-off release control unit.

  As described above, the power consumption can be appropriately suppressed by stopping only the internal clocks of some CPUs without erroneously stopping the internal clocks of all the CPUs.

  In the above configuration, when the signal supply control unit resumes the supply of the clock signal of any one of the CPUs, the cutoff release control unit is set in advance for any of the CPUs. It is preferable to notify the abnormality (claim 2).

  According to this configuration, when the supply of the clock signal to any one of the CPUs is restarted, the cutoff release control unit performs a preset abnormality notification to any one of the CPUs.

  As a result, when any of the CPUs receives the supply of the clock signal and enters an operating state, it can be seen that an abnormal state has occurred in which the supply of the clock signal to all the CPUs is interrupted. Therefore, any one of the CPUs stores in the log that an abnormal state occurs in which the supply of the clock signal to all the CPUs is interrupted, and then performs an error analysis based on the log. It can be performed.

  The said structure WHEREIN: It is preferable to further provide the frequency change part which is controlled by each said CPU and changes the frequency of the said clock signal supplied to the said CPU (Claim 3).

  According to this configuration, the frequency of the clock signal supplied to each CPU can be changed by each CPU.

  Therefore, the supply of the clock signal to other CPUs other than the CPU can be cut off, and the frequency of the internal clock of the CPU itself can be reduced. Thereby, further power saving can be achieved.

  An image forming apparatus according to another aspect of the present invention forms a power-saving multi-CPU system according to any one of claims 1 to 3 and image data representing an image of a document on a recording sheet. And an image forming unit (claim 4).

  According to this configuration, it is possible to provide an image forming apparatus including the power saving multi-CPU system according to any one of claims 1 to 3. Therefore, it is possible to provide an image forming apparatus having the effects described in any one of claims 1 to 3.

  According to the present invention, it is possible to appropriately suppress power consumption by stopping only the internal clocks of some CPUs without erroneously stopping the internal clocks of all the CPUs.

1 is a schematic cross-sectional view of an image forming apparatus according to an embodiment of the present invention. FIG. 2 is a functional block diagram illustrating an example of a schematic configuration of the image forming apparatus illustrated in FIG. 1. It is the functional block diagram which showed an example of schematic structure of a control part. It is the flowchart which showed the state which the main CPU of an operation state changes to a dormant state, and the sub CPU of a dormant state changes to an operation state. It is the flowchart which showed the state which the sub CPU of an operation state changes to a dormant state, and the main CPU of a dormant state changes to an operation state. It is the flowchart which showed an example of the basic operation | movement of the monitoring part and the interruption | blocking cancellation | release control part.

  Hereinafter, an embodiment of a power saving multi-CPU system and an image forming apparatus according to the present invention will be described with reference to the drawings. In addition, the structure which attached | subjected the same code | symbol in each figure shows that it is the same structure, The description is abbreviate | omitted.

  FIG. 1 is a schematic sectional view of an image forming apparatus according to an embodiment of the present invention. As shown in FIG. 1, the image forming apparatus A includes an image reading unit 200 and an apparatus main body 3. The image reading unit 200 includes a document feeding unit 210, a scanner unit 220, a CIS 231, a user interface unit I, and a reversing mechanism described later.

  The document feeder 210 includes an ADF (Automatic Document Feeder), and includes a document tray 211, a pickup roller 212, a platen 213, a paper discharge roller 214, and a paper discharge tray 215. A document to be read is placed on the document tray 211. Documents placed on the document tray 211 are picked up one by one by the pickup roller 212 and sequentially conveyed to the platen 213 through the gap. Documents that have passed through the platen 213 are sequentially discharged to the discharge tray 215 by the discharge rollers 214.

  Of the positions facing the peripheral surface of the platen 213, a timing sensor (not shown) for detecting paper is installed at a predetermined position before the reading position P in the document transport direction. The document transport timing to the reading position P is achieved based on the output request. The timing sensor is configured by, for example, a photo interrupter.

  The scanner unit 220 optically reads an image of a document and generates image data. The scanner unit 220 includes a glass 221, a light source 222, a first mirror 223, a second mirror 224, a third mirror 225, a first carriage 226, a second carriage 227, an imaging lens 228, and a CCD (Charged Coupled Device) 229. .

  In the scanner unit 220, a white fluorescent lamp such as a cold cathode fluorescent tube is used as the light source 222, and the first mirror 223, the second mirror 224, the third mirror 225, the first carriage 226, the second carriage 227, and the imaging. A lens 228 guides light from the document to the CCD 229. Since the scanner unit 220 is configured using a white fluorescent lamp such as a cold cathode fluorescent tube as the light source 222, the scanner unit 220 is superior in color reproducibility to a CIS 231 described later in which a three-color LED or the like is used as the light source.

  On the glass 221, a document is manually placed by the user when reading the document without using the document feeder 210. The light source 222 and the first mirror 223 are supported by the first carriage 226, and the second mirror 224 and the third mirror 225 are supported by the second carriage 227.

  As a document reading method of the image reading unit 200, the scanner unit 220 reads a document placed on the glass 221 and the document is read by the document feeding unit 210 (ADF). There is an ADF reading mode for reading.

  In the flatbed reading mode, the light source 222 irradiates a document placed on the glass 221, and reflected light for one line in the main scanning direction is reflected in the order of the first mirror 223, the second mirror 224, and the third mirror 225. Then, the light enters the imaging lens 228. The light incident on the imaging lens 228 is imaged on the light receiving surface of the CCD 229.

  The CCD 229 is a one-dimensional image sensor and processes the image data of one line of the document in an overlapping manner. The first carriage 226 and the second carriage 227 are configured to be movable in a direction orthogonal to the main scanning direction (sub-scanning direction, arrow Y direction). When reading for one line is completed, the first carriage 226 and the second carriage 227 are moved in the sub-scanning direction. The first carriage 226 and the second carriage 227 move, and the next line is read.

  In the ADF reading mode, the document feeder 210 takes in the documents placed on the document tray 211 one by one by the pickup roller 212. At this time, the first carriage 226 and the second carriage 227 are disposed at a predetermined reading position P located below the reading window 230.

  When the document is transported by the document feeder 210, when the document passes over the reading window 230 provided in the transport path from the platen 213 to the paper discharge tray 215, the light source 222 irradiates the document, and the main scanning one line. The reflected light is reflected in the order of the first mirror 223, the second mirror 224, and the third mirror 225 and enters the imaging lens 228. The light incident on the imaging lens 228 is imaged on the light receiving surface of the CCD 229. Subsequently, the document is conveyed by the document feeder 210 and the next line is read.

  Further, the document feeder 210 has a document reversing mechanism including a switching guide 216, a reversing roller 217, and a reversing conveyance path 218. This document reversing mechanism reverses the front and back of the original whose surface has been read by the first ADF reading and transports it again to the reading window 230, whereby the CCD 229 reads the back side again.

  This document reversing mechanism operates only when reading both sides, and does not operate when reading one side. After reading the back side during single-sided reading and double-sided reading, the switching guide 216 is switched to the upper side, and the document that has passed through the platen 213 is discharged to the discharge tray 215 by the discharge roller 214.

  After the front side reading at the time of double-sided reading, the switching guide 216 is switched to the lower side, and the document that has passed through the platen 213 is transported to the reverse transport path 218 by the reverse roller 217. Thereafter, the switching guide 216 is switched upward, and the reverse roller 217 rotates in the reverse direction to re-feed the document to the platen 213. Hereinafter, a mode in which both sides of a document are read using the document reversing mechanism is referred to as a double-sided reversal reading mode.

  Further, when the image reading unit 200 according to the present embodiment causes the CCD 229 (scanner unit 220) to read the surface of the document while the document is being conveyed as described above in the ADF reading mode, the image reading unit 200 substantially overlaps (substantially parallel). Thus, the back side of the document can be read by the CIS 231. In this case, the surface of the document conveyed from the document tray 211 by the document feeder 210 is read by the CCD 229 when passing through the reading window 230, and the back surface is read when passing through the location where the CIS 231 is arranged. In CIS231, RGB three-color LEDs or the like are used as light sources.

  By using the CCD 229 and the CIS 231 in this way, it is possible to read both the front and back sides of a document by a single document transport operation (one pass) from the document tray 211 to the discharge tray 215 by the document feeding unit 210. Hereinafter, a mode in which both sides of a document are read using the CCD 229 and the CIS 231 in this way is referred to as a double-sided simultaneous reading mode.

  The double-sided reverse reading mode and the double-sided simultaneous reading mode are provided as reading modes when performing double-sided reading of a document using the ADF reading mode. The double-sided reverse reading mode is used when you want to match the image quality of both-side printed images, while the double-sided simultaneous reading mode gives priority to shortening the reading time even if there is a difference in the image quality of both-side printed images Used in cases. Note that the image forming apparatus A in the present embodiment is initially set to the double-sided simultaneous reading mode, and when the image forming instruction is input without performing any mode setting operation in the reading mode, the double-sided simultaneous reading mode is set. A document image reading operation is performed in the reading mode.

  The image processing apparatus A includes an apparatus main body 3 and a stack tray 6 disposed on the left side of the apparatus main body 3. The apparatus main body 3 includes a plurality of paper feed cassettes 461, a paper feed roller 462 that feeds recording paper from the paper feed cassette 461 one by one and transports it to the image forming unit 40, and a recording paper transported from the paper feed cassette 461. And an image forming unit 40 for forming an image. The apparatus body 3 also includes a paper feed tray 471 and a feed roller 472 that feeds the originals placed on the paper feed tray 471 one by one toward the image forming unit 40.

  The image forming unit 40 includes a charge removing device 421 that removes residual charges from the surface of the photosensitive drum 43, a charging device 422 that charges the surface of the photosensitive drum 43 after charge removal, and image data acquired by the scanner unit 220. Based on the electrostatic latent image, an exposure device 423 that outputs a laser beam to expose the surface of the photosensitive drum 43 to form an electrostatic latent image on the surface of the photosensitive drum 43. Above, developing devices 44K, 44Y, 44M, and 44C that form toner images of cyan (C), magenta (M), yellow (Y), and black (K), and various colors formed on the photosensitive drum 43. A transfer drum 49 on which the toner image is transferred and superimposed, a transfer device 41 for transferring the toner image on the transfer drum 49 to the paper, and the paper on which the toner image is transferred to the toner by heating The and a fixing device 45 for fixing on the paper.

  Note that toner is supplied to cyan, magenta, yellow, and black colors from a toner cartridge (not shown). Further, conveyance rollers 463 and 464 that convey the recording paper that has passed through the image forming unit 40 to the stack tray 6 or the discharge tray 48 are provided.

  When forming images on both sides of the recording paper, the image forming unit 40 forms an image on one side of the recording paper, and then the recording paper is nipped by the conveyance roller 463 on the discharge tray 48 side. In this state, the conveyance roller 463 is reversed to switch back the recording paper, and the recording paper is sent to the paper conveyance path L and conveyed again to the upstream area of the image forming unit 40, and an image is formed on the other surface by the image forming unit 40. After the formation, the recording paper is discharged to the stack tray 6 or the discharge tray 48.

  Further, in front of the apparatus main body 3, a display unit 106 configured with a touch panel and a user interface unit I including an operation unit 105 having various operation buttons are exposed in front of the apparatus main body 3. Is provided.

  FIG. 2 is a functional block diagram showing an example of a schematic configuration of the image forming apparatus shown in FIG. As shown in FIG. 2, the image forming apparatus A includes a user interface I, a main CPU 10, a sub CPU 11, and the like, a control unit 1, a ROM (Read Only Memory) 101, and a RAM (Random Access Memory) 102. An image reading unit 200, an image forming unit 40, an image processing unit 100 for performing predetermined image processing on image data, a network interface 103 for connecting to a communication network such as a LAN, and facsimile communication through a public line. A FAX communication unit 17 for performing the operation is provided.

  In the image forming apparatus A, the ROM 101 and the RAM 102 store various programs necessary for the operation of the image forming apparatus A.

  FIG. 3 is a functional block diagram illustrating an example of a schematic configuration of the control unit 1. In the control unit 1 shown in FIG. 3, the first bus B <b> 1 and the second bus B <b> 2 are connected by a bus bridge 25. The main CPU 10 is disposed on the first bus B1, and the sub CPU 11 is disposed on the second bus B2.

  In addition to the main CPU 10, a first register 12 and a message box 18 are disposed on the first bus B1. In addition to the sub CPU 11, a second register 14 and a message box 18 are arranged on the second bus B2.

  Further, the control unit 1 includes an AND circuit 13, an AND circuit 15, a monitoring unit 16, and a cutoff release control unit 17. The AND circuit 13, the AND circuit 15, the monitoring unit 16, and the cutoff release control unit 17 may be arranged on any one of the first bus B1 and the second bus B2.

  In the control unit 1, the first register 12 and the AND circuit 15 are controlled by the main CPU 10, and constitute a first signal supply control unit that supplies a clock signal to the sub CPU 11 and blocks the supply.

  The second register 14 and the AND circuit 13 are controlled by the sub CPU 11 and constitute a second signal supply control unit that supplies a clock signal to the main CPU 10 and blocks the supply.

  Further, the third register 21 constitutes a first frequency changing unit for changing the frequency of the clock signal generated by the clock signal source 23. Further, the fourth register 22 constitutes a second frequency changing unit for changing the frequency of the clock signal generated by the clock signal source 24.

  The first register 12 stores a numerical value “1” for putting the sub CPU 11 in a dormant state or a numerical value “0” for putting the sub CPU 11 in an operating state. The numerical value “1” stored in the first register 12 is converted to a numerical value “0” by the NOT circuit 20 and output to the AND circuit 15. On the other hand, the numerical value “0” stored in the first register 12 is converted to a numerical value “1” by the NOT circuit 20 and output to the AND circuit 15.

  The second register 14 stores a numerical value “1” for setting the main CPU 10 in a dormant state or a numerical value “0” for setting the main CPU 10 in an operating state. The numerical value “1” stored in the second register 14 is converted into a numerical value “0” by the NOT circuit 19 and output to the AND circuit 13. On the other hand, the numerical value “0” stored in the second register 14 is changed to a numerical value “1” by the NOT circuit 19 and output to the AND circuit 13.

  The message box 18 is written with data for requesting the main CPU 10 to cut off the supply of the clock signal because the main CPU 10 transitions from the operating state to the hibernate state.

  Further, the message box 18 is written with data for requesting the sub CPU 11 to cut off the supply of the clock signal since the sub CPU 11 transits from the operating state to the hibernate state.

  The third register 21 stores a numerical value for setting the frequency of the clock signal output from the clock signal source 23. Writing of such numerical values to the third register 21 is performed under the control of the main CPU 10.

  The numerical value stored in the third register 21 is output to the clock signal source 23, and the clock signal source 23 generates a clock signal having a frequency based on the numerical value output from the third register 21. The clock signal generated by the clock signal source 23 is output toward the AND circuit 13.

  The fourth register 22 stores a numerical value for setting the frequency of the clock signal output from the clock signal source 24. Writing of such numerical values to the fourth register 22 is performed under the control of the sub CPU 11.

  The numerical value stored in the fourth register 22 is output to the clock signal source 24, and the clock signal source 24 generates a clock signal having a frequency based on the numerical value output from the fourth register 22. The clock signal generated by the clock signal source 24 is output toward the AND circuit 15.

  A clock signal output from the clock signal source 24 is input to the AND circuit 15, and a numerical value stored in the first register 12 is inverted by the NOT circuit 20 and input.

  When the numerical value “1” is input from the NOT circuit 20, the AND circuit 15 outputs the input clock signal as an output signal as it is. On the other hand, when the numerical value “0” is input from the NOT circuit 20, the AND circuit 15 outputs a signal having a constant voltage level and no pulse.

  Thus, when the numerical value “0” is stored in the first register 12, the clock signal is supplied to the sub CPU 11, but when the numerical value “1” is stored in the first register 12, the sub CPU 11 receives the clock signal. Is not supplied with a clock signal.

  A clock signal output from the clock signal source 23 is input to the AND circuit 13, and a numerical value stored in the second register 14 is inverted by the NOT circuit 19 and input.

  When the numerical value “1” is input from the NOT circuit 19, the AND circuit 13 outputs the input clock signal as an output signal as it is. On the other hand, when the numerical value “0” is input from the NOT circuit 19, the AND circuit 13 outputs a signal that has a constant voltage level and does not include a pulse.

  Thus, when the numerical value “0” is stored in the second register 14, the clock signal is supplied to the main CPU 10, but when the numerical value “1” is stored in the second register 14, Is not supplied with a clock signal.

  The monitoring unit 16 monitors the numerical value stored in the first register 12 and the numerical value stored in the second register 14. The monitoring unit 16 determines that the clock signal is not supplied to both the main CPU 10 and the sub CPU 11 when the numerical value “1” is stored in both the first register 12 and the second register 14. Then, the cutoff release control unit 17 is notified.

  When receiving the notification from the monitoring unit 16, the cutoff release control unit 17 updates the numerical value “1” stored in the first register 12 and the second register 14 to the numerical value “0”, The CPU 11 is notified of abnormality by outputting data indicating abnormality. As a result, the main CPU 10 and the sub CPU 11 accept supply of a clock signal, transition to an operating state, and accept an abnormality notification.

  The control unit 1 having this configuration executes the normal operation mode and the power saving mode. In the normal operation mode, the main CPU 10 is in the operating state and the sub CPU 11 is in the inactive state.

  However, in the image forming apparatus A, a state in which no operation is performed in the user interface unit I, the FAX communication unit 104 does not receive a call through the public line, or no signal is input to the network interface 103 is constant. When the time continues, the control unit 1 executes the power saving mode.

  In the power saving mode, the main CPU 10 is in a dormant state and the sub CPU 11 is in an operating state. In the power saving mode, the frequency of the clock signal for the sub CPU 11 in the operating state may be reduced. In this way, further power saving can be achieved.

  Here, when the power saving mode is being executed, the sub CPU 11 monitors an event such as an operation in the user interface unit I that should end the power saving mode.

  The basic operation of the control unit 1 will be described with reference to FIGS. FIG. 4 is a flowchart showing a state in which the main CPU 10 in the operating state transitions to the hibernating state and the sub CPU 11 in the hibernating state transitions to the operating state.

  As shown in FIG. 4, when the main CPU 10 transits from the operating state (step S10) to the hibernation state, the numerical value “0” is stored in the first register 12 (step S11). As a result, the supply of the clock signal to the sub CPU 11 is resumed, and the sub CPU 11 transitions to the operating state.

  Further, the main CPU 10 writes data for requesting the supply of the clock signal to the main CPU 10 in the message box 18 (step S12). Thereby, the data for requesting the cutoff of the supply of the clock signal to the main CPU 10 is accepted by the sub CPU 11 that has transitioned to the operating state.

  The main CPU 10 maintains the operating state until the numerical value stored in the second register 14 is changed to “1” by the sub CPU 11 (NO in step S13). On the other hand, when the numerical value stored in the second register 14 is changed to “1” by the sub CPU 11 (YES in step S13), the main CPU 10 changes to the sleep state because the supply of the clock signal is stopped. (Step S14).

  On the other hand, when the main CPU 10 rewrites the value of the first register to “0”, the sub CPU 11 transitions to the operation state (steps S20 to S22).

  Then, when the data for requesting the main CPU 10 to cut off the supply of the clock signal to the main CPU 10 is written in the message box 18 (YES in step S23), the sub CPU 11 stores the numerical value “ 1 "is stored (step S24). As a result, the supply of the clock signal to the main CPU 10 is interrupted, and the main CPU 10 transitions to a dormant state.

  With the above processing, the supply of the clock signal to the main CPU 10 in the operating state is stopped and transited to the inactive state, while the supply of the clock signal to the sub CPU 11 in the inactive state is resumed to transit to the operating state.

  Note that after the supply of the clock signal to the sub CPU 11 is resumed, the sub CPU 11 may rewrite the numerical value stored in the fourth register 22 as a numerical value indicating the frequency of the clock signal to reduce the frequency of the clock signal. Good. In this way, it is possible to achieve a further power saving effect.

  FIG. 5 is a flowchart showing a state where the sub CPU 11 in the operating state transitions to the hibernating state and the main CPU 10 in the hibernating state transitions to the operating state.

  As shown in FIG. 5, the sub CPU 11 in the operating state monitors an event for ending the power saving mode, and when the event occurs (YES in steps S30 and S31), a numerical value “0” is stored in the second register 14. Is stored (step S32). As a result, the supply of the clock signal to the main CPU 10 is resumed, and the main CPU 10 transitions to the operating state.

  Further, the sub CPU 11 writes data for requesting the supply of the clock signal to the sub CPU 11 in the message box 18 (step S33). Thereby, the data for requesting the interruption of the supply of the clock signal to the sub CPU 11 is accepted by the main CPU 10 that has transitioned to the operating state.

  The sub CPU 11 maintains the operation state until the numerical value stored in the first register 12 is changed to “1” by the main CPU 10 (NO in step S34). On the other hand, when the numerical value stored in the first register 12 is shifted to “1” by the main CPU 10 (YES in step S34), the sub CPU 11 shifts to the sleep state because the supply of the clock signal is stopped. (Step S35).

  On the other hand, when the sub CPU 11 rewrites the value of the second register 14 to “0”, the main CPU 10 transitions to an operating state (steps S40 to S42).

  When the sub CPU 11 has written data for requesting the supply of the clock signal to the sub CPU 11 in the message box 18 (YES in step S43), the main CPU 10 stores the numerical value “ 1 "is stored (step S44). As a result, the supply of the clock signal to the sub CPU 11 is interrupted, and the sub CPU 11 transitions to a dormant state.

  Through the above processing, the supply of the clock signal to the sub CPU 11 in the operating state is stopped and transited to the inactive state, while the supply of the clock signal to the main CPU 10 in the inactive state is resumed to transit to the operating state.

  FIG. 6 is a flowchart illustrating an example of basic operations of the monitoring unit 16 and the cutoff release control unit 17.

  The monitoring unit 16 constantly monitors the numerical values stored in the first register 12 and the second register 14, and when both the first register 12 and the second register 14 store the numerical value “1”. (YES in step S50 and YES in step S51), the fact is notified to the cutoff release control unit 17.

  Then, the cutoff release control unit 17 rewrites the numerical values stored in the first register 12 and the second register 14 to “0” (step S52). Further, the cutoff release control unit 17 notifies the main CPU 10 and the sub CPU 11 of an abnormality in order to notify that an abnormal state in which the supply of the clock signal to all the CPUs is interrupted (step S53).

  As a result, the supply of the clock signal to the main CPU 10 and the sub CPU 11 is resumed, so that the main CPU 10 and the sub CPU 11 transition from the sleep state to the operating state.

  In addition, since the abnormality notification to the main CPU 10 and the sub CPU 11 is performed, it can be seen that the main CPU 10 and the sub CPU 11 have an abnormal state in which the supply of the clock signal to all the CPUs is interrupted. For this reason, the main CPU 10 and the sub CPU 11 store in the log that an abnormal state in which the supply of the clock signal to the main CPU 10 and the sub CPU 11, that is, all the CPUs is interrupted, and then based on the log. Process such as error analysis.

  The cutoff release control unit 17 may store the numerical value “0” only in one of the first register 12 and the second register 14. For example, the cutoff release control unit 17 rewrites the numerical value stored in the second register 14 to “0”, while keeping the numerical value stored in the first register 12 “1”. At this time, the shutoff cancellation control unit 17 sends an abnormality notification only to the main CPU 10.

  As a result, the supply of the clock signal to the main CPU 10 is resumed, and the main CPU 10 transitions from the sleep state to the operating state. At this time, since the abnormality notification is made to the main CPU 10, the main CPU 10 knows that an abnormal state in which the supply of the clock signal to all the CPUs is interrupted has occurred.

  As a result, the main CPU 10 stores in the log that an abnormal state in which the supply of the clock signal to all the CPUs is interrupted, and then performs processing such as error analysis based on the log. be able to.

A Image forming apparatus 10 Main CPU
11 Sub CPU
12 first register 13, 15 AND circuit 14 second register 16 monitoring unit 17 shut-off release control unit 18 message box 19, 20 NOT circuit 21 third register 22 fourth register 23, 24 clock signal source

Claims (4)

Multiple CPUs (Central Processing Units) that operate by receiving clock signals;
A signal supply control unit that is controlled by each CPU and supplies the clock signal to other CPUs other than the CPU and shuts off the supply;
A monitoring unit that monitors the supply of the clock signal to each CPU and determines whether or not all of the supply of the clock signal to each CPU is interrupted;
When the monitoring unit determines that all of the supply of the clock signal to each CPU is blocked, the signal supply control unit supplies the clock signal to any one of the CPUs. A shutdown release control unit to resume;
A power-saving multi-CPU system comprising: The blocking release control unit
When the supply of the clock signal to any one of the CPUs is resumed by the signal supply control unit, a preset abnormality notification is given to any of the CPUs. Item 4. The power saving multi-CPU system according to Item 1. The power-saving multi-CPU system according to claim 1, further comprising a frequency changing unit that is controlled by each CPU and changes a frequency of the clock signal supplied to the CPU. A power-saving multi-CPU system according to any one of claims 1 to 3,
An image forming unit for forming image data representing an image of a document on recording paper;
An image forming apparatus comprising:

Images