JP2011203612A - Liquid crystal device, electronic equipment, and driving method of the liquid crystal device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure long write period while suppressing power consumption in a liquid crystal device.SOLUTION: This liquid crystal device 1 is provided. The liquid crystal device 1 is equipped with: a data signal generation circuit 211 for generating a data signal of a size according to the gradation to be displayed; and a precharge signal generation circuit 20 for generating a precharge signal Vpre. The liquid crystal device 1 supplies the precharge signal Vpre to data lines 103 and 105 in a precharge period Pre, and supplies the data signal to the data line 103 in a data period Da. Here, the data signal generation circuit 211 inverts the polarity of the data signal every predetermined number of dots. The liquid crystal device 1 measures the period after the supply of the precharge signal Vpre to the data line 105 is started until the voltage of the data line 105 reaches a comparing voltage, and controls the data signal generation circuit 211 so that respective data signals corresponding to the predetermined number of dots are generated only in a uniform period in the data period Da, based on the measured period.

Description

The present invention relates to a liquid crystal device, a driving method thereof, and electronic equipment, and more particularly to optimization of precharge and voltage writing.

One type of liquid crystal device is a liquid crystal display device that displays a color image. The liquid crystal display device includes a plurality of scanning lines, a plurality of data lines, and a plurality of dots provided corresponding to the intersections of the scanning lines and the data lines. Each dot includes a liquid crystal element and a writing control TFT (thin film transistor) that controls writing of a voltage applied to the liquid crystal element, and has a color of R (red), G (green), or B (blue). Can be displayed. In each dot, a gradation corresponding to the voltage written by supplying a data signal from the data line via the write control TFT is displayed.

The liquid crystal display device adopts a-TFT (amorphous TFT) formed using amorphous silicon and LTPS-TFT formed using LTPS (low temperature polysilicon) as the write control TFT. There is something you did. A liquid crystal display device employing an a-TFT is configured such that three dots (dots that can display R, G, and B colors) constituting one pixel correspond to different data lines. Therefore, as the definition becomes higher, wiring becomes difficult.

On the other hand, what employ | adopted the demultiplex drive system is known as a liquid crystal display device which employ | adopted LTPS-TFT. In the demultiplex drive method, three dots constituting one pixel correspond to one data line, and voltage writing to these dots is performed by using one data line in a time division manner. Done. Therefore, in the liquid crystal display device adopting the a-TFT, if the demultiplex driving method is adopted, the number of wirings can be reduced, so that the above problem can be solved.

However, when one data line is used in a time-sharing manner, the writing period for writing a voltage to the dots may be shortened. Since the a-TFT has a lower mobility than the LTPS-TFT, shortening the writing period may cause insufficient writing. Further, in the liquid crystal display device, it is necessary to periodically invert the polarity of the data signal in order to suppress the deterioration of the liquid crystal element due to the residual DC component. In other words, it is necessary to periodically vary the voltage of the data line. However, since the data line has a considerable parasitic capacitance and the mobility of the a-TFT is low, it takes a long time to reverse the polarity.

For example, as shown in FIG. 9, when polarity inversion is performed for each dot, it is necessary to change the voltage of the data line significantly and frequently, and there is a risk of insufficient writing during the writing period of each dot. is there. On the other hand, as shown in FIG. 10, when the polarity inversion is performed every three dots, the number of times that the voltage of the data line is significantly changed is reduced. However, since the time required for one polarity inversion does not change, in the writing period (writing periods R1 and R2 in FIG. 10) in which polarity inversion is performed,
There is a risk of insufficient writing.

On the other hand, Patent Document 1 discloses a liquid crystal display device that performs precharging. In this device, a positive voltage or negative voltage precharge signal is supplied to the data line in the precharge period immediately before the writing period. As a result, the data line is charged with positive charge or negative charge (
And then the writing period is reached. Therefore, the occurrence of insufficient writing can be suppressed.

JP 2009-109705 A

In a liquid crystal display device adopting an a-TFT, if a demultiplex driving method is adopted and a precharge period is provided before a writing period in which polarity inversion is performed, occurrence of insufficient writing can be suppressed. it can. In this case, in order to ensure a long writing period, it is preferable to shorten the precharge period as much as possible. In order to charge a sufficient amount of charge in a short period, it is necessary to increase the precharge signal.

However, as shown in FIG. 11, if the precharge signal is too large, much of the charged charge is wasted and power consumption increases. On the other hand, if the precharge signal is too small, only an insufficient amount of charge is charged, so that the occurrence of insufficient writing cannot be sufficiently suppressed. In order to charge a sufficient amount of charge without increasing the precharge signal, the precharge period must be lengthened. However, this may lead to insufficient writing due to shortening of the writing period.

The present invention has been made in view of the above-described circumstances, and an object thereof is to ensure a long writing period while suppressing power consumption.

In order to solve the above problems, a liquid crystal device of the present invention includes a plurality of scanning lines, a plurality of data lines,
A liquid crystal device comprising a plurality of pixel circuits provided corresponding to intersections of the scanning lines and the data lines, generating a data signal having a magnitude corresponding to a gradation to be displayed, A data signal generation unit that reverses the polarity every predetermined number of dots, a precharge signal generation unit that generates a precharge signal, and one of the data signal and the precharge signal is selected and applied to the data line. A selection unit that outputs, a voltage detection unit that detects a voltage of the data line and outputs a detection voltage in a precharge period in which the selection unit outputs the precharge signal to the data line, and the detection voltage is predetermined. The selection unit is controlled so as to switch the signal to be output to the data line from the precharge signal to the data signal by detecting that the comparison voltage has been reached. A first control unit for ending the charge period; a time measurement unit for measuring a length of the precharge period and outputting a precharge time; and the selection unit selecting the data signal based on the precharge time And a second control unit that controls the data signal generation unit so that a data signal corresponding to each of the predetermined number of dots is generated for an equal period of time.

In the present invention, a precharge signal is output to the data line during the precharge period, and a data signal is output to the data line during the data period. The precharge period ends when the voltage of the data line reaches the comparison voltage. Therefore, even if the precharge signal is increased, there is no possibility that excess charges are charged to the data line. That is, power consumption can be suppressed by shortening the precharge period. In the present invention, in the data period, the length of the precharge period (precharge time)
Based on the above, a data signal corresponding to each of the predetermined number of dots is generated for a uniform time.
That is, it is possible to secure a longer voltage writing period to the pixel circuit as much as the precharge period is shortened. As described above, according to the present invention, it is possible to ensure a long writing period while suppressing power consumption.

By the way, the time from the start of the output of the precharge signal to the data line until the voltage of the data line reaches the comparison voltage varies depending on the change in characteristics of each unit such as the precharge signal generation unit. Therefore, when the precharge period is fixed, there are cases where the amount of charge to be charged is insufficient and writing is insufficient, or the amount of charge to be charged is excessive and power consumption is increased. appear. On the other hand, in the present invention, when the voltage of the data line reaches the comparison voltage, the precharge period ends, and the write period is determined based on the measured precharge time, that is, the measured precharge time. Since the precharge period Pre and the write periods R, G, and B are dynamically set based on the above, such a case does not occur.

In the above-described liquid crystal device, the precharge signal generation unit corresponds to a positive potential supply unit that supplies a positive potential, a negative potential supply unit that supplies a negative potential, and a cycle of polarity inversion of the data signal. It is preferable to further include a potential selection unit that selects the positive potential and the negative potential and outputs the selected potential as the precharge signal.

In each of the liquid crystal devices, the first control unit includes a comparison voltage generation unit that generates the comparison voltage, and a comparison unit that compares the detection voltage with the comparison voltage. Preferably, the selection unit is controlled to switch from the precharge signal to the data signal.

In each of the above liquid crystal devices, the second control unit calculates a difference time obtained by subtracting the precharge time from the unit time, where the time when the data signal is positive or negative is set as a unit time. It is preferable that the time allocated to the predetermined number of dots is determined by dividing by the predetermined number.

By the way, the measured precharge time becomes shorter as the difference between the detection voltage at the start of the precharge period and the comparison voltage is smaller. On the other hand, when a data line contributing to display is a detection target, the detection voltage at the start of the precharge period depends on the voltage written immediately before using the data line. That is, in this case, the time corresponding to the display content is measured as the precharge time. The precharge period related to the precharge time is sufficiently long for the data line to be detected, but may be too short for the other data lines. Therefore, in each of the liquid crystal devices described above, it is preferable that the data line on which the voltage detection unit detects a voltage is a dummy data line that does not contribute to display among the plurality of data lines. If a dummy data line that does not contribute to display is targeted for detection, the detection voltage at the start of the precharge period can be set to a voltage that can ensure a sufficiently long precharge period without affecting the display. Because.

In each of the above liquid crystal devices, the pixel circuit includes a pixel electrode, a counter electrode, a liquid crystal sandwiched between the pixel electrode and the counter electrode, the scanning line and the gate, and the data line and the source. Alternatively, the pixel electrode may be connected to the a-TFT to which one of the source and the drain is connected. Since the a-TFT has a lower mobility than the LTPS-TFT, it is necessary to ensure a longer writing period when voltage is written through the a-TFT. Because the writing period is secured
A configuration in which a voltage is written through an a-TFT can be employed.

Moreover, this invention can also be grasped | ascertained as an electronic device provided with each said liquid crystal device. The present invention can also be grasped as a method for driving a liquid crystal device. In this case, the gradation to be displayed is driven by a liquid crystal device including a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits provided corresponding to intersections of the scanning lines and the data lines. Generating a data signal having a magnitude corresponding to the data signal, inverting the polarity of the data signal every predetermined number of dots, selecting one of the data signal and the precharge signal, and outputting the selected data signal to the data line, In the precharge period in which the precharge signal is output to the data line, the voltage of the data line is detected as a detection voltage, and when the detection voltage has reached a predetermined comparison voltage, the data line is detected. The output signal is controlled to be switched from the precharge signal to the data signal, the precharge period is ended, the length of the precharge period is measured, and the precharge time is measured. Obtained, on the basis of the pre-charge time, the data period for selecting the data signal, the data signal corresponding to each of said predetermined number of dots are controlled to be generated by equal time.

1 is a block diagram illustrating a schematic configuration of a liquid crystal device 1 according to a first embodiment of the present invention. 2 is a block diagram showing a configuration of a data line driving circuit 200 in the liquid crystal device 1. FIG. 2 is a block diagram showing a configuration of a drive circuit 210 in a data line drive circuit 200. FIG. 3 is a block diagram showing a configuration of a timing control circuit 220 in the data line driving circuit 200. FIG. 4 is a timing chart for explaining the operation of the liquid crystal device 1. 1 is a perspective view illustrating a configuration of a personal computer that employs a liquid crystal device 1. FIG. 1 is a perspective view showing a configuration of a mobile phone employing a liquid crystal device 1. FIG. 1 is a perspective view illustrating a configuration of a portable information terminal that employs a liquid crystal device 1. FIG. It is a figure for demonstrating the conventional liquid crystal device. It is a figure for demonstrating the conventional liquid crystal device. It is a figure for demonstrating the conventional liquid crystal device.

<A: Embodiment>
FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal device 1 according to the first embodiment of the present invention.
The liquid crystal device 1 is a liquid crystal display device that displays a color image, and includes an electro-optical panel AA, a data line driving circuit 200, and a control circuit 300. In the electro-optical panel AA, the pixel region A and the scanning line driving circuit 100 are formed. Among these, m scanning lines 101 are formed in the pixel region A in parallel with the X direction. m is a multiple of 3. Y that is orthogonal to the X direction
In parallel with the direction, n data lines 103 are formed. A pixel circuit 400 is provided corresponding to each intersection of the scanning line 101 and the data line 103. That is, in the pixel region A, the pixel circuit 400 of m rows and n columns is arranged.

The pixel circuit 400 is a dot provided with a normally black liquid crystal element, and can display a color of R, G, or B. In each row, dots that can display the same color are arranged, and in each column, three types of dots (R, G, and B dots) that can display R, G, and B colors are alternately arranged. Are lined up. Three dots (R, G, and B arranged in the order of R, G, and B in each row)
(Dot) constitutes a pixel capable of displaying white. In other words, m / 3 rows and n columns of pixels are arranged in the pixel region A.

The liquid crystal element includes a pixel electrode 6, a counter electrode (not shown), and a liquid crystal that is sandwiched between the two electrodes and driven by a voltage (drive voltage) between the two electrodes. The transmittance or reflectance of the liquid crystal element changes according to the driving voltage. In addition to the liquid crystal element, the pixel circuit 400 includes an N-channel TFT 50 interposed between the corresponding data line 103 and the pixel electrode 6 and a capacitive element 5 that holds a driving voltage.
1 and displays a gradation corresponding to the driving voltage. The TFT 50 is an a-TFT, its gate is connected to the corresponding scanning line 101, its source is connected to the corresponding data line 103, and its drain is connected to the pixel electrode 6. Note that a P-channel TFT or an LTPS-TFT may be employed as the TFT 50.

In the pixel area A, a data line 105 is provided in parallel with the Y direction. Data line 1
05 is a wiring formed by the same process as the n data lines 103, and the capacitance value thereof is equal to the capacitance value of the data lines 103. The data lines 105 are connected to m dummy circuits 500 that do not contribute to display. That is, the data line 105 is a dummy wiring that does not contribute to display. The dummy circuit 500 is composed of, for example, a capacitive element, and the capacitance value thereof is equal to the input capacitance value of the pixel circuit 400 in which the TFT 50 is off.

That is, the load when charging the data line 105 is equal to the load when charging the data line 103 corresponding to the m pixel circuits 400 in which the TFT 50 is off. Instead of the data lines 105 and the m dummy circuits 500, the load when charging the charge is the load when charging the data lines 103 corresponding to the m pixel circuits 400 in which the TFT 50 is off. Any circuit equal to can be employed.

The scanning line driving circuit 100 generates scanning signals Y1, Y2, Y3,..., Ym based on the clock signal YCLK and the start pulse DY that defines the vertical scanning period. When i is a natural number equal to or less than m, the scanning signal Yi is supplied to the data line 103 corresponding to the n pixel circuits 400 in the i-th row. The scanning signals Y1, Y2, Y3,..., Ym are pulse signals for sequentially selecting the m scanning lines 101, and are exclusively at the H level. The n pixel circuits 400 in the i-th row and the scanning lines 101 corresponding to these pixel circuits 400 have a period during which the scanning signal Yi supplied to the scanning line 101 is at the H level (a period corresponding to the pulse width). Selected. Hereinafter, this period is referred to as a “selection period”.

The data line driving circuit 200 includes n data lines 103 based on a clock signal CLK, gradation data Dr, Dg, and Db, a polarity signal Vpl, and a reset signal XRES described later.
And data line signals X1 to Xn corresponding to, and an output signal Vout described later. When j is a natural number equal to or less than n, the data line signal Xj is supplied to the data line 103 corresponding to the pixel circuit 400 in the j-th column. Further, the output signal Vout is supplied to the data line 105.

The gradation data Dr indicates the gradation to be displayed on the R dot. Similarly, the gradation data Dg indicates the gradation to be displayed on the G dot, and the gradation data Db indicates the gradation to be displayed on the B dot. The gradation indicated by each gradation data is any one of a plurality of gradations from the highest gradation (white) to the lowest gradation (black).
One. The data line signal Xj is supplied to the m pixel circuits 40 corresponding to the data lines 103 to which the data is supplied.
In any one selection period of 0, the level (potential) corresponds to the gradation to be displayed on the one pixel circuit 400.

In the pixel circuit 400, the TFT 50 is turned on over the selection period. Therefore, during the selection period of the pixel circuit 400, the data line signal supplied from the data line 103 corresponding to the pixel circuit 400 is supplied to the pixel electrode 6 via the TFT 50, and the drive voltage corresponding to the level of the data line signal Is held by the capacitive element 51. That is, the pixel circuit 400 includes
In the selection period, a driving voltage corresponding to the gradation to be displayed is written.

Incidentally, one vertical scanning period (1F) includes m / 3 1H (one horizontal scanning period). In 1H, a driving voltage is written to 3 × n dots that form pixels for one row. That is, 1H includes three writing periods (selection periods). These writing periods are R in order from the top.
A dot writing period R, a G dot writing period G, and a B dot writing period B. In the following description, a period in which these are connected is referred to as a data period Da, and a length of 1H is defined as a unit time. Called.

The polarity of the data line signal Xj is inverted every 1H (every unit time). The pulse specifying the inversion timing is the polarity signal Vpl, and the level is switched every 1H between the positive level and the negative level. In the following description, 1H of the polarity signal Vpl is referred to as a positive unit period, and 1H of the negative level is referred to as a negative unit period.

The data line driving circuit 200 precharges the data line before writing the driving voltage using the data line. The precharge is a process of charging positive or negative charges to set the voltage of the data line to the reference voltage GND, and is performed by supplying a precharge signal Vpre to the data line to be charged. In the following description, a period during which precharge is performed is referred to as a precharge period Pre. That is, 1H includes a precharge period Pre and a data period Da. The level of the precharge signal Vpre becomes a positive potential Vp in the precharge period Pre included in the positive unit period, and becomes a negative potential Vn in the precharge period Pre included in the negative unit period.

The control circuit 300 inputs image data Din indicating an image to be displayed by pixels of m / 3 rows and n columns from a host device (not shown) and outputs various signals. Specifically, the start pulse DY and the clock signal YCLK are supplied to the scanning line driving circuit 100, while the clock signal CLK, the gradation data Dr, Dg and Db, the polarity signal Vpl, and a reset signal XRES, which will be described later, Is supplied to the data line driving circuit 200.

The gradation data Dr, Dg, and Db are supplied in parallel. That is, 1H
Note that n × 3 pieces of gradation data (n pieces of gradation data Dr, n) indicating gradations to be displayed on n × 3 dots constituting pixels for one row corresponding to 1H. Pieces of gradation data D
g and n pieces of gradation data Db) are respectively supplied over 1H. Note that the gradation data Dr, Dg, and Db relating to a pixel both indicate the highest gradation when displaying white on the pixel, and indicate the lowest gradation when displaying black on the pixel.

FIG. 2 is a block diagram showing a configuration of the data line driving circuit 200. As shown in FIG.
The data line driving circuit 200 includes a driving circuit 210 and a timing control circuit 220.
The drive circuit 210 generates data line signals X1 to Xn based on the gradation data Dr, Dg, and Db, the selection signal SEL, the enable signal XENB, and the precharge signal Vpre. The selection signal SEL is a signal that defines the writing periods R, G, and B. The enable signal XENB is a signal that defines the precharge period Pre and the data period Da, and maintains the L level during the precharge period Pre and the H level during the data period Da.

The timing control circuit 220 includes a precharge signal generation circuit 20 and a clock signal C.
Based on LK, polarity signal Vpl, and reset signal XRES described later, selection signal SEL is selected.
An enable signal XENB, a precharge signal Vpre, and an output signal Vout. The output signal Vout is a signal obtained by switching between a precharge signal Vpre and a data signal Xw described later, and is supplied to the data line 105.

FIG. 3 is a block diagram showing the configuration of the drive circuit 210. As shown in FIG. 3, the drive circuit 210 includes n selection units U <b> 1 to Un corresponding to the n data lines 103. The configurations of the selection units U1 to Un are similar to each other, and the data line 1 corresponding to the dot in the jth column
The selection unit Uj corresponding to 03 includes an enable signal XENB, a selection signal SEL, a precharge signal Vpre, and gradation data Dr, Dg and Db indicating gradations to be displayed on the m dots in the j-th column. Based on the above, the data line signal Xj is generated.

The selection unit Uj includes a data signal generation circuit 211, a buffer circuit 215, and a selection circuit 216. The data signal generation circuit 211 is based on the selection signal SEL and gradation data Dr, Dg, and Db indicating gradations to be displayed on the m pixel circuits 400 in the j-th column.
A circuit that generates data signals X1r, X1g, and X1b; a data selection circuit 214;
A DAC 213 and a voltage follower 212 are provided.

The data selection circuit 214 generates grayscale data Dr, Dg, and Db based on the selection signal SEL.
Among them, one gradation data is selected. The DAC 213 performs DA conversion on the gradation data selected by the data selection circuit 214 to generate an analog signal. Then, this analog signal is output as it is in the positive unit period, and is output after inverting the polarity in the negative unit period. The output signal of the DAC 213 becomes the input signal of the voltage follower 212, and the output signal of the voltage follower 212 becomes the data signal X1r, X1g, or X1b.
The voltages of the data signals X1r, X1g, and X1b are zero or more in the positive unit period and zero or less in the negative unit period.

The buffer circuit 215 temporarily holds and outputs the precharge signal Vpre. The selection circuit 216 selects one of the data signal generated by the data signal generation circuit 211 and the precharge signal Vpre from the buffer circuit 215 as the data line signal Xj based on the enable signal XENB. . That is, the precharge signal Vpre is selected when the enable signal XENB is at the L level (precharge period Pre), and the data signal is selected when the enable signal XENB is at the H level (data period Da).

FIG. 4 is a block diagram showing a configuration of the timing control circuit 220. As shown in FIG. 4, the timing control circuit 220 includes a precharge signal generation circuit 20, a data signal generation circuit 30, a comparison voltage generation circuit 222, selection circuits 221, 223, and 224, a comparator 225, and a counter circuit. 226 and an arithmetic circuit 227. The precharge signal generation circuit 20 is a circuit that generates a precharge signal Vpre based on the polarity signal Vpl, and includes a positive potential supply unit 21, a negative potential supply unit 22, a selection circuit 23, a voltage follower 24, Is provided.

The positive potential supply unit 21 supplies the positive potential Vp to the selection circuit 23, and the negative potential supply unit 2.
2 supplies the negative potential Vn to the selection circuit 23. The positive potential Vp is equal to the driving voltage of the dot when the dot displays the maximum gradation in the positive unit period, and the negative potential Vn is
Although it is equal to the drive voltage of the dot when the dot displays the maximum gradation in the positive unit period, the present invention is not limited to this.

The selection circuit 23 selects one of the two supplied potentials based on the polarity signal Vpl, and outputs a signal having the selected potential. The positive potential Vp is selected in the positive unit period, and the negative potential Vn is selected in the negative unit period. The output signal of the selection circuit 23 becomes the input signal of the voltage follower 24, and the output signal of the voltage follower 24 is the precharge signal Vpre.
It becomes. As is clear from the above description, the selection circuit 23 selects the positive potential Vp and the negative potential Vn according to the polarity inversion period of the data signal, and outputs it as the precharge signal Vpre. Function as.

The data signal generation circuit 30 is a circuit that generates a data signal Xw based on specific data D, and includes a DAC 31 and a voltage follower 32. Data D is data indicating the driving voltage of the dot when the dot displays the maximum gradation in the positive unit period. D
The AC 31 performs DA conversion on the data D to generate an analog signal having a voltage corresponding to the highest gradation. Then, this analog signal is output as it is in the positive unit period, and is output after inverting the polarity in the negative unit period. The output signal of the DAC 31 is the voltage follower 3
2 and the output signal of the voltage follower 32 becomes the data signal Xw. The voltage of the data signal Xw becomes a positive voltage (positive potential Vp) in the positive unit period and a negative voltage (negative potential Vn) in the negative unit period.

The selection circuit 221 selects either the precharge signal Vpre or the data signal Xw based on the enable signal XENB. That is, the precharge signal Vpre is selected during the period when the enable signal XENB is at the L level (precharge period Pre).
The data signal Xw is selected while the enable signal XENB is at the H level (data period Da). The selected signal is supplied to the data line 105 as the output signal Vout.

The comparison voltage generation circuit 222 generates a comparison voltage to be compared with the voltage of the data line 105.
The comparison voltage is equal to the reference voltage GND, but is not limited thereto. Selection circuits 223 and 2
24 selects either the comparison voltage or the voltage of the data line 105 based on the polarity signal Vpl, and outputs the selected voltage. Specifically, the selection circuit 223 includes:
The voltage of the data line 105 is selected in the positive unit period, and the comparison voltage is selected in the negative unit period. On the other hand, the selection circuit 224 selects the comparison voltage in the positive unit period and the data line 10 in the negative unit period.
A voltage of 5 is selected. That is, the selection circuits 223 and 224 function as a voltage detection unit that detects the voltage of the data line 105.

The comparator 225 compares the output voltage of the selection circuit 223 with the output voltage of the selection circuit 224, and outputs a binary enable signal XENB based on the comparison result. The enable signal XENB is H when the output voltage of the selection circuit 223 exceeds the output voltage of the selection circuit 224.
Level, otherwise L level. That is, the enable signal XENB indicates the data period Da when the voltage of the data line 105 exceeds the comparison voltage in the positive unit period, indicates the precharge period Pre in other cases, and indicates the data line during the negative unit period. The data period Da is indicated when the voltage 105 is lower than the comparison voltage, and the precharge period Pre is indicated otherwise.

As is clear from this, the comparator 225 functions as a comparison unit that compares the voltage of the data line 105 and the comparison voltage, while detecting that the voltage of the data line 105 has reached the comparison voltage, It functions as a first control unit that controls the selection circuit 221 to switch the signal to be output to 105 from the precharge signal Vpre to the data signal Da and ends the precharge period Pre.

The counter circuit 226 is a circuit that counts the pulses of the clock signal CLK. The counter circuit 226 starts counting when the enable signal XENB becomes L level, and stops counting when the enable signal XENB becomes H level, and the count value FB at that time The arithmetic circuit 227
To supply. Further, the counter circuit 226 resets the count value FB at a timing specified by the reset signal XRES. The reset signal XRES is a binary signal that designates the timing for resetting the count value FB, and the level is maintained at the L level in a period from a certain time before the end of 1H to the end of 1H, At H level. The count value FB is reset when the reset signal XRES becomes L level.

As described above, in the liquid crystal device 1, polarity inversion is performed every 1H, and precharge is first performed in 1H. Therefore, the voltage of the data line 105 rises from the start in the positive unit period, eventually exceeds the reference voltage GND, decreases in the negative unit period, and decreases from the start and eventually falls below the reference voltage GND. Therefore, the counter circuit 226 has a precharge period Pr.
It functions as a time measuring unit that measures the length of e, and the count value FB indicates the length of the precharge period Pre of the data line 105.

The arithmetic circuit 227 selects the selection signal SEL based on the count value FB and the known unit time.
Is generated. Specifically, first, a precharge time (the length of the precharge period Pre) indicated by the count value FB is subtracted from the unit time to calculate a differential time. Next, the time allocated to each of these pixel circuits 400 is calculated by dividing this difference time by the number of pixel circuits 400 constituting one pixel, that is, three. Next, a selection signal SEL is generated so that this allocation is achieved.

The selection signal SEL generated in the arithmetic circuit 227 is supplied to the data selection circuit 214 in FIG. That is, the arithmetic circuit 227 generates the data signals X1r, X1g, and X1b corresponding to the R, G, and B dots for the equal time period in the data period Da based on the precharge time measured by the counter circuit 226. As shown, the data signal generation circuit 21
1 functions as a second control unit for controlling 1.

FIG. 5 is a timing chart for explaining the operation of the liquid crystal device 1. In FIG.
Although the fluctuation of the voltage of the data line 103 is shown, the voltage of the n data lines 103 actually fluctuates. Also, of the two 1Hs shown in FIG. 5, the preceding 1H is a positive unit period in which the driving voltage is written for the first pixel, and the subsequent 1H is a negative unit in which the driving voltage is written for the second pixel. It is a period.

First, the polarity signal Vpl becomes a positive level, and the positive unit period starts. Then, the selection circuit 23 in FIG. 4 selects the positive potential Vp, the precharge signal generation circuit 20 generates the precharge signal Vpre whose level is the positive potential Vp, and the selection circuit 223 generates the data line 1
The voltage of 05 is selected, and the selection circuit 224 selects the comparison voltage. As shown in FIG.
Since the voltage of the data line 105 at this time is lower than the comparison voltage, the enable signal XENB output from the comparator 225 becomes L level.

When the enable signal XENB becomes L level, the precharge signal Vpre is selected in the selection circuit 221 in FIG. 4, and this is supplied to the data line 105 as the output signal Vout.
That is, precharge for the data line 105 is started. Since the level of the precharge signal Vpre at this time is the positive potential Vp, the precharge increases the voltage of the data line 105 as shown in FIG. 5, and eventually reaches the comparison voltage.

When the enable signal XENB becomes L level, the selection circuit 216 in FIG. 3 selects the precharge signal Vpre whose level is the positive potential Vp, and this is supplied to the data line 103 as the data line signal X1. That is, precharge for the data line 103 is started. By this precharge, as shown in FIG. 5, the voltage of the data line 105 rises and eventually reaches the reference voltage GND.

Further, when the enable signal XENB becomes L level, the counter circuit 226 starts counting. Accordingly, the count value FB increases with time.

When the voltage of the data line 105 reaches the comparison voltage and the output voltage of the selection circuit 223 in FIG. 4 exceeds the output voltage of the selection circuit 224, the enable signal XENB becomes H level. When the enable signal XENB becomes H level, the selection circuit 221 selects the data signal Xw, which is supplied to the data line 105 as the output signal Vout. That is, the precharge period P
re ends and the data period Da starts.

The voltage of the data signal Xw in the data period Da is a positive voltage. Therefore, as shown in FIG. 5, the voltage of the data line 105 continues to rise and gradually approaches the positive voltage. Therefore, the enable signal XENB maintains the H level from the end of the precharge period Pre to the end of the positive unit period.

When the enable signal XENB becomes H level, the counter circuit 226 in FIG. 4 stops counting, and the count value FB at this time is supplied to the arithmetic circuit 227. The count value FB is reset when the reset signal XRES becomes L level for a predetermined time before the end of the positive unit period. In the arithmetic circuit 227, the time indicated by the supplied count value FB is 1
The difference time obtained by subtracting from the length of H (the length of the data period Da) is divided by 3, and the time allocated to each of the data signals X1r, X1g, and X1b is calculated, so that this allocation is achieved. A selection signal SEL is generated. In the data selection circuit 214 of FIG. 3, a data signal is selected based on the selection signal SEL. That is, the data signal X1r is selected in the writing period R1, the data signal X1g is selected in the writing period G1, and the data signal X1b is selected in the writing period B1.

The enable signal XENB maintains the H level from the end of the precharge period Pre to the end of the positive unit period, that is, over the write periods R1, G1, and B1. Therefore, the selection circuit 216 selects the data signal selected by the data selection circuit 214, and
This is supplied to the data line 103 as the data line signal X1. That is, the data signal 103 is supplied with the data signal X1r in the writing period R1, the data signal X1g in the writing period G1, and the data signal X1b in the writing period B1. Since the potentials of these data signals are all zero or more, the voltage of the data line 103 changes as illustrated in FIG.

Then, the polarity signal Vpl becomes a negative level. Then, the negative potential Vn is selected in the selection circuit 23 in FIG. 4, the precharge signal Vpre whose level is the negative potential Vn is generated in the precharge signal generation circuit 20, and the comparison voltage is selected in the selection circuit 223. Selection circuit 2
In 24, the voltage of the data line 105 is selected. As shown in FIG. 5, since the comparison voltage at this time is lower than the voltage of the data line 105, the enable signal XENB output from the comparator 225 becomes L level.

Then, the enable signal XENB becomes L level and the negative unit period starts. Even in the negative unit period, the same operation as described above is performed. However, in the negative unit period, the level of the precharge signal Vpre becomes the negative potential Vn. Therefore, in the precharge period Pre, the voltage of the data line 105 decreases to reach the comparison voltage, and the voltage of the data line 103 is It decreases and reaches the reference voltage GND. Further, since the voltage of the data signal Xw becomes a negative voltage in the negative unit period, the voltage of the data line 105 continues to decrease through the writing periods R2, G2, and B2, and gradually approaches the negative voltage. In the negative unit period, since the voltages of the data signals X1r, X1g, and X1b are all equal to or lower than zero, the voltage of the data line 103 changes as illustrated in FIG.

As described above, in the present embodiment, the precharge period Pre ends when the voltage of the data line 105 reaches the comparison voltage. Therefore, even if the precharge signal Vpre is increased in order to shorten the precharge period Pre, there is no possibility that extra charge is charged to the data lines 103 and 105, and power consumption is suppressed. Further, in the data period Da, data signals corresponding to R, G, and B dots are generated for an equal period of time based on the length of the precharge period Pre (precharge time). That is, when the precharge period Pre is shortened, the voltage writing period R, G, and B to the R, G, and B dots is longer by that amount.
Is secured. Therefore, according to the present embodiment, it is possible to ensure a long writing period while suppressing power consumption. An a-TFT having lower mobility than the LTPS-TFT can be adopted as the TFT 50 because a long writing period can be secured.

By the way, the precharge time varies depending on a change in characteristics of each part such as the precharge signal generation circuit 20 over time. Therefore, when the precharge period is fixed, there are cases where the amount of charge to be charged is insufficient and writing is insufficient, or the amount of charge to be charged is excessive and power consumption is increased. appear. On the other hand, in the present embodiment, when the voltage of the data line reaches the comparison voltage, the precharge period Pre ends, and the write periods R, G, and B are determined based on the measured precharge time. That is, since the precharge period Pre and the write periods R, G, and B are dynamically set based on the measured precharge time, such a case does not occur.

<B: Modification>
Note that the above-described embodiment is modified and the data line 105 and the dummy circuit 500 are not provided.
One voltage among the plurality of data lines 103 may be compared with the comparison voltage. In this case, the voltage of the one data line 103 at the start of the precharge period Pre depends on the voltage written immediately before using the data line 103. And the precharge time measured becomes short, so that the difference of this voltage and a comparison voltage is small. That is, the time corresponding to the display content is measured as the precharge time. The precharge period with the precharge time as a length may be too short for the data lines 103 other than the one data line 103.

On the other hand, in the above-described embodiment, the voltage of the data line 105 is compared with the comparison voltage. The data line 105 includes a data signal Xw having a positive potential Vp in the positive unit period and a negative potential Vn in the negative unit period in the data period Da.
Is supplied. Therefore, a precharge period that is not too short for any of the plurality of data lines 103, that is, a sufficiently long precharge period can be set. Also,
Since the data line 105 is a dummy wiring that does not contribute to display, even if the data signal Xw is supplied in the data period Da, the display is not affected.

In the above-described embodiment, the pixel circuit 400 includes a normally black liquid crystal element. However, the pixel circuit 400 may be modified to include a normally white liquid crystal element. In the above-described embodiment, the polarity inversion is performed every three dots. However, the present invention is not limited to this. That is, the present invention can include a form in which polarity inversion is performed for every predetermined number of dots of 1 or more. In the above-described embodiment, the present invention is applied to a liquid crystal display device that displays a color image. However, the present invention is applicable to a liquid crystal display device that displays a monochrome image or a liquid crystal device that does not display an image. Applicable.

<C: Application example>
Next, an electronic apparatus using the liquid crystal device 1 will be described. FIG. 6 is a perspective view showing a configuration of a mobile personal computer adopting the liquid crystal device 1 as a display device. The personal computer 2000 includes a liquid crystal device 1 as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002.

FIG. 7 shows a configuration of a mobile phone that employs the liquid crystal device 1 as a display device. Mobile phone 3
000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the liquid crystal device 1 as a display device. By operating the scroll button 3002, the screen displayed on the liquid crystal device 1 is scrolled.

FIG. 8 shows a personal digital assistant (PDA: Personal Digit) employing the liquid crystal device 1 as a display device.
al Assistants). The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the liquid crystal device 1 as a display device. When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the liquid crystal device 1.

Electronic devices to which the liquid crystal device according to the present invention is applied include those shown in FIGS. 6 to 8, digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic papers, calculators. , Word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like.

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device, 20 ... Precharge signal generation circuit (precharge signal generation part), 21 ...
Positive potential supply unit, 22... Negative potential supply unit, 23... Selection circuit (potential selection unit), 216.
Selection circuit 30, 211 ... data signal generation circuit (data signal generation unit), 101 ... scanning line,
103, 105 ... data line, 200 ... data line driving circuit, 210 ... driving circuit, 220 ... timing control circuit, 221 ... selection circuit (selection unit), 223, 224 ... selection circuit (voltage detection unit), 214 ... data selection Circuit 222... Comparison voltage generation circuit (comparison voltage generation unit) 225
... Comparator (first control unit, comparison unit), 226 ... Counter circuit (time measurement unit), 22
7: arithmetic circuit (second control unit), 400: pixel circuit, 500: dummy circuit.

Claims (8)

A liquid crystal device comprising a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits provided corresponding to intersections of the scanning lines and the data lines,
A data signal generation unit that generates a data signal having a magnitude corresponding to a gradation to be displayed, and inverts the polarity of the data signal for each predetermined number of dots;
A precharge signal generator for generating a precharge signal;
A selection unit that selects one of the data signal and the precharge signal and outputs the selected signal to the data line;
A voltage detection unit that detects a voltage of the data line and outputs a detection voltage in a precharge period in which the selection unit outputs the precharge signal to the data line;
The precharge period is controlled by detecting that the detection voltage has reached a predetermined comparison voltage and controlling the selection unit to switch the signal output to the data line from the precharge signal to the data signal. A first control unit for terminating
A time measuring unit that measures the length of the precharge period and outputs a precharge time;
Based on the precharge time, in the data period in which the selection unit selects the data signal, the data signal generation unit is configured to generate a data signal corresponding to each of the predetermined number of dots for an equal time. A second control unit to control;
A liquid crystal device comprising: The precharge signal generator is
A positive potential supply section for supplying a positive potential;
A negative potential supply unit for supplying a negative potential;
A potential selection unit that selects the positive potential and the negative potential according to a cycle of polarity inversion of the data signal and outputs the selected precharge signal;
The liquid crystal device according to claim 1. The first controller is
A comparison voltage generator for generating the comparison voltage;
A comparison unit that compares the detection voltage with the comparison voltage;
Controlling the selection unit to switch from the precharge signal to the data signal based on the comparison result of the comparison unit;
The liquid crystal device according to claim 1, wherein the liquid crystal device is a liquid crystal device. The second control unit divides the difference time obtained by subtracting the precharge time from the unit time by the predetermined number when the time when the data signal is positive or negative is set as a unit time. Determining the time allocated to the predetermined number of dots;
The liquid crystal device according to claim 1, wherein the liquid crystal device is a liquid crystal device. The data line on which the voltage detection unit detects a voltage is a dummy data line that does not contribute to display among the plurality of data lines.
The liquid crystal device according to claim 1, wherein the liquid crystal device is a liquid crystal device. The pixel circuit includes a pixel electrode, a counter electrode, a liquid crystal sandwiched between the pixel electrode and the counter electrode, the scanning line and the gate, and the data line and one of the source and the drain connected. The pixel electrode and an amorphous thin film transistor to which one of a source or a drain is connected,
The liquid crystal device according to claim 1, wherein the liquid crystal device is a liquid crystal device.   An electronic apparatus comprising the liquid crystal device according to claim 1. A driving method of a liquid crystal device comprising a plurality of scanning lines, a plurality of data lines, and a plurality of pixel circuits provided corresponding to intersections of the scanning lines and the data lines,
A data signal having a magnitude corresponding to the gradation to be displayed is generated, and the polarity of the data signal is inverted every predetermined number of dots,
One of the data signal and the precharge signal is selected and output to the data line,
Detecting a voltage of the data line as a detection voltage in a precharge period of outputting the precharge signal to the data line;
Detecting that the detection voltage has reached a predetermined comparison voltage, controlling the signal output to the data line to switch from the precharge signal to the data signal, and terminating the precharge period,
Measure the length of the precharge period to obtain the precharge time,
Based on the precharge time, the data signal corresponding to each of the predetermined number of dots is controlled to be generated for an equal time in a data period for selecting the data signal.
A driving method of a liquid crystal device.

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