JP2011199607A - Oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit which suppresses oscillation stop at a time when an oscillation frequency is switched.SOLUTION: An oscillation circuit has: first and second inductors L, Lx provided at a first reference voltage side; first and second transistors P1, Px1 which are provided between a second reference voltage and the first and second inductors, respectively, and the gates and the drains of which are cross-connected; first and second capacitor groups connected to the first and the second inductances, respectively, and having a plurality of frequency control capacitors C-C, C-Cin parallel; a plurality of first switches SW-SWprovided between corresponding frequency control capacitors of the first and the second capacitor groups and controlled to be conducted or non-conducted on the basis of an oscillation frequency control signal; and a plurality of second switches SW, SWprovided between both terminals of the first switches and a prescribed voltage. When switching the oscillation frequency control signal, the second switches provided in both the terminals of the first switches changed over from conducted to non-conducted are temporarily conducted.

Description

  The present invention relates to an oscillation circuit whose frequency is variably controlled.

  As the oscillation circuit, an LC oscillation circuit using the oscillation of the LC circuit is widely used. For example, an LC oscillation circuit is also adopted for a local oscillator that generates a local frequency signal of a wireless communication device. Such an oscillation circuit is configured to change its oscillation frequency by a frequency control signal.

  The LC oscillation circuit has an LC circuit that oscillates and a drive transistor for maintaining the oscillation. The oscillation frequency can be variably controlled by variably controlling the capacitance value of the capacitor C in the LC circuit. The variable control of the capacitance value of the capacitor is performed by continuously changing the capacitance value of the variable capacitance capacitor such as a varactor capacitance based on the control voltage, or by changing a plurality of capacitors having discrete capacitance values such as a power of 2 times. Based on the control code, the capacitance value is discretely changed by selecting or deselecting with a switch. Such LC oscillation circuits are described in Patent Documents 1 and 2 and the like.

JP 2006-238084 A JP 2007-221864 A

  In the LC oscillation circuit described above, when a plurality of capacitors are switched by a control code and the oscillation frequency is switched, the output voltage of the oscillation circuit is temporarily fixed to the ground potential or the power supply potential, and oscillation may stop. The LC oscillator circuit restarts the oscillation operation again when noise that synchronizes with the oscillation frequency occurs in the LC circuit. However, if the oscillation stops temporarily, the operation time becomes longer in operations such as performing band search by switching the frequency continuously or creating the oscillation frequency table of the oscillation circuit by switching the frequency continuously. There is a problem.

  Therefore, an object of the present invention is to provide an oscillation circuit that suppresses oscillation stop when the oscillation frequency is switched.

The first aspect of the oscillator circuit is
First and second inductors provided on the first reference voltage side;
First and second transistors, each provided between a second reference voltage and the first and second inductors and having a gate and a drain cross-connected,
First and second capacitor groups connected to each of the first and second inductances and having a plurality of frequency control capacitors in parallel;
A plurality of first switches provided between corresponding frequency control capacitors of the first and second capacitor groups and controlled to be conductive or non-conductive based on an oscillation frequency control signal;
A plurality of second switches respectively provided between both terminals of the first switch and a predetermined voltage;
When the oscillation frequency control signal is switched, the second switch provided at both terminals of the first switch that is switched from conduction to non-conduction is temporarily conducted.

  According to the first aspect, it is possible to suppress temporary oscillation stop when switching the oscillation frequency.

It is a figure explaining the oscillation operation of LC circuit. It is a circuit diagram of the conventional oscillation circuit. It is a figure explaining the operation | movement stop of an oscillation circuit. It is a figure explaining the 1st operation which causes the stop of an oscillation circuit. It is a figure explaining the 2nd operation which causes a stop of an oscillation circuit. It is a block diagram of the oscillation circuit in 1st Embodiment. It is a block diagram of the oscillation circuit in 2nd Embodiment. It is a block diagram of the oscillation circuit in 2nd Embodiment. 1 is a circuit diagram of an oscillation circuit according to a first embodiment. FIG. It is a circuit diagram of the oscillation circuit of 2nd Embodiment. It is a circuit diagram of the oscillation circuit of 3rd Embodiment. It is a circuit diagram of the oscillation circuit of 4th Embodiment. It is a circuit diagram of the oscillation circuit of 5th Embodiment. It is a block diagram of a PLL synthesizer using the oscillation circuit of the present embodiment.

  FIG. 1 is a diagram for explaining the oscillation operation of the LC circuit. FIG. 1A shows the oscillation voltage waveform, and FIG. 1B shows the oscillation state of the LC circuit. First, at time t4, charge is accumulated in the capacitor C, and the voltage at the node n1 has a positive maximum value. From this state, at time t1, the electric charge of the capacitor C is discharged and a current I1 is generated, and a magnetic flux H1 that cancels the current I1 is generated in the inductor L opposite to the current I1. Even after the charge in the capacitor C is discharged, the current I1 continues to flow due to the magnetic flux H1 stored in the inductor L, and at time t2, charge having a polarity opposite to that at time t4 is accumulated in the capacitor C. In this state, the node n1 has a negative maximum value. From this state, at time t3, the electric charge of the capacitor C is discharged and a current I3 is generated, and a magnetic flux H3 that cancels the current I3 is generated in the inductor L opposite to the current I3. Further, even after the charge in the capacitor C is discharged, the current I3 continues to flow due to the magnetic flux H3 stored in the inductor L, and at time t4, charge having a polarity opposite to that at time t2 is accumulated in the capacitor C. The above operation is repeated and the LC oscillation operation continues.

  The LC circuit of FIG. 1 theoretically repeats LC oscillation forever, but the LC oscillation gradually attenuates and stops due to the parasitic resistance in the LC circuit. For this reason, in order to continue the LC oscillation, the oscillation circuit is provided with a drive transistor (not shown) to assist the charging operation to the capacitor.

FIG. 2 is a circuit diagram of a conventional oscillation circuit. This oscillation circuit includes first and second inductors L and Lx provided on the ground GND side which is a first reference voltage, a power supply voltage VDD which is a second reference voltage, and first and second inductors L. , Lx, P-channel type first and second transistors P1, Px1 (driving transistors) whose gates and drains are cross-connected, and first and second inductances L, Lx, respectively. Between the first and second capacitor groups C _{0 to} C _n and C _{x0 to} C _{xn that} are connected and have a plurality of frequency control capacitors C _{0 to} C _n and C _{x0 to} C _xn in parallel, and between the frequency control capacitors And a plurality of first switches SW _{0 to} SW _n that are controlled to be conductive or non-conductive based on the oscillation frequency control signals FC _{0 to} FC _n .

  Further, capacitors Cv and Cxv for fine frequency control of the frequency are provided, and the capacitance values of these capacitors Cv and Cxv are controlled based on the fine control voltage VT.

  In this oscillation circuit, LC circuits are provided on the left and right, and sine waves of opposite phases are generated at the left and right output terminals Out and Xout. The oscillation circuit includes P-channel transistors P1 and Px1 between output terminals Out and Xout, which are connection points between the two inductors L and Lx, and the first and second capacitor groups, and the power supply voltage VDD, respectively. Provided, and their gates and drains are cross-connected. The left and right LC circuits oscillate in opposite phases, and the transistors P1 and Px1 also have opposite phases and become conductive, supporting the oscillation of each LC circuit. For example, transistors P1 and Px1 conduct more deeply when the corresponding LC circuit is at times t3 and t4 in FIG. 1 to assist charging of the capacitor. By providing these transistors P1 and Px1, the oscillation operation of the left and right LC circuits is continued.

In the above oscillation circuit, if the first switches SW _{0 to} SW _n connecting the frequency control capacitors are turned on, the frequency control capacitors on both sides thereof are connected to the virtual ground, and the frequency control capacitors are connected. C _{0 to} C _n and C _{x0 to} C _xn are capacitors in the LC circuit, and the LC oscillation circuit oscillates at a frequency corresponding to the capacitance value of the capacitor and the inductance of the inductor. When the first switches SW _{0 to} SW _n are turned off, the corresponding frequency control capacitors C _{0 to} C _n and C _{x0 to} C _xn are disconnected from the LC circuit. Therefore, the oscillation frequency can be variably controlled by selecting and deselecting the frequency control capacitors C _{0 to} C _n and C _{x0 to} C _xn based on the frequency control signals FC _{0 to} FC _n .

These frequency control capacitors C _{0 to} C _n and C _{x0 to} C _xn have a capacitance value that is a power of 2 of the unit capacitance value C, as shown in FIG. Therefore, by combining these frequency control capacitors, the capacitance value of the frequency control capacitor can be variably controlled with 2 _{n + 1} gradations.

  Also, the oscillation frequency is variably controlled by the fine adjustment capacitors Cv and Cxv based on the same principle. That is, the oscillation frequency is finely controlled by changing the capacitance values of the fine control capacitors Cv and Cxv by raising and lowering the control voltage VT.

  FIG. 3 is a diagram for explaining operation stop of the oscillation circuit. In FIG. 3, the differential outputs Out and Xout of the oscillation circuit LC-OSC shown in FIG. 2 are sine waves, and the sine waves are shaped by a buffer into rectangular waves, and the rectangular waves are frequency dividers. The structure divided by is shown. Such a configuration is a part of a PLL circuit described later.

By switching the frequency control signals FC _{0 to} FC _n during the oscillation operation of FIG. 3A, the oscillation frequency is switched. However, depending on the combination of frequency control signals before and after switching, the oscillation circuit LC-OSC may temporarily stop as shown in FIG. In this temporary stop state, the outputs Out and Xout of the oscillation circuit are fixed to the power supply voltage VDD or the ground voltage GND. However, the LC circuit restarts the oscillation operation with the noise having the same frequency as the oscillation frequency after a predetermined time. This is as shown in FIG.

  Such a temporary stop of the oscillation circuit is not preferable as described above. Hereinafter, the temporary stop of the oscillation operation will be described in detail.

FIG. 4 is a diagram for explaining a first operation that causes the oscillation circuit to stop. This first operation is when the frequency difference before and after frequency switching is small. For example, as shown in FIG. 4, the first switch group SW _{0 to} SW _n-1 is changed from the conductive state to the non-conductive state. This is an operation in which the first switch SW _n is switched from the non-conductive state to the conductive state. That is, this is an operation in which the capacitance value of the LC circuit is switched from the following capacitance value Ctotal1 to Ctotal2, and the frequency difference before and after switching is very small.
Ctotal1 = (2 ⁰ +2 ¹ + +2 ^n-1 ) * C
Ctotal2 = 2 ⁿ * C
In the first operation, for example, as shown in the figure, the capacitors C _{0 to} C _n-1 and C _{x0 to} C _xn-1 are charged, and the first switch groups SW _{0 to} SW _n are charged. _-1 changes from ON to OFF, and the first switch SW _n changes from OFF to ON. At this time, the charges of the capacitors C _{0 to} C _n−1 are discharged by the currents Im and Ip, and the capacitors C _{x0 to} C _xn−1 are also discharged by the currents Ixm and Ixp, and the capacitors C _n , _Cxn charging and discharging must be initiated.

However, when the first switch group SW _{0 to} SW _n-1 is turned off, the path of the discharge currents Ip and Ixm through the first switch group SW _{0 to} SW _n-1 is cut off, and these first switches Discharge currents Ip and Ixm flow only through power supply resistors r and rx provided parasitically between the source and drain of the MOS transistors constituting the switch groups SW _{0 to} SW _n−1 and the ground. Since the amount of charge on both electrodes of the capacitor is kept the same by Gauss's theorem, if the currents Ip and Ixm are small, the currents Im and Ixp are also small, and the discharge time of the charges of the capacitors C _{0 to} C _n-1 becomes long. . Due to the discharge of the charges of the capacitors C _{0 to} C _n−1 , a magnetic flux is formed in the inductances I and Ix and the capacitor C _n is charged, and re-oscillation by the next capacitor C _n starts. Therefore, the capacitors C _{0 to} C _{n If} the discharge time of _-1 charge becomes long, it will take a long time to re-oscillate.

FIG. 5 is a diagram for explaining a second operation that causes the oscillation circuit to stop. This second operation is a case where the frequency difference before and after frequency switching is large and the capacitance value is switched from a small capacitance value to a large capacitance value. As shown in FIG. 5, the first switch SW ₀ is switched from the conductive state to the non-conductive state. In addition, the first switch group SW _{1 to} SW _n is switched from the non-conductive state to the conductive state. That is, this is an operation in which the capacitance value of the LC circuit is switched from the following capacitance value Ctotal1 to Ctotal2, an operation in which the capacitance value changes from a minute capacitance value to a large capacitance value, and the frequency difference is very large.
Ctotal1 = 2 ⁰ * C
Ctotal2 = (2 ¹ + +2 ^n-1 +2 ⁿ ) * C
In the second operation, for example, as shown in the figure, the first switch SW ₀ is turned off from the first switch group SW ₁ while the capacitors C ₀ and C _x0 are charged. ~ SW _n turns from off to on. At this time, the charge of the capacitor C ₀ is discharged by the currents Im and Ip, and the capacitor C _x0 is also discharged by the currents Ixm and Ixp, and instead of these capacitors, the capacitors C _{1 to} C _{n and} C _{x1 to} C _xn are discharged. The next oscillation operation must be resumed by charging and discharging.

However, the amount of charge in the capacitors C ₀ and C _x0 is very small, and the capacitors C _{1 to} C _{n and} C _{x1 to} C _xn have very large capacitance values, so that the oscillation operation can be performed. As a result, the oscillation operation is stopped. Such oscillation stoppage is likely to occur when the total capacitance of the capacitor before switching is small and the difference from the total capacitance of the capacitor after switching is large.

FIG. 6 is a configuration diagram of the oscillation circuit according to the first embodiment. In order to prevent oscillation from being stopped in the first operation of FIG. 4, the oscillation circuit includes first switch groups SW _{0 to} SW _n−1 and capacitor groups C _{0 to} C _n−1 and C _{x0 to} C _xn. The second switch groups SWp and SWxp for charge discharge are provided at the connection nodes n10 and n10x to _-1 . That is, the second switch groups SWp and SWxp are provided on both sides of the first switch groups SW _{0 to} SW _n−1 , respectively.

Then, when the first switch group SW _{0 to} SW _n-1 is switched from on to off and the first switch SW _n is switched from off to on, as shown in the switch control signal shown in FIG. , Temporarily turn on the second switch group SWp, SWxp. The conduction resistances of the second switch groups SWp and SWxp are sufficiently smaller than the feed resistances r and rx, so that the discharge currents Ip and Ixm of the capacitor groups C _{0 to} C _n-1 and C _{x0 to} C _xn-1 Flows through the second switch group SWp, SWxp, which is temporarily turned on, and the capacitor group charges are discharged rapidly, and the energy is rapidly transferred to the inductors I, Ix and the next capacitors C _n , C _xn. Is done. As a result, oscillation stop can be avoided.

FIG. 7 is a configuration diagram of an oscillation circuit according to the second embodiment. This oscillation circuit prevents oscillation stop in the first operation of FIG. In the oscillation circuit, when the first switch group SW _{0 to} SW _n-1 is switched from on to off and the first switch SW _n is switched from off to on, as indicated by the switch control signal in the figure, First, the first switch SW _n is switched from OFF to ON, and the first switch group SW _{0 to} SW _n−1 is maintained in the ON state for a temporary short time dT, and then switched to the OFF state.

Thus, via the capacitor group C ₀ -C _n-1 and C _x0 -C _xn-1 of the discharge current Ip, the first switch group Ixm continues to conduct for a short time dT SW ₀ ~SW _n-1 The electric charge of the capacitor group is rapidly discharged, and the energy is rapidly transmitted to the inductors I and Ix and the next capacitors C _n and C _xn . As a result, oscillation stop can be avoided.

  The oscillation stop by the first operation in FIG. 4 is the total capacitance value of the capacitors that are disconnected from the LC circuit when the first switch is turned off and is connected to the LC circuit when the first switch is turned on from off. This occurs when the difference from the total capacitance value of the capacitor is small. Therefore, the operations of the first and second embodiments of FIGS. 6 and 7 may be performed when the switching of the frequency control signal corresponds to the case where the difference between the total capacitance values before and after the frequency switching is smaller than the reference value. .

FIG. 8 is a configuration diagram of an oscillation circuit according to the third embodiment. This oscillation circuit prevents oscillation stop in the second operation of FIG. In this oscillation circuit, a third switch SWvdd is provided between the power supply voltage VDD and the output terminal Out, and a fourth switch SWgnd is provided between the output terminal Xout and the ground GND. The first switch SW ₀ is turned from on to off, when the first switch group SW ₁ to SW _n are turned from OFF to ON, the third and fourth switches SWvdd, to temporarily conduct SWgnd . As a result, the discharge currents Icp and Ixcm flow to the new capacitor groups C _{1 to} C _n and C _{x1 to} C _{xn in} which the first switch is turned on via the third and fourth switches SWvdd and SWgnd. , Discharge is prevented from stopping. Note that the discharge currents Icp and Izcm are not generated in the capacitor in which the first switch is not turned on.

The third and fourth switches SWvdd and SWgnd may be provided opposite to the left and right. This is because _if the capacitor groups C _{1 to} C _n and C _{x1 to} C _{xn of} the first switch groups SW _{1 to} SW _{n that} are turned on by switching are charged to any polarity, new oscillation is performed. The third and fourth switches SWvdd and SWgnd may be connected to another reference voltage other than the power supply voltage VDD and another reference voltage other than the ground GND. However, for charging / discharging, the reference voltage connected to the third switch needs to be higher than the reference voltage connected to the fourth switch.

  The oscillation stop by the second operation in FIG. 5 is connected to the LC circuit by turning the first switch from off to on based on the total capacitance value of the capacitors that are disconnected from the LC circuit by turning off the first switch. This occurs when the total capacitance value of the capacitors is large and the difference between them is larger than a certain reference value. Therefore, temporary conduction control of the third and fourth switches in FIG. 8 may be performed when the switching of the frequency control signal corresponds to such a case.

FIGS. 9, 10, and 11 are circuit diagrams of the oscillation circuits of the first, second, and third embodiments of FIGS. 6, 7, and 8. FIG. 9 to 11, the switches SW _{0 to} SW _n , SWp, SWxp, and SWgnd are N-channel transistors and the switch SWvdd is a P-channel transistor, and control signals FC _{0 to} FC _n , TM _{0 to} TM for controlling the switches _n , TM _vdd and TM _gnd are supplied to the gate of the transistor. When the control signal is at the H level, the corresponding N channel transistor is turned on, the P channel transistor is turned off, and when the control signal is at the L level, the N channel transistor is turned off and the P channel transistor is turned on. Therefore, the signal waveforms of these control signals are waveforms corresponding to the ON / OFF waveforms of the corresponding switches shown in FIGS.

FIG. 12 is a circuit diagram of an oscillation circuit according to the fourth embodiment. In the oscillation circuit LC-OSC of FIG. 12, inductances L and Lx are provided on the ground GND side, and P-channel transistors P1 and Px1 are provided on the power supply voltage VDD side. In addition, the first, second, and third embodiments shown in FIGS. 9, 10, and 11 are realized in the oscillation circuit LC-OSC. That is, on both sides of the node of the first switch group SW ₀ to SW _n, the second switch SWp, SWxp are respectively provided, respectively, by the control signal TM ₀ to Tm _n is controlled between the ground GND . The first switch group SW ₀ to SW _n are respectively controlled by the frequency control signal FC ₀ ~FC _n. Further, the third switch SWvdd and the fourth switch SWgnd are controlled by control signals TMvdd and TMgnd, respectively.

  Further, the oscillation circuit is provided with fine variable capacitance capacitors Cv and Cxv, and the capacitance value is variably controlled by the control voltage VT.

In addition to the fine adjustment control voltage VT, a coarse adjustment frequency control code Fcode is supplied from a control unit (not shown). The frequency control circuit 10 generates frequency control signals FC _{0 to} FC _n for controlling the first switch groups SW _{0 to} SW _n in response to the frequency control code Fcode. Further, the frequency control circuit 10 controls the control signals TM _{0 to} TM _n for controlling the second switch groups SWp and SWxp and the third and fourth switches SWvdd and SWgnd in response to the frequency control code Fcode. Generate control signals TMvdd and TMgnd.

The control signals TM _{0 to} TM _n are controlled so as to temporarily turn on the second switch corresponding to the first switch controlled from on to off. Further, the control signals TMvdd and TMgnd are controlled so that the third and fourth switches are temporarily turned on when the small total capacity value is switched to the large total capacity value.

Frequency control circuit 10 refers to the control table 12 which is set in advance, depending on the combination of the frequency control signal FC ₀ ~FC _n after switching to the previous frequency control signal FC ₀ ~FC _n switches, second Control signals TM _{0 to} TM _n and TMvdd, TMgnd for temporarily turning on the switch group or the third and fourth switches at the time of frequency switching are generated. Similarly, the frequency control circuit 10 delays the timing of turning off the first switch group controlled from on to off, and temporarily turns on simultaneously with the second switch controlled from off to on. Frequency control signals FC _{0 to} FC _n are generated so as to be in a state.

  The oscillation circuit LC-OSC of FIG. 12 can perform any control of the first and second embodiments. When the oscillation stop of the first operation is avoided by the control of the first switch group according to the second embodiment, the second switch groups SWp and SWxp in FIG. 12 are unnecessary.

FIG. 13 is a circuit diagram of an oscillation circuit according to the fifth embodiment. In the oscillation circuit LC-OSC of FIG. 13, inductances L and Lx are provided on the power supply voltage VDD side, and N-channel transistors N1 and Nx1 are provided on the ground GND side. The second switch groups SWp and SWxp are P-channel transistors, and the first switch groups SW _{0 to} SW _n are N-channel transistors.

In addition, the first, second, and third embodiments shown in FIGS. 9, 10, and 11 are realized in the oscillation circuit LC-OSC. That is, the second switches SWp and SWxp are respectively provided between the power supply voltage VDD at the nodes on both sides of the first switch group SW _{0 to} SW _n and are controlled by the control signals TM _{0 to} TM _n , respectively. The The first switch group SW ₀ to SW _n are respectively controlled by the frequency control signal FC ₀ ~FC _n. Further, the third switch SWvdd and the fourth switch SWgnd are controlled by control signals TMvdd and TMgnd, respectively. Further, the oscillation circuit is provided with fine variable capacitance capacitors Cv and Cxv, and the capacitance value is variably controlled by the control voltage VT.

In FIG. 13, as in FIG. 12, in response to the frequency control code Fcode, the frequency control circuit 10 refers to the control table 12 and the frequency control signals FC _{0 to} FC _n and the control signals TM _{0 to} TM _n Generate TMvdd and TMgnd. Thereby, as described above, each switch is controlled at the time of frequency switching.

  FIG. 14 is a configuration diagram of a PLL synthesizer using the oscillation circuit of the present embodiment. This PLL synthesizer outputs from the output terminals Out and Xout, for example, a high-frequency clock having a phase opposite to that of the reference clock CKref generated by the crystal oscillator C-OSC. The PLL synthesizer includes a frequency divider 1 / N that divides an output high-frequency clock, a phase detector PD that detects a phase difference between the divided controlled clock CKvari and a reference clock CKref, and a phase detector PD A charge pump circuit CP that outputs a charge based on the output of, a low-pass filter LPF that outputs a low-frequency component of the output, and an oscillation circuit LC-OSC of the present embodiment.

  The oscillation circuit LC-OSC finely adjusts the oscillation frequency according to the control voltage VT generated by the loop filter LPF, and changes the oscillation frequency in response to a frequency control code Fcode supplied from a control unit (not shown). . In this case, even if the frequency is switched by the frequency control code Fcode, the oscillation of the oscillation circuit LC-VCO is prevented from stopping as described above.

  Therefore, when a communication apparatus having such a PLL synthesizer performs a predetermined initial operation by scanning a high-speed clock generated by the PLL synthesizer, the initial operation time can be shortened.

  The above embodiment is summarized as follows.

(Appendix 1)
First and second inductors provided on the first reference voltage side;
First and second transistors, each provided between a second reference voltage and the first and second inductors and having a gate and a drain cross-connected,
First and second capacitor groups connected to each of the first and second inductances and having a plurality of frequency control capacitors in parallel;
A plurality of first switches provided between corresponding frequency control capacitors of the first and second capacitor groups and controlled to be conductive or non-conductive based on an oscillation frequency control signal;
A plurality of second switches respectively provided between both terminals of the first switch and a predetermined voltage;
An oscillation circuit in which the second switch provided at both terminals of the first switch that is switched from conduction to non-conduction temporarily conducts when the oscillation frequency control signal is switched.

(Appendix 2)
In Appendix 1,
When the oscillation frequency control signal is switched, the first switch that is switched from conduction to non-conduction is an oscillation that is switched from conduction to non-conduction a predetermined time after the first switch that is switched from non-conduction to conduction is switched. circuit.

(Appendix 3)
In Appendix 1 or 2,
Further, first and second connection nodes between the first and second inductances and the first and second capacitor groups, and first and second reference voltages respectively provided between the first and second connection nodes. 3, having a fourth switch,
An oscillation circuit in which the third and fourth switches are temporarily turned on when the oscillation frequency control signal is switched.

(Appendix 4)
In Appendix 1,
The temporary continuity of the second switch is determined based on the capacitance value of the frequency control capacitor connected to the first switch that is turned off from conduction based on the oscillation frequency control signal and the first value that is turned off from conduction. An oscillation circuit that is generated when a difference from a capacitance value of a frequency control capacitor connected to one switch is smaller than a first reference value.

(Appendix 5)
First and second inductors provided on the first reference voltage side;
First and second transistors, each provided between a second reference voltage and the first and second inductors and having a gate and a drain cross-connected,
First and second capacitor groups connected to each of the first and second inductances and having a plurality of frequency control capacitors in parallel;
A plurality of first switches provided between corresponding frequency control capacitors of the first and second capacitor groups and controlled to be conductive or non-conductive based on an oscillation frequency control signal;
When the oscillation frequency control signal is switched, the first switch that is switched from conduction to non-conduction is an oscillation that is switched from conduction to non-conduction a predetermined time after the first switch that is switched from non-conduction to conduction is switched. circuit.

(Appendix 6)
First and second inductors provided on the first reference voltage side;
First and second transistors, each provided between a second reference voltage and the first and second inductors and having a gate and a drain cross-connected,
First and second capacitor groups connected to each of the first and second inductances and having a plurality of frequency control capacitors in parallel;
A plurality of first switches provided between corresponding frequency control capacitors of the first and second capacitor groups and controlled to be conductive or non-conductive based on an oscillation frequency control signal;
Third and third reference electrodes provided between the first and second connection nodes between the first and second inductances and the first and second capacitor groups and the third and fourth reference voltages, respectively. 4 switches,
An oscillation circuit in which the third and fourth switches are temporarily turned on when the oscillation frequency control signal is switched.

(Appendix 7)
In Appendix 5,
The temporary continuity of the third and fourth switches is determined when the capacitance value of the frequency control capacitor connected to the first switch that is turned off is turned on based on the oscillation frequency control signal. An oscillation circuit that occurs when the capacitance value of the frequency control capacitor connected to the first switch becomes smaller than the first reference value.

(Appendix 8)
In Appendix 5,
An oscillation circuit in which the third reference voltage and the fourth reference voltage are different voltages.

(Appendix 9)
In Appendix 8,
The oscillation circuit in which the third reference voltage is the first or second reference voltage, and the fourth reference voltage is the second or first reference voltage.

L, Lx: First and second inductors
P1, Px1: First and second transistors
C _{0 to} C _n , C _{x0 to} C _xn : Multiple frequency control capacitors
SW _{0 to} SW _n : First switch
SWp, SWxp: Second switch

Claims (5)

First and second inductors provided on the first reference voltage side;
First and second transistors, each provided between a second reference voltage and the first and second inductors and having a gate and a drain cross-connected,
First and second capacitor groups connected to each of the first and second inductances and having a plurality of frequency control capacitors in parallel;
A plurality of first switches provided between corresponding frequency control capacitors of the first and second capacitor groups and controlled to be conductive or non-conductive based on an oscillation frequency control signal;
A plurality of second switches respectively provided between both terminals of the first switch and a predetermined voltage;
An oscillation circuit in which the second switch provided at both terminals of the first switch that is switched from conduction to non-conduction temporarily conducts when the oscillation frequency control signal is switched. In claim 1,
When the oscillation frequency control signal is switched, the first switch that is switched from conduction to non-conduction is an oscillation that is switched from conduction to non-conduction a predetermined time after the first switch that is switched from non-conduction to conduction is switched. circuit. In claim 1 or 2,
Further, first and second connection nodes between the first and second inductances and the first and second capacitor groups, and first and second reference voltages respectively provided between the first and second connection nodes. 3, having a fourth switch,
An oscillation circuit in which the third and fourth switches are temporarily turned on when the oscillation frequency control signal is switched. First and second inductors provided on the first reference voltage side;
First and second transistors, each provided between a second reference voltage and the first and second inductors and having a gate and a drain cross-connected,
First and second capacitor groups connected to each of the first and second inductances and having a plurality of frequency control capacitors in parallel;
A plurality of first switches provided between corresponding frequency control capacitors of the first and second capacitor groups and controlled to be conductive or non-conductive based on an oscillation frequency control signal;
When the oscillation frequency control signal is switched, the first switch that is switched from conduction to non-conduction is an oscillation that is switched from conduction to non-conduction a predetermined time after the first switch that is switched from non-conduction to conduction is switched. circuit. First and second inductors provided on the first reference voltage side;
First and second transistors, each provided between a second reference voltage and the first and second inductors and having a gate and a drain cross-connected,
First and second capacitor groups connected to each of the first and second inductances and having a plurality of frequency control capacitors in parallel;
A plurality of first switches provided between corresponding frequency control capacitors of the first and second capacitor groups and controlled to be conductive or non-conductive based on an oscillation frequency control signal;
Third and third reference electrodes provided between the first and second connection nodes between the first and second inductances and the first and second capacitor groups and the third and fourth reference voltages, respectively. 4 switches,
An oscillation circuit in which the third and fourth switches are temporarily turned on when the oscillation frequency control signal is switched.

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