JP2011199051A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device for improving amplification factor, while assuring the breakdown voltage for the gate.SOLUTION: The semiconductor device 10 includes a channel layer 13 and a gate electrode 19. The device additionally includes, between the channel layer 13 and the gate electrode 19, a spacer layer 14 arranged on the channel layer 13, an electron supply layer 15 arranged on the spacer layer 14 and a barrier layer 16 arranged on the electron supply layer 15. Energy level Ec1 at the lower end of a conduction band of the spacer layer 14 is lower than energy level Ec2 at the lower end of the conduction band of the electron supply layer 15, while energy level Ec3 at the lower end of the conduction band of the barrier layer 16 is higher than the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15.

Description

  The present invention relates to a semiconductor device.

  Conventionally, a high electron mobility transistor (HEMT) is used.

  The HEMT is a field effect type semiconductor device formed using a compound semiconductor such as an InP material, and has excellent high speed characteristics and excellent low noise characteristics.

  The HEMT having high-speed characteristics is applied to, for example, a signal processing circuit of an optical communication system or other high-speed digital circuits. Further, HEMT having low noise characteristics is expected to be applied to amplifiers in the microwave and millimeter wave bands.

In order to operate the circuit at such a high speed as described above, it is required to further increase the mutual inductance g _m that is a parameter related to the amplification factor of the HEMT.

Further, by increasing the value of the mutual inductance g _m , it is possible to improve the value of the cutoff frequency f _T that is the upper limit of the frequency of the amplification operation related to the current gain of the HEMT and the low noise characteristic of the HEMT.

The value of the mutual inductance g _m can generally be increased by shortening the distance between the gate electrode and the channel layer. Between the gate electrode and the channel layer, for example, a spacer layer, an electron supply layer, and a barrier layer are sequentially stacked from the channel layer side. However, if the thickness of the barrier layer is reduced to shorten the distance between the gate electrode and the channel layer, the number of electrons that move from the electron supply layer to the gate electrode beyond the barrier layer increases. There arises a problem that the number of supplied electrons is reduced. Further, reducing the barrier layer reduces the gate breakdown voltage. Further, there is a limit to the lower limit of the thickness of the spacer layer.

JP 2000-323704 A JP 2009-60043 A JP 2005-5646 A JP-A-9-55494 JP 2006-80152 A

  An object of the present specification is to provide a semiconductor device that increases an amplification factor while ensuring a gate breakdown voltage.

  In order to solve the above problems, according to one embodiment of a semiconductor device disclosed in this specification, a channel layer, a spacer layer disposed on the channel layer, an electron supply layer disposed on the spacer layer, A barrier layer disposed on the electron supply layer; and a gate electrode disposed on the barrier layer, wherein an energy level at a lower end of the conduction band of the spacer layer is an energy level at a lower end of the conduction band of the electron supply layer. The energy level at the lower end of the conduction band of the barrier layer is lower than the energy level at the lower end of the conduction band of the electron supply layer.

  According to one embodiment of the semiconductor device disclosed in this specification, the amplification factor can be increased while ensuring the gate breakdown voltage.

  The objects and advantages of the invention will be realized and obtained by means of the elements and combinations particularly pointed out in the appended claims.

  Both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention as claimed.

It is sectional drawing which shows Example 1 of the semiconductor device disclosed to this specification. FIG. 2 is an energy band diagram of the semiconductor device of FIG. 1. It is a figure which shows the principal part of the energy band of the semiconductor device of FIG. It is an energy band figure of the semiconductor device in which the barrier layer is not arranged. It is a figure which shows the IV curve of the semiconductor device of FIG. FIG. 6 is an energy band diagram of Modification 1 of the semiconductor device of Example 1; FIG. 6 is an energy band diagram of a second modification of the semiconductor device according to the first embodiment. FIG. 11 is an energy band diagram of Modification 3 of the semiconductor device of Example 1; FIG. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device of Example 1; FIG. 6 is a second diagram illustrating a manufacturing process of the semiconductor device according to Example 1; FIG. 3 is a diagram (part 3) illustrating a manufacturing step of the semiconductor device of Example 1; FIG. 6 is a diagram (part 4) illustrating a manufacturing step of the semiconductor device of Example 1; It is sectional drawing which shows Example 2 of the semiconductor device disclosed to this specification. It is a figure which shows the principal part of the energy band of the semiconductor device of FIG. It is sectional drawing which shows Example 3 of the semiconductor device disclosed to this specification. It is a figure which shows the principal part of the energy band of the semiconductor device of FIG. It is a figure which shows the modification of the semiconductor device of Examples 1-3 disclosed by this specification. It is a figure which shows the other modification of the semiconductor device of Examples 1-3 disclosed in this specification. FIG. 10 is an energy band diagram of Example 4 of the semiconductor device disclosed in this specification. It is a figure which shows the principal part of the energy band of the semiconductor device of FIG. It is a figure which shows the principal part of the energy band of the modification 1 of the semiconductor device of Example 4. FIG. It is a figure which shows the principal part of the energy band of the modification 2 of the semiconductor device of Example 4. FIG. FIG. 10 is an energy band diagram of Example 5 of a semiconductor device disclosed in this specification. It is a figure which shows the principal part of the energy band of the semiconductor device of FIG.

  Hereinafter, preferred embodiments of a semiconductor device disclosed in this specification will be described with reference to the drawings. However, it should be noted that the technical scope of the present invention is not limited to the embodiments, but extends to the invention described in the claims and equivalents thereof.

  FIG. 1 is a cross-sectional view illustrating a first embodiment of a semiconductor device disclosed in this specification.

  Hereinafter, a case where the semiconductor device 10 is applied to an InP-HEMT that is a field effect transistor will be described as an example.

  In the semiconductor device 10 of this embodiment, as shown in FIG. 1, a buffer layer 12 is disposed on a substrate 11, and a channel layer 13 is disposed on the buffer layer 12. A spacer layer 14 is disposed on the channel layer 13, an electron supply layer 15 is disposed on the spacer layer 14, and a barrier layer 16 is disposed on the electron supply layer 15.

  On the barrier layer 16, the cap layers 17a and 17b are spaced apart and a recess 21 is formed between the cap layer 17a and the cap layer 17b.

  A drain electrode 20 is disposed on the cap layer 17a, and a source electrode 19 is disposed on the cap layer 17b. In the recess 21, the gate electrode 18 is disposed on the barrier layer 16.

  The substrate 11 is a semi-insulating compound semiconductor substrate. I. -InP (SemiInsulation-InP) is used.

  The buffer layer 12 has a function of relaxing lattice mismatch between the substrate 11 and the channel layer 13. In the semiconductor device 10, i-InAlAs is used as a material for forming the buffer layer 12.

  The channel layer 13 is supplied with electrons from the electron supply layer 15, and a two-dimensional electron gas layer is formed in the vicinity of the interface with the spacer layer 14 to function as an electron transit layer. In the semiconductor device 10, i-InGaAs is used as a material for forming the channel layer 13.

  The spacer layer 14 prevents the dopant added in the electron supply layer 15 from diffusing into the channel layer 13. In the semiconductor device 10, i-InAlAs is used as a material for forming the spacer layer 14.

The electron supply layer 15 is uniformly doped with an n-type dopant, and supplies electrons to the channel layer 13 through the spacer layer 14. As the n-type dopant, for example, Si can be used. In the semiconductor device 10, i-InAl _x P is used as a material for forming the electron supply layer 15. In i-InAlP, as the Al composition x increases, the energy gap increases. However, the lattice constant of i-InAlP increases away from the lattice constant of i-InP forming the substrate. Therefore, it is preferable that an upper limit is provided for the Al composition x in the thickness of i-InAlP from the viewpoint of lattice matching with the substrate. Specifically, in the semiconductor device 10, i-InAl _0.3 P is used as a material for forming the electron supply layer 15.

  The barrier layer 16 is in Schottky junction with the gate electrode 18. The barrier layer 16 prevents electrons in the electron supply layer 15 from moving to the gate electrode 18.

  The cap layers 17 a and 17 b reduce the electrical resistance between the source electrode 19 or the drain electrode 20 and the barrier layer 16. In the semiconductor device 10, n-InGaAs is used as a material for forming the cap layers 17a and 17b. The cap layers 17 a and 17 b are in ohmic contact with the source electrode 19 or the drain electrode 20.

FIG. 2 is an energy band diagram of the semiconductor device of FIG. 1 in a thermal equilibrium state. In FIG. 2, a part of the buffer layer 12, the channel layer 13, the spacer layer 14, the electron supply layer 15, the barrier layer 16, and a part of the gate electrode 19 are shown. E _F is the Fermi level.

  FIG. 3 is a diagram showing the main part of the energy band of the semiconductor device of FIG. In FIG. 3, the channel layer 13, the spacer layer 14, the electron supply layer 15, and the barrier layer 16 are shown. Here, FIG. 3 shows the energy levels at the upper end of the valence band and the lower end of the conduction band in a state before carriers such as electrons in each layer move to another layer, and the energy levels at the lower end of the conduction band. In order to show the difference in level, the energy levels of the bands of each layer are relatively arranged. The energy level of each layer shown in FIG. 3 corresponds to that in a state where each layer is spatially separated. Ei in FIG. 3 indicates an intermediate level of the energy gap between the upper end of the valence band and the lower end of the conduction band.

  2 and 3, the energy level Ec1 at the lower end of the conduction band of the spacer layer 14 is lower than the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15, and the conduction level of the barrier layer 16 The energy level Ec3 at the lower end is higher than the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15. The energy level Ec1 at the lower end of the conduction band of the spacer layer 14 is higher than the energy level Ec4 at the lower end of the conduction band of the channel layer 13.

  The energy level Ec1 at the lower end of the conduction band of the spacer layer 14 and the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15 are connected discontinuously. Specifically, the difference ΔEc12 between the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15 and the energy level Ec1 at the lower end of the conduction band of the spacer layer 14 is 0.06 eV.

  The energy level Ec3 at the lower end of the conduction band of the barrier layer 16 and the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15 are connected discontinuously. Specifically, the difference ΔEc23 between the energy level Ec3 at the lower end of the conduction band of the barrier layer 16 and the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15 is 0.11 eV.

  Furthermore, the energy level Ec1 at the lower end of the conduction band of the spacer layer 14 and the energy level Ec4 at the lower end of the conduction band of the channel layer 13 are connected discontinuously. Specifically, the difference ΔEc14 between the energy level Ec1 at the lower end of the conduction band of the spacer layer 14 and the energy level Ec4 at the lower end of the conduction band of the channel layer 13 is 0.52 eV.

  That is, as shown in FIGS. 2 and 3, the energy level at the lower end of the conduction band of each layer increases stepwise from the channel layer 13 side toward the barrier layer 16 side.

  The energy level Ev1 at the upper end of the valence band of the spacer layer 14 is higher than the energy level Ev2 at the upper end of the valence band of the electron supply layer 15, and the energy level at the upper end of the valence band of the barrier layer 16. Ev3 is lower than the energy level Ev2 at the upper end of the valence band of the electron supply layer 15. The energy level Ev1 at the upper end of the valence band of the spacer layer 14 is lower than the energy level Ev4 at the upper end of the valence band of the channel layer 13.

  Therefore, the energy gap Eg2 between the conduction band and the valence band of the electron supply layer 15 is larger than the energy gap Eg1 between the conduction band and the valence band of the spacer layer 14. The energy gap Eg2 between the conduction band and the valence band of the electron supply layer 15 is smaller than the energy gap Eg3 between the conduction band and the valence band of the barrier layer 16. That is, there is a relationship of Eg3> Eg2> Eg1. Further, the energy gap Eg1 between the conduction band and the valence band of the spacer layer 14 is larger than the energy gap Eg4 between the conduction band and the valence band of the channel layer 13.

  The energy level Ev1 at the upper end of the valence band of the spacer layer 14 and the energy level Ev2 at the upper end of the valence band of the electron supply layer 15 are connected discontinuously, and the valence band of the barrier layer 16 The energy level Ev3 at the top of the valence band and the energy level Ev2 at the top of the valence band of the electron supply layer 15 are connected discontinuously. The energy level Ev1 at the upper end of the valence band of the spacer layer 14 and the energy level Ev4 at the upper end of the valence band of the channel layer 13 are connected discontinuously.

  That is, as shown in FIGS. 2 and 3, the energy level at the upper end of the valence band of each layer increases stepwise from the barrier layer 16 side toward the channel layer 13 side.

  In FIG. 2, the level when the energy level at the lower end of the conduction band of the electron supply layer 15 and the barrier layer 16 is the same as the energy level at the lower end of the conduction band of the spacer layer 14 is indicated by a chain line. ing. Similarly, the chain level indicates the level when the energy level at the top of the valence band of the electron supply layer 15 and the barrier layer 16 is the same as the energy level at the top of the valence band of the spacer layer 14. Has been. The chain lines are similarly shown in other band energy drawings to be described later.

  In the semiconductor device 10 having such a band energy structure, as shown in FIG. 2, the electrons e generated in the electron supply layer 15 can easily move to the conduction band of the spacer layer 14. Then, the electrons e moved to the spacer layer 14 further easily move to the channel layer 13 to form a two-dimensional electron gas layer near the interface with the spacer layer 14.

  Further, in the semiconductor device 10, by making the energy gap Eg <b> 2 of the electron supply layer 15 larger than the energy gap Eg <b> 1 of the spacer layer 14, electrons generated in the electron supply layer 15 easily move toward the gate electrode 19. That has been reduced.

  Further, since the electrons e generated in the electron supply layer 15 cannot easily overcome the energy barrier of the barrier layer 16, it is difficult to move over the barrier layer 15 to the gate electrode 19.

Therefore, in the semiconductor device 10, electrons e generated in the electron supply layer 15, it is possible to see easily moved in the direction of the channel layer 13, thereby improving the sheet electron concentration N _S in the two-dimensional electron gas layer in the channel layer 13 is . The semiconductor device 10 has a high gate breakdown voltage.

  The difference between the energy level Ec1 at the lower end of the conduction band of the spacer layer 14 and the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15 is larger than the thermal energy at room temperature. It is preferable for preventing migration from the conduction band 14 to the electron supply layer 15. For example, when the room temperature is 300 Kelvin (27 ° C.), the thermal energy at room temperature is kT = 4.14E-21J = 0.026 eV. On the other hand, as shown in FIG. 3, in the semiconductor device 10, ΔEc12 = 0.06 eV, and ΔEc12 is larger than the thermal energy at room temperature.

  Further, the difference between the energy level Ec1 at the lower end of the conduction band of the spacer layer 14 and the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15 is greater than the thermal energy at the operating temperature of the semiconductor device 10. Is preferable from the same viewpoint.

Next, the semiconductor device 10 can increase the mutual inductance g _m , which is a parameter related to the amplification factor, by reducing the distance between the channel layer 13 and the gate electrode 19 without reducing the gate breakdown voltage. This will be described below.

First, the intrinsic mutual inductance g _m ^int observed from the inside of the semiconductor device 10 is expressed by Expression (1).

g _m ^int = ε _S W _g v _S / d (1)

Here, ε _S is the dielectric constant of the portion between the gate electrode 19 and the channel layer 13, W _g is the gate width, ν _S is the electron saturation velocity, and d is the gate electrode 19 and the channel layer. 13 is the distance between. Therefore, it can be seen from equation (1) that g _m ^int can be increased by reducing the distance d.

Further, the external mutual inductance g _m ^ext observed from the outside of the semiconductor device 10 is expressed by Expression (2).

g _m ^ext = g _m ^int / (1 + R _S · g _m ^int ) (2)

Here, R _S is a source resistance. This source resistance R _S is proportional to the reciprocal of the sheet electron density N _S.

  In the semiconductor device 10, as shown in FIG. 2, between the gate electrode 19 and the channel layer 13, a spacer layer 14 having a thickness t1, an electron supply layer 15 having a thickness t2, and a barrier layer 16 having a thickness t3. And are arranged. Therefore, it can be seen that in order to reduce the distance d between the gate electrode 19 and the channel layer 13, the thickness of each layer may be reduced.

  Here, the thickness t <b> 1 of the spacer layer 14 is preferably equal to or greater than the thickness that prevents the dopant in the electron supply layer 15 from diffusing into the channel layer 13. The thickness t1 of the spacer layer 14 is also preferably a thickness that allows electrons in the electron supply layer 15 to move to the channel layer 13 via the spacer layer 14 by the tunnel effect. From such a viewpoint, the lower limit of the thickness t1 of the spacer layer 14 can be determined. In the semiconductor device 10, the thickness t1 of the spacer layer 14 is set to this lower limit value.

  On the other hand, the thickness t3 of the barrier layer 16 is not less than a thickness that prevents electrons in the electron supply layer 15 from moving to the gate electrode 19 through the barrier layer 16 due to the tunnel effect. It is preferable in securing the above. From such a viewpoint, the thickness t3 is usually at least about the thickness t1.

  From the viewpoint described above, the gate breakdown voltage is ensured when the thickness t1 of the spacer layer 14, the thickness t2 of the electron supply layer 15, and the thickness t3 of the barrier layer 16 satisfy the relationship of Expression (3). In addition, it is preferable for reducing the distance d between the gate electrode 19 and the channel layer 13.

  t1 ≦ t2 + t3 ≦ 2 × t1 (3)

In the semiconductor device 10, when the thickness of each layer satisfies the relationship of the expression (3), the distance d can be reduced and the intrinsic mutual inductance g _m ^int can be increased.

In the semiconductor device 10, even if the distance d is reduced, as described above, electrons in the electron supply layer 15 are prevented from moving to the gate electrode 19 through the barrier layer 16. sheet electron concentration N _S does not decrease with being. Therefore, since the source resistance R _S proportional to the reciprocal of the sheet electron concentration N _S does not increase, the external mutual inductance g _m ^ext also increases with an increase in g _m ^int .

Further, since the intrinsic mutual inductance g _m ^int increases in the semiconductor device 10, the cutoff frequency f _T expressed by the equation (4) also increases.

f _T = g _m ^int / 2π (C _gs + C _gd ) (4)

Here, C _gs is a capacitance between the gate electrode and the source electrode, and C _gd is a capacitance between the gate electrode and the drain electrode.

Furthermore, since the intrinsic mutual inductance g _m ^int and the cut-off frequency f _T increase in the semiconductor device 10, the noise F ₀ expressed by the equation (5) is reduced.

F ₀ = 1 + K _f · (f / f _T ) · (g _m ^int · (R _S + R _g )) ^1/2 (5)

Here, K _f is a fitting parameter, and R _g is a gate resistance.

  Next, the role of the barrier layer 16 of the semiconductor device 10 of this embodiment will be further described by describing the case where no barrier layer is disposed in the semiconductor device 10 shown in FIG. 2 with reference to the drawings. .

  FIG. 4 is an energy band diagram in a thermal equilibrium state of a semiconductor device in which no barrier layer is disposed.

  The semiconductor device 100 shown in FIG. 4 has the same structure as the semiconductor device shown in FIG. 2 except that the barrier layer is not disposed. In the semiconductor device 100, the electron supply layer 15 is in Schottky junction with the gate electrode 19.

  In the semiconductor device 100, the thickness t1 of the spacer layer 14 and the thickness t2 of the electron supply layer 15 are the same in order to reduce the distance d between the gate electrode 19 and the channel layer 13 and improve the amplification factor. ing.

In the semiconductor device 100, by making the energy gap Eg2 of the electron supply layer 15 larger than the energy gap Eg1 of the spacer layer 14, it is possible to reduce the movement of electrons generated in the electron supply layer 15 to the gate electrode 19 easily. ing. However, when the energy gap Eg2 of the electron supply layer 15 is increased, the upper limit value of the dopant concentration that can be added to the electron supply layer 15 decreases. Thus, increasing the energy gap Eg2 of the electron supply layer 15, the dopant concentration can be added is decreased, the sheet electron concentration N _S of channel layer 13 is reduced.

  Further, in the semiconductor device 100, since the thickness t2 of the electron supply layer 15 is thin, the barrier height is low, so that electrons generated in the electron supply layer 15 are sufficiently prevented from moving to the gate electrode 19. I can't.

  Further, in the semiconductor device 100, since the barrier layer is not disposed, it is not possible to sufficiently prevent the electrons generated in the electron supply layer 15 from moving to the gate electrode 19.

Therefore, in the semiconductor device 100, the gate breakdown voltage is reduced. Further, by electrons generated in the electron supply layer 15 is easily moved to the gate electrode 19, the sheet electron concentration N _S of channel layer 13 is reduced.

As described above, in the semiconductor device 100 in which the barrier layer is not disposed, when the sheet electron concentration Ns is decreased, the source resistance R _S is increased, so that the external mutual inductance g _m ^ext shown in Expression (2) is decreased. Become. That is, in the semiconductor device 100, it is difficult to improve the amplification factor by reducing the distance d between the gate electrode 19 and the channel layer 13 while ensuring the gate breakdown voltage.

  On the other hand, in the semiconductor device 10 of the present embodiment shown in FIG. 2, the barrier layer 16 having an energy gap larger than that of the electron supply layer 15 is disposed, so that the energy gap Eg <b> 2 of the electron supply layer 15 is as large as the semiconductor device 100. You don't have to make it big. Therefore, in the semiconductor device 10, since a sufficient dopant concentration can be added to the electron supply layer 15, it is possible to prevent a reduction in the sheet electron concentration Ns. In addition, since the barrier layer 16 is disposed in the semiconductor device 10, electrons generated in the electron supply layer 15 can be sufficiently prevented from moving to the gate electrode 19.

  In other words, the semiconductor device 10 can improve the amplification factor by reducing the distance d between the gate electrode 19 and the channel layer 13 while ensuring the gate breakdown voltage.

  FIG. 5 is a diagram showing an IV curve of the semiconductor device of FIG.

  In FIG. 5, the IV curve of the semiconductor device 10 of the present embodiment is shown by a solid line, and the IV curve of the semiconductor device 100 shown in FIG. 4 is shown by a chain line. Compared with the semiconductor device 100, the semiconductor device 10 has a higher gate breakdown voltage and a higher forward voltage Vf. In addition, the amplification factor of the semiconductor device 10 is increased as compared with the semiconductor device 100.

  Next, a modification of the above-described first embodiment will be described below with reference to the drawings.

  6 is an energy band diagram in a thermal equilibrium state of Modification 1 of the semiconductor device of Example 1. FIG.

  In the semiconductor device 10a of Modification 1, the addition of the n-type dopant to the electron supply layer 15 is δ-doped (also referred to as planar doping). In the electron supply layer 15, the n-type dopant is added in a planar shape only to the central portion in the thickness direction.

  As shown in FIG. 6, the electron supply layer 15 of the semiconductor device 10 a is bent downward with the δ-doped portion as the center in the energy band structure.

  FIG. 7 is an energy band diagram in a thermal equilibrium state of the second modification of the semiconductor device according to the first embodiment.

  In the semiconductor device 10b of Modification 2, the barrier layer 16 is formed of two layers 16a and 16b, and the energy level at the lower end of the conduction band of each of the layers 16a and 16b forming the barrier layer 16 is the electron supply layer. It increases in steps from the 15 side toward the gate electrode 19 side.

  In this way, the semiconductor device 10b has a higher gate breakdown voltage.

  FIG. 8 is an energy band diagram in a thermal equilibrium state of Modification 3 of the semiconductor device of Example 1.

  In the semiconductor device 10c of Modification 3, the spacer layer 14 is formed of two layers 14a and 14b, and the energy level at the lower end of the conduction band of each of the layers 14a and 14b forming the spacer layer 14 is the channel layer 13. It increases in steps from the side toward the electron supply layer 15 side. The other structure of the semiconductor device 10c is the same as that of the second modification described above.

  Next, an example of a preferred method for manufacturing the semiconductor device 10 of the first embodiment will be described below with reference to the drawings.

First, as shown in FIG. 9, a buffer layer (i-InAlAs) 12 is formed on a semi-insulating substrate (SI-InP) 11. A channel layer (i-InGaAs) 13 is formed on the buffer layer 12. A spacer layer (i-InAlAs) 14 is formed on the channel layer 13. An electron supply layer (n-InAl _0.3 P) 15 is formed on the spacer layer 14. On the electron supply layer 15, a barrier layer (i-InAl _0.4 P) 16 is formed. A cap film (n-InGaAs) 17 is formed on the barrier layer 16. As a method for forming each layer, for example, a metal organic chemical vapor deposition method (MOCVD method) can be used. For example, an n-type dopant is added to the electron supply layer 15 at a concentration of 1 × 10 ¹⁹ cm ⁻³ . An n-type dopant is added to the cap film 17 at a concentration of 1 × 10 ¹⁹ cm ⁻³ , for example.

  The thickness of the buffer layer 12 is, for example, 300 nm. The thickness of the channel layer 13 is 15 nm, for example. The thickness of the spacer layer 14 is 3 nm, for example. The thickness of the electron supply layer 15 is, for example, 1 nm. The thickness of the barrier layer 16 is 3 nm, for example. The thickness of the cap film 17 is 50 nm, for example.

  Then, the first mask layer 30 is formed on the cap film 17.

  Next, the first mask layer 30 is patterned using a photolithography technique so as to define an element operation region. Then, using the patterned first mask layer 30 as a mask, the cap film 17 is selectively wet etched until the barrier layer 16 is exposed. As the etching solution, for example, a mixed solution of phosphoric acid, hydrogen peroxide, and water can be used.

  Then, using the patterned first mask layer 30 and cap film 17 as a mask, the barrier layer 16 and the electron supply layer 15 are selectively wet etched until the spacer layer 14 is exposed. For example, hydrochloric acid can be used as the etching solution.

  Then, using the electron supply layer 15 as a mask from the patterned first mask layer 30, the spacer layer 14, the channel layer 13, and the buffer layer 12 are selectively wet etched until the substrate 11 is exposed. As the etching solution, for example, a mixed solution of phosphoric acid, hydrogen peroxide, and water can be used. Thereafter, the first mask layer 30 is removed, and a mesa structure is formed in the element operation region as shown in FIG.

  Next, as illustrated in FIG. 11, the source electrode 19 and the drain electrode 20 are formed on the cap film 17 by using a photolithography technique. Specifically, first, a mask pattern that defines the source electrode 19 and the drain electrode 20 is formed on the cap film 17. Next, Ti (thickness 10 nm), Pt (thickness 30 nm), and Au (thickness 200 nm) are sequentially deposited on the mask pattern. Next, Ti / Pt / Au deposited on the mask pattern together with this mask pattern is removed (that is, by lift-off method), so that the source electrode 19 and the drain electrode 20 having a three-layer structure of Ti / Pt / Au are formed. , Formed on the cap film 17.

  Next, as shown in FIG. 12, cap layers 17 a and 17 b are formed together with the recess 21. Specifically, the second mask layer 31 having an opening for defining the recess 21 is formed on the cap film 17 and the source electrode 19 and the drain electrode 20 on the cap film 17 by using a photolithography technique or an electron beam exposure method. It is formed to be embedded. The portion of the cap film 17 exposed in the opening defining the recess 21 is selectively wet etched until the barrier layer 16 is exposed, and the cap layers 17 a and 17 b are formed together with the recess 21. Thereafter, the second mask layer 31 is removed. As the etching solution, for example, a mixed solution of citric acid, hydrogen peroxide, and water can be used.

  Next, as shown in FIG. 1, the gate electrode 19 is formed on the portion of the barrier layer 16 exposed to the recess 21 by using a photolithography technique or an electron beam exposure method. Specifically, first, a mask pattern for defining the gate electrode 19 is formed on a portion of the barrier layer 16 exposed at the recess 21. Next, Ti (thickness 10 nm), Pt (thickness 30 nm), and Au (thickness 500 nm) are sequentially deposited on the mask pattern. Next, Ti / Pt / Au deposited on the mask pattern together with this mask pattern is removed (that is, by lift-off method), so that the gate electrode 19 having a three-layer structure of Ti / Pt / Au is formed on the barrier layer 16. It is formed on the part exposed to the recess 21.

  According to the semiconductor device 10 of this embodiment described above, the amplification factor can be increased while ensuring the gate breakdown voltage.

Specifically, the semiconductor device 10 can reduce the distance d between the gate electrode 19 and the channel layer 13 while maintaining the gate breakdown voltage and maintaining the sheet electron concentration Ns of the channel layer 13. Therefore, the intrinsic mutual inductance g _m ^int and the external mutual inductance g _m ^ext are improved in the semiconductor device 10.

  In addition, the semiconductor device 10 has an improved amplification factor and improved noise characteristics.

  The semiconductor device 10 of the present embodiment described above can be applied to, for example, a monolithic microwave integrated circuit (MMIC).

  Next, semiconductor devices of Example 2 and Example 3 disclosed in this specification will be described below with reference to the drawings. For the points that are not particularly described in the second embodiment and the third embodiment, the description in detail regarding the first embodiment is applied as appropriate. Moreover, in FIGS. 13-16, the same code | symbol is attached | subjected to the same formation element as FIGS. 1-3.

  FIG. 13 is a cross-sectional view illustrating a second embodiment of the semiconductor device disclosed in this specification. FIG. 14 is a diagram showing the main part of the energy band of the semiconductor device of FIG.

The semiconductor device 40 of Example 2 is different from Example 1 in that i-GaP having a larger energy gap than i-InAl _0.4 P forming the barrier layer of Example 1 is used as a material for forming the barrier layer 16. Is different.

  As shown in FIG. 14, the energy gap Eg3 of i-GaP forming the barrier layer 16 is 2.78 eV in the case of direct transition. The difference ΔEc23 between the energy level Ec3 at the lower end of the conduction band of the barrier layer 16 and the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15 is 1.08 eV. Note that the energy gap Eg3 of i-GaP forming the barrier layer 16 is 2.24 eV in the case of indirect transition.

  Here, FIG. 14 shows energy levels at the upper end of the valence band and the lower end of the conduction band in a state before carriers such as electrons in each layer move to another layer, and the energy levels at the lower end of the conduction band. In order to show the difference in level, the energy levels of the bands of each layer are relatively arranged. The energy level of each layer shown in FIG. 3 corresponds to that in a state where each layer is spatially separated.

  The thickness of the buffer layer 12 is, for example, 300 nm. The thickness of the channel layer 13 is 15 nm, for example. The thickness of the spacer layer 14 is 3 nm, for example. The thickness of the electron supply layer 15 is, for example, 1 nm. The thickness of the barrier layer 16 is 2 nm, for example. The cap layers 17a and 17b have a thickness of 50 nm, for example.

For example, an n-type dopant is added to the electron supply layer 15 at a concentration of 1 × 10 ¹⁹ cm ⁻³ . An n-type dopant is added to the cap layers 17a and 17b at a concentration of 1 × 10 ¹⁹ cm ⁻³ , for example.

  In the semiconductor device 40 of Example 2, the energy level Ev3 at the upper end of the valence band of the barrier layer 16 is higher than the energy level Ev2 at the upper end of the valence band of the electron supply layer 15.

  Other structures of the semiconductor device 40 are the same as those of the first embodiment. The semiconductor device 40 can be formed in the same manner as in the first embodiment.

  Further, in the semiconductor device 40 of Example 2, i-AlP may be used as a material for forming the barrier layer 16.

  FIG. 15 is a cross-sectional view illustrating a third embodiment of the semiconductor device disclosed in this specification. FIG. 16 is a diagram showing the main part of the energy band of the semiconductor device of FIG.

  In the semiconductor device 50 according to the third embodiment, the material for forming the spacer layer 14, the electron supply layer 15, and the barrier layer 16 is different from that of the first embodiment.

In the semiconductor device 50, all of the formation materials of the spacer layer 14, the electron supply layer 15, and the barrier layer 16 are formed of compound semiconductor InAlAs, although the proportion of Al composition is different. Specifically, the spacer layer 14 is formed of i-InAl _0.48 As, the electron supply layer 15 is formed of n-InAl _0.6 As, and the barrier layer 16 is formed of i-InAl _0.8 As.

  InAlAs has an Al composition of 0.48 and is lattice-matched with InP, which is a material for forming the substrate 11, so that the Al composition of the spacer layer is 0.48.

  As shown in FIG. 16, the energy gap of InAlAs increases as the proportion of Al composition increases. Specifically, the energy gap Eg1 of the spacer layer 14 is 1.46 eV, the energy gap Eg2 of the electron supply layer 15 is 1.78 eV, and the energy gap Eg3 of the barrier layer 16 is 2.37 eV. .

  In FIG. 16, the channel layer 13, the spacer layer 14, the electron supply layer 15, and the barrier layer 16 are shown. Here, FIG. 16 shows the energy levels at the upper end of the valence band and the lower end of the conduction band in the state before carriers such as electrons in each layer move to another layer, and the energy levels at the lower end of the conduction band. In order to show the difference in level, the energy levels of the bands of each layer are relatively arranged. The energy level of each layer shown in FIG. 16 corresponds to that in a state where each layer is spatially separated. Ei in FIG. 16 indicates an intermediate level of the energy gap between the upper end of the valence band and the lower end of the conduction band.

  The difference ΔEc12 between the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15 and the energy level Ec1 at the lower end of the conduction band of the spacer layer 14 is 0.23 eV. The difference ΔEc23 between the energy level Ec3 at the lower end of the conduction band of the barrier layer 16 and the energy level Ec2 at the lower end of the conduction band of the electron supply layer 15 is 0.42 eV.

  Thus, in Example 3, the difference between the energy levels at the lower end of the conduction band between the electron supply layer 15 and the spacer layer 14 and the energy level at the lower end of the conduction band between the barrier layer 16 and the electron supply layer 15 are obtained. The difference is larger than that in the first embodiment.

  The thickness of the buffer layer 12 is, for example, 300 nm. The thickness of the channel layer 13 is 15 nm, for example. The thickness of the spacer layer 14 is 3 nm, for example. The thickness of the electron supply layer 15 is 2 nm, for example. The thickness of the barrier layer 16 is 2 nm, for example. The cap layers 17a and 17b have a thickness of 50 nm, for example.

For example, an n-type dopant is added to the electron supply layer 15 at a concentration of 5 × 10 ¹⁸ cm ⁻³ . An n-type dopant is added to the cap layers 17a and 17b at a concentration of 1 × 10 ¹⁹ cm ⁻³ , for example.

  Other structures of the semiconductor device 50 are the same as those of the first embodiment. The semiconductor device 50 can be formed in the same manner as in the first embodiment.

  Next, modified examples of the semiconductor devices of Examples 1 to 3 described above will be described below with reference to the drawings.

  FIG. 17 is a diagram illustrating a modified example of the semiconductor devices according to the first to third embodiments disclosed in this specification.

  FIG. 17 shows combinations of forming materials that can be substituted for the barrier layer, the electron supply layer, and the spacer layer in the first to third embodiments. If the combination shown in FIG. 17 is used, the energy level of the lower end of the conduction band of the spacer layer is lower than the energy level of the lower end of the conduction band of the electron supply layer, and the energy level of the lower end of the conduction band of the barrier layer is It becomes higher than the energy level at the lower end of the conduction band of the electron supply layer.

  FIG. 18 is a diagram illustrating another modified example of the semiconductor device according to the first to third embodiments disclosed in this specification.

  The semiconductor device 10 d of the modification shown in FIG. 18 includes an etching stop layer 22 between the gate electrode 19 and the barrier layer 16. The etching stop 22 is formed using InP, for example. The etching stop layer 22 has an etching stop function when the cap layers 17a and 17b are formed by etching. The etching stop layer 22 has a function of accurately adjusting the threshold voltage at the gate electrode 19. Furthermore, the etching stop layer 22 also functions as a surface protective layer.

  FIG. 19 is an energy band diagram in a thermal equilibrium state of the semiconductor device according to the fourth embodiment disclosed in this specification.

  FIG. 20 is a diagram showing the main part of the energy band of the semiconductor device of FIG. In FIG. 20, the spacer layer 14, the electron supply layer 15, and the barrier layer 16 are shown. Here, FIG. 20 shows the energy level of the lower end of the conduction band in a state before carriers such as electrons in each layer move to another layer. The energy level of each layer shown in FIG. 20 corresponds to that in a state where each layer is spatially separated. Ei in FIG. 20 indicates an intermediate level of the energy gap between the upper end of the valence band and the lower end of the conduction band. The above description regarding FIG. 20 also applies to FIGS. 21, 22 and 24 described later.

  In the semiconductor device 60 of the fourth embodiment, the energy band structure in the spacer layer 14, the electron supply layer 15, and the barrier layer 16 is different from that of the first embodiment.

  Specifically, in the semiconductor device 60, the energy level at the lower end of the conduction band of the spacer layer 14 and the energy level at the lower end of the conduction band of the electron supply layer 15 are continuously connected, and the barrier layer 16 The energy level at the lower end of the conduction band and the energy level at the lower end of the conduction band of the electron supply layer 15 are continuously connected.

  In the semiconductor device 60, the energy level at the lower end of the conduction band of the spacer layer 14 gradually decreases from the electron supply layer 15 side toward the channel layer 13 side.

  In the semiconductor device 60, the energy level at the lower end of the conduction band of the electron supply layer 15 gradually increases from the spacer layer 14 side toward the barrier layer 16 side.

  Furthermore, the energy level at the lower end of the conduction band of the barrier layer 16 gradually increases from the electron supply layer 15 side to the gate electrode 19 side.

  Specifically, as shown in FIG. 20, the energy levels at the lower ends of the conduction bands of the spacer layer 14, the electron supply layer 15, and the barrier layer 16 are linear from the channel layer 13 side to the gate electrode 19 side. Has increased.

  Further, as shown in FIG. 19, the energy level at the upper end of the valence band of the spacer layer 14 and the energy level at the upper end of the valence band of the electron supply layer 15 are continuously connected, and the barrier layer The energy level at the upper end of the 16 valence band and the energy level at the upper end of the valence band of the electron supply layer 15 are continuously connected.

  Next, materials for forming the spacer layer 14, the electron supply layer 15, and the barrier layer 16 in the semiconductor device 60 will be described below.

  The spacer layer 14, the electron supply layer 15, and the barrier layer 16 are all formed of compound semiconductor InAlAs, and the Al composition continuously increases from the channel layer 13 side to the gate electrode 19 side. . The energy level at the lower end of the conduction band of InAlAs increases as the Al composition increases. Similarly, the energy gap of InAlAs increases as the Al composition increases.

  As shown in FIG. 20, the Al composition in the spacer layer 14, the electron supply layer 15, and the barrier layer 16 increases linearly from the channel layer 13 side to the gate electrode 19 side. In the example shown in FIG. 20, the Al composition is 0.48 at the end of the spacer layer 14 on the channel layer 13 side, and the Al composition is 0.8 at the end of the barrier layer 16 on the gate electrode 19 side. ing.

  Further, the electron supply layer 15 is doped with an n-type dopant, that is, n-InAlAs (n layer in FIG. 20). The spacer layer 14 and the barrier layer 16 are not doped with dopant, i.e., i-InAlAs (i layer in FIG. 20).

  The semiconductor device 60 of Example 4 is the same as Example 1 described above except for the energy band structure in the spacer layer 14, the electron supply layer 15, and the barrier layer 16.

  The semiconductor device 60 can be formed in the same manner as in the first embodiment. In this case, when the spacer layer 14, the electron supply layer 15, and the barrier layer 16 are formed, each layer is deposited while the Al concentration is continuously increased.

  According to the semiconductor device 60 of the present embodiment described above, the same effects as those of the first embodiment can be obtained.

  Next, a modified example of the semiconductor device of Example 4 described above will be described below with reference to the drawings.

  FIG. 21 is a diagram illustrating the main part of the energy band of the first modification of the semiconductor device according to the fourth embodiment.

  The semiconductor device of Modification 1 shown in FIG. 21 is different from that of Embodiment 4 in the formation materials of the spacer layer 14, the electron supply layer 15, and the barrier layer 16. In the first modification, the spacer layer 14, the electron supply layer 15, and the barrier layer 16 are all formed of InAlP, and the Al composition continuously increases from the channel layer 13 side to the gate electrode 19 side. ing. The energy level at the lower end of the conduction band of InAlP increases as the Al composition increases. Similarly, the energy gap of InAlP increases as the Al composition increases.

  Specifically, the Al composition is 0.2 at the end of the spacer layer 14 on the channel layer 13 side, and at the end of the barrier layer 16 on the gate electrode 19 side. The Al composition is 0.4. The Al composition in the spacer layer 14, the electron supply layer 15, and the barrier layer 16 increases linearly from the channel layer 13 side to the gate electrode 19 side. Other structures of the first modification are the same as those of the fourth embodiment.

  FIG. 22 is a diagram illustrating the main part of the energy band of the second modification of the semiconductor device according to the fourth embodiment.

  The semiconductor device of Modification 2 shown in FIG. 22 is different from that of Embodiment 4 in the formation materials of the spacer layer 14, the electron supply layer 15, and the barrier layer 16. In Modification 2, the spacer layer 14, the electron supply layer 15, and the barrier layer 16 are all formed of InGaP, and the Ga composition continuously increases from the channel layer 13 side to the gate electrode 19 side. ing. The energy level at the lower end of the conduction band of InGaP increases as the Ga composition increases. Similarly, the energy gap of InGaP increases with increasing Ga composition.

  Specifically, the Ga composition is 0.2 at the end of the spacer layer 14 on the channel layer 13 side, and at the end of the barrier layer 16 on the gate electrode 19 side. The Ga composition is 0.4. The Ga composition in the spacer layer 14, the electron supply layer 15, and the barrier layer 16 increases linearly from the channel layer 13 side to the gate electrode 19 side. Other structures of the second modification are the same as those of the fourth embodiment.

  FIG. 23 is an energy band diagram in a thermal equilibrium state of the semiconductor device according to the fifth embodiment disclosed in this specification. FIG. 24 is a diagram showing the main part of the energy band of the semiconductor device of FIG.

  The semiconductor device 70 of Example 5 is different from Example 4 described above in that the energy level at the lower end of the conduction band of the electron supply layer 15 is constant.

  As shown in FIG. 24, in the semiconductor device 70, the energy level at the lower end of the conduction band of the spacer layer 14 gradually increases linearly from the channel layer 13 side toward the electron supply layer 15 side. In the electron supply layer 15, the energy level at the lower end of the conduction band is constant. The energy level at the lower end of the conduction band of the barrier layer 16 gradually increases linearly from the electron supply layer 15 side to the gate electrode 19 side.

  In the semiconductor device 70, the spacer layer 14, the electron supply layer 15, and the barrier layer 16 are all formed of InAlAs, and are the same as those in the fourth embodiment. However, it differs from Example 4 in that the Al composition in the electron supply layer 15 is constant.

  As shown in FIG. 24, the Al composition at the end of the spacer layer 14 on the channel layer 13 side is 0.48, and the Al composition in the spacer layer 14 is from the channel layer 13 side toward the electron supply layer 15 side. Ascending linearly. In the electron supply layer 15, the Al composition is constant. The Al composition in the barrier layer 16 gradually increases linearly from the electron supply layer 15 side to the gate electrode 19 side, and the Al composition is 0.8 at the end of the barrier layer 16 on the gate electrode 19 side.

  The other structure of the semiconductor device 70 is the same as that of the fourth embodiment described above.

  The semiconductor device 70 can be formed in the same manner as in Example 4 described above. In this case, when the spacer layer 14 and the barrier layer 16 are formed, each layer is deposited while the Al concentration is continuously increased. When the electron supply layer 15 is formed, the Al concentration is constant and the layers are deposited. Is done.

  According to the semiconductor device 70 of the present embodiment described above, the same effects as those of the first embodiment can be obtained.

  In the present invention, the semiconductor devices of the above-described embodiments can be appropriately changed without departing from the spirit of the present invention. In addition, the requirements in the above-described one embodiment or modification can be appropriately interchanged between the embodiment and the modification.

  For example, in the above-described embodiments, the description has been given using the electron supply layer which is an n-type semiconductor in which majority carriers are electrons. However, the electron supply layer is a p-type semiconductor in which majority carriers are holes. Also good. Specifically, in Example 1 or Example 3 or Example 4 or Example 5, the energy level at the top of the valence band of the spacer layer is higher than the energy level at the top of the valence band of the electron supply layer. It is preferable that the energy level at the upper end of the valence band of the barrier layer is lower than the energy level at the upper end of the valence band of the electron supply layer in order to improve the gate breakdown voltage and the amplification factor.

  In each of the above-described embodiments, the barrier layer is an intrinsic semiconductor to which no dopant is added, but the barrier layer may be a semiconductor to which an n-type dopant is added.

  All examples and conditional words mentioned herein are intended for educational purposes to help the reader deepen and understand the inventions and concepts contributed by the inventor. All examples and conditional words mentioned herein are to be construed without limitation to such specifically stated examples and conditions. Also, such exemplary mechanisms in the specification are not related to showing the superiority and inferiority of the present invention. While embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions or modifications can be made without departing from the spirit and scope of the invention.

  Regarding the above-described embodiments, the following additional notes are disclosed.

(Appendix 1)
A channel layer;
A spacer layer disposed on the channel layer;
An electron supply layer disposed on the spacer layer;
A barrier layer disposed on the electron supply layer;
A gate electrode disposed on the barrier layer;
With
The energy level of the lower end of the conduction band of the spacer layer is lower than the energy level of the lower end of the conduction band of the electron supply layer,
The semiconductor device, wherein the energy level at the lower end of the conduction band of the barrier layer is higher than the energy level at the lower end of the conduction band of the electron supply layer.

(Appendix 2)
The semiconductor device according to appendix 1, wherein a thickness t1 of the spacer layer, a thickness t2 of the electron supply layer, and a thickness t3 of the barrier layer satisfy a relationship of t1 ≦ t2 + t3 ≦ 2 × t1.

(Appendix 3)
The energy level at the lower end of the conduction band of the spacer layer and the energy level at the lower end of the conduction band of the electron supply layer are connected discontinuously,
The semiconductor device according to appendix 1 or 2, wherein the energy level at the lower end of the conduction band of the barrier layer and the energy level at the lower end of the conduction band of the electron supply layer are connected discontinuously.

(Appendix 4)
The semiconductor device according to attachment 3, wherein the difference between the energy level at the lower end of the conduction band of the spacer layer and the energy level at the lower end of the conduction band of the electron supply layer is larger than the thermal energy at room temperature.

(Appendix 5)
The barrier layer is formed of a plurality of layers,
The semiconductor device according to appendix 3 or 4, wherein the energy level at the lower end of the conduction band of each layer forming the barrier layer increases stepwise from the electron supply layer side toward the gate electrode side.

(Appendix 6)
The spacer layer is formed of a plurality of layers,
6. The semiconductor according to any one of appendices 3 to 5, wherein an energy level at a lower end of a conduction band of each layer forming the spacer layer increases stepwise from the channel layer side toward the electron supply layer side. apparatus.

(Appendix 7)
The energy level at the top of the valence band of the spacer layer and the energy level at the top of the valence band of the electron supply layer are connected discontinuously,
The energy level at the upper end of the valence band of the barrier layer and the energy level at the upper end of the valence band of the electron supply layer are connected to each other in a discontinuous manner. Semiconductor device.

(Appendix 8)
The energy level at the lower end of the conduction band of the spacer layer and the energy level at the lower end of the conduction band of the electron supply layer are continuously connected,
The semiconductor device according to appendix 1 or 2, wherein the energy level at the lower end of the conduction band of the barrier layer and the energy level at the lower end of the conduction band of the electron supply layer are continuously connected.

(Appendix 9)
The energy level at the lower end of the conduction band of the spacer layer gradually decreases from the electron supply layer side toward the channel layer side,
The semiconductor device according to appendix 8, wherein the energy level at the lower end of the conduction band of the barrier layer is gradually increased from the electron supply layer side toward the gate electrode side.

(Appendix 10)
The semiconductor device according to appendix 8 or 9, wherein an energy level at a lower end of a conduction band of the electron supply layer is gradually increased from the spacer layer side toward the barrier layer side.

(Appendix 11)
The semiconductor device according to appendix 8 or 9, wherein the energy level at the lower end of the conduction band of the electron supply layer is constant.

(Appendix 12)
The energy level at the upper end of the valence band of the spacer layer and the energy level at the upper end of the valence band of the electron supply layer are continuously connected,
The energy level at the upper end of the valence band of the barrier layer and the energy level at the upper end of the valence band of the electron supply layer are connected continuously, according to any one of appendices 8 to 11. Semiconductor device.

(Appendix 13)
The energy level at the upper end of the valence band of the spacer layer is higher than the energy level at the upper end of the valence band of the electron supply layer,
The semiconductor device according to any one of appendices 1 to 12, wherein an energy level at an upper end of the valence band of the barrier layer is lower than an energy level at the upper end of the valence band of the electron supply layer.

(Appendix 14)
The energy gap between the conduction band and the valence band of the electron supply layer is larger than the energy gap between the conduction band and the valence band of the spacer layer,
The energy gap between the conduction band and the valence band of the electron supply layer is smaller than the energy gap between the conduction band and the valence band of the barrier layer, according to any one of appendices 1 to 13. Semiconductor device.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Substrate 12 Buffer layer 13 Channel layer 14, 14a, 14b Spacer layer 15 Electron supply layer 16, 16a, 16b Barrier layer 17a, 17b Cap layer 18 Gate electrode 19 Source electrode 20 Drain electrode 21 Recess 22 Etching stop layer 30 First mask layer 31 Second mask layer Ec1 Energy level at the lower end of the conduction band of the spacer layer Ec2 Energy level at the lower end of the conduction band of the electron supply layer Ec3 Energy level at the lower end of the conduction band of the barrier layer Ev1 of the spacer layer Energy level at the top of the valence band Ev2 Energy level at the top of the valence band of the electron supply layer Ev3 Energy level at the top of the valence band of the barrier layer

Claims (5)

A channel layer;
A spacer layer disposed on the channel layer;
An electron supply layer disposed on the spacer layer;
A barrier layer disposed on the electron supply layer;
A gate electrode disposed on the barrier layer;
With
The energy level of the lower end of the conduction band of the spacer layer is lower than the energy level of the lower end of the conduction band of the electron supply layer,
The semiconductor device, wherein the energy level at the lower end of the conduction band of the barrier layer is higher than the energy level at the lower end of the conduction band of the electron supply layer.   2. The semiconductor device according to claim 1, wherein a thickness t <b> 1 of the spacer layer, a thickness t <b> 2 of the electron supply layer, and a thickness t <b> 3 of the barrier layer satisfy a relationship of t <b> 1 ≦ t <b> 2 + t <b> 3 ≦ 2 × t <b> 1. The energy level at the lower end of the conduction band of the spacer layer and the energy level at the lower end of the conduction band of the electron supply layer are connected discontinuously,
The semiconductor device according to claim 1, wherein the energy level at the lower end of the conduction band of the barrier layer and the energy level at the lower end of the conduction band of the electron supply layer are connected discontinuously. The energy level at the lower end of the conduction band of the spacer layer and the energy level at the lower end of the conduction band of the electron supply layer are continuously connected,
The semiconductor device according to claim 1, wherein the energy level at the lower end of the conduction band of the barrier layer and the energy level at the lower end of the conduction band of the electron supply layer are continuously connected. The energy level at the lower end of the conduction band of the spacer layer gradually decreases from the electron supply layer side toward the channel layer side,
The semiconductor device according to claim 4, wherein an energy level at a lower end of a conduction band of the barrier layer is gradually increased from the electron supply layer side toward the gate electrode side.

Images