JP2011198999A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
JP2011198999A
JP2011198999A JP2010064044A JP2010064044A JP2011198999A JP 2011198999 A JP2011198999 A JP 2011198999A JP 2010064044 A JP2010064044 A JP 2010064044A JP 2010064044 A JP2010064044 A JP 2010064044A JP 2011198999 A JP2011198999 A JP 2011198999A
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Prior art keywords
wiring board
metal shield
semiconductor device
semiconductor element
resin
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Izumi Kobayashi
泉 小林
Ryoji Kotaki
良次 小瀧
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

PROBLEM TO BE SOLVED: To reliably fix a metal shield to a wiring board.SOLUTION: In a semiconductor device 1, a semiconductor element 3 is mounted on the wiring board 2, and a latching member 5 is bonded to a ground terminal 13 provided to an outer periphery of the wiring board 2. The semiconductor element 3 is sealed by resin 6, and a part of the latching member 5 is exposed on a side face 6C of the resin 6. An end face 5D of the latching member 5 is flush with a side face 2C of the wiring board 2 and the side face 6C of the resin 6. The metal shield 7 covering the resin 6 is formed with a claw 7C on a side 7B, and it is attached to the wiring board 2 via the latching member 5 by engaging the claw 7C with the latching member 5.

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

半導体装置には、配線基板に半導体素子などを実装した後に樹脂で封止し、さらに、樹脂を金属シールドで覆ったものがある。金属シールドは、配線基板に設けられた接地端子に電気的に接続され、半導体素子などから発生したノイズが外部に放射されることを防止したり、外部で生じたノイズが内部に浸入することを防止したりする機能を有する。   In some semiconductor devices, a semiconductor element or the like is mounted on a wiring board and then sealed with a resin, and the resin is covered with a metal shield. The metal shield is electrically connected to the ground terminal provided on the wiring board to prevent the noise generated from the semiconductor element from being radiated to the outside, and to prevent the noise generated from entering the inside. It has a function to prevent.

金属シールドを有する半導体装置の一例の断面図として、図２８に、無線通信モジュールの断面図を示す。無線通信モジュール２０１は、配線基板２０２を有し、配線基板２０２の上面には半導体素子２０３と、コンデンサやコイルなどの受動部品２０４とが搭載されている。さらに、配線基板２０２の外周部には、金属ポスト２０５が取り付けられている。半導体素子２０３及び受動部品２０４は、エポキシ樹脂２０６で封止されている。さらに、無線通信モジュール２０１には、エポキシ樹脂２０６の外表面を覆うように、金属シールド２０７が取り付けられている。
金属シールド２０７は、エポキシ樹脂２０６の表面から露出した金属ポスト２０５にハンダ２０５Ａを介して固定されている。また、金属シールド２０７は、エポキシ樹脂２０６の上面を覆う天井部２０７Ａと、エポキシ樹脂２０６の側面を覆う側部２０７Ｂとを有する。
なお、配線基板２０２の下面には、配線基板２０２内のビア（不図示）を介して半導体素子２０３、受動部品２０４に接続される配線パッド２０２Ａが形成されている。 As a cross-sectional view of an example of a semiconductor device having a metal shield, FIG. 28 shows a cross-sectional view of a wireless communication module. The wireless communication module 201 includes a wiring board 202, and a semiconductor element 203 and a passive component 204 such as a capacitor and a coil are mounted on the upper surface of the wiring board 202. Further, a metal post 205 is attached to the outer peripheral portion of the wiring board 202. The semiconductor element 203 and the passive component 204 are sealed with an epoxy resin 206. Furthermore, a metal shield 207 is attached to the wireless communication module 201 so as to cover the outer surface of the epoxy resin 206.
The metal shield 207 is fixed to the metal post 205 exposed from the surface of the epoxy resin 206 via solder 205A. In addition, the metal shield 207 has a ceiling portion 207 </ b> A that covers the upper surface of the epoxy resin 206 and a side portion 207 </ b> B that covers the side surface of the epoxy resin 206.
Note that a wiring pad 202A connected to the semiconductor element 203 and the passive component 204 through a via (not shown) in the wiring board 202 is formed on the lower surface of the wiring board 202.

配線基板の金属シールドの接合構造の他の例として、図２９に半導体装置２０８の断面図を示す。半導体装置２０８は、エポキシ樹脂２０６を覆う金属シールド２０９を有している。金属シールド２０９の側部２０９Ｂは、配線基板２０２の半導体素子２０３が搭載されない下面２０２Ｂ側に折り返しされた曲折部２０９Ｃを有する。曲折部２０９Ｃを配線基板２０２の下面に係合させることで、金属シールド２０９が配線基板２０２に固定される。   FIG. 29 shows a cross-sectional view of a semiconductor device 208 as another example of the bonding structure of the metal shield of the wiring board. The semiconductor device 208 has a metal shield 209 that covers the epoxy resin 206. The side portion 209B of the metal shield 209 has a bent portion 209C that is folded back to the lower surface 202B side where the semiconductor element 203 of the wiring board 202 is not mounted. The metal shield 209 is fixed to the wiring board 202 by engaging the bent portion 209 </ b> C with the lower surface of the wiring board 202.

さらに、このような金属シールドは、半導体素子や受動部品を樹脂封止しない半導体装置においても設けられることがある。このような半導体装置の一例を図３０に示す。半導体装置２１０は、空間を介して半導体素子２０３や受動部品２０４を覆う金属シールド２１１を有し、金属シールド２１１の側部２１１Ａの端を外側に屈曲させた屈曲部２１２を配線基板２０２上に載せ、屈曲部２１２をハンダ２１３で接合している。   Furthermore, such a metal shield may be provided even in a semiconductor device that does not encapsulate semiconductor elements and passive components. An example of such a semiconductor device is shown in FIG. The semiconductor device 210 has a metal shield 211 that covers the semiconductor element 203 and the passive component 204 through a space, and a bent portion 212 that is bent outward from the side portion 211A of the metal shield 211 is placed on the wiring board 202. The bent portion 212 is joined with the solder 213.

国際公開ＷＯ２００８／０９３４１４号公報International Publication WO2008 / 093414 特開２００８−１４７５７２号公報JP 2008-147572 A 特開２００６−１３３７５号公報JP 2006-13375 A 特開２００１−２４３１２号公報Japanese Patent Laid-Open No. 2001-24312 特開２００４−１７２１７６号公報JP 2004-172176 A 特開２００８−２８８６１０号公報JP 2008-288610 A 特開２００４−２６０１０３号公報JP 2004-260103 A

しかしながら、図２８に示すような従来の半導体装置では、金属シールド２０７と金属ポスト２０５の接合面積が小さい。このため、電極パッド２０２Ａのハンダ付け工程で金属シールド２０７が熱変形すると、条件によってはハンダ２０５Ａの接着力に抗して金属ポスト２０５から金属シールド２０７が浮くおそれがあった。これは、金属シールド２０７と金属ポスト２０５の接合面積が小さいからである。これに対し、金属ポスト２０５の数を増やせば接合面積を増大できるが、半導体装置の外形サイズが大きくなってしまう。   However, in the conventional semiconductor device as shown in FIG. 28, the bonding area between the metal shield 207 and the metal post 205 is small. For this reason, if the metal shield 207 is thermally deformed in the soldering process of the electrode pad 202A, the metal shield 207 may float from the metal post 205 against the adhesive force of the solder 205A depending on conditions. This is because the bonding area between the metal shield 207 and the metal post 205 is small. In contrast, if the number of metal posts 205 is increased, the bonding area can be increased, but the outer size of the semiconductor device is increased.

また、図２９に示すように金属シールド２０９の側部２０９Ｂの曲折部２０９Ｃを配線基板２０２の下面に係合させる構造では、金属ポストを用いて接合する場合に比べて、金属シールド２０９と配線基板２０２の接触面積を大きくすることができる。しかしながら、配線基板２０２の下面から金属シールド２０９が突出するので、半導体装置２０８を他の装置等に搭載するときの取り付け高さを低くできなかった。   Also, as shown in FIG. 29, in the structure in which the bent portion 209C of the side portion 209B of the metal shield 209 is engaged with the lower surface of the wiring board 202, the metal shield 209 and the wiring board are compared with the case where the metal post is used for joining. The contact area 202 can be increased. However, since the metal shield 209 protrudes from the lower surface of the wiring board 202, the mounting height when the semiconductor device 208 is mounted on another device or the like cannot be reduced.

さらに、図３０に示すように樹脂封止しない半導体装置２１０では、金属シールド２１１の屈曲部２１２の面積を大きくして金属シールド２１１と配線基板２０２の接合面積の増大が図れる。しかしながら、半導体装置の外形サイズは、金属シールド２１１の接合部分を広げた分だけ大型化してしまう。   Furthermore, as shown in FIG. 30, in the semiconductor device 210 that is not resin-sealed, the area of the bent portion 212 of the metal shield 211 can be increased to increase the bonding area between the metal shield 211 and the wiring board 202. However, the outer size of the semiconductor device is increased by an amount corresponding to the expansion of the joint portion of the metal shield 211.

本発明は、このような事情を鑑みてなされたものであり、配線基板に対して金属シールドを簡単に、かつ確実に固定できるようにすることを目的とする。   The present invention has been made in view of such circumstances, and an object thereof is to enable a metal shield to be easily and reliably fixed to a wiring board.

本願の一観点によれば、配線基板と、前記配線基板の一方の面の上に実装された半導体素子と、前記半導体素子を覆う金属シールドと、前記配線基板の前記一方の面に形成された接地端子と、前記接地端子に電気的に接続されると共に、前記一方の面の上で前記金属シールドに係合する掛け止め部材と、を含む半導体装置が提供される。   According to one aspect of the present application, a wiring board, a semiconductor element mounted on one surface of the wiring board, a metal shield covering the semiconductor element, and the one surface of the wiring board are formed. There is provided a semiconductor device including a ground terminal and a latch member electrically connected to the ground terminal and engaged with the metal shield on the one surface.

また、本発明の別の観点によれば、配線基板を複数隣接して形成する領域を有する集合基板に半導体素子を実装する工程と、前記集合基板上で隣り合う前記配線基板の領域の境界線上に、凹部又は空隙を有する蓋部材を固定する工程と、前記境界線に沿って前記集合基板及び前記蓋部材を切断し、前記集合基板から前記配線基板を形成すると同時に、前記蓋部材から前記半導体素子を覆う金属シールドを係合させる凹形状を有する掛け止め部材を形成する工程と、前記掛け止め部材に前記金属シールドを係合させる工程と、を含む半導体装置の製造方法が提供される。   According to another aspect of the present invention, a step of mounting a semiconductor element on a collective substrate having a region in which a plurality of wiring substrates are formed adjacent to each other, and a boundary line between adjacent regions of the wiring substrate on the collective substrate A step of fixing a cover member having a recess or a gap, and cutting the collective substrate and the cover member along the boundary line to form the wiring substrate from the collective substrate, and at the same time from the cover member to the semiconductor A method of manufacturing a semiconductor device is provided, which includes a step of forming a latching member having a concave shape for engaging a metal shield that covers an element, and a step of engaging the metal shield with the latching member.

この半導体装置及びその製造方法によれば、掛け止め部材に金属シールドを係合させて配線基板に金属シールドを取り付けるようにしたので、金属シールドと配線基板の間に十分な接触面積を確保できる。これにより、金属シールドの変形や、配線基板からの脱離が防止される。   According to this semiconductor device and the manufacturing method thereof, since the metal shield is attached to the wiring board by engaging the metal shield with the latch member, a sufficient contact area can be secured between the metal shield and the wiring board. This prevents deformation of the metal shield and detachment from the wiring board.

図１は、本発明の第１の実施の形態に係る半導体装置の構成を示す断面図である。FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to the first embodiment of the present invention. 図２は、本発明の第１の実施の形態に係る半導体装置の一部を示す斜視図である。FIG. 2 is a perspective view showing a part of the semiconductor device according to the first embodiment of the present invention. 図３は、本発明の第１の実施の形態に係る金属シールドの斜視図である。FIG. 3 is a perspective view of the metal shield according to the first embodiment of the present invention. 図４は、本発明の第１の実施の形態に係る半導体装置の製造工程を説明する断面図である。FIG. 4 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention. 図５は、本発明の第１の実施の形態に係る半導体装置の製造工程を説明する平面図である。FIG. 5 is a plan view illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 図６（ａ）は、本発明の第１の実施の形態に係る半導体装置の製造に使用する蓋部材の第１の例を示す斜視図、図６（ｂ）は、図６（ａ）に示す蓋部材を切断したときに形成される掛け止め部材を示す斜視図である。6A is a perspective view showing a first example of a lid member used for manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6B is a perspective view of FIG. It is a perspective view which shows the latching member formed when the shown cover member is cut | disconnected. 図７は、本発明の第１の実施の形態に係る半導体装置の製造工程を説明する断面図である。FIG. 7 is a cross-sectional view illustrating a manufacturing process of the semiconductor device according to the first embodiment of the present invention. 図８は、本発明の第１の実施の形態に係る半導体装置の製造工程における切断工程を説明する断面図である。FIG. 8 is a cross-sectional view illustrating a cutting process in the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 図９は、本発明の第１の実施の形態に係る半導体装置の製造工程における切断工程を説明する平面図である。FIG. 9 is a plan view illustrating a cutting process in the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 図１０は、本発明の第１の実施の形態に係る半導体装置の製造工程における金属シールドの取り付け工程を説明する図である。FIG. 10 is a diagram for explaining a metal shield attaching process in the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 図１１（ａ）は、本発明の第１の実施の形態に係る半導体装置の製造に使用する蓋部材の第２の例を示す斜視図、図１１（ｂ）は、図１１（ａ）に示す蓋部材を切断したときに形成される掛け止め部材を示す斜視図である。FIG. 11A is a perspective view showing a second example of a lid member used for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. 11B is FIG. 11A. It is a perspective view which shows the latching member formed when the shown cover member is cut | disconnected. 図１２（ａ）は、本発明の第１の実施の形態に係る半導体装置の製造に使用する蓋部材の第３の例を示す斜視図、図１１（ｂ）は、図１１（ａ）に示す蓋部材を切断したときに形成される掛け止め部材を示す斜視図である。FIG. 12A is a perspective view showing a third example of the lid member used for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. 11B is FIG. 11A. It is a perspective view which shows the latching member formed when the shown cover member is cut | disconnected. 図１３（ａ）は、本発明の第１の実施の形態に係る半導体装置の製造に使用する蓋部材の第４の例を示す斜視図、図１１（ｂ）は、図１１（ａ）に示す蓋部材を切断したときに形成される掛け止め部材を示す斜視図である。FIG. 13A is a perspective view showing a fourth example of the lid member used for manufacturing the semiconductor device according to the first embodiment of the present invention, and FIG. 11B is FIG. 11A. It is a perspective view which shows the latching member formed when the shown cover member is cut | disconnected. 図１４は、本発明の第２の実施の形態に係る半導体装置の構成を示す断面図である。FIG. 14 is a cross-sectional view showing a configuration of a semiconductor device according to the second embodiment of the present invention. 図１５は、本発明の第２の実施の形態に係る半導体装置の製造工程を説明する断面図である。FIG. 15 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to the second embodiment of the present invention. 図１６は、本発明の第２の実施の形態に係る半導体装置の製造工程を説明する平面図である。FIG. 16 is a plan view for explaining the manufacturing process for the semiconductor device according to the second embodiment of the present invention. 図１７は、本発明の第２の実施の形態に係る半導体装置の製造工程を説明する断面図である。FIG. 17 is a cross-sectional view illustrating a manufacturing process of a semiconductor device according to the second embodiment of the present invention. 図１８は、本発明の第２の実施の形態に係る半導体装置の製造工程を説明する平面図である。FIG. 18 is a plan view for explaining a manufacturing process of the semiconductor device according to the second embodiment of the present invention. 図１９は、本発明の第２の実施の形態に係る半導体装置の製造工程における金属シールドの取り付け工程を説明する図である。FIG. 19 is a diagram illustrating a metal shield attaching process in the manufacturing process of the semiconductor device according to the second embodiment of the present invention. 図２０は、本発明の第２の実施の形態に係る半導体装置の変形例の製造工程における金属シールドの取り付け工程を説明する図である。FIG. 20 is a diagram for explaining a metal shield attaching process in the manufacturing process of the modification of the semiconductor device according to the second embodiment of the present invention. 図２１は、本発明の第３の実施の形態に係る半導体装置の斜視分解図である。FIG. 21 is a perspective exploded view of a semiconductor device according to the third embodiment of the present invention. 図２２は、本発明の第３の実施の形態に係る半導体装置の掛け止め部材の斜視図である。FIG. 22 is a perspective view of the latch member of the semiconductor device according to the third embodiment of the present invention. 図２３は、本発明の第３の実施の形態に係る半導体装置の製造工程を説明する平面図である。FIG. 23 is a plan view for explaining the manufacturing process for the semiconductor device according to the third embodiment of the present invention. 図２４は、本発明の第４の実施の形態に係る半導体装置の分解斜視図である。FIG. 24 is an exploded perspective view of a semiconductor device according to the fourth embodiment of the present invention. 図２５は、本発明の第４の実施の形態に係る半導体装置の製造工程を説明する平面図である。FIG. 25 is a plan view illustrating the manufacturing process for the semiconductor device according to the fourth embodiment of the present invention. 図２６は、本発明の第５の実施の形態に係る半導体装置の分解斜視図である。FIG. 26 is an exploded perspective view of a semiconductor device according to the fifth embodiment of the present invention. 図２７は、本発明の第５の実施の形態に係る半導体装置の製造工程を説明する平面図である。FIG. 27 is a plan view for explaining the manufacturing process for the semiconductor device according to the fifth embodiment of the present invention. 図２８は、従来の半導体装置を示す断面図である。FIG. 28 is a cross-sectional view showing a conventional semiconductor device. 図２９は、別の従来の半導体装置を示す断面図である。FIG. 29 is a cross-sectional view showing another conventional semiconductor device. 図３０は、さらに別の半導体装置を示す断面図である。FIG. 30 is a cross-sectional view showing still another semiconductor device.

以下に、図面を参照して本発明の好ましい実施の形態を説明する。図面において、同様の構成要素には同じ参照番号が付されている。
（第１の実施の形態）
図１に、本実施の形態に係る半導体装置の断面図を示す。半導体装置１は、配線基板２を有し、配線基板２の一方の面２Ａ上には、電子部品として、半導体素子３と、受動部品４とが実装されている。さらに、配線基板２の一方の面２Ａ上には、導電性を有する掛け止め部材５が取り付けられている。半導体素子３と受動部品４は樹脂６に封止され、さらに樹脂６は金属シールド７で覆われている。また、配線基板２の他方の面２Ｂには、外部装置（不図示）に電気的に接続するための外部接続端子（ランド）８が格子状に形成されている。 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. In the drawings, similar components are given the same reference numerals.
(First embodiment)
FIG. 1 shows a cross-sectional view of the semiconductor device according to the present embodiment. The semiconductor device 1 has a wiring board 2, and a semiconductor element 3 and a passive part 4 are mounted as electronic parts on one surface 2 </ b> A of the wiring board 2. Furthermore, a conductive latch member 5 is attached on one surface 2A of the wiring board 2. The semiconductor element 3 and the passive component 4 are sealed with a resin 6, and the resin 6 is further covered with a metal shield 7. Further, on the other surface 2B of the wiring board 2, external connection terminals (lands) 8 for electrical connection to an external device (not shown) are formed in a lattice shape.

半導体素子３は、信号の入出力などに用いられる電極が配線基板２に向け、フェイスダウンで金やハンダを用いた金属材料９を介して配線基板２に実装されている。半導体素子３と配線基板２の間に生じた隙間は、熱硬化接着剤１０で埋められている。熱硬化接着剤１０としては、例えば、エポキシ樹脂を用いても良い。
受動部品４としては、例えば、コンデンサや抵抗器、コイルなどがあげられ、配線基板２上に形成された導電性パターン１１の上にハンダ１２Ａを用いて接合されている。 The semiconductor element 3 is mounted on the wiring board 2 via a metal material 9 using gold or solder face down with electrodes used for signal input and output directed to the wiring board 2. A gap generated between the semiconductor element 3 and the wiring board 2 is filled with a thermosetting adhesive 10. For example, an epoxy resin may be used as the thermosetting adhesive 10.
Examples of the passive component 4 include a capacitor, a resistor, and a coil, which are joined to the conductive pattern 11 formed on the wiring board 2 by using solder 12A.

樹脂６には、例えば、エポキシ樹脂が用いられる。図２（ａ）の斜視図に示すように、樹脂６の側面６Ｃは、配線基板２の側面２Ｃと面一になっている。さらに、樹脂６の側面６Ｃには、掛け止め部材５の一部が露出している。そして、樹脂６の上面６Ａの全体と、側面６Ｃの少なくとも一部を覆うように、金属シールド７が配線基板２の上方に配置されている。   For example, an epoxy resin is used as the resin 6. As shown in the perspective view of FIG. 2A, the side surface 6 </ b> C of the resin 6 is flush with the side surface 2 </ b> C of the wiring board 2. Furthermore, a part of the latch member 5 is exposed on the side surface 6 </ b> C of the resin 6. A metal shield 7 is disposed above the wiring board 2 so as to cover the entire upper surface 6A of the resin 6 and at least a part of the side surface 6C.

掛け止め部材５は、四角形の配線基板２の外周部、より具体的には、配線基板２の４つの辺のそれぞれの略中央に１つずつ配置されており、配線基板２上の接地端子１３にハンダ１２Ｂを用いて接合されている。このような掛け止め部材５は、例えば、銅やステンレス、洋白から製造されている。   The latch members 5 are arranged one by one at the outer peripheral portion of the rectangular wiring board 2, more specifically, at approximately the center of each of the four sides of the wiring board 2, and the ground terminal 13 on the wiring board 2. Are joined using solder 12B. Such a latching member 5 is manufactured from, for example, copper, stainless steel, or white.

次に、掛け止め部材５について、図２（ｂ）を参照して説明する。なお、図２（ｂ）は、掛け止め部材５を配線基板の底面側から見た斜視図である。
掛け止め部材５は、配線基板２の一方の面２Ａに対して略垂直に延びる背面壁部５Ａを有し、背面壁部５Ａの両端のそれぞれには側壁部５Ｂが前方に屈曲して形成されている。さらに、背面壁部５Ａ及び一対の側壁部５Ｂのそれぞれの上端からは上壁部５Ｃが庇状に形成されている。これにより、掛け止め部材５は、底側と前方の一方のそれぞれが開放された凹形状を有している。掛け止め部材５の背面壁部５Ａ及び側壁部５Ｂのそれぞれの下端は、接地端子１３に電気的に接続される。また、背面壁部５Ａの内面は、配線基板２の外側に向けて配置される。これにより、上壁部５Ｃは、背面壁部５Ａ上端から配線基板２の外側に向けて突出し、かつ配線基板２と平行に配置される。 Next, the latch member 5 will be described with reference to FIG. FIG. 2B is a perspective view of the latch member 5 as seen from the bottom side of the wiring board.
The latching member 5 has a back wall portion 5A extending substantially perpendicular to one surface 2A of the wiring board 2, and side wall portions 5B are formed by bending forward at both ends of the back wall portion 5A. ing. Further, an upper wall portion 5C is formed in a bowl shape from the upper ends of the back wall portion 5A and the pair of side wall portions 5B. Thereby, the latching member 5 has a concave shape in which one of the bottom side and the front side is opened. The lower ends of the rear wall portion 5A and the side wall portion 5B of the latch member 5 are electrically connected to the ground terminal 13. Further, the inner surface of the back wall portion 5 </ b> A is disposed toward the outside of the wiring board 2. Thus, the upper wall portion 5C protrudes from the upper end of the rear wall portion 5A toward the outside of the wiring board 2 and is disposed in parallel with the wiring board 2.

ここで、掛け止め部材５の上壁部５Ｃと配線基板２の間には間隙が形成される。さらに、上壁部５Ｃと側壁部５Ｂにより形成される開口の端面５Ｄは、樹脂６の側面６Ｃ及び配線基板２の側面２Ｃと面一になっている。そして、掛け止め部材５は、端面５Ｄを除いて外側から樹脂６で覆われているが、背面壁部５Ａ、側壁部５Ｂ及び上壁部５Ｃで区画される内部の空間２５には、樹脂６は注入されていない。   Here, a gap is formed between the upper wall portion 5 </ b> C of the latch member 5 and the wiring board 2. Furthermore, the end surface 5D of the opening formed by the upper wall portion 5C and the side wall portion 5B is flush with the side surface 6C of the resin 6 and the side surface 2C of the wiring board 2. The latch member 5 is covered with the resin 6 from the outside except for the end face 5D, but the internal space 25 defined by the back wall portion 5A, the side wall portion 5B, and the upper wall portion 5C has a resin 6 Is not injected.

図１の側断面及び図３の斜視図に示すように、金属シールド７は、樹脂６の上面６Ａと側面６Ｃのそれぞれを覆うキャップ形状を有する。より具体的には、金属シールド７は、四角形の天井部７Ａと、天井部７Ａの各辺から下方に延びる４つの側部７Ｂとを有する。隣り合う側部７Ｂは、互いの境界部分が切り欠かれることで分離させられている。さらに、各側部７Ｂの下端部分は、内側に折り曲げられることで爪７Ｃを形成している。このような金属シールド７は、例えば、ステンレス、洋白などから製造される。なお、各側部７Ｂは、外力により湾曲可能になっている。   As shown in the side cross section of FIG. 1 and the perspective view of FIG. 3, the metal shield 7 has a cap shape that covers each of the upper surface 6 </ b> A and the side surface 6 </ b> C of the resin 6. More specifically, the metal shield 7 has a quadrangular ceiling portion 7A and four side portions 7B extending downward from each side of the ceiling portion 7A. Adjacent side portions 7B are separated by cutting out their boundary portions. Furthermore, the lower end portion of each side portion 7B is bent inward to form a claw 7C. Such a metal shield 7 is manufactured from, for example, stainless steel, white or white. Each side portion 7B can be bent by an external force.

図１に示すように、この爪７Ｃは、掛け止め部材５で区画される空間２５に挿入され、掛け止め部材５の上壁部５Ｃに当接させられる。これにより、金属シールド７が掛け止め部材５を介して配線基板２に固定される。このため、爪７Ｃは、空間２５に挿入可能で、かつ金属シールド７を配線基板２に固定するのに必要な大きさに形成されている。   As shown in FIG. 1, the claw 7 </ b> C is inserted into a space 25 defined by the latch member 5 and is brought into contact with the upper wall portion 5 </ b> C of the latch member 5. As a result, the metal shield 7 is fixed to the wiring board 2 via the latch member 5. For this reason, the claw 7 </ b> C can be inserted into the space 25 and has a size necessary for fixing the metal shield 7 to the wiring board 2.

次に、図４から図１１を参照して半導体装置１の製造方法について説明する。
まず、図４及び図５に示す構造を得るまでの工程について説明する。なお、図４は、集合基板３１の断面図、図５は、集合基板３１を上から見た平面図である。 Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS.
First, steps required until a structure shown in FIGS. 4 and 5 is obtained will be described. 4 is a cross-sectional view of the collective substrate 31, and FIG. 5 is a plan view of the collective substrate 31 as viewed from above.

ガラスエポキシからなる集合基板３１内において隣接して区画される四角形の複数の配線基板形成領域３１Ａには、スルーホール３２と、接地端子１３を含む導電パターン１１などが形成されている。接地端子１３は、少なくとも、隣接する配線基板形成領域３１Ａを区画する四角形の各辺の中央に配置されている。
まず、集合基板３１の配線基板形成領域３１Ａ内のそれぞれにハンダ１２Ａを介して受動部品４を実装する。さらに、導電性を有する細長の蓋部材４１をハンダ１２Ｂにより集合基板３１の接地端子１３上に接続する。蓋部材４１は、後のダイシング工程で切断されて掛け止め部材５として使用される部材である。 In a plurality of rectangular wiring board forming regions 31A that are adjacently partitioned in the aggregate substrate 31 made of glass epoxy, the through hole 32, the conductive pattern 11 including the ground terminal 13, and the like are formed. The ground terminal 13 is arranged at least in the center of each side of the quadrangle that partitions the adjacent wiring board formation region 31A.
First, the passive component 4 is mounted on each of the wiring board formation regions 31A of the collective board 31 via the solder 12A. Further, the elongated lid member 41 having conductivity is connected to the ground terminal 13 of the collective substrate 31 by the solder 12B. The lid member 41 is a member that is used as the latching member 5 by being cut in a later dicing process.

蓋部材４１は、集合基板３１内の配線基板形成領域３１Ａの境界線となるダイシングライン３５を跨ぐ領域に、蓋部材４１の長手方向の中心線とダイシングライン３５の中心線とが一致するように配置される。また、ダイシングライン３５上において、蓋部材４１は、集合基板３１の縦方向及び横方向のそれぞれにおいて、等間隔で複数配置される。   The lid member 41 has a longitudinal center line of the lid member 41 and a center line of the dicing line 35 in a region straddling the dicing line 35 that is a boundary line of the wiring board forming region 31A in the collective substrate 31. Be placed. On the dicing line 35, a plurality of lid members 41 are arranged at equal intervals in each of the vertical direction and the horizontal direction of the collective substrate 31.

ここで、図５及び図６（ａ）を参照して蓋部材４１の構成について説明する。
図６（ａ）は、蓋部材４１を底面側から見た斜視図である。蓋部材４１は、四角形の枠４２と、枠４２に一体に連なる上面部４３とを有し、底面側に開口部４４を有する凹部が設けられている。蓋部材４１は、例えば、銅やステンレス、洋白などをプレス加工や、切削加工することで製造される。蓋部材４１のサイズは、半導体装置１のサイズによっても異なるが、例えば、長さを約２．０ｍｍ、幅を約１．２ｍｍ、高さを約０．３ｍｍ、厚さを約０．１ｍｍにする。 Here, the configuration of the lid member 41 will be described with reference to FIGS. 5 and 6A.
FIG. 6A is a perspective view of the lid member 41 as seen from the bottom surface side. The lid member 41 includes a rectangular frame 42 and an upper surface portion 43 that is integrally connected to the frame 42, and a recess having an opening 44 on the bottom surface side. The lid member 41 is manufactured, for example, by pressing or cutting copper, stainless steel, or white. The size of the lid member 41 varies depending on the size of the semiconductor device 1. For example, the length is about 2.0 mm, the width is about 1.2 mm, the height is about 0.3 mm, and the thickness is about 0.1 mm. To do.

蓋部材４１は、開口部４４を集合基板３１に向けて配置した後、枠４２の下端がハンダ１２Ｂで接地端子１３に接合される。これにより、開口部４４が集合基板３１で塞がれて、蓋部材４１の内部の空間４５が集合基板３１によって密閉される。   The lid member 41 is arranged with the opening 44 facing the collective substrate 31, and then the lower end of the frame 42 is joined to the ground terminal 13 by the solder 12 </ b> B. As a result, the opening 44 is closed by the collective substrate 31, and the space 45 inside the lid member 41 is sealed by the collective substrate 31.

次に、集合基板３１の配線基板形成領域３１Ａ内の半導体素子実装領域に熱硬化接着剤１０を塗布する。その後、半導体素子実装領域に半導体素子３をフェイスダウンで取り付け、半導体素子３の下面のバンプを金属材料９を介して導電パターン１１に接続した後に、熱硬化接着材１０を熱硬化させる。   Next, the thermosetting adhesive 10 is applied to the semiconductor element mounting region in the wiring substrate forming region 31 </ b> A of the collective substrate 31. Thereafter, the semiconductor element 3 is attached face-down to the semiconductor element mounting region, the bumps on the lower surface of the semiconductor element 3 are connected to the conductive pattern 11 via the metal material 9, and then the thermosetting adhesive 10 is thermally cured.

次に、図７の側断面図に示すように、半導体素子３、受動部品４及び蓋部材４１を覆う
ようにエポキシ樹脂を集合基板３１上に充填してから硬化させる。これにより、半導体素子３、受動部品４及び蓋部材４１が樹脂６で封止される。この際、蓋部材４１は、集合基板３１で密着しているので、内部の空間４５にエポキシ樹脂が流入することはない。 Next, as shown in the side sectional view of FIG. 7, an epoxy resin is filled on the collective substrate 31 so as to cover the semiconductor element 3, the passive component 4, and the lid member 41, and then cured. As a result, the semiconductor element 3, the passive component 4, and the lid member 41 are sealed with the resin 6. At this time, since the lid member 41 is in close contact with the collective substrate 31, the epoxy resin does not flow into the internal space 45.

この後、図８の側断面図に示すように、ダイシングライン３５に沿って、樹脂６及び集合基板３１をブレード３６によって切断する。これにより、図９の平面図に示すように、集合基板３１が、半導体素子３等を搭載した複数の配線基板２に個片化される。ここで、ダイシングライン３５上には、蓋部材４１が配置されているので、集合基板３１を切断すると同時に蓋部材４１がブレード３６によって２つの部材に切断される。蓋部材４１の長手方向の中心線とダイシングライン３５の中心線がほぼ一致するように配置されていることにより、中心線を挟んで左右対称な形状を有する蓋部材４１は２つの同じ形状の部材に切断される。そして、底面から見た図６（ｂ）の斜視図に示すように、蓋部材４１が切断されることで２つに分割された部材のそれぞれが掛け止め部材５になり、掛け止め部材５は、配線基板２の各辺に沿って細長に配置される。   Thereafter, as shown in the side sectional view of FIG. 8, the resin 6 and the collective substrate 31 are cut by the blade 36 along the dicing line 35. As a result, as shown in the plan view of FIG. 9, the collective substrate 31 is separated into a plurality of wiring substrates 2 on which the semiconductor elements 3 and the like are mounted. Here, since the lid member 41 is disposed on the dicing line 35, the lid member 41 is cut into two members by the blade 36 at the same time as the collective substrate 31 is cut. Since the center line in the longitudinal direction of the lid member 41 and the center line of the dicing line 35 are arranged so as to substantially coincide with each other, the lid member 41 having a symmetrical shape with respect to the center line is two members having the same shape. Disconnected. Then, as shown in the perspective view of FIG. 6B as viewed from the bottom, each of the members divided into two by the lid member 41 being cut becomes the latch member 5, and the latch member 5 is These are arranged in a slender shape along each side of the wiring board 2.

ここで、図２（ｂ）の掛け止め部材５の端面５Ｄは、ダイシング工程における蓋部材４１の切断面に相当する。同様に、図１に示す半導体素子３等を封止する樹脂６の側面６Ｃは、ダイシング工程における樹脂６の切断面に相当する。したがって、掛け止め部材５の端面５Ｄと、樹脂６の側面６Ｃとが面一になる。
さらに、配線基板２の側面２Ｃは、ダイシング工程における集合基板３１の切断面に相当する。このため、掛け止め部材５の端面５Ｄと、配線基板２の側面２Ｃとが面一になる。なお、蓋部材４１の中心がダイシングライン３５からずれていても、ダイシング時の切断面が掛け止め部材５の端面５Ｄになるので、端面５Ｄを樹脂６の側面６Ｃ及び配線基板２の側面２Ｃと面一にすることができる。 Here, the end surface 5D of the latching member 5 in FIG. 2B corresponds to a cut surface of the lid member 41 in the dicing process. Similarly, the side surface 6C of the resin 6 that seals the semiconductor element 3 and the like shown in FIG. 1 corresponds to a cut surface of the resin 6 in the dicing process. Therefore, the end surface 5D of the latch member 5 and the side surface 6C of the resin 6 are flush with each other.
Furthermore, the side surface 2C of the wiring board 2 corresponds to a cut surface of the collective substrate 31 in the dicing process. For this reason, the end surface 5D of the latching member 5 and the side surface 2C of the wiring board 2 are flush with each other. Even if the center of the lid member 41 is deviated from the dicing line 35, the cut surface at the time of dicing becomes the end surface 5D of the latching member 5. Therefore, the end surface 5D is connected to the side surface 6C of the resin 6 and the side surface 2C of the wiring board 2. Can be flush.

次に、図１０の側断面図に示すように、金属シールド７は、その側面７Ｂを外側に広げられながら、半導体素子３等を搭載させた配線基板２に上方から被せられる。これにより、金属シールド７の天井部７Ａが樹脂６の上面６Ａを覆うとともに、金属シールド７の側部７Ｂが樹脂６の側面６Ｃを覆う。
このとき、金属シールド７の側部７Ｂの爪７Ｃは、樹脂６から露出する掛け止め部材５の端面５Ｄの開口部を通して内部の空間２５内に侵入する。これにより、爪７Ｃが上壁部５Ｃに係合し、掛け止め部材５を介して金属シールド７が配線基板２に支持される。
掛け止め部材５が導電性を有し、かつ接地端子１３に接合されているので、金属シールド７が掛け止め部材５を介して接地端子１３に電気的に接続される。そして、このときの金属シールド７と配線基板２の係合面積は、爪７Ｃと掛け止め部材５の接触面積の合計に略等しくなる。 Next, as shown in the side sectional view of FIG. 10, the metal shield 7 is placed on the wiring board 2 on which the semiconductor element 3 and the like are mounted from above while the side surface 7B is spread outward. Accordingly, the ceiling portion 7A of the metal shield 7 covers the upper surface 6A of the resin 6, and the side portion 7B of the metal shield 7 covers the side surface 6C of the resin 6.
At this time, the claw 7 </ b> C of the side portion 7 </ b> B of the metal shield 7 enters the internal space 25 through the opening of the end surface 5 </ b> D of the latching member 5 exposed from the resin 6. Thereby, the claw 7 </ b> C engages with the upper wall portion 5 </ b> C, and the metal shield 7 is supported by the wiring board 2 through the latching member 5.
Since the latch member 5 has conductivity and is joined to the ground terminal 13, the metal shield 7 is electrically connected to the ground terminal 13 through the latch member 5. The engagement area between the metal shield 7 and the wiring board 2 at this time is substantially equal to the total contact area between the claw 7C and the latch member 5.

金属シールド７は、４つの爪７Ｃを用いて４つの掛け止め部材５に係合させられるので、配線基板２に対して強固に固定させることができる。また、金属シールド７は、掛け止め部材５及び樹脂６を覆うように配置されるので、金属シールド７の側部７Ｂが配線基板２より外側に配置される。そのはみ出し量は、側部７Ｂの厚さであるので半導体装置１を大型にすることはない。なお、金属シールド７の各側部７Ｂは、互いに分離されており、その下端部分を独立して弾性変形させられるので、金属シールド７は上方から掛け止め部材５に容易に係合させられる。   Since the metal shield 7 is engaged with the four latching members 5 using the four claws 7C, the metal shield 7 can be firmly fixed to the wiring board 2. Further, since the metal shield 7 is disposed so as to cover the retaining member 5 and the resin 6, the side portion 7 </ b> B of the metal shield 7 is disposed outside the wiring board 2. Since the protruding amount is the thickness of the side portion 7B, the semiconductor device 1 is not enlarged. The side portions 7B of the metal shield 7 are separated from each other, and the lower end portions thereof can be elastically deformed independently, so that the metal shield 7 can be easily engaged with the latch member 5 from above.

このように、半導体素子３等を樹脂６で封止した配線基板２に金属シールド７を上方から嵌め込んで固定させることで、半導体装置１の製造が完了する。また、半導体装置１では、金属シールド７の存在によって、半導体素子３などから発生したノイズが外部に放射されることが防止されると共に、外部からのノイズが内部に浸入することが防止される。   As described above, the metal shield 7 is fitted and fixed to the wiring board 2 in which the semiconductor element 3 and the like are sealed with the resin 6, thereby completing the manufacture of the semiconductor device 1. In the semiconductor device 1, the presence of the metal shield 7 prevents noise generated from the semiconductor element 3 and the like from being radiated to the outside, and prevents noise from the outside from entering the inside.

以上、説明したように、この実施の形態では、配線基板２の一方の面２Ａ上にハンダ１２Ｂで接合した掛け止め部材５に金属シールド７を機械的に係合させるように構成したので、金属シールド７を確実に配線基板２に取り付けることが可能になる。さらに、掛け止め部材５が配線基板２の各辺に沿って細長に延びるので、配線基板２と金属シールド７の接触面積を増大させることができ、かつ金属シールド７を４箇所でバランス良く支持することが可能になる。   As described above, in this embodiment, the metal shield 7 is mechanically engaged with the latch member 5 joined to the one surface 2A of the wiring board 2 by the solder 12B. The shield 7 can be securely attached to the wiring board 2. Furthermore, since the latching member 5 is elongated along each side of the wiring board 2, the contact area between the wiring board 2 and the metal shield 7 can be increased, and the metal shield 7 is supported in a balanced manner at four locations. It becomes possible.

ここで、金属シールド７の爪７Ｃと掛け止め部材５の上壁部５Ｃとの係合方向は、爪７Ｃの上昇、すなわち金属シールド７の天井部７Ａに向う方向への移動を妨げる方向である。このため、金属シールド７が熱を受けて変形しようとした場合でも、爪７Ｃの上昇、すなわち金属シールド７の天井部７Ａが樹脂６から離れる方向への移動が妨げられるので、金属シールド７全体として変形と、これに起因する樹脂６からの剥離が抑制される。これにより、後の処理や、半導体装置１の使用時などに、金属シールド７が変形したり、配線基板２から脱離したりすることが防止される。   Here, the engagement direction of the claw 7C of the metal shield 7 and the upper wall portion 5C of the latching member 5 is a direction that prevents the claw 7C from rising, that is, the movement of the metal shield 7 in the direction toward the ceiling portion 7A. . For this reason, even when the metal shield 7 is about to be deformed by receiving heat, the claw 7C is raised, that is, the ceiling portion 7A of the metal shield 7 is prevented from moving away from the resin 6. Deformation and separation from the resin 6 due to this are suppressed. Thereby, it is possible to prevent the metal shield 7 from being deformed or detached from the wiring board 2 during subsequent processing or when the semiconductor device 1 is used.

また、この実施の形態では、金属シールド７が、配線基板２の一方の面２Ａ側の内側で掛け止め部材５に係合させられるように構成したので、金属シールド７が配線基板２の他方の面２Ｂ側に突出することはない。これにより、半導体装置１を他の装置などに取り付ける際の取り付け高さを低くできる。   Further, in this embodiment, since the metal shield 7 is configured to be engaged with the latch member 5 on the inner side of the one side 2A of the wiring board 2, the metal shield 7 is connected to the other side of the wiring board 2. It does not protrude to the surface 2B side. Thereby, the attachment height at the time of attaching the semiconductor device 1 to another apparatus etc. can be made low.

さらに、掛け止め部材５の端面５Ｄと、配線基板２の側面２Ｃを一致させるように構成したので、掛け止め部材５及び樹脂６を覆う金属シールド７の側部７Ｂが配線基板２より外側に突出させられる。これにより、金属シールド７の側部７Ｂを把持して半導体装置１をハンドリングすることが可能になる。配線基板２のみを把持する場合には、配線基板に応力が集中することがあるが、この実施の形態では、半導体装置１のハンドリング時に配線基板２に応力が集中することが防止される。   Further, since the end surface 5D of the latch member 5 and the side surface 2C of the wiring board 2 are made to coincide with each other, the side portion 7B of the metal shield 7 covering the latch member 5 and the resin 6 projects outward from the wiring board 2. Be made. As a result, the semiconductor device 1 can be handled by holding the side portion 7B of the metal shield 7. When only the wiring board 2 is gripped, stress may concentrate on the wiring board, but in this embodiment, stress is prevented from concentrating on the wiring board 2 when the semiconductor device 1 is handled.

また、この実施の形態では、掛け止め部材５が最初に下面が開放された蓋部材４１として供給されるので、集合基板３１に接合したときに内部の空間４５を密閉することができる。このため、半導体素子３等を樹脂封止するときに、掛け止め部材５の内部に樹脂が流入することが防止される。さらに、掛け止め部材５は、配線基板２をダイシングにより個片化するときに、同時に形成されるので、製造工程を簡略化することができる。また、配線基板２を個片化するのと同時に、掛け止め部材５、配線基板２、及び樹脂６のそれぞれの端面５Ｄ、側面２Ｃ，６Ｃを一致させることができる。   In this embodiment, the latch member 5 is first supplied as the lid member 41 whose bottom surface is opened, so that the internal space 45 can be sealed when it is joined to the collective substrate 31. For this reason, when the semiconductor element 3 or the like is sealed with resin, the resin is prevented from flowing into the latch member 5. Furthermore, since the latching member 5 is formed at the same time when the wiring board 2 is separated into pieces by dicing, the manufacturing process can be simplified. Further, at the same time when the wiring substrate 2 is separated into pieces, the end face 5D and the side surfaces 2C and 6C of the latching member 5, the wiring substrate 2, and the resin 6 can be made to coincide with each other.

なお、金属シールド７と掛け止め部材５の係合部分は、必要に応じてハンダで接合しても良い。この場合は、金属シールド７がさらに強固に配線基板２に対して固定される。   In addition, you may join the engaging part of the metal shield 7 and the latching member 5 with solder as needed. In this case, the metal shield 7 is fixed to the wiring board 2 more firmly.

配線基板２に搭載される部品の種類や数、レイアウトは図１及び図５に限定されない。また、半導体素子３は、フェイスアップで配線基板２に実装しても良い。この場合は、半導体素子３側の電極と、配線基板２側の電極とを、図示を省略する金などの導電性ワイヤを用いて電気的に接続させる。さらに、配線基板２の他方の面２Ｂにおいて、平面状の外部接続端子８上にハンダバンプを設けて、ＢＧＡ（Ball Grid Array）を形成しても良い。   The type, number, and layout of components mounted on the wiring board 2 are not limited to those shown in FIGS. The semiconductor element 3 may be mounted on the wiring board 2 face up. In this case, the electrode on the semiconductor element 3 side and the electrode on the wiring board 2 side are electrically connected using a conductive wire such as gold (not shown). Further, on the other surface 2B of the wiring board 2, a solder bump may be provided on the planar external connection terminal 8 to form a BGA (Ball Grid Array).

ここで、蓋部材の変形例について、図１１、図１２及び図１３を参照して説明する。なお、図１１、図１２及び図１３は、蓋部材及び掛け止め部材を底面側から見た斜視図である。
図１１（ａ）に示す蓋部材５１は、断面が半円形になっており、底面側に開口部５１Ａを有する凹部が設けられている。この蓋部材５１は、ダイシングライン３５を跨いで配置
され、開口部５１Ａが集合基板３１で密閉されるように接地端子１３にハンダ接合される。ダイシング工程では、集合基板３１が複数の配線基板２に個片化されるのと同時に、図１１（ｂ）に示すように、蓋部材５１が２つに切断されて掛け止め部材５２が２つずつ形成される。 Here, a modified example of the lid member will be described with reference to FIGS. 11, 12, and 13. 11, 12 and 13 are perspective views of the lid member and the latch member as seen from the bottom surface side.
The lid member 51 shown in FIG. 11A has a semicircular cross section and is provided with a recess having an opening 51A on the bottom surface side. The lid member 51 is disposed across the dicing line 35 and is soldered to the ground terminal 13 so that the opening 51A is sealed with the collective substrate 31. In the dicing step, the collective substrate 31 is separated into a plurality of wiring substrates 2 and at the same time, as shown in FIG. 11B, the lid member 51 is cut into two and two latching members 52 are provided. Formed one by one.

掛け止め部材５２は、曲面からなる壁部５３と、この壁部５３の両端からＬ字状に屈曲した２つの側壁部５４とを有し、壁部５３及び側壁部５４の下端がハンダ１２Ｂで接地端子１３に接続される。壁部５３の内面は配線基板２の外側に向けて配置される。これにより、掛け止め部材５２は、壁部５３の上端部分を配線基板２の外側に向けて取り付けられる。
掛け止め部材５２を介して金属シールド７を配線基板２に支持させるときは、壁部５３及び側壁部５４で区画される空間５５内に金属シールド７の爪７Ｃを挿入させ、係合させる。 The latch member 52 has a wall portion 53 formed of a curved surface and two side wall portions 54 bent in an L shape from both ends of the wall portion 53, and the lower ends of the wall portion 53 and the side wall portion 54 are solder 12B. Connected to the ground terminal 13. The inner surface of the wall portion 53 is disposed toward the outside of the wiring board 2. Thereby, the latching member 52 is attached with the upper end portion of the wall portion 53 facing the outside of the wiring board 2.
When the metal shield 7 is supported on the wiring board 2 through the latching member 52, the claw 7C of the metal shield 7 is inserted into the space 55 defined by the wall portion 53 and the side wall portion 54 and engaged.

なお、蓋部材５１の断面形状は、切断線を中心にして左右対称の形状であれば良く、半円形に限定されない。例えば、楕円を半分にカットした断面や、その他の曲面形状であっても良い。また、蓋部材５１の断面形状は、台形や三角形であっても良い。そのような蓋部材５１を２つに切断したときに得られる掛け止め部材５２の断面は、それぞれ台形を２分した形状や、三角形を２分した形状になり、掛け止め部材５２によって区画される空間５５に金属シールド７の爪７Ｃが挿入され、係合させられる。   In addition, the cross-sectional shape of the cover member 51 should just be a left-right symmetric shape centering on a cutting line, and is not limited to a semicircle. For example, it may be a cross section obtained by cutting an ellipse in half, or another curved surface shape. Further, the cross-sectional shape of the lid member 51 may be a trapezoid or a triangle. The cross section of the latching member 52 obtained when the lid member 51 is cut into two has a shape that divides the trapezoid into two or a shape that divides the triangle into two, and is partitioned by the latching member 52. The claw 7C of the metal shield 7 is inserted into the space 55 and engaged.

また、図１２（ａ）に示す蓋部材６１は、半球形で底面側に開口部６１Ａを有する凹部が設けられている。この蓋部材６１は、ダイシングライン３５を跨いで配置され、開口部６１Ａが集合基板３１で密閉されるように接地端子１３にハンダ接合される。ダイシング工程では、集合基板３１が切断されて複数の配線基板２に個片化されるのと同時に、図１２（ｂ）に示すように、蓋部材６１が２つに切断されて掛け止め部材６２が２つずつ形成される。
掛け止め部材６２は、曲面形状を有する壁部６３の下端がハンダ１２で接地端子１３に接続される。壁部６３の逆Ｕ字形の端面６２Ｃが配線基板２の外側に向けて取り付けられ、壁部６３によって区画される空間６４内に金属シールド７の爪７Ｃが挿入され、係合させられる。なお、蓋部材６１の断面形状は、半球形に限定されず、楕円球を半分にカットした断面や、その他の曲面形状であっても良い。 Moreover, the lid member 61 shown in FIG. 12A is hemispherical and has a recess having an opening 61A on the bottom surface side. The lid member 61 is disposed across the dicing line 35 and is soldered to the ground terminal 13 so that the opening 61A is sealed by the collective substrate 31. In the dicing process, the collective substrate 31 is cut and separated into a plurality of wiring boards 2, and at the same time, as shown in FIG. Are formed two by two.
The lower end of the wall portion 63 having a curved surface shape is connected to the ground terminal 13 by the solder 12. An inverted U-shaped end face 62 </ b> C of the wall portion 63 is attached to the outside of the wiring board 2, and the claw 7 </ b> C of the metal shield 7 is inserted into and engaged with the space 64 defined by the wall portion 63. Note that the cross-sectional shape of the lid member 61 is not limited to a hemispherical shape, and may be a cross-sectional shape obtained by cutting an elliptical sphere into half or other curved surface shapes.

さらに、図１３（ａ）に示す蓋部材７１は、内部に空間７２が形成された直方体形を有する。この蓋部材７１は、ダイシングライン３５を跨いで配置され、接地端子１３にハンダ接合される。ダイシング工程では、集合基板３１が切断されて複数の配線基板２に個片化されると同時に、図１３（ｂ）に示すように、蓋部材７１が２つに切断されて掛け止め部材７３が２つずつ形成される。
掛け止め部材７３は、底部７４と、背面壁部７５と、２つの側壁部７６と、上壁部７７とを有し、底部７４がハンダ１２で接地端子１３に接続されている。背面壁部７５の内面は配線基板２の外側に向けて取り付けられることで、上壁部７７が配線基板２の外側に向けて配置される。掛け止め部材７３の各壁部７４〜７７によって形成される空間７８に金属シールド７の爪７Ｃが挿入され、係合させられる。 Furthermore, the lid member 71 shown in FIG. 13A has a rectangular parallelepiped shape in which a space 72 is formed. The lid member 71 is disposed across the dicing line 35 and soldered to the ground terminal 13. In the dicing process, the collective substrate 31 is cut and separated into a plurality of wiring boards 2, and at the same time, as shown in FIG. Two are formed.
The latch member 73 has a bottom portion 74, a back wall portion 75, two side wall portions 76, and an upper wall portion 77, and the bottom portion 74 is connected to the ground terminal 13 by the solder 12. The inner surface of the back wall portion 75 is attached toward the outside of the wiring substrate 2, so that the upper wall portion 77 is disposed toward the outside of the wiring substrate 2. The claw 7C of the metal shield 7 is inserted into and engaged with a space 78 formed by the wall portions 74 to 77 of the latch member 73.

なお、図１１（ａ）、図１２（ａ）、図１３（ａ）のそれぞれに示す蓋部材５１，６１、７１の切断面は、配線基板２及び樹脂６の切断面に一致するので、各掛け止め部材５２，６２，７３の端面５２Ｃ，６２Ｃ，７３Ｃが配線基板２及び樹脂６のそれぞれの側面２Ｃ，６Ｃと面一になる。
また、図１１（ａ）及び図１２（ａ）に示す蓋部材５１，６１において、図１３（ａ）と同様の底部７４を設けると、製造過程で樹脂６が空間５５，６４に流入することをより
確実に防止できる。また、接地端子１３との接合面積を増やしてハンダ接合が強固になる。 In addition, since the cut surfaces of the lid members 51, 61, and 71 shown in FIGS. 11A, 12A, and 13A correspond to the cut surfaces of the wiring board 2 and the resin 6, respectively. End surfaces 52C, 62C, and 73C of the latching members 52, 62, and 73 are flush with the side surfaces 2C and 6C of the wiring board 2 and the resin 6, respectively.
In addition, in the lid members 51 and 61 shown in FIGS. 11A and 12A, if the bottom portion 74 similar to that in FIG. 13A is provided, the resin 6 flows into the spaces 55 and 64 during the manufacturing process. Can be prevented more reliably. Further, the bonding area with the ground terminal 13 is increased, and the solder bonding is strengthened.

（第２の実施の形態）
図１４から図２０を参照して、第２の実施の形態について説明する。この実施の形態は、半導体素子等が樹脂で封止されないタイプの半導体装置に関する。
図１４の断面図に示すように、半導体装置８１には、配線基板２の一方の面２Ａ上に半導体素子３と、コンデンサや抵抗器、コイルなどの受動部品４と、導電性を有する掛け止め部材５が搭載されている。半導体素子３及び受動部品４を覆う金属シールド７は、第１の実施の形態と同様にして、掛け止め部材５に係合させられている。また、配線基板２の他方の面２Ｂには、外部接続端子８によるＬＧＡが形成されている。 (Second Embodiment)
A second embodiment will be described with reference to FIGS. 14 to 20. This embodiment relates to a semiconductor device in which a semiconductor element or the like is not sealed with resin.
As shown in the cross-sectional view of FIG. 14, the semiconductor device 81 includes a semiconductor element 3, a passive component 4 such as a capacitor, a resistor, and a coil on one surface 2A of the wiring board 2, and a conductive latch. A member 5 is mounted. The metal shield 7 covering the semiconductor element 3 and the passive component 4 is engaged with the latch member 5 in the same manner as in the first embodiment. In addition, an LGA formed by the external connection terminals 8 is formed on the other surface 2B of the wiring board 2.

ここで、半導体装置８１は、半導体素子３及び受動部品４と、金属シールド７の間に樹脂が封止されない中空構造になっている。このため、掛け止め部材５と配線基板２のハンダ１２Ｂによる接合部分の少なくとも一部は熱硬化接着剤８２で覆われている。   Here, the semiconductor device 81 has a hollow structure in which the resin is not sealed between the semiconductor element 3 and the passive component 4 and the metal shield 7. For this reason, at least a part of the joining portion of the latch member 5 and the wiring board 2 by the solder 12 </ b> B is covered with the thermosetting adhesive 82.

次に、図１５から図１９を参照して、この半導体装置８１の製造方法について説明する。
まず、図１５及び図１６に示す構造を得るまでの工程について説明する。なお、図１５、図１６は、それぞれ半導体素子３、受動部品４等が搭載された集合基板３１を側方から見た断面図と上方からみた平面図である。
最初に、エポキシ樹脂などから形成された集合基板３１の配線基板形成領域３１Ａに、スルーホール３２と、接地端子１３を含む導電性パターン１１が形成される。この後、集合基板３１の配線基板形成領域３１Ａに、半導体素子３が金属材料９を用いてフェイスダウンで実装される。また、受動部品４と、導電性を有する細長の蓋部材４１が、それぞれ集合基板３１の所定位置にハンダ１２Ａ，１２Ｂを用いて接合される。蓋部材４１は、開口部４４が集合基板３１によって密閉されるように取り付けられる。 Next, a method for manufacturing the semiconductor device 81 will be described with reference to FIGS.
First, steps required until a structure shown in FIGS. 15 and 16 is obtained will be described. FIGS. 15 and 16 are a cross-sectional view from the side and a plan view from above, respectively, of the collective substrate 31 on which the semiconductor element 3, the passive component 4, and the like are mounted.
First, the conductive pattern 11 including the through hole 32 and the ground terminal 13 is formed in the wiring board forming region 31A of the collective board 31 formed of epoxy resin or the like. Thereafter, the semiconductor element 3 is mounted face down using the metal material 9 in the wiring board formation region 31 </ b> A of the collective substrate 31. In addition, the passive component 4 and the elongated lid member 41 having conductivity are joined to predetermined positions of the collective substrate 31 using solder 12A and 12B, respectively. The lid member 41 is attached so that the opening 44 is sealed by the collective substrate 31.

さらに、半導体素子３と配線基板２の間の隙間にエポキシ樹脂を用いた熱硬化接着剤１０が塗布され、半導体素子３を導電パターン１１に接続した後に熱硬化接着剤１０が熱硬化させられる。
また、掛け止め部材５と配線基板２を接合するハンダ１２Ｂを覆うように、熱硬化接着剤８２が塗布され、その後に熱硬化接着剤８２が硬化される。なお、熱硬化接着剤１０，８２は、同じ接着剤であっても良いし、異なる接着剤でも良い。また、熱硬化接着剤１０，８２は、同じ製造工程で塗布及び硬化させても良い。これにより、蓋部材４１と配線基板２の接合部分が補強、及び保護される。なお、蓋部材４１は、長手方向の中心線とダイシングライン３５の中心線とが一致するように配置される。 Further, a thermosetting adhesive 10 using an epoxy resin is applied to the gap between the semiconductor element 3 and the wiring board 2, and after the semiconductor element 3 is connected to the conductive pattern 11, the thermosetting adhesive 10 is thermoset.
Further, a thermosetting adhesive 82 is applied so as to cover the solder 12B that joins the latch member 5 and the wiring board 2, and then the thermosetting adhesive 82 is cured. The thermosetting adhesives 10 and 82 may be the same adhesive or different adhesives. Further, the thermosetting adhesives 10 and 82 may be applied and cured in the same manufacturing process. Thereby, the junction part of the cover member 41 and the wiring board 2 is reinforced and protected. The lid member 41 is arranged so that the center line in the longitudinal direction coincides with the center line of the dicing line 35.

ここで、蓋部材４１は、後の工程で掛け止め部材５になる。蓋部材４１の形状やサイズ、材料は、第１の実施の形態と同じである。   Here, the lid member 41 becomes the latch member 5 in a later step. The shape, size, and material of the lid member 41 are the same as those in the first embodiment.

この後、図１７及び図１８に示すように、ダイシングライン３５に沿って、集合基板３１を切断する。これにより、集合基板３１が、半導体素子３等を搭載した複数の配線基板２に個片化される。ここで、ダイシングライン３５上には、蓋部材４１が配置されているので、集合基板３１を個片化するときに、同時に蓋部材４１が切断され、２つの掛け止め部材５が形成される。このとき、掛け止め部材５は、配線基板２の各辺に沿って細長に延び、その端面５Ｄと、配線基板２の側面２Ｃとが面一になる。   Thereafter, as shown in FIGS. 17 and 18, the collective substrate 31 is cut along the dicing line 35. As a result, the collective substrate 31 is separated into a plurality of wiring substrates 2 on which the semiconductor elements 3 and the like are mounted. Here, since the lid member 41 is disposed on the dicing line 35, when the collective substrate 31 is separated into pieces, the lid member 41 is cut at the same time, and the two latching members 5 are formed. At this time, the latching member 5 is elongated along each side of the wiring board 2, and the end face 5 </ b> D and the side face 2 </ b> C of the wiring board 2 are flush with each other.

次に、図１９に示すように、金属シールド７が、その側面７Ｂを外側に広げられながら、半導体素子３等を搭載させた配線基板２に上方から被せられる。これにより、金属シー
ルド７の側部７Ｂの爪７Ｃが、掛け止め部材５の端面５Ｄの開口部を通して空間２５に浸入し、金属シールド７が掛け止め部材５を介して配線基板２に支持される。掛け止め部材５が導電性を有し、かつ接地端子１３に接合されているので、金属シールド７が掛け止め部材５を介して接地端子１３に電気的に接続される。このときの金属シールド７と配線基板２の接合面積は、爪７Ｃと掛け止め部材５の接触面積の合計に略等しくなる。
金属シールド７は、掛け止め部材５を覆うように配置されるので、その側部が配線基板２より外側に配置され、金属シールド７と配線基板２とで形成される空間内に、半導体素子３及び受動部品４が収容される。 Next, as shown in FIG. 19, the metal shield 7 is placed on the wiring board 2 on which the semiconductor element 3 and the like are mounted from above while the side surface 7B is spread outward. Thereby, the claw 7C of the side portion 7B of the metal shield 7 enters the space 25 through the opening of the end surface 5D of the latch member 5, and the metal shield 7 is supported by the wiring board 2 via the latch member 5. . Since the latch member 5 has conductivity and is joined to the ground terminal 13, the metal shield 7 is electrically connected to the ground terminal 13 through the latch member 5. At this time, the bonding area between the metal shield 7 and the wiring board 2 is substantially equal to the total contact area between the claw 7 </ b> C and the latch member 5.
Since the metal shield 7 is disposed so as to cover the latch member 5, the side portion thereof is disposed outside the wiring substrate 2, and the semiconductor element 3 is disposed in a space formed by the metal shield 7 and the wiring substrate 2. And the passive component 4 is accommodated.

このように、半導体素子３等を搭載させた配線基板２に金属シールド７を上方から嵌め込んで固定させることで、半導体装置１の製造が完了する。   In this manner, the metal shield 7 is fitted and fixed to the wiring board 2 on which the semiconductor element 3 and the like are mounted from above to complete the manufacture of the semiconductor device 1.

以上、説明したように、この実施の形態では、半導体素子３や受動部品４を樹脂で封止しないタイプの半導体装置８１において、第１の実施の形態と同様の効果が得られる。   As described above, in this embodiment, in the semiconductor device 81 of the type in which the semiconductor element 3 and the passive component 4 are not sealed with resin, the same effects as in the first embodiment can be obtained.

なお、半導体装置８１は、図１１（ｂ）、図１２（ｂ）、図１３（ｂ）に示す掛け止め部材５２，６２，７３及び、図１１（ａ）、図１２（ａ）、図１３（ａ）に示す蓋部材５１，６１，７１を用いて構成及び製造しても良い。   The semiconductor device 81 includes latching members 52, 62, and 73 shown in FIGS. 11B, 12B, and 13B, and FIGS. 11A, 12A, and 13B. You may comprise and manufacture using the cover members 51, 61, and 71 shown to (a).

ここで、この実施の形態の変形例について説明する。
集合基板３１に受動部品４等を実装する際に、蓋部材４１の代わりに、掛け止め部材５を直接に実装しても良い。このとき、掛け止め部材５は、端面５Ｄが配線基板２の側面２Ｃと面一になるように接地端子１３にハンダ１２Ｂで接合される。この場合、後のダイシング工程では、掛け止め部材５を切断することなく、集合基板３１のみが切断される。
また、集合基板３１に掛け止め部材５を直接に実装する場合は、図１４に示す向きと同じ向きで、かつ掛け止め部材５の端面５Ｄが配線基板２の側面２Ｃより内側に配置されるように実装しても良い。 Here, a modified example of this embodiment will be described.
When mounting the passive component 4 or the like on the collective substrate 31, the latch member 5 may be directly mounted instead of the lid member 41. At this time, the latch member 5 is joined to the ground terminal 13 with the solder 12 </ b> B so that the end surface 5 </ b> D is flush with the side surface 2 </ b> C of the wiring board 2. In this case, in the subsequent dicing step, only the collective substrate 31 is cut without cutting the retaining member 5.
Further, when the latching member 5 is directly mounted on the collective substrate 31, the end surface 5D of the latching member 5 is arranged on the inner side of the side surface 2C of the wiring board 2 in the same direction as shown in FIG. May be implemented.

さらに、図２０に示す半導体装置８１のように、掛け止め部材５の凹部を配線基板２の中央に向けて実装しても良い。このときに、掛け止め部材５は、背面壁部５Ａの内面が配線基板２の内側に向けて配置される。これにより、上壁部５Ｃが背面壁部５Ａから配線基板２の内側に向けて突出し、かつ配線基板２と平行に配置される。これに対応して、掛け止め部材５に係合させられる金属シールド８５は、側部８５Ｂに外側に突出する爪７Ｃが形成される。   Further, as in the semiconductor device 81 shown in FIG. 20, the recess of the latch member 5 may be mounted toward the center of the wiring board 2. At this time, the latch member 5 is disposed with the inner surface of the back wall portion 5 </ b> A facing the inside of the wiring board 2. As a result, the upper wall portion 5 </ b> C protrudes from the rear wall portion 5 </ b> A toward the inside of the wiring board 2 and is arranged in parallel with the wiring board 2. Correspondingly, the metal shield 85 engaged with the latch member 5 is formed with a claw 7C protruding outward on the side portion 85B.

また、掛け止め部材５を凸形状にし、これに係合させる凹部を金属シールド７に形成しても良い。
この半導体装置８１は、樹脂による封止を行わないので、掛け止め部材５は側壁部５Ｂを有しない構成にすることもできる。この場合の蓋部材４１は、２つの掛け止め部材５を連結させた形状になる。 Further, the latch member 5 may be formed in a convex shape, and a concave portion to be engaged therewith may be formed in the metal shield 7.
Since the semiconductor device 81 does not perform sealing with resin, the latching member 5 can be configured not to have the side wall portion 5B. The lid member 41 in this case has a shape in which the two latching members 5 are connected.

（第３の実施の形態）
図２１及び図２２を参照して、第３の実施の形態について説明する。この実施の形態に係る半導体装置は、掛け止め部材の配置が第１の実施の形態と異なる。
図２１の分解斜視図に示すように、半導体装置９１は、配線基板２の外周部に掛け止め部材９２が設けられている。掛け止め部材９２は、配線基板２の４つの角に１つずつ設けられ、その各々が配線基板２上の接地端子１３にハンダ１２Ｂで接合されている。 (Third embodiment)
A third embodiment will be described with reference to FIGS. 21 and 22. The semiconductor device according to this embodiment is different from the first embodiment in the arrangement of the latching members.
As shown in the exploded perspective view of FIG. 21, the semiconductor device 91 is provided with a latch member 92 on the outer peripheral portion of the wiring board 2. One latch member 92 is provided at each of the four corners of the wiring board 2, and each of them is joined to the ground terminal 13 on the wiring board 2 by solder 12 </ b> B.

上から見た図２２の斜視図に示すように、掛け止め部材９２は、９０°に屈曲させられた背面壁部９３Ａと、背面壁部９３Ａの上端から屈曲して伸びる上壁部９３Ｂとを有する
。この掛け止め部材９２は、背面壁部９３Ａの内面が配線基板２の外側に向けて配置される。これにより、上壁部９３Ｂが背面壁部９３Ａから配線基板２の外側に向けて突出し、かつ配線基板２と平行に配置される。そして、このような掛け止め部材９２によって区画される空間には、金属シールド９４のアーム９５の下端に形成された爪７Ｃが挿入され、係合させられている。 As shown in the perspective view of FIG. 22 as viewed from above, the latch member 92 includes a back wall portion 93A bent at 90 ° and an upper wall portion 93B bent and extended from the upper end of the back wall portion 93A. Have. The latch member 92 is arranged with the inner surface of the back wall portion 93 </ b> A facing the outside of the wiring board 2. As a result, the upper wall portion 93 </ b> B protrudes from the rear wall portion 93 </ b> A toward the outside of the wiring board 2 and is disposed in parallel with the wiring board 2. Then, a claw 7C formed at the lower end of the arm 95 of the metal shield 94 is inserted into and engaged with the space defined by the latch member 92.

図２１に示すように、金属シールド９４は、天井部９４Ａと、天井部９４Ａの各辺から下方に延びる４つの側部９４Ｂとを有する。さらに、天井部９４Ａの４つの角からは、４つのアーム９５が下向きに延びている。各アーム９５と壁部９４Ｂの間は、天井部９４Ａ側の一部を除いて切り欠かれており、アーム９５を弾性的に変形させることが可能になっている。なお、側部９４Ｂは、アーム９５の長さより短くなっているが、アーム９５の長さと略同じでも良い。   As shown in FIG. 21, the metal shield 94 has a ceiling portion 94A and four side portions 94B extending downward from each side of the ceiling portion 94A. Further, four arms 95 extend downward from the four corners of the ceiling portion 94A. Each arm 95 and the wall portion 94B are cut out except for a part on the ceiling portion 94A side, and the arm 95 can be elastically deformed. The side portion 94B is shorter than the length of the arm 95, but may be substantially the same as the length of the arm 95.

次に、図２１及び図２３を主に参照して、半導体装置９１を製造工程について説明する。なお、図２３は、集合基板３１を上方から見た平面図である。
最初に、集合基板３１の配線基板形成領域３１Ａに、半導体素子３と、受動部品４と、蓋部材９７とを、ハンダ１２Ａ，１２Ｂ等を用いて実装する。蓋部材９７は、図６（ａ）に示す蓋部材４１と長さが異なるものの、同様の構成を有する。なお、蓋部材９７は、平面視で略正方形のものが用いられているが、その他の形状であっても良い。
蓋部材９７は、集合基板３１内の配線基板形成領域３１Ａの境界にあるダイシングライン３５が交差する位置に合わせて１つずつ、開口部を集合基板３１で塞ぐように、ハンダ１２Ｂで接地端子１３に接合される。なお、接地端子１３は、蓋部材９７の配置に対応して、配線基板形成領域３１Ａの４つの角のそれぞれを跨いで配置されている。 Next, a manufacturing process of the semiconductor device 91 will be described with reference mainly to FIGS. FIG. 23 is a plan view of the collective substrate 31 as viewed from above.
First, the semiconductor element 3, the passive component 4, and the lid member 97 are mounted on the wiring board formation region 31 </ b> A of the collective substrate 31 using solder 12 </ b> A, 12 </ b> B, or the like. The lid member 97 has the same configuration as the lid member 41 shown in FIG. The lid member 97 has a substantially square shape in plan view, but may have other shapes.
The lid member 97 is connected to the ground terminal 13 by the solder 12B so that the opening is closed by the collective substrate 31 one by one according to the position where the dicing lines 35 at the boundary of the wiring substrate forming region 31A in the collective substrate 31 intersect. To be joined. Note that the ground terminal 13 is disposed across each of the four corners of the wiring board formation region 31 </ b> A corresponding to the arrangement of the lid member 97.

続いて、半導体素子３及び受動部品４、並びに蓋部材９７を樹脂封止した後、集合基板３１をダイシングライン３５に沿ってダイシングすると、集合基板３１が切断されて複数の配線基板２に個片化される。これと同時に、直交する２つのダイシングライン３５のそれぞれに対して対称な形状を有する蓋部材９７がダイシングライン３５に沿って４つの部材に切断される。これら切断された部材のそれぞれが、掛け止め部材９２になる。掛け止め部材９２は、配線基板２の各角に１つずつ配置され、掛け止め部材９２の端面９２Ｃと、配線基板２の側面２Ｃ及び樹脂６の側面６Ｃとが面一になる。   Subsequently, after the semiconductor element 3, the passive component 4, and the lid member 97 are sealed with resin, the collective substrate 31 is diced along the dicing line 35, so that the collective substrate 31 is cut and separated into a plurality of wiring substrates 2. It becomes. At the same time, the lid member 97 having a symmetrical shape with respect to each of the two orthogonal dicing lines 35 is cut into four members along the dicing line 35. Each of these cut members becomes a latch member 92. One latching member 92 is disposed at each corner of the wiring board 2, and the end surface 92 </ b> C of the latching member 92 is flush with the side surface 2 </ b> C of the wiring substrate 2 and the side surface 6 </ b> C of the resin 6.

金属シールド９４を上方から供給し、樹脂６の上面６Ａ及び側面６Ｃを覆い、かつ４つのアーム９５のそれぞれの爪７Ｃを対応して配置されている掛け止め部材９２に係合させると、半導体素子３等を実装した配線基板２に金属シールド９４が取り付けられ、半導体装置９１の製造が完了する。   When the metal shield 94 is supplied from above, the upper surface 6A and the side surface 6C of the resin 6 are covered, and the claws 7C of the four arms 95 are engaged with the corresponding latch members 92, the semiconductor element The metal shield 94 is attached to the wiring board 2 on which 3 and the like are mounted, and the manufacture of the semiconductor device 91 is completed.

この実施の形態では、掛け止め部材９２を配線基板２の４つの角のそれぞれに１つずつ配置したので、金属シールド９４を４箇所でバランス良く支持することが可能になる。アーム９５が天井部９４Ａの４つの角からそれぞれ延びており、そのそれぞれが掛け止め部材９２に係合させられるので、金属シールド９４の天井部９４Ａの角部の変形を防止できる。その他の効果は、第１の実施の形態と同様である。   In this embodiment, since the latching members 92 are arranged one by one at each of the four corners of the wiring board 2, the metal shield 94 can be supported in four locations with good balance. Since the arms 95 extend from the four corners of the ceiling portion 94A and are respectively engaged with the latching members 92, deformation of the corner portions of the ceiling portion 94A of the metal shield 94 can be prevented. Other effects are the same as those of the first embodiment.

なお、掛け止め部材９２の配置数は、４つ限定されずに、３つ又は２つでも良い。掛け止め部材９２を２つのみ配置するときは、配線基板２の対角線上に、電子部品（半導体素子３）を挟むように、掛け止め部材９２を１つずつ配置すると、バランス良く金属シールド９４を支持できる。また、掛け止め部材９２は、隣り合う２つの角に１つずつ配置しても良い。
また、この半導体装置９１では、図１１（ａ）、図１２（ａ）、図１３（ａ）に示す蓋部材５１，６１，７１を用いることが可能である。また、この実施の形態は、半導体素子
３や受動部品４を樹脂で封止しないタイプにも適用できる。 In addition, the number of arrangement | positioning of the latching member 92 is not limited to four, Three or two may be sufficient. When only two latching members 92 are arranged, if the latching members 92 are arranged one by one on the diagonal line of the wiring board 2 so as to sandwich the electronic component (semiconductor element 3), the metal shield 94 is well balanced. I can support it. Moreover, you may arrange | position the latching member 92 1 each in two adjacent corners.
In the semiconductor device 91, the lid members 51, 61, 71 shown in FIGS. 11A, 12A, and 13A can be used. This embodiment can also be applied to a type in which the semiconductor element 3 and the passive component 4 are not sealed with resin.

（第４の実施の形態）
図２４及び図２５を参照して、第４の実施の形態について説明する。この実施の形態に係る半導体装置は、掛け止め部材の配置が第１の実施の形態と異なる。なお、図２４は、半導体装置の分解斜視図であり、図２５は、集合基板を上方からみた平面図である。
図２４に示すように、半導体装置１０１は、配線基板２の外周部に掛け止め部材５が設けられている。掛け止め部材５は、配線基板２の４つ辺のうちの３つの辺の略中央に相当する位置に１つずつ配置されており、その各々が配線基板２上の接地端子１３にハンダ１２で接合されている。 (Fourth embodiment)
A fourth embodiment will be described with reference to FIGS. 24 and 25. FIG. The semiconductor device according to this embodiment is different from the first embodiment in the arrangement of the latching members. FIG. 24 is an exploded perspective view of the semiconductor device, and FIG. 25 is a plan view of the collective substrate as viewed from above.
As shown in FIG. 24, the semiconductor device 101 is provided with a latch member 5 on the outer periphery of the wiring board 2. The latch members 5 are arranged one by one at positions corresponding to approximately the center of three of the four sides of the wiring board 2, and each of them is connected to the ground terminal 13 on the wiring board 2 by the solder 12. It is joined.

金属シールド１０２は、天井部１０２Ａを有し、天井部１０２Ａの各辺のうちの３つ辺からは側部１０２Ｂが下方に向けて延びている。３つ側部１０２Ｂは、配線基板２側の３つの掛け止め部材５の配置に対応した位置のそれぞれに設けられており、それぞれの下端には、爪７Ｃが形成されている。   The metal shield 102 has a ceiling portion 102A, and side portions 102B extend downward from three sides of each side of the ceiling portion 102A. The three side portions 102B are provided at positions corresponding to the arrangement of the three latching members 5 on the wiring board 2 side, and a claw 7C is formed at each lower end.

図２５に示すように、半導体装置９１を製造するときは、最初に集合基板３１の配線基板形成領域３１Ａに、半導体素子３と、受動部品４と、蓋部材４１とを、ハンダ１２Ａ，１２Ｂ等を用いて実装する。蓋部材４１は、集合基板３１のダイシングライン３５を跨いで、かつ底面側の開口部４４を配線基板２で塞ぐように、３箇所ずつ配置される。図２５の例では、蓋部材４１は、１つの半導体素子３をダイシングライン３５に沿って囲むように３つずつ配置される。なお、蓋部材４１は、平面視で略正方形のものが用いられているが、図１１から図１３に示すような形状であっても良い。   As shown in FIG. 25, when the semiconductor device 91 is manufactured, first, the semiconductor element 3, the passive component 4, the lid member 41, the solder 12A, 12B, and the like are provided in the wiring board formation region 31A of the collective substrate 31. Implement using. The lid member 41 is arranged in three places so as to straddle the dicing line 35 of the collective substrate 31 and close the opening 44 on the bottom surface side with the wiring substrate 2. In the example of FIG. 25, three lid members 41 are arranged so as to surround one semiconductor element 3 along the dicing line 35. In addition, although the substantially square thing is used for the cover member 41 by planar view, the shape as shown in FIGS. 11-13 may be sufficient.

次に、半導体素子３及び受動部品４、並びに蓋部材４１を樹脂封止した後、集合基板３１をダイシングする。集合基板３１が切断されて複数の配線基板２に個片化されると同時に、蓋部材４１が切断される。蓋部材４１は、長手方向の中心線とダイシングライン３５の中心線が一致するように配置され、中心線を挟んで左右対称な形状を有することから、２つの同じ形状の部材に切断される。そして、これら切断された部材のそれぞれが、掛け止め部材５になる。   Next, after the semiconductor element 3, the passive component 4, and the lid member 41 are sealed with resin, the collective substrate 31 is diced. The collective substrate 31 is cut and separated into a plurality of wiring boards 2, and at the same time, the lid member 41 is cut. The lid member 41 is arranged so that the center line in the longitudinal direction coincides with the center line of the dicing line 35 and has a symmetrical shape with respect to the center line, so that it is cut into two members having the same shape. Then, each of these cut members becomes the latch member 5.

金属シールド１０２は、側部１０２Ｂが形成されずに開放されている側部から樹脂６に向ってスライドさせ、掛け止め部材５に係合させられる。スライド方向に平行に配置された１組の爪７Ｃは、広げられ、樹脂６を乗り越えて移動し、樹脂６の側部６Ｃに開口している掛け止め部材５に係合する。これにより、半導体素子３等を実装した配線基板２に金属シールド１０２が取り付けられ、半導体装置１０１の製造が完了する。   The metal shield 102 is slid toward the resin 6 from the open side portion without forming the side portion 102 </ b> B and is engaged with the latching member 5. The pair of claws 7C arranged in parallel to the sliding direction is spread, moves over the resin 6, and engages with the latching member 5 opened on the side portion 6C of the resin 6. Thereby, the metal shield 102 is attached to the wiring board 2 on which the semiconductor element 3 and the like are mounted, and the manufacture of the semiconductor device 101 is completed.

この実施の形態では、掛け止め部材５を配線基板２の３箇所に配置したので、金属シールド１０２を側方からスライドさせて係合させることができる。その他の効果は、第１の実施の形態と同様である。   In this embodiment, since the latching members 5 are arranged at three places on the wiring board 2, the metal shield 102 can be slid from the side to be engaged. Other effects are the same as those of the first embodiment.

なお、掛け止め部材５は、配線基板２に２つのみ配置しても良い。この場合、配線基板２上の半導体素子３を挟むように、掛け止め部材５を１つずつ配置すると、バランス良く金属シールド１０２を支持できる。
また、この半導体装置１０１では、図１１（ａ）、図１２（ａ）、図１３（ａ）に示す蓋部材５１，６１，７１を用いることが可能である。また、この実施の形態は、半導体素子３や受動部品４を樹脂で封止しないタイプにも適用できる。 Note that only two latch members 5 may be arranged on the wiring board 2. In this case, if the latching members 5 are arranged one by one so as to sandwich the semiconductor element 3 on the wiring board 2, the metal shield 102 can be supported with a good balance.
In the semiconductor device 101, the lid members 51, 61, 71 shown in FIGS. 11A, 12A, and 13A can be used. This embodiment can also be applied to a type in which the semiconductor element 3 and the passive component 4 are not sealed with resin.

（第５の実施の形態）
図２６及び図２７を参照して、第５の実施の形態について説明する。この実施の形態に
係る半導体装置は、掛け止め部材の配置が第１の実施の形態と異なる。なお、図２６は、半導体装置の分解斜視図であり、図２７は、集合基板を上方からみた平面図である。
図２６の分解斜視図に示すように、半導体装置１１１は、配線基板２の外周部に掛け止め部材１１２が設けられている。掛け止め部材１１２は、配線基板２の対向する２つの辺の全長にわたって１つずつ配置されており、配線基板２の接地端子１３に電気的に接続された背面壁部１１３Ａから上壁部１１３Ｂが伸びている。そして、背面壁部１１３Ａの内面が配線基板２の外側に向けて配置されることで、上壁部１１３Ｂが背面壁部１１３Ａから配線基板２の外側に向けて突出し、かつ配線基板２と平行に配置される。 (Fifth embodiment)
With reference to FIGS. 26 and 27, a fifth embodiment will be described. The semiconductor device according to this embodiment is different from the first embodiment in the arrangement of the latching members. FIG. 26 is an exploded perspective view of the semiconductor device, and FIG. 27 is a plan view of the collective substrate as viewed from above.
As shown in the exploded perspective view of FIG. 26, the semiconductor device 111 is provided with a latch member 112 on the outer peripheral portion of the wiring board 2. The latching members 112 are arranged one by one over the entire length of the two opposing sides of the wiring board 2, and the back wall 113 </ b> A to the upper wall 113 </ b> B electrically connected to the ground terminal 13 of the wiring board 2 are arranged. It is growing. The inner surface of the back wall 113A is arranged toward the outside of the wiring board 2 so that the upper wall 113B protrudes from the back wall 113A toward the outside of the wiring board 2 and is parallel to the wiring board 2. Be placed.

この掛け止め部材１１２に係合させられる金属シールド１１４は、天井部１１４Ａから２つの側部１１４Ｂが対向して下向きに延び、２つの側部１１４Ｂのそれぞれの先端に爪７Ｃが形成されている。２つの側部１１４Ｂは、配線基板２側の２つの掛け止め部材１１２の配置に対応した位置に１つずつ設けられている。   The metal shield 114 engaged with the latching member 112 extends downward from the ceiling portion 114A so that the two side portions 114B face each other, and a claw 7C is formed at the tip of each of the two side portions 114B. The two side portions 114B are provided one by one at positions corresponding to the arrangement of the two latching members 112 on the wiring board 2 side.

図２７に示すように、半導体装置１１１を製造するときは、最初に集合基板３１の配線基板形成領域３１Ａに、半導体素子３と、受動部品４と、蓋部材１２１とを、ハンダ１２Ａ，１２Ｂを用いて実装する。蓋部材１２１は、図６に示す蓋部材４１と長さが異なるだけで、同じ構成及び同じ材料から製造される。蓋部材１２１は、集合基板３１のダイシングライン３５を跨ぐように、かつ蓋部材１２１の底面側の開口部を配線基板２で塞ぐように複数配置される。なお、蓋部材１２１は、平面視で長方形のものが用いられているが、その他の形状であっても良い。   As shown in FIG. 27, when manufacturing the semiconductor device 111, first, the semiconductor element 3, the passive component 4, the lid member 121, and the solders 12A and 12B are placed in the wiring board forming region 31A of the collective substrate 31. Use to implement. The lid member 121 is manufactured from the same configuration and the same material, except that the length is different from the lid member 41 shown in FIG. A plurality of lid members 121 are arranged so as to straddle the dicing line 35 of the collective substrate 31 and to close the opening on the bottom surface side of the lid member 121 with the wiring board 2. The lid member 121 has a rectangular shape in plan view, but may have other shapes.

次に、半導体素子３及び受動部品４、並びに蓋部材１２１を樹脂封止した後、集合基板３１をダイシングする。集合基板３１が複数の配線基板２に個片化されると同時に、蓋部材１２１が切断される。蓋部材１２は、長手方向の中心線とダイシングライン３５の中心線が一致するように配置され、中心線を挟んで左右対称な形状を有することから、２つの同じ形状の部材に切断される。そして、これら切断された部材のそれぞれが、掛け止め部材１１２になる。
掛け止め部材１１２は、配線基板２の辺に平行に、かつその全長にわたって延びる。さらに、掛け止め部材１１２の端面１１２Ｃと、配線基板２の側面２Ｃ及び樹脂６の側面６Ｃとが面一になる。 Next, after the semiconductor element 3, the passive component 4, and the lid member 121 are sealed with resin, the collective substrate 31 is diced. At the same time that the collective substrate 31 is separated into a plurality of wiring substrates 2, the lid member 121 is cut. The lid member 12 is arranged so that the center line in the longitudinal direction coincides with the center line of the dicing line 35 and has a symmetrical shape with respect to the center line, so that it is cut into two members having the same shape. Each of these cut members becomes a latching member 112.
The latch member 112 extends in parallel to the side of the wiring board 2 and over its entire length. Furthermore, the end surface 112C of the latch member 112 is flush with the side surface 2C of the wiring board 2 and the side surface 6C of the resin 6.

金属シールド１１４は、側部１１４Ｂが形成されずに開放されている面から樹脂６に向けてスライドさせる。スライド方向に平行に配置された１組の爪７Ｃが、樹脂６の側部６Ｃに開口している掛け止め部材１１２に係合させられる。これにより、半導体素子３等を実装した配線基板２に金属シールド１１４が取り付けられ、半導体装置１１１の製造が完了する。   The metal shield 114 is slid toward the resin 6 from the open surface without the side portion 114B being formed. A pair of claws 7 </ b> C arranged in parallel with the sliding direction is engaged with the latching member 112 that opens to the side portion 6 </ b> C of the resin 6. Thereby, the metal shield 114 is attached to the wiring board 2 on which the semiconductor element 3 and the like are mounted, and the manufacture of the semiconductor device 111 is completed.

この実施の形態では、掛け止め部材１１２を配線基板２の２箇所に配置したので、金属シールド１１４を側方からスライドさせて係合させることができる。その他の効果は、第１の実施の形態と同様である。   In this embodiment, since the latching members 112 are disposed at two locations on the wiring board 2, the metal shield 114 can be slid from the side to be engaged. Other effects are the same as those of the first embodiment.

なお、掛け止め部材１１２は、配線基板２の角のみに設けても良い。この場合に、掛け止め部材１１２の数は、２つ以上であることが好ましい。
また、この半導体装置１１１では、図１１（ａ）、図１２（ａ）、図１３（ａ）に示す蓋部材５１，６１，７１を用いることが可能である。また、この実施の形態は、半導体素子３や受動部品４を樹脂で封止しないタイプにも適用できる。 The latch member 112 may be provided only at the corner of the wiring board 2. In this case, the number of the latch members 112 is preferably two or more.
In the semiconductor device 111, the lid members 51, 61, 71 shown in FIGS. 11A, 12A, and 13A can be used. This embodiment can also be applied to a type in which the semiconductor element 3 and the passive component 4 are not sealed with resin.

ここで挙げた全ての例および条件的表現は、発明者が技術促進に貢献した発明および概念を読者が理解するのを助けるためのものであり、ここで具体的に挙げたそのような例お
よび条件に限定することなく解釈するものであり、また、明細書におけるそのような例の編成は本発明の優劣を示すこととは関係ない。本発明の実施の形態を詳細に説明したが、本発明の精神および範囲から逸脱することなく、それに対して種々の変更、置換および変形を施すことができる。 All examples and conditional expressions given here are intended to help the reader understand the inventions and concepts that have contributed to the promotion of technology, such examples and It is to be construed without being limited to the conditions, and the organization of such examples in the specification is not related to showing the superiority or inferiority of the invention. Although the embodiments of the present invention have been described in detail, various changes, substitutions and modifications can be made thereto without departing from the spirit and scope of the present invention.

以下に、実施の形態をさらに付記する。
（付記１） 配線基板と、前記配線基板の一方の面の上に実装された半導体素子と、前記半導体素子を覆う金属シールドと、前記配線基板の前記一方の面に形成された接地端子と、前記接地端子に電気的に接続されると共に、前記一方の面の上で前記金属シールドに係合する掛け止め部材と、を含む半導体装置。
（付記２） 前記金属シールドは、内側、外側のいずれかに折り曲げられた爪を有し、
前記掛け止め部材は、前記爪に係合する壁部を有する付記１に記載の半導体装置。
（付記３） 前記掛け止め部材は、前記爪を挿入する空間を有する付記２に記載の半導体装置。
（付記４） 前記掛け止め部材の側面と、前記配線基板の側面とが面一である付記１から付記３のいずれか一項に記載の半導体装置。
（付記５） 前記半導体素子を覆う樹脂を有し、前記樹脂の側面と、前記掛け止め部材の側面とが面一である付記４に記載の半導体装置。
（付記６） 前記掛け止め部材は、四角形の前記配線基板の辺又は角の対向位置に配置されている付記１乃至付記５のいずれか一項に記載の半導体装置。
（付記７） 前記掛け止め部材は、矩形の前記配線基板の辺の略中央、又は角に、前記半導体素子を挟むように少なくとも２つ配置されている付記１乃至付記５のいずれか一項に記載の半導体装置。
（付記８） 配線基板を複数隣接して形成する領域を有する集合基板に半導体素子を実装する工程と、前記集合基板上で隣り合う前記配線基板の領域の境界線上に、凹部又は空隙を有する蓋部材を固定する工程と、前記境界線に沿って前記集合基板及び前記蓋部材を切断し、前記集合基板から前記配線基板を形成すると同時に、前記蓋部材から前記半導体素子を覆う金属シールドを係合させる凹形状を有する掛け止め部材を形成する工程と、前記掛け止め部材に前記金属シールドを係合させる工程と、を含む半導体装置の製造方法。
（付記９） 前記凹部を有する前記蓋部材は、前記凹部が前記集合基板で密閉される向きに固定される付記８に記載の半導体装置の製造方法。
（付記１０） 前記蓋部材を切断して前記掛け止め部材を形成する工程は、前記配線基板の側面と前記掛け止め部材の側面を面一にすることを含む付記８又は付記９に記載の半導体装置の製造方法。 The embodiment will be further described below.
(Appendix 1) A wiring board, a semiconductor element mounted on one surface of the wiring board, a metal shield covering the semiconductor element, a ground terminal formed on the one surface of the wiring board, And a latch member electrically connected to the ground terminal and engaged with the metal shield on the one surface.
(Supplementary Note 2) The metal shield has a claw bent to either the inner side or the outer side,
The semiconductor device according to appendix 1, wherein the latching member has a wall portion that engages with the claw.
(Additional remark 3) The said latching member is a semiconductor device of Additional remark 2 which has the space which inserts the said nail | claw.
(Supplementary note 4) The semiconductor device according to any one of supplementary notes 1 to 3, wherein a side surface of the latching member and a side surface of the wiring board are flush with each other.
(Additional remark 5) The semiconductor device of Additional remark 4 which has resin which covers the said semiconductor element, and the side surface of the said resin and the side surface of the said latching member are flush.
(Additional remark 6) The said latching member is a semiconductor device as described in any one of additional remark 1 thru | or additional remark 5 arrange | positioned in the opposing position of the edge | side or corner | angular of the said square wiring board.
(Additional remark 7) At least two said latching members are arrange | positioned so that the said semiconductor element may be pinched | interposed into the approximate center of the edge | side of the said rectangular said wiring board, or an addition to any one of Additional remark 5. The semiconductor device described.
(Supplementary Note 8) A step of mounting a semiconductor element on a collective substrate having a region in which a plurality of wiring boards are formed adjacent to each other, and a lid having a recess or a gap on a boundary line between adjacent wiring substrate regions on the collective substrate A step of fixing the member, and cutting the collective substrate and the lid member along the boundary line to form the wiring substrate from the collective substrate, and simultaneously engaging a metal shield covering the semiconductor element from the lid member A method of manufacturing a semiconductor device, comprising: forming a latching member having a concave shape to be engaged; and engaging the metal shield with the latching member.
(Additional remark 9) The said cover member which has the said recessed part is a manufacturing method of the semiconductor device of Additional remark 8 fixed to the direction in which the said recessed part is sealed with the said aggregate substrate.
(Supplementary note 10) The semiconductor according to supplementary note 8 or supplementary note 9, wherein the step of cutting the lid member to form the latching member includes making a side surface of the wiring board flush with a side surface of the latching member. Device manufacturing method.

１，８１，９１，１０１，１１１ 半導体装置
２ 配線基板
２Ａ 一方の面
２Ｃ 側面
３ 半導体素子
５，５２，６２，７３，９２，１１２ 掛け止め部材
５Ｄ，５２Ｃ，６２Ｃ，７３Ｃ，９２Ｃ，１１２Ｃ 端面
６ 樹脂
６Ｃ 側面
７，８５，９４，１１４ 金属シールド
７Ｃ 爪
２３，７７，９４，１１３Ｂ 上壁部
３５ ダイシングライン（境界線）
４１，５１，６１，７１，１２１ 蓋部材
４４，５１Ａ，６１Ａ 開口部
５５ 空間
６３ 壁部
７２ 空間（空隙） 1, 81, 91, 101, 111 Semiconductor device 2 Wiring board 2A One surface 2C Side surface 3 Semiconductor element 5, 52, 62, 73, 92, 112 Latching member 5D, 52C, 62C, 73C, 92C, 112C End surface 6 Resin 6C Side 7, 85, 94, 114 Metal shield 7C Claw 23, 77, 94, 113B Upper wall 35 Dicing line (boundary line)
41, 51, 61, 71, 121 Lid member 44, 51A, 61A Opening 55 Space 63 Wall 72 Space (gap)

Claims (5)

配線基板と、
前記配線基板の一方の面の上に実装された半導体素子と、
前記半導体素子を覆う金属シールドと、
前記配線基板の前記一方の面に形成された接地端子と、
前記接地端子に電気的に接続されると共に、前記一方の面の上で前記金属シールドに係合する掛け止め部材と、
を含む半導体装置。 A wiring board;
A semiconductor element mounted on one surface of the wiring board;
A metal shield covering the semiconductor element;
A ground terminal formed on the one surface of the wiring board;
A latch member that is electrically connected to the ground terminal and engages the metal shield on the one surface;
A semiconductor device including: 前記金属シールドは、内側、外側のいずれかに折り曲げられた爪を有し、
前記掛け止め部材は、前記爪に係合する壁部を有する
請求項１に記載の半導体装置。 The metal shield has a claw bent to either the inside or the outside,
The semiconductor device according to claim 1, wherein the latching member has a wall portion that engages with the claw. 前記掛け止め部材は、前記爪を挿入する空間を有する請求項２に記載の半導体装置。   The semiconductor device according to claim 2, wherein the latch member has a space for inserting the claw. 前記掛け止め部材は、四角形の前記配線基板の辺又は角の対向位置に配置されている請求項１乃至請求項３のいずれか一項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the latching member is disposed at a position opposite to a side or a corner of the rectangular wiring board. 5. 配線基板を複数隣接して形成する領域を有する集合基板に半導体素子を実装する工程と、
前記集合基板上で隣り合う前記配線基板の領域の境界線上に、凹部又は空隙を有する蓋部材を固定する工程と、
前記境界線に沿って前記集合基板及び前記蓋部材を切断し、前記集合基板から前記配線基板を形成すると同時に、前記蓋部材から前記半導体素子を覆う金属シールドを係合させる凹形状を有する掛け止め部材を形成する工程と、
前記掛け止め部材に前記金属シールドを係合させる工程と、
を含む半導体装置の製造方法。 Mounting a semiconductor element on a collective substrate having a region where a plurality of wiring boards are formed adjacent to each other;
Fixing a lid member having a recess or a gap on a boundary line between adjacent wiring board regions on the assembly board;
A latch having a concave shape that cuts the collective substrate and the lid member along the boundary line to form the wiring substrate from the collective substrate and simultaneously engages a metal shield that covers the semiconductor element from the lid member. Forming a member;
Engaging the metal shield with the latch member;
A method of manufacturing a semiconductor device including:
JP2010064044A 2010-03-19 2010-03-19 Semiconductor device and method of manufacturing the same Pending JP2011198999A (en)

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KR20160002675U (en) * 2016-06-21 2016-08-01 주식회사 케이엠더블유 Switching mode power supply
WO2017212965A1 (en) * 2016-06-08 2017-12-14 三菱電機株式会社 Semiconductor device, and method for manufacturing same
WO2018211915A1 (en) * 2017-05-19 2018-11-22 株式会社村田製作所 Electronic device and communication device
JPWO2018198856A1 (en) * 2017-04-28 2019-12-12 株式会社村田製作所 Circuit module and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017212965A1 (en) * 2016-06-08 2017-12-14 三菱電機株式会社 Semiconductor device, and method for manufacturing same
JPWO2017212965A1 (en) * 2016-06-08 2019-02-21 三菱電機株式会社 Semiconductor device and manufacturing method thereof
KR20160002675U (en) * 2016-06-21 2016-08-01 주식회사 케이엠더블유 Switching mode power supply
KR200483570Y1 (en) 2016-06-21 2017-05-30 주식회사 케이엠더블유 Switching mode power supply
JPWO2018198856A1 (en) * 2017-04-28 2019-12-12 株式会社村田製作所 Circuit module and manufacturing method thereof
WO2018211915A1 (en) * 2017-05-19 2018-11-22 株式会社村田製作所 Electronic device and communication device

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