JP2011198896A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2011198896A
JP2011198896A JP2010062201A JP2010062201A JP2011198896A JP 2011198896 A JP2011198896 A JP 2011198896A JP 2010062201 A JP2010062201 A JP 2010062201A JP 2010062201 A JP2010062201 A JP 2010062201A JP 2011198896 A JP2011198896 A JP 2011198896A
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sputtering
silicon substrate
sputtering step
semiconductor device
thin film
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JP5569068B2 (en
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Ayumi Onoyama
歩 小野山
Tamio Matsumura
民雄 松村
Yuichiro Suzuki
裕一郎 鈴木
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of uniformizing the reflection factor of a metallic thin-film in a surface when no abnormal conditions are present in a sputtering without damaging the throughput of a sputtering device.SOLUTION: A method of manufacturing the semiconductor device includes: a first sputtering step forming a metal film on a silicon substrate by a sputtering growth; and a second sputtering step further growing the metal film by the sputtering by a DC power higher than the first sputtering step after the first sputtering step. The method of manufacturing the semiconductor device further includes an inspection step measuring the uniformity of the reflection factor of the metal film formed by the first sputtering step and the second sputtering step after the first sputtering step and the second sputtering step.

Description

本発明は、スパッタにより金属薄膜を成膜した後に当該金属薄膜の反射率を測定する検査工程を行なう半導体装置の製造方法に関する。   The present invention relates to a method for manufacturing a semiconductor device in which an inspection process is performed in which a reflectance of a metal thin film is measured after the metal thin film is formed by sputtering.

高耐圧用途で広く用いられているＩＧＢＴはシリコン基板の表面にｐ型のチャネル領域、ｎ型のエミッタ領域、エミッタ電極が形成される。シリコン基板の裏面にはｐ型コレクタ層とコレクタ電極が形成される。ｐ型コレクタ層はシリコン基板の裏面にイオンを注入することで形成される。コレクタ電極は、たとえばアルミニウム、アルミニウム合金、モリブデン、チタン、バナジウム、ニッケル、白金、金、銀の中から選択された複数の金属薄膜からなる積層構造を有している。ＩＧＢＴでは、ｐ型コレクタ層と接する金属薄膜にアルミニウムやアルミニウム合金が用いられる。アルミニウムやアルミニウム合金を用いることで、チタンなどと比較して、ｐ型コレクタ層（ｐ型半導体層）に対するバリアハイトを低減できる。そのため飽和電圧を低減できて好適である。   An IGBT widely used for high breakdown voltage applications has a p-type channel region, an n-type emitter region, and an emitter electrode formed on the surface of a silicon substrate. A p-type collector layer and a collector electrode are formed on the back surface of the silicon substrate. The p-type collector layer is formed by implanting ions into the back surface of the silicon substrate. The collector electrode has a laminated structure composed of a plurality of metal thin films selected from, for example, aluminum, aluminum alloy, molybdenum, titanium, vanadium, nickel, platinum, gold, and silver. In the IGBT, aluminum or an aluminum alloy is used for the metal thin film in contact with the p-type collector layer. By using aluminum or an aluminum alloy, the barrier height with respect to the p-type collector layer (p-type semiconductor layer) can be reduced as compared with titanium or the like. Therefore, the saturation voltage can be reduced, which is preferable.

特許文献１には金属薄膜の平坦性を向上させるために薄膜のグレインサイズを制御する方法などが開示されている。   Patent Document 1 discloses a method for controlling the grain size of the thin film in order to improve the flatness of the metal thin film.

特開２００２−３３４８７５号公報JP 2002-334875 A 特開昭６３−２９６２１６号公報JP-A 63-296216 特開平０３−１８８６２５号公報Japanese Patent Laid-Open No. 03-188625 特開平０５−２７５３６９号公報JP 05-275369 A 特開平０６−１５１８１５号公報Japanese Patent Laid-Open No. 06-151815

シリコン基板と接する金属薄膜には主に以下の三つの特性が要求される。第１にシリコン基板との接触抵抗が低いことである。第２にスパッタ装置の処理能力向上のために高い成膜レートで形成できることである。第３に薄膜反射率の測定値に基づいて金属薄膜の均一性が検査できることである。第３の要求は、スパッタ時の異常放電などに起因する金属薄膜の膜厚均一性低下を検出するために必要となる。すなわち、スパッタに異常がないときはシリコン基板の面内で金属薄膜の反射率が一定であることが要求される。   The following three characteristics are mainly required for the metal thin film in contact with the silicon substrate. First, the contact resistance with the silicon substrate is low. Secondly, it can be formed at a high film formation rate in order to improve the throughput of the sputtering apparatus. Thirdly, the uniformity of the metal thin film can be inspected based on the measured value of the thin film reflectance. The third requirement is necessary to detect a decrease in film thickness uniformity of the metal thin film caused by abnormal discharge during sputtering. That is, when there is no abnormality in sputtering, the reflectance of the metal thin film is required to be constant within the surface of the silicon substrate.

第１の要求は適切な金属薄膜材料の選択により満たすことができる。シリコン基板の表面がｐ型層であるときは金属薄膜としてアルミニウムもしくはアルミニウム合金を用いればよい。第２の要求はスパッタ装置のＤＣパワーを高くすることで満たすことができる。ところが、スパッタ装置のＤＣパワーを高くしてアルミニウムなどをスパッタすると、成膜前のシリコン基板の面荒れや化学的終端の面内ばらつきなどが成膜後の金属薄膜表面の反射率分布に顕著に反映される。つまり実際はスパッタに異常がないにもかかわらず、シリコン基板の面内における当該反射率のばらつきが大きくなり第３の要求を満たせない問題があった。よって金属薄膜の均一性を適切に検査することができなくなる問題があった。   The first requirement can be met by selection of a suitable metal thin film material. When the surface of the silicon substrate is a p-type layer, aluminum or an aluminum alloy may be used as the metal thin film. The second requirement can be met by increasing the DC power of the sputtering apparatus. However, when aluminum or the like is sputtered by increasing the DC power of the sputtering apparatus, surface roughness of the silicon substrate before film formation, in-plane variation of chemical termination, etc. are conspicuous in the reflectance distribution on the surface of the metal thin film after film formation. Reflected. In other words, in spite of the fact that there is no abnormality in sputtering, there is a problem that the variation of the reflectance in the surface of the silicon substrate becomes large and the third requirement cannot be satisfied. Therefore, there is a problem that the uniformity of the metal thin film cannot be properly inspected.

そうすると、金属薄膜の均一性を検査する工程が機能せず、その後の工程で不良率が高まることが懸念される問題があった。   If it does so, the process which test | inspects the uniformity of a metal thin film did not function, but there existed a problem which was anxious about a defect rate increasing in a subsequent process.

本発明は、上述のような課題を解決するためになされたもので、スパッタ装置の処理能力を損なうことなく、スパッタに異常がないときは金属薄膜の反射率を面内で均一にすることができる半導体装置の製造方法を提供することを目的とする。   The present invention has been made in order to solve the above-described problems, and it is possible to make the reflectance of the metal thin film uniform in the plane when there is no abnormality in sputtering without impairing the processing capability of the sputtering apparatus. An object of the present invention is to provide a method for manufacturing a semiconductor device.

本願の発明にかかる半導体装置の製造方法は、シリコン基板にスパッタ成長により金属膜を形成する第１スパッタ工程と、該第１スパッタ工程の後に該第１スパッタ工程よりも高いＤＣパワーでさらに金属膜をスパッタ成長させる第２スパッタ工程と、該第１スパッタ工程と該第２スパッタ工程の後に、該第１スパッタ工程および該第２スパッタ工程で形成された金属膜の反射率の均一性を測定する検査工程とを備えたことを特徴とする。   A method of manufacturing a semiconductor device according to the present invention includes a first sputtering step of forming a metal film on a silicon substrate by sputter growth, and a metal film that is higher in DC power than the first sputtering step after the first sputtering step. And measuring the uniformity of the reflectance of the metal film formed in the first sputtering step and the second sputtering step after the first sputtering step and the second sputtering step. And an inspection process.

本発明によれば、スパッタ装置の処理能力を損なうことなく、スパッタに異常がないときは金属薄膜の反射率を面内で均一にすることができる。   According to the present invention, the reflectance of the metal thin film can be made uniform in the surface when there is no abnormality in sputtering without impairing the processing capability of the sputtering apparatus.

本発明の実施の形態の半導体装置の製造方法を説明するフローチャートである。3 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. シリコン基板の裏面を説明する図である。It is a figure explaining the back surface of a silicon substrate. 初期の第１スパッタ工程を説明する図である。It is a figure explaining an initial 1st sputtering process. 第１スパッタ工程により形成された第１金属薄膜について説明する図である。It is a figure explaining the 1st metal thin film formed by the 1st sputtering process. 第２スパッタ工程により形成された第２金属薄膜について説明する図である。It is a figure explaining the 2nd metal thin film formed by the 2nd sputtering process. 実施の形態の半導体装置による反射率のばらつき低減効果を説明する図である。It is a figure explaining the dispersion | variation reduction effect of the reflectance by the semiconductor device of embodiment. 変形例を説明する図である。It is a figure explaining a modification.

実施の形態
本実施の形態は図１ないし図７を参照して説明する。なお、同一又は対応する構成要素には同一の符号を付して複数回の説明を省略する場合がある。 Embodiment This embodiment will be described with reference to FIGS. In addition, the same code | symbol may be attached | subjected to the same or corresponding component, and description of multiple times may be abbreviate | omitted.

図１は本実施の形態の半導体装置の製造方法を説明するフローチャートである。本実施の形態の半導体装置はＩＧＢＴである。このＩＧＢＴはｎ型シリコン基板の表面にｐ型のチャネル領域、ｎ型のエミッタ領域、エミッタ電極を備えている。裏面（表面と逆の面）にはシリコン基板に形成されたｐ型コレクタ層とコレクタ電極が形成されている。   FIG. 1 is a flowchart for explaining a method of manufacturing a semiconductor device according to the present embodiment. The semiconductor device of the present embodiment is an IGBT. This IGBT includes a p-type channel region, an n-type emitter region, and an emitter electrode on the surface of an n-type silicon substrate. A p-type collector layer and a collector electrode formed on the silicon substrate are formed on the back surface (the surface opposite to the front surface).

以後図１に沿って本実施の形態の半導体装置の製造方法を説明する。まず、ステップ５０において、前述した表面の構造が形成されたシリコン基板の裏面にｐ型コレクタ層が形成される。その結果得られる構造を図２に示す。すなわち、シリコン基板１０の裏面にｐ型コレクタ層１２が形成された状態を示している。   Hereinafter, the manufacturing method of the semiconductor device of the present embodiment will be described with reference to FIG. First, in step 50, a p-type collector layer is formed on the back surface of the silicon substrate on which the above-described surface structure is formed. The resulting structure is shown in FIG. That is, the p-type collector layer 12 is formed on the back surface of the silicon substrate 10.

ステップ５０を終えるとステップ５２へと処理が進められる。ステップ５２ではコレクタ電極をスパッタする前に、シリコン基板の裏面に前処理が施される。ステップ５２では以下の３種類の中の前処理から適当な前処理が選択される。第１の前処理はシリコン基板裏面に、加工を加えずに希フッ酸などの処理を施すものである。第２の前処理はシリコン基板裏面に、研削加工後に希フッ酸などの処理を施すものである。第３の処理はシリコン基板裏面をＣＭＰ処理やウェットエッチングなどでミラー面に加工した後、その面に希フッ酸などの処理を施すものである。   When step 50 is completed, the process proceeds to step 52. In step 52, before the collector electrode is sputtered, the back surface of the silicon substrate is pretreated. In step 52, an appropriate preprocessing is selected from the following three types of preprocessing. In the first pretreatment, the back surface of the silicon substrate is subjected to a treatment such as dilute hydrofluoric acid without any processing. In the second pretreatment, the back surface of the silicon substrate is subjected to a treatment such as dilute hydrofluoric acid after grinding. In the third process, the rear surface of the silicon substrate is processed into a mirror surface by CMP or wet etching, and then the surface is subjected to a treatment such as dilute hydrofluoric acid.

ステップ５２を終えるとステップ５４へと処理が進められる。ステップ５４は第１スパッタ工程である。コレクタ電極の成膜はこの第１スパッタ工程と後述の第２スパッタ工程により行われる。本実施の形態ではコレクタ電極としてアルミニウムを１μｍ成膜する。第１スパッタ工程ではこのうち２０ｎｍのアルミニウムがｐ型コレクタ層１２に成膜される。また、第１スパッタ工程ではスパッタのＤＣパワーは２ｋＷである。第１スパッタ工程の初期には図３に示すようにｐ型コレクタ層１２の表面に結晶核１４が形成される。第１スパッタ工程では、さらにスパッタが継続される。その結果、図４に示すようにシリコン基板１０を被覆するように第１金属薄膜１６が形成される。第１金属薄膜１６が形成された時点で、第１スパッタ工程が終了される。   When step 52 is completed, the process proceeds to step 54. Step 54 is a first sputtering process. The collector electrode is formed by the first sputtering process and the second sputtering process described later. In this embodiment, 1 μm of aluminum is deposited as the collector electrode. In the first sputtering step, 20 nm of aluminum is formed on the p-type collector layer 12. In the first sputtering step, the sputtering DC power is 2 kW. In the initial stage of the first sputtering step, crystal nuclei 14 are formed on the surface of the p-type collector layer 12 as shown in FIG. In the first sputtering process, sputtering is further continued. As a result, the first metal thin film 16 is formed so as to cover the silicon substrate 10 as shown in FIG. When the first metal thin film 16 is formed, the first sputtering process is finished.

ステップ５４を終えるとステップ５６へと処理が進められる。ステップ５６は第２スパッタ工程である。第２スパッタ工程では真空状態の下で９８０ｎｍのアルミニウムが第１金属薄膜１６上に形成される。また、第２スパッタ工程ではスパッタのＤＣパワーは４ｋＷにまで高められる。第２スパッタ工程では図５に示すように、第１金属薄膜１６上に多結晶の第２金属薄膜１８が形成される。第１金属薄膜１６と第２金属薄膜１８がコレクタ電極となる。   When step 54 is completed, the process proceeds to step 56. Step 56 is a second sputtering step. In the second sputtering step, 980 nm of aluminum is formed on the first metal thin film 16 under vacuum. In the second sputtering step, the DC power of sputtering is increased to 4 kW. In the second sputtering step, a polycrystalline second metal thin film 18 is formed on the first metal thin film 16 as shown in FIG. The first metal thin film 16 and the second metal thin film 18 serve as collector electrodes.

ステップ５６を終えるとステップ５８へと処理が進められる。ステップ５８は金属薄膜の膜厚均一性を検査する検査工程である。この検査工程では、第１スパッタ工程および第２スパッタ工程で形成された膜の反射率の面内分布が検査される。本実施の形態のＩＧＢＴの製造方法は上述のとおりである。   When step 56 is finished, the process proceeds to step 58. Step 58 is an inspection process for inspecting the film thickness uniformity of the metal thin film. In this inspection process, the in-plane distribution of the reflectance of the film formed in the first sputtering process and the second sputtering process is inspected. The manufacturing method of the IGBT of the present embodiment is as described above.

ステップ５２で行った前処理では、第１の処理から第３の処理までのいずれの場合であっても、前処理に起因してシリコン基板裏面で面荒れが生じることがある。また、シリコンの化学的な終端が同裏面の場所ごとに相違する場合もある。特に第３の処理を行った場合にはミラー面の領域が正常な面となる為、局所的に面荒れが発生する場合がある。なお、他の薬液処理などに起因して面荒れなどが発生することもある。   In the pretreatment performed in step 52, surface roughness may occur on the back surface of the silicon substrate due to the pretreatment in any case from the first treatment to the third treatment. Also, the chemical termination of silicon may be different for each location on the back side. In particular, when the third process is performed, the region of the mirror surface becomes a normal surface, and thus surface roughness may occur locally. Note that surface roughness may occur due to other chemical processing.

このようなシリコン基板の裏面に対して、成膜レートを高めるためにスパッタのＤＣパワーを高くして成膜を行うと、金属薄膜表面の反射率がばらつくことがある。つまり、コレクタ電極成膜前のシリコン基板の面荒れや化学的終端の面内ばらつきなどがコレクタ電極成膜後のコレクタ電極の反射率分布に顕著に反映される。面荒れなどが発生している領域は発生していない領域（ミラー面）よりも金属薄膜表面の反射率が大きくなる。面荒れなどにより反射率が高い領域は、密着性などの諸特性は他の領域と同等であるので検査工程でスクリーニングされる必要はない。それにもかかわらず、反射率の面内分布が大きいため、検査工程で不良と判断される問題があった。その結果、検査工程の本来の機能である膜厚均一性低下の検出が困難となる問題があった。   When film formation is performed on such a back surface of a silicon substrate by increasing the DC power of sputtering in order to increase the film formation rate, the reflectance of the metal thin film surface may vary. That is, surface roughness of the silicon substrate before the collector electrode film formation, in-plane variation of the chemical termination, etc. are remarkably reflected in the reflectance distribution of the collector electrode after the collector electrode film formation. The reflectance of the surface of the metal thin film is higher in the region where the surface roughness is generated than in the region where the surface is not generated (mirror surface). A region having a high reflectivity due to surface roughness or the like does not need to be screened in an inspection process because various characteristics such as adhesion are the same as those of other regions. Nevertheless, since the in-plane distribution of the reflectance is large, there is a problem that it is judged as defective in the inspection process. As a result, there is a problem that it is difficult to detect a decrease in film thickness uniformity, which is the original function of the inspection process.

本実施の形態の半導体装置の製造方法によれば、上述の問題を解消できる。本実施の形態ではコレクタ電極の形成を第１スパッタ工程と第２スパッタ工程に分割している。そして、第１スパッタ工程ではスパッタのＤＣパワーを低減している。よって第１スパッタ工程ではスパッタレートが低い。そのため、シリコン基板裏面における面荒れの分布や異なる化学的終端の分布が金属薄膜表面の反射率分布に反映されない。このように、面荒れや化学的終端の分布による悪影響をなくした上で、第２スパッタ工程でスパッタレートの高い成膜を行う。よって、スパッタ装置の処理能力を損なうことなく、金属薄膜の反射率を面内で均一にすることができる。故に検査工程の本来の機能であるコレクタ電極の膜厚均一性低下の検出が可能となる。   According to the semiconductor device manufacturing method of the present embodiment, the above-described problems can be solved. In the present embodiment, the formation of the collector electrode is divided into a first sputtering process and a second sputtering process. In the first sputtering step, the DC power of sputtering is reduced. Therefore, the sputtering rate is low in the first sputtering process. Therefore, the distribution of surface roughness on the back surface of the silicon substrate and the distribution of different chemical terminations are not reflected in the reflectance distribution on the surface of the metal thin film. In this way, film formation with a high sputter rate is performed in the second sputtering step after eliminating adverse effects due to surface roughness and chemical termination distribution. Therefore, the reflectance of the metal thin film can be made uniform in the surface without impairing the processing capability of the sputtering apparatus. Therefore, it is possible to detect a decrease in film thickness uniformity of the collector electrode, which is an original function of the inspection process.

本実施の形態の第１スパッタ工程および第２スパッタ工程で１μｍの厚さの成膜を行うのに要した時間は５１．５秒である。一方、常に高いＤＣパワー（４ｋＷ）でスパッタを行い１μｍの厚さの成膜を行う（この成膜方法を従来方法という）のに要する時間は５０秒であった。第１スパッタ工程は、シリコン基板１０を被覆する程度で終えるため要する時間が非常に短い。よって、実用上スパッタ装置の処理能力を損なうことはない。   The time required to form a film having a thickness of 1 μm in the first sputtering process and the second sputtering process of this embodiment is 51.5 seconds. On the other hand, it took 50 seconds to always perform sputtering at a high DC power (4 kW) to form a film having a thickness of 1 μm (this film forming method is called a conventional method). Since the first sputtering process is completed to the extent that the silicon substrate 10 is covered, the time required is very short. Therefore, practically, the processing capability of the sputtering apparatus is not impaired.

図６は本発明によりコレクタ電極の反射率の面内分布が均一化されたことを説明する図である。図６の左側には、従来方法でコレクタ電極が形成された３枚の基板の反射率面内分布が記載されている。一方、図６の右側には、本発明の方法によってコレクタ電極が形成された３枚の基板の反射率面内分布が記載される。この比較により、本発明の方法によれば、反射率の面内分布を効果的に抑制できることが分かる。   FIG. 6 is a diagram for explaining that the in-plane distribution of the reflectance of the collector electrode is made uniform according to the present invention. On the left side of FIG. 6, the reflectance in-plane distribution of three substrates on which collector electrodes are formed by a conventional method is described. On the other hand, on the right side of FIG. 6, the reflectance in-plane distribution of the three substrates on which the collector electrodes are formed by the method of the present invention is described. From this comparison, it can be seen that the in-plane distribution of reflectance can be effectively suppressed according to the method of the present invention.

本実施の形態の半導体装置の製造方法は最初に成膜レートの遅い成膜を行い、その後に成膜レートの早い成膜を行うことが特徴である。この特徴により反射率を面内で均一にすることができるため、金属薄膜の均一性を適切に検査することができる。本発明の特徴を失わない限りにおいて様々な変形が可能であるのでその一部を以下に説明する。   The manufacturing method of the semiconductor device of this embodiment is characterized in that film formation with a low film formation rate is first performed and then film formation with a high film formation rate is performed thereafter. Due to this feature, the reflectance can be made uniform in the surface, so that the uniformity of the metal thin film can be appropriately inspected. Since various modifications are possible as long as the characteristics of the present invention are not lost, some of them will be described below.

たとえば、本発明はＭＯＳＦＥＴやダイオードなどにも応用できる。ＭＯＳＦＥＴの場合はｎ型シリコン基板の表面にｐ型のチャネル領域、ｎ型のソース領域、ソース電極を形成する。そして裏面にはｎ型のドレイン層およびドレイン電極を形成する。図７はこの例を説明する図である。シリコン基板１００の裏面に形成されたｎ型ドレイン層１０２と接するようにドレイン電極１０８が形成される。ドレイン電極１０８は第１金属薄膜１０４と第２金属薄膜１０６を備える。ドレイン電極１０８として、たとえばチタンを第１スパッタ工程、第２スパッタ工程に分けてスパッタして本発明の効果を得ることができる。ダイオードの場合はｎ型シリコン基板の表面にｐ型アノード領域とアノード電極を形成する。そして裏面にはｎ型のカソードとカソード電極が形成される。カソード電極にはチタンなどが使用される。カソード電極についても同様に第１スパッタ工程、第２スパッタ工程を行えばよい。   For example, the present invention can also be applied to MOSFETs and diodes. In the case of a MOSFET, a p-type channel region, an n-type source region, and a source electrode are formed on the surface of an n-type silicon substrate. Then, an n-type drain layer and a drain electrode are formed on the back surface. FIG. 7 is a diagram for explaining this example. A drain electrode 108 is formed in contact with the n-type drain layer 102 formed on the back surface of the silicon substrate 100. The drain electrode 108 includes a first metal thin film 104 and a second metal thin film 106. As the drain electrode 108, for example, titanium can be sputtered separately in the first sputtering process and the second sputtering process, and the effects of the present invention can be obtained. In the case of a diode, a p-type anode region and an anode electrode are formed on the surface of an n-type silicon substrate. An n-type cathode and a cathode electrode are formed on the back surface. Titanium or the like is used for the cathode electrode. The cathode electrode may be similarly subjected to the first sputtering process and the second sputtering process.

ＭＯＳＦＥＴのドレイン電極もダイオードのカソード電極も、たとえば、ＤＣパワー１ｋＷで２０ｎｍを成膜し、その後ＤＣパワーを３ｋＷにして２８０ｎｍを成膜することにより形成される。この場合、成膜には３２秒を要する。そして、ＤＣパワーを３ｋＷに維持して３００ｎｍの成膜を行うのに要した時間は３０秒である。よって実用上スパッタ装置の処理能力を損なうことはない。   Both the drain electrode of the MOSFET and the cathode electrode of the diode are formed, for example, by depositing 20 nm with a DC power of 1 kW and then depositing 280 nm with a DC power of 3 kW. In this case, the film formation takes 32 seconds. And, the time required to perform the film formation of 300 nm while maintaining the DC power at 3 kW is 30 seconds. Therefore, practically, the processing capability of the sputtering apparatus is not impaired.

たとえば、ＩＧＢＴのコレクタ電極として、アルミニウムに代えてアルミニウムにシリコンあるいは銅を０．１％〜３％添加したアルミニウム合金を使用してもよい。その他、密着性やバリアハイトなどの諸特性を考慮してスパッタする材料を選択してもよい。   For example, an aluminum alloy obtained by adding 0.1% to 3% of silicon or copper to aluminum instead of aluminum may be used as the collector electrode of the IGBT. In addition, a material to be sputtered may be selected in consideration of various characteristics such as adhesion and barrier height.

１０ シリコン基板、 １２ ｐ型コレクタ層、 １６ 第１金属薄膜、 １８ 第２金属薄膜   10 silicon substrate, 12 p-type collector layer, 16 first metal thin film, 18 second metal thin film

Claims (4)

シリコン基板にスパッタ成長により金属膜を形成する第１スパッタ工程と、
前記第１スパッタ工程の後に前記第１スパッタ工程よりも高いＤＣパワーでさらに金属膜をスパッタ成長させる第２スパッタ工程と、
前記第１スパッタ工程と前記第２スパッタ工程の後に、前記第１スパッタ工程および前記第２スパッタ工程で形成された金属膜の反射率の均一性を測定する検査工程とを備えたことを特徴とする半導体装置の製造方法。 A first sputtering step of forming a metal film on the silicon substrate by sputtering growth;
A second sputtering step of sputter-growing a metal film with a higher DC power than the first sputtering step after the first sputtering step;
An inspection step for measuring the uniformity of the reflectance of the metal film formed in the first sputtering step and the second sputtering step is provided after the first sputtering step and the second sputtering step. A method for manufacturing a semiconductor device. 前記第１スパッタ工程はスパッタ成長により形成された金属膜が前記シリコン基板を被覆した時点で終了されることを特徴とする請求項１に記載の半導体装置の製造方法。   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first sputtering step is terminated when a metal film formed by sputtering growth covers the silicon substrate. 3. 前記シリコン基板の裏面にはｐ型の層が形成され、
前記第１スパッタ工程と前記第２スパッタ工程では前記シリコン基板の裏面に対してスパッタ成長のための処理が施され、
前記第１スパッタ工程と前記第２スパッタ工程ではアルミニウムまたはアルミニウム合金が形成されることを特徴とする請求項１または２のいずれかに記載の半導体装置の製造方法。 A p-type layer is formed on the back surface of the silicon substrate,
In the first sputtering step and the second sputtering step, a treatment for sputtering growth is performed on the back surface of the silicon substrate,
3. The method of manufacturing a semiconductor device according to claim 1, wherein aluminum or an aluminum alloy is formed in the first sputtering step and the second sputtering step. 4. 前記シリコン基板の裏面にはｎ型の層が形成され、
前記第１スパッタ工程と前記第２スパッタ工程では前記シリコン基板の裏面に対してスパッタ成長のための処理が施され、
前記第１スパッタ工程と前記第２スパッタ工程ではチタンが形成されることを特徴とする請求項１または２のいずれかに記載の半導体装置の製造方法。 An n-type layer is formed on the back surface of the silicon substrate,
In the first sputtering step and the second sputtering step, a treatment for sputtering growth is performed on the back surface of the silicon substrate,
The method for manufacturing a semiconductor device according to claim 1, wherein titanium is formed in the first sputtering step and the second sputtering step.
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