JP2011198219A - Data access control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten an access period in configuration of connecting accessed parts from an access control part through a serial bus.SOLUTION: The access control part 1 specifies sequence data and non-sequence data and specifies an access destination from the serial bus 3 to carry out data transmission. The accessed parts 5, 7 are connected in series to the serial bus 3 so that the non-sequence data and sequence data are accessed. Each of the accessed parts 5, 7 has first and second memory spaces 11, 13, an arbitration part 15 and an access space 17. The first memory space 11 is connected to the serial bus 3 and stores the non-sequence data. The second memory space 13 is connected to the serial bus 3 and stores the sequence data. The arbitration part 15 arbitrates the non-sequence data and sequence data. The access space 17 receives access of the non-sequence data and sequence data from the arbitration part 15.

Description

  The present invention relates to a data access control apparatus, for example, accessing a chip device such as a semiconductor memory component inserted and connected in series to a serial bus such as a PCI (peripheral component interconnect) Express bus through the serial bus. The present invention relates to an improvement in a data access control apparatus suitable for a configuration for transmitting data.

  As this type of data access control device, as shown in FIG. 3, for example, a plurality of memory units 5 and 7 are connected from an access control unit 1 such as a CPU (central processing unit) via a serial bus 3 and serially connected. The switch unit 9 is inserted in the middle of the bus 3, and the memory unit 5, 7 is selectively connected to the access control unit 1 by the switch unit 9 under the control of the access control unit 1. A configuration for selectively accessing and storing data is known.

  In addition, when the memory units 5 and 7 are registers or the like, so-called I / O is used to access the internal access space via the built-in I / O (input / output interface) space for sequence data that requires sequence processing as a transmission processing procedure. If the memory unit 5 or 7 is a DRAM (dynamic random-access memory) or the like while the O address system is adopted, non-sequence data that does not require sequence processing is accessed in the internal access space using the built-in memory space. The memory mapped I / O method is generally adopted.

  For example, there is a bus master device as disclosed in Japanese Patent Application Laid-Open No. 11-184809 (Patent Document 1).

JP-A-11-184809

  However, in the conventional configuration described above, the data to be stored by accessing the memory units 5 and 7 from the access control unit 1 via the serial bus 3 includes sequence data and non-sequence data as described above. In this case, since the I / O space is used to access the access space and the next write access is not issued until the write access is completed, the next access is waited for both sequence data and non-sequence data. Speed is difficult to improve.

  Therefore, as a result of careful observation and examination of the configurations of various accessed units connected from the access control unit 1 via the serial bus 3, the present inventor found that non-sequence data that does not require a sequence has no relation to the access order. There is no problem even if access overtaking occurs, and even setting data such as a register is not necessarily data that needs to be sequenced, and various types of accessed parts can occupy memory space and I / O space. The present invention has been completed by paying attention to the fact that it is possible to access the access space from any location.

  The present invention has been made to solve such a problem, and provides a data access control device that can easily shorten an access period in a configuration in which an access target unit is connected to the access control unit via a serial bus. With the goal.

  In order to solve such a problem, a data access control apparatus according to claim 1 of the present invention specifies a serial bus, an access destination, sequence data that requires a sequence process that is a predetermined transmission process procedure, and its non-existence. An access control unit that specially orders necessary non-sequence data and controls access via the serial bus, and the non-sequence data and sequence data that are serially inserted and connected to the serial bus are input and accessed. A first memory space for storing non-sequence data transmitted at one end connected to the access control unit side of the serial bus, and the first memory space. One end is connected to the serial bus access control side and stores the transmitted sequence data. A memory space, an arbitration unit that arbitrates and outputs outputs from the first and second memory spaces, and an access space that receives access to the non-sequence data and sequence data from the arbitration unit. Yes.

  The data access control device according to claim 2 of the present invention is configured such that the arbitration unit preferentially arbitrates and outputs non-sequence data from the first memory space.

  According to a third aspect of the present invention, in the data access control device, a plurality of accessed parts are connected in series to the serial bus, and the first and second memory spaces in the accessed part in the subsequent stage are the access space in the preceding stage. The non-sequence data or the sequence data is stored in an access space corresponding to the access destination.

  In such a data access control device according to claim 1 of the present invention, if the data transmitted by the serial bus by designating the access destination from the access control unit is non-sequence data, the access unit receives the first If the transmitted data is sequence data, it is stored in the second memory space, and the output from the first and second memory spaces is arbitrated by the arbitration unit to access the access space. Therefore, even if data is conventionally accessed to the internal access space via the I / O space, the access space can be accessed via the first memory space if it is non-sequence data. It is easy to shorten the access period.

  In the data access control device according to claim 2 of the present invention, since the arbitration unit preferentially arbitrates and outputs the non-sequence data from the first memory space, the overall access period can be further shortened. It is.

  In the data access control device according to claim 3 of the present invention, a plurality of accessed sections are connected in series to the serial bus, and the first and second memory spaces in the accessed section in the subsequent stage are access spaces in the preceding stage. Since the non-sequence data or sequence data is stored in the access space corresponding to the access destination, even in a configuration in which a plurality of accessed units are connected in series, The access period can be shortened easily, and transmission data can be stored and stored reliably.

It is a schematic block diagram which shows embodiment of the data access control apparatus which concerns on this invention. It is a schematic block diagram explaining the to-be-accessed part in this invention. It is a schematic block diagram explaining the conventional data access control apparatus.

  Embodiments of a data access control apparatus according to the present invention will be described below with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same part as a conventional structure.

  FIG. 1 is a schematic block diagram showing an embodiment of a data access control apparatus according to the present invention.

  In FIG. 1, a serial bus 3 extends from the access control unit 1, and memory units 5 and 7 as accessed units are inserted and connected in series in the middle of the serial bus 3.

  In FIG. 1, two memory units 5 and 7 are connected. However, in the present invention, a configuration in which a plurality of memory units 5 and 7 are arranged is possible, and the memory units 5 and 7 are functionally similar. Then, only the memory unit 5 will be described, and the description of the memory unit 7 will be omitted.

  The access control unit 1 includes a CPU, a memory storing a startup program for the CPU, and an input / output interface (none of which are shown), and the memory units 5 and 7 are accessed via the serial bus 3. In addition to the function of instructing the access destination to transmit data, it has the following functions.

  That is, when the memory units 5 and 7 are connected via the serial bus 3, the access control unit 1 accesses a memory space 11, an I / O space 13, an access space 17 and the like to be described later in the memory units 5 and 7. It has a function to acquire information and create a data table.

  Examples of the access information include the addresses and identification codes of the memory units 5 and 7 themselves, the identification codes of the memory space 11 and the I / O space 13 itself, the identification codes of the access space 17 itself, and address information in which data is stored.

  When the access control unit 1 accesses and transmits data to the target memory units 5 and 7, the access control unit 1 refers to the data table, and in addition to the address of the memory unit 5 and 7 itself that is the access destination, It has a function of attaching and specifying 17 identification codes and designated address information, and characterizing whether the data to be transmitted is sequence data that requires sequence processing or unnecessary non-sequence data.

  Note that the access control unit 1 characterizes and transmits the sequence data as unnecessary non-sequence data when it is data that does not require a sequence even if it is setting data such as a register.

  As shown in FIG. 2, the memory unit 5 includes a memory space 11, an I / O space 13, and an access space 17.

  The memory space 11 is, for example, a simple buffer, and has a function as a first memory space that is connected to the access control unit 1 side of the serial bus 3 at one end and receives non-sequence data that is transmitted and temporarily stores it. And connected to the arbitration unit 15. The memory space 11 is assigned with a part of a storage unit (to be described later) that forms the access space 17 of the memory unit 5 and a built-in register (not shown).

  Like the sequence data described above, the I / O space 13 does not issue or send the next write access until the write access in the predetermined order is completed in the process of storing or storing the data in the access destination, and all the data As a second memory space for temporarily storing data in the order of transmission, and having one end connected together with the memory space 11 on the access control unit 1 side of the serial bus 3 and connected to the arbitration unit 15 Has been. The I / O space 13 is assigned a built-in register (not shown) for control instructions and control data in the memory unit 5.

  The arbitration unit 15 has a function of arbitrating both outputs from the memory space 11 and the I / O space 13 and selectively outputting them to the access space 17. It has a function to preferentially adjust and output sequence data first.

  The access space 17 is a storage unit that receives access to non-sequence data or sequence data from the arbitration unit 15 and stores it in correspondence with the memory space 11 and the I / O space 13. The memory space 11 and the I / O space 13 are not connected via the serial bus 3.

  Therefore, the non-sequence data or sequence data input to the memory unit 5 is stored in the memory space 11 or the I / O space 13, and if the memory unit 5 is not an access destination, the non-sequence data in the memory space 11 is transferred from the arbitration unit 15. The sequence data or the sequence data is temporarily stored in the access space 17 and output to the memory unit 7 at the subsequent stage.

  If the memory unit 5 is an access destination, both sequence data output from the arbitration unit 15 are stored in the designated address of the access space 17.

  Next, the operation of the data access control device according to the present invention will be briefly described.

  When sequence data or non-sequence data is transmitted from the access control unit 1 by specifying an access destination including a storage destination address, the non-sequence data is transferred to the memory space 11 in the memory unit 5 closest to the access control unit 1. Is temporarily stored in the I / O space 13.

  The arbitration unit 15 preferentially adjusts any non-sequence data from the memory space 11 and outputs the non-sequence data to the access space 17, and there is no non-sequence data from the memory space 11 or non-sequence from the memory space 11. If there is sequence data from the I / O space 13 after the data is output, it is output to the access space 17.

  When the sequence data is stored in the I / O space 13 and is output from the arbitration unit 15 to the access space 17, the serial bus 3 is occupied until the final write access is completed, and the I / O by the arbitration unit 15 is An output from the O space 13 to the access space 17 is secured.

  If the access space 17 itself is the sequence data or non-sequence data access destination (target device), the sequence data or the non-sequence data is stored and stored in the corresponding address. 7 via the serial bus 3 to the memory space 11 and the I / O space 13 (not shown). Thereafter, operation processing similar to that of the memory unit 5 is performed in the subsequent memory unit 7. The same applies to the memory unit (not shown) thereafter.

  As described above, the data access control device according to the present invention characterizes the serial bus 3, the sequence data that specifies the access destination and the sequence processing that is a predetermined transmission processing procedure, and the unnecessary non-sequence data. An access control unit 1 that performs access control via the serial bus 3, and memory units (accessed units) 5 and 7 that are accessed by inputting the non-sequence data and sequence data that are serially connected to the serial bus 3 and transmitted. It is equipped with.

  In addition, the memory units 5 and 7 are connected at one end to the access control unit 1 side of the serial bus 3 and store the transmitted non-sequence data (first memory space) 11 and the first memory. An I / O space (second memory space) 13 for storing sequence data transmitted at one end together with the space 11 to the access control unit 1 side of the serial bus 3, and the memory space 11 and the I / O space 13 Is provided with an arbitration unit 15 that preferentially arbitrates and outputs non-sequence data from the memory space 11, and an access space 17 that receives access to the non-sequence data and sequence data from the arbitration unit 15.

  Therefore, if the transmission data is divided into non-sequence and sequence data and is transmitted from the access control unit 1, the individual memory units 5 and 7 can access the access space 17 from either the memory space 11 or the I / O space 13. Is accessible.

  Therefore, even if the data has conventionally been stored by accessing the internal access space 17 via the I / O space 13, the access space 17 can be accessed via the memory space 11 if it is non-sequence data. Since only the sequence data is accessed to the access space 17 via the I / O space 13, the latency is reduced and the overall access period can be easily shortened.

  However, the memory access control device of the present invention is not necessarily limited to the configuration in which the non-sequence data from the memory space 11 is preferentially arbitrated and output, for example, the memory space 11 or the I / O space 13 is output first. The basic object of the present invention can be achieved if the configuration is similar to the conventional one that mediates data.

  In addition, since the access space 17 can be accessed from either the memory space 11 or the I / O space 13, in addition to the access control unit 1, access from a master that is an access source for accessing the memory units 5 and 7 is performed. However, it is easy to access the access space 17 without any trouble, and in this respect, the overall access period can be shortened easily.

  Further, in a configuration in which a plurality of memory units 5, 7 are connected in series to the serial bus 3, the access space of the subsequent memory unit 7 that is the access destination via the previous memory unit 5 or the access target unit thereafter. Even when non-sequence data or sequence data is stored and saved, the overall access period can be easily shortened and transmission data can be stored and saved reliably.

  In the memory access control device according to the present invention described above, the memory units 5 and 7 have been described as examples of the accessed unit. However, the present invention is not limited to this, and the accessed unit may include data. The present invention can be implemented in various memories and peripheral devices that are built in or externally connected to the transmission destination device.

  The memory access control apparatus according to the present invention can be implemented in image forming apparatuses such as copying machines, facsimile machines, and multifunction machines, computers, and other various electronic devices.

1 Access control unit 3 Serial bus (PCI bus)
5, 7 Memory part (accessed part)
9 Switch unit 11 Memory space (first memory space)
13 I / O space (second memory space)
15 Mediation unit 17 Access space (storage unit)

Claims (3)

A serial bus,
An access control unit that specifies an access destination and characterizes sequence data required for sequence processing that is a predetermined transmission processing procedure and unnecessary non-sequence data, and performs access control via the serial bus;
The non-sequence data that is inserted and connected in series to the serial bus and transmitted, and the accessed part to which the sequence data is input and accessed;
Comprising
The accessed section has one end connected to the access control section side of the serial bus and stores the transmitted non-sequence data, and one end of the serial bus together with the first memory space. A second memory space that is connected to the access control unit and stores the transmitted sequence data; an arbitration unit that arbitrates and outputs outputs from the first and second memory spaces; and An access space for receiving the non-sequence data and the sequence data;
A data access control device comprising:   The data access control device according to claim 1, wherein the arbitration unit performs priority arbitration and outputs the non-sequence data from the first memory space.   A plurality of the accessed parts are connected in series to the serial bus, and the first and second memory spaces in the accessed part in the subsequent stage are connected to the access space in the preceding stage via the serial bus, The data access control device according to claim 1, wherein the non-sequence data or the sequence data is stored in the access space corresponding to an access destination.

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