JP2011196904A - Sensor voltage processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly adjust an offset voltage and a gain of a sensor voltage processing circuit.SOLUTION: The sensor voltage processing circuit 100 includes: an amplifier circuit 120 which outputs a voltage obtained by amplifying a sensor voltage based on the offset voltage, and adjusts the offset voltage and the gain; an extremal value storage circuit 160 for storing an extremal value of an output voltage of the amplifier circuit 120; a binarization circuit 200 for binarizing the output voltage of the amplifier circuit based on the extremal value stored in the extremal value storage circuit; and an adjusting circuit 400. During the initializing processing, the adjusting circuit 400, (1) sets the gain at a maximum value, (2) adjusts the offset voltage so that the output voltage of the amplifier circuit enters the intermediate zone of the operating voltage range of the amplifier circuit, (3) adapts the extremal value to a voltage within the intermediate zone, (4) reduces the gain and corrects the extremal value when a variation width from the extremal value of the output voltage of the amplifier circuit exceeds a given width, and (5) repeats the processing (4) until the output voltage of the amplifier circuit indicates a variation pattern specific to the rotation movement of a rotating body.

Description

  The present invention relates to a circuit that is used by being connected to a sensor that outputs a voltage that periodically changes following the rotation of a rotating body, and relates to a circuit that processes a sensor voltage (an output voltage of the sensor).

  In order to detect the rotation of the rotating body, a technique described in Patent Document 1 has been proposed. As shown in FIG. 21, the technique of Patent Document 1 includes a pair of sensors 901, a preamplifier 902, an offset adjuster 921, in order to detect the rotation of a rotating body 907 having a large number of teeth 908 on the outer periphery. A main amplifier 920, a logic determination unit 904, an initialization determination unit 903, and a reinitialization determination unit 930 are provided.

This rotation detection device detects a rotation speed and the like by the following mechanism.
(1) Each sensor 901 is a Hall element, and outputs a sensor voltage that changes following the change in the positional relationship between the teeth 908 of the rotating body 907 and the sensor 901.
(2) The preamplifier 902 primarily amplifies and outputs the sensor voltage.
(3) When the rotating body 907 rotates, the sensor voltage after the primary amplification periodically changes. The sensor voltage after the primary amplification is a voltage in which the direct current component overlaps the alternating current component that periodically changes.
(4) The value of the DC voltage included in the sensor voltage after the primary amplification changes depending on the change of the power supply voltage or the change of the environmental temperature. If the offset voltage is not adjusted appropriately, the sensor voltage after secondary amplification by the main amplifier 920 may fall outside the operating voltage range of the circuit.
(5) The amplitude of the AC voltage included in the sensor voltage after the primary amplification changes depending on a change in the power supply voltage or a change in the environmental temperature. If the amplification factor of the main amplifier 920 is not adjusted appropriately, the amplitude of the sensor voltage after the secondary amplification becomes excessive and falls outside the operation range of the circuit, or becomes too small and the signal processing accuracy decreases. There is.
(6) The offset adjuster 921 adjusts the offset voltage so that the median amplitude of the sensor voltage after the primary amplification falls within a predetermined range, and the difference between the sensor voltage after the primary amplification and the offset voltage is adjusted to the main amplifier 920. Output to.
(7) The main amplifier 920 outputs a voltage obtained by superimposing the offset voltage on the voltage obtained by amplifying the difference to the logic determination unit 904.
(8) The logic determination unit 904 performs a logical operation on the sensor voltage after the secondary amplification that periodically changes with reference to the offset voltage, and outputs a pulse train obtained by binarizing the sensor voltage.

The rotation detection device includes an initialization determination unit 903 and a reinitialization determination unit 930 in order to adjust the offset voltage and the amplification factor appropriately.
(9) The initialization determination unit 903 adjusts the amplification factor of the main amplifier 920 to an amplification factor in which the amplitude of the sensor voltage after the secondary amplification is not excessive or excessive in the initial state immediately after the power is turned on.
(10) Although the rotating body 907 is not rotating in the initial state immediately after the power is turned on, for example, the rotation center position of the rotating body 907 vibrates with respect to the sensor 901, or the rotating body 907 is in a minute angle range. The sensor voltage may fluctuate periodically. In this case, the amplitude of the sensor voltage is small, and the initialization determination unit 903 may adjust the amplification factor to a large value in order to amplify the small amplitude to an appropriate amplitude.
(11) When the above (10) occurs, when the rotating body 907 starts rotating, the amplitude of the sensor voltage increases, and the main amplifier 920 amplifies with the amplification factor adjusted by the initialization determination unit 903. The amplitude of the sensor voltage after secondary amplification may become excessive.
(12) The reinitialization determination unit 930 reduces the amplification factor when the amplification factor adjusted by the initialization determination unit 903 is excessive. Specifically, the sensor voltage after the secondary amplification rises above a level that is lower than the upper limit voltage of the operating voltage range of the circuit by a predetermined voltage (hereinafter referred to as a high level), and is higher than the lower limit voltage of the operating voltage range. When the voltage falls below a level higher by a predetermined voltage (hereinafter referred to as a low level), the amplification factor of the main amplifier 920 is reduced. That is, the amplification factor is reduced so that the sensor voltage after the secondary amplification falls within the range from the high level to the low level.

JP 2006-145528 A

In the technique of Patent Document 1, the period until the amplification factor is not adjusted to an appropriate value until the amplification factor is corrected by the reinitialization determination unit 930, and the rotation of the rotating body 907 can be accurately detected. Will become longer.
In particular, in the technique of Patent Document 1, the sensor voltage after secondary amplification exceeds a high level in order to distinguish between the case where the offset voltage is improperly adjusted and the case where the amplification factor is improperly adjusted. At the same time, it takes a long time to adjust the amplification factor to an appropriate value in order to adjust the amplification factor after confirming that it is below the low level.

  In the present invention, the period until the rotation can be detected is shortened. Therefore, in the present invention, by adopting a method in which the offset voltage is adjusted early and the change width of the subsequent amplified voltage is monitored, the amplification factor can be obtained without waiting for the amplitude of the amplified sensor voltage to be determined. Adjust. Further, the amplification factor is adjusted to an appropriate value through a process of reducing the amplification factor from the maximum amplification factor. The conventional technique goes through a two-step process of temporarily determining an appropriate value of the amplification factor and correcting it. In the present invention, the amplification factor is adjusted in a one-step process, and no subsequent adjustment is performed.

  The present invention provides a new circuit for processing a sensor voltage that periodically changes following the rotation of a rotating body. The processing circuit of the present invention outputs a voltage obtained by amplifying the sensor voltage with reference to the offset voltage, and stores the maximum value and the minimum value of the output voltage of the amplifier circuit, the amplifier circuit capable of adjusting the offset voltage and the amplification factor An extreme value storage circuit, a binarization circuit that binarizes the output voltage of the amplifier circuit based on the local maximum value and the local minimum value stored in the local extreme value storage circuit, and an adjustment circuit. The adjustment circuit outputs an adjustment signal for the offset voltage and an adjustment signal for the amplification factor to the amplification circuit based on the output voltage of the amplification circuit and the local maximum value or the local minimum value stored in the extreme value storage circuit. A signal for correcting the extreme value stored in the extreme value storage circuit is output to the value storage circuit. Further, during the initialization process, the adjustment circuit 1) outputs an adjustment signal that maximizes the amplification factor to the amplifier circuit, and 2) outputs the output voltage of the amplifier circuit to the amplifier circuit in the middle of the operating voltage range. 3) A signal for making the maximum value and the minimum value stored in the extreme value storage circuit equal to the voltage in the intermediate band with respect to the extreme value storage circuit. Output. The adjustment circuit then adjusts the amplification circuit to reduce the amplification factor when the output voltage of the amplification circuit changes beyond a predetermined value from a maximum value or a minimum value stored in the extreme value storage circuit. A signal is output and a signal for correcting the extreme value stored in the extreme value storage circuit is output to the extreme value storage circuit. The process of 4) is repeated until the output voltage of the amplifier circuit shows a change pattern unique to the rotational motion of the rotating body.

  The amplifying circuit may amplify the sensor voltage itself, or may amplify the primary amplified voltage obtained by amplifying the sensor voltage by the preamplifier circuit. The width of the intermediate band is not particularly limited. If the operating voltage range is about half or less of the operating voltage range, the intended purpose can be achieved. The adjustment circuit only needs to refer to the maximum value or the minimum value stored in the extreme value storage circuit when outputting the adjustment signal of at least the amplification factor. When the offset voltage adjustment signal is output, the maximum value or the minimum value may not be referred to. In this case, the adjustment circuit also outputs “the offset voltage adjustment signal and the amplification factor adjustment signal to the amplification circuit based on the output voltage of the amplification circuit and the maximum value or the minimum value stored in the extreme value storage circuit. Corresponds to the adjustment circuit.

The adjustment circuit described above adjusts the offset voltage so that the output voltage (amplified voltage) of the amplifier circuit falls in the intermediate band of the operating voltage range with the amplification factor fixed to the maximum value. Therefore, even if the amplification factor is adjusted thereafter, the amplified voltage is adjusted to an offset voltage that does not fall outside the operating voltage range. In addition, it is possible to process an amplified voltage that changes at least in the range from the intermediate band to the upper limit or lower limit of the operating voltage range.
The adjustment circuit described above outputs a signal that uses the extreme value stored in the extreme value storage circuit as a voltage in the intermediate band of the operating voltage range to the extreme value storage circuit. As a result, the maximum value stored in the extreme value storage circuit and the initial value of the minimum value are set as intermediate values, and the maximum value stored in the extreme value storage circuit follows the change in the voltage after amplification. Values and local minimums are updated. The extreme value stored first by the extreme value storage circuit may be equal to the amplified voltage when the offset voltage has been adjusted. The amplified voltage when the offset voltage is adjusted is within the intermediate band.
The adjustment circuit adjusts the amplification factor thereafter. In this case, the amplification factor is adjusted based on the change range from the maximum value or the minimum value stored in the extreme value storage circuit. For example, when the sensor voltage is rising, if the increase from the last minimum value of the amplified voltage exceeds a predetermined width, the amplification factor is reduced because the amplitude of the amplified voltage is excessive. On the contrary, when the sensor voltage is decreasing, if the amount of decrease from the last maximum value of the amplified voltage exceeds a predetermined width, the amplification factor is reduced because the amplitude of the amplified voltage is excessive. In either case, the amplification factor is reduced without waiting for the next extreme value (in other words, without waiting for the magnitude of the amplitude of the amplified voltage to be known). The predetermined width here is a voltage based on whether or not to change the amplification factor, and corresponds to the amplification factor change determination voltage.
This processing circuit corrects the extreme value stored in the extreme value storage circuit with respect to the extreme value storage circuit when the adjustment signal for reducing the amplification factor is output when the amplification factor is found to be excessive. Is output. As a result, it is possible to determine whether or not the amplification factor after the reduction is excessive based on the change width from the maximum value or the minimum value.
Until the amplified voltage shows a change pattern unique to rotational movement, the amplification factor reduction process and the stored extreme value correction process are repeated, and when the amplified voltage shows a change pattern specific to rotational movement, the amplification factor Complete the adjustment process.
Through the above processing, the amplified voltage is adjusted to an offset voltage that falls within the operating voltage range, and adjusted to an amplification factor that effectively uses the operating voltage range. In addition, the gain is adjusted to an amplification factor that does not need to be adjusted afterwards.
According to the above sensor voltage processing circuit, it is possible to shorten the period from turning on the power to adjusting to an appropriate offset voltage and an appropriate amplification factor, and shortening the period until the rotation phenomenon can be detected with high accuracy. Can be

There are at least two methods for correcting the extreme value stored in the extreme value storage circuit when the amplification factor is reduced in 4).
In one method, both the maximum value and the minimum value stored in the extreme value storage circuit during the process of (4) are made equal to the output voltage of the amplification circuit amplified with the reduced amplification factor.
In this case, update processing of the maximum value and the minimum value is started immediately after the execution of (4). Until the phenomenon occurs in which the output voltage of the amplifier circuit changes beyond the maximum or minimum value stored in the extreme value storage circuit beyond a predetermined range, the maximum or minimum value used for the determination is not true. The value has been updated. By this method, it is possible to determine whether the amplification factor is excessive or not based on the change width from the maximum value or the minimum value of the amplified voltage.

Instead, at the time of the process (4), the old maximum value and the old minimum value stored in the extreme value storage circuit are updated to the new maximum value and the new minimum value calculated by the following equations. Also good.
New maximum value = (old maximum value−offset voltage) × (new gain / old gain) + offset voltage New minimum value = (old minimum value−offset voltage) × (new gain / old gain) + offset voltage According to this method, when the amplification factor is reduced by the process of (4), the maximum value and the minimum value stored in the extreme value storage circuit are the maximum value of the amplified voltage amplified by the reduced amplification factor. It is updated to the minimum value.
When the maximum value stored in the extreme value storage circuit is updated following the increase in voltage after amplification, and the minimum value stored in the extreme value storage circuit is updated following the decrease in voltage after amplification, At the timing when the change width from the maximum value or minimum value of the amplified voltage exceeds the specified width, the change width from the maximum value or minimum value of the amplified voltage = the maximum value and minimum value stored in the extreme value storage circuit It makes a difference.
Therefore, the change width may be calculated from the maximum value or the minimum value of the amplified voltage from the difference between the maximum value and the minimum value stored in the extreme value storage circuit.

If the minimum value of the sensor voltage amplitude during the rotating motion of the rotating body is greater than or equal to the maximum value of the sensor voltage amplitude during the vibrating motion of the rotating body, the change from the extreme value of the output voltage of the amplifier circuit is the vibration motion. It can be treated that the rotational motion is detected when the amplitude of the sensor voltage at the time exceeds the maximum value. In this case, the output voltage of the amplifier circuit has changed from the maximum value or the minimum value stored in the extreme value storage circuit to exceed the maximum value of the amplitude of the output voltage of the amplifier circuit caused by the vibration phenomenon of the rotating body. It is preferable to repeat the process (4) until the output of the binarization circuit is inverted three times later.
If the output of the binarization circuit is reversed three times after the start of the rotary motion of the rotating body, the sensor voltage during the rotation changes from the maximum value to the minimum value during that time, so that the amplification factor is further reduced. It is not necessary, and it is confirmed that the amplified voltage with the amplification factor adjusted so far falls within the operating range.

It can also be set as the processing circuit used by connecting to the 1st sensor and 2nd sensor from which the positional relationship with respect to a rotary body differs. The processing circuit in this case includes an amplifier circuit that processes the first sensor voltage, an extreme value storage circuit, a binarization circuit, and an adjustment circuit, an amplifier circuit that processes the second sensor voltage, an extreme value storage circuit, and a binarization circuit. And an adjustment circuit. In this processing circuit, the process (4) is performed until the phase difference between the processing result of the binarization circuit that processes the first sensor voltage and the processing result of the binarization circuit that processes the second sensor voltage falls within a predetermined range. repeat.
As will be described later, if the phase difference is within a predetermined range, it can be determined that not a vibration motion but a rotational motion has been detected, and it can be determined that there is no need to further reduce and adjust the amplification factor.

  The amplifier circuit preferably includes an offset voltage adjustment circuit, and the offset voltage adjustment circuit is preferably composed of an analog / digital mixed circuit. A circuit for adjusting the offset voltage can be easily realized.

  It is also preferable that the extreme value storage circuit is composed of an analog / digital mixed circuit. An extreme value storage circuit that can correct the stored extreme values can be easily realized.

A preamplifier circuit may be inserted between the sensor and the amplifier circuit. In that case, it is preferable to use a resistance whose resistance value varies with temperature as the feedback resistance of the preamplifier circuit.
The temperature compensation function can be realized by the preamplifier circuit, and it is easy to understand the amplifier circuit (the main amplifier circuit is distinguished from the preamplifier circuit. However, in the present invention, the preamplifier circuit is necessarily present. Since it is not limited, it is possible to eliminate the need to incorporate a temperature compensation function in the amplification factor adjustment circuit (simply referred to as an amplification circuit in this specification).

  When the output voltage of the amplifier circuit exceeds the operating voltage range after adjusting the amplification factor in (5), it is preferable to adjust the offset voltage and the extreme value stored in the extreme value storage circuit in conjunction with each other. According to this technology, there is no need to readjust the amplification factor. As long as the offset voltage is adjusted, the output voltage of the amplifier circuit falls within the operating voltage range. If the value stored in the extreme value storage circuit is adjusted in accordance with the adjustment amount of the offset voltage, the binarization processing of the output voltage of the amplifier circuit can be continued before and after the adjustment of the offset voltage.

  According to the sensor voltage processing circuit of the present invention, when the bias voltage included in the sensor voltage and the amplitude of the sensor voltage are unknown, the sensor voltage after amplification is quickly adjusted to an offset voltage that falls within the operating voltage range. The gain can be quickly adjusted to effectively utilize the operating voltage range. It is possible to detect rotation with high accuracy within a short time after the power is turned on.

The figure which shows the rotary body of 1st Example, a sensor, and a sensor voltage processing circuit. The figure which shows the structure of the sensor voltage processing circuit of 1st Example. The figure which shows the structure of the amplifier circuit of 1st Example, an offset voltage adjustment circuit, and an amplification factor adjustment circuit. The figure which shows the structure of the peak hold circuit and bottom hold circuit of 1st Example. The figure which shows the process which supplements an extreme value when a sensor voltage fluctuates gently. The figure which shows another process which supplements an extreme value when a sensor voltage fluctuates gently. 1 is a flowchart 1 showing the procedure of a sensor voltage processing routine of the first embodiment. 2 of the flowchart which shows the procedure of the sensor voltage processing routine of 1st Example. The figure explaining the phenomenon which arises by the process sequence of FIG. The figure explaining the phenomenon which arises by the process sequence of FIG. 7 and FIG. The figure which shows the modification of FIG. The figure which shows the rotary body of 2nd Example, a sensor, and a sensor voltage processing circuit. The figure explaining the processing content of 2nd Example. The figure which shows the rotary body of 3rd Example, a sensor, and a sensor voltage processing circuit. The figure which shows the structure of the sensor voltage processing circuit of 3rd Example. The figure which shows the characteristic used for the rotation / vibration determination of 3rd Example. The figure which shows the structure of the binarization circuit of 3rd Example. The figure which shows the content of the binarization process of 3rd Example. The figure which shows the structure of the rotation / vibration determination circuit of 3rd Example. Flowchart 1 showing the procedure of the sensor voltage processing routine of the third embodiment. Explanatory drawing which shows the conventional rotation detection system.

The present invention can also be realized as a more preferable embodiment by including, for example, the following features alone or in combination.
(First Feature) The offset voltage adjustment circuit includes a digital circuit and a D / A conversion circuit, and an offset voltage is adjusted by inputting a signal to the digital circuit.
(Second Feature) The extreme value storage circuit includes a digital circuit and a D / A conversion circuit, and an extreme value stored in the extreme value storage circuit is adjusted by inputting a signal to the digital circuit.
(Third feature) The amplitude of the sensor output decreases as the environmental temperature increases, and the amplification factor of the preamplifier circuit increases as the environmental temperature increases. The decrease rate of the sensor output per unit temperature and the increase rate of the amplification factor of the preamplifier circuit per unit temperature are set to be almost equal, and the amplitude of the output voltage of the preamplifier circuit is almost resistant to temperature changes. Maintained constant. Once the gain of the main amplifier (amplifier circuit) is adjusted, the preamplifier circuit compensates for the effects of subsequent temperature changes by adjusting the gain, so it is necessary to readjust the gain of the main amplifier (amplifier circuit). There is no.
(Fourth feature) An intermediate value between the maximum value and the minimum value of the amplified sensor voltage (not necessarily mathematically exact intermediate) is compared with the amplified sensor voltage to be binarized.
(Fifth feature) The sensor voltage after amplification is increased or decreased so that the intermediate value (not necessarily mathematically exact intermediate) between the maximum value and the minimum value of the amplified sensor voltage becomes a predetermined value. The amplified sensor voltage after the increase / decrease adjustment is compared with a predetermined value and binarized. The method of the fourth feature and the method of the fifth feature process the same contents and bring about the same result. Both are equal.
(Sixth feature) When the rotational motion and the vibration phenomenon cannot be distinguished only by the amplitude of the sensor voltage, the two motion sensors are used to distinguish the rotational motion and the vibration phenomenon with reference to the phase difference between the two sensor voltages. However, when the amplitude of the sensor voltage is small, the rotational motion and the vibration phenomenon may not be distinguished from the phase difference. In other words, even if the phase difference is viewed with the sensor voltage amplitude being small, the rotational motion and the vibration phenomenon cannot be distinguished. The vibration phenomenon may not be distinguished. In this embodiment, a process of amplifying with a large amplification factor and detecting a phase difference is performed to reduce the amplification factor to an appropriate amplification factor. That is, a process is performed in which the phase difference is determined by amplifying the sensor voltage with an amplification factor that provides a voltage with a magnitude that can distinguish rotation and vibration from the phase difference. It is possible to accurately distinguish between rotational motion and vibration phenomena.
(Seventh feature) By referencing the binarization processing result of two sensor voltages at the inversion timing of the delayed binarization result that inverts later than that, the binarization processing result of the two sensor voltages Specify the phase difference.

Hereinafter, in order to clearly describe the operation and effects of the present invention based on the above-described features, examples of the present invention will be described in the following order.
A. Sensor voltage processing circuit according to the first embodiment of the present invention:
A-1. Configuration of a processing circuit according to the first embodiment of the present invention:
A-2. Operation of the processing circuit according to the first embodiment of the present invention:
B. Sensor voltage processing circuit according to the second embodiment of the present invention:
B-1. Configuration of processing circuit according to second embodiment of the present invention:
B-2. Operation of the processing circuit according to the second embodiment of the present invention:
C. Sensor voltage processing circuit according to the third embodiment of the present invention:
C-1. Configuration of processing circuit according to third embodiment of the present invention:
C-2. Operation of the processing circuit according to the third embodiment of the present invention:
D. Variations:

A. Sensor voltage processing circuit according to the first embodiment of the present invention:
A-1. Configuration of a sensor voltage processing circuit according to the first embodiment of the present invention:
FIG. 1 shows a rotation detection system including a rotator 10, a sensor 11, and a sensor voltage processing circuit 100 according to the first embodiment. The rotating body 10 is a magnetic body and is mechanically connected to a rotating member that rotates only in one direction, such as an engine crankshaft. The sensor 11 is a Hall element, and outputs a sensor voltage Vin that changes following a magnetic change caused by a change in the positional relationship with the tooth 10 t of the rotating body 10. When the rotating body 10 rotates, the teeth 10t and valleys (between the teeth) alternately pass through the position facing the sensor 11, so that the sensor voltage Vin periodically changes. The sensor voltage processing circuit 100 amplifies the sensor voltage Vin, performs binarization processing, and outputs a digital signal Vout that is inverted between high and low. The sensor voltage processing circuit 100 includes an amplifier circuit, a binarization circuit, an adjustment circuit that adjusts an offset voltage and an amplification factor of the amplifier circuit, and an extreme value storage circuit that stores a maximum value and a minimum value of the amplified voltage. ing. The adjustment circuit outputs a signal V′off for adjusting the offset voltage to the amplification circuit based on the amplified voltage Vm, and a signal for adjusting the amplification factor based on the amplified voltage Vm and the maximum value Vp or the minimum value Vb. S is output to the amplifier circuit. When adjusting the amplification factor, the adjustment circuit outputs a signal S2 for correcting the maximum value Vp and the minimum value Vb stored in the extreme value storage circuit to the extreme value storage circuit. The binarization circuit binarizes the amplified voltage Vm using the maximum value Vp and the minimum value Vb stored in the extreme value storage circuit.

The rotating body 10 is disposed with a gap δ between the rotating body 10 and the sensor 11. The gap δ changes depending on the rotation angle of the rotating body 10 (hereinafter referred to as “swell”) when the rotational center and the geometric center of the rotating body 10 are deviated. If the outer peripheral surface of the rotating body 10 is not a perfect circle, the same undulation occurs.
The sensor voltage Vin is a voltage obtained by superimposing a DC voltage (bias voltage) on an AC voltage that periodically changes following the passage of teeth 10t and valleys alternately. The magnitude of the bias voltage varies depending on the power supply voltage and the environmental temperature. The amplitude of the AC voltage varies depending on the size of the gap δ, the power supply voltage, the environmental temperature, and the like. When the sensor voltage Vin is amplified by the sensor voltage processing circuit 100, if the reference voltage (offset voltage) is appropriately adjusted and the amplification factor is not adjusted appropriately, the amplified sensor voltage is a voltage range suitable for processing. Therefore, it does not change with an amplitude suitable for processing. The sensor voltage processing circuit 100 needs to adjust the offset voltage and the amplification factor to appropriate values immediately after the power is turned on.

  The positional relationship between the rotator 10 and the sensor 11 is that the rotator 10 continuously rotates in one direction, and also rotates and vibrates within a minute angle range, or the rotation center position vibrates relative to the sensor 11 There is. In the first embodiment, when the rotating body 10 continuously rotates in one direction, the sensor voltage varies with a large amplitude, and when the rotating body 10 vibrates, the sensor voltage varies with a small amplitude. From the magnitude of the amplitude of the sensor voltage, it can be determined whether the rotating body is rotating or oscillating. It may not be possible to determine whether the rotator is rotating or oscillating only from the magnitude of the amplitude of the sensor voltage. In that case, the third embodiment is used. In the following description, the term “rotation” refers to a state of motion that continues to rotate in the same direction, and the term “vibration” refers to rotational vibration within a minute angle range or vibration of the center of rotation.

FIG. 2 shows the internal configuration of the sensor voltage processing circuit 100. The sensor voltage processing circuit 100 includes a preamplifier circuit 110, an amplifier circuit 120, an adjustment circuit 400, an extreme value storage circuit 160, and a binarization circuit 200. The adjustment circuit 400 includes an offset voltage adjustment circuit 130, an amplification factor adjustment circuit 140, a first voltage determination unit 150, a second voltage determination unit 155, and a change width determination unit 145. The extreme value storage circuit 160 includes a peak hold circuit 160p and a bottom hold circuit 160b. The binarization circuit 200 includes a binarization processing unit 170 and a circuit that obtains a reference voltage Vref for binarization from the storage voltage of the extreme value storage circuit 160.
The power supply voltage is Vcc, and the operating voltage range of the circuit is 0 to Vcc.

  The preamplifier circuit 110 inverts and amplifies the difference between the sensor voltage Vin and Vcc / 2, and outputs a voltage obtained by adding Vcc / 2 thereto. The amplification factor of the preamplifier circuit 110 is fixed (increase / decrease depending on the temperature as described later, but it is not switched depending on the magnitude of the sensor voltage Vin, so it is fixed here), and the offset voltage is Vcc / 2. It is fixed to. Since the amplification factor of the preamplifier circuit 110 is relatively small, even if the bias voltage of the sensor voltage Vin changes or the amplitude of the sensor voltage Vin changes, the output voltage of the preamplifier circuit 110 remains the circuit operating voltage. It falls within the range of 0 to Vcc.

  The amplifier circuit 120 further amplifies the output voltage of the preamplifier circuit 110. At this time, if the offset voltage is not set appropriately, the voltage Vm amplified by the amplifier circuit 120 reaches zero volts (hereinafter referred to as 0) or Vcc, and cannot be amplified with a necessary amplification factor, and is binarized. A phenomenon occurs in which processing cannot be executed correctly. Similarly, if the amplification factor is not set appropriately, the voltage Vm amplified by the amplifier circuit 120 reaches 0 or Vcc, and the amplification cannot be performed with the necessary amplification factor, resulting in a phenomenon in which the binarization process cannot be executed correctly. . In order to avoid this problem, an offset voltage adjustment circuit 130 and an amplification factor adjustment circuit 140 are prepared. The offset voltage adjustment circuit 130 and the amplification factor adjustment circuit 140 can also be regarded as part of the amplification circuit 120. It can be said that the amplifier circuit 120 has a built-in offset voltage adjustment function and an amplification factor adjustment function.

The offset voltage adjustment circuit 130 has a reset terminal, and a reset signal RST is applied when the power is turned on. Then, the offset adjustment circuit 130 transmits the offset voltage Voff to the amplifier circuit 120 as Vcc / 2. When the power is turned on, the amplifier circuit 120 starts to amplify with the offset voltage set to Vcc / 2.
The voltage Vm amplified by the amplifier circuit 120 is input to the first voltage determination unit 150 and compared with Vcc / 2. If the amplified voltage Vm> Vcc / 2, the offset voltage adjustment circuit 130 decreases the offset voltage Voff by a predetermined width. As a result, the amplified voltage Vm decreases and approaches Vcc / 2. If the amplified voltage Vm <Vcc / 2, the offset voltage adjustment circuit 130 increases the offset voltage Voff by a predetermined width. As a result, the amplified voltage Vm increases and approaches Vcc / 2. The offset voltage adjustment circuit 130 adjusts the offset voltage Voff until the amplified voltage Vm approaches Vcc / 2. Vcc / 2 belongs to the intermediate band of the operating voltage range of 0 to Vcc. The offset voltage adjustment circuit 130 adjusts the offset voltage Voff until the amplified voltage Vm becomes a value that falls within the intermediate band of the operating voltage range. The target value of the amplified voltage Vm used when adjusting the offset voltage Voff does not have to be Vcc / 2, and may be a voltage belonging to the intermediate band of the operating voltage range of 0 to Vcc.

The amplification factor adjustment circuit 140 includes a reset terminal, and a reset signal RST is applied when the power is turned on. Then, the amplification factor adjustment circuit 140 switches the amplification factor of the amplification circuit 120 to the maximum value. The amplification factor is maintained at the maximum value until the offset voltage Voff is adjusted and the amplified voltage Vm becomes Vcc / 2.
When the power is turned on, the hold voltage stored in the peak hold circuit 160p and the bottom hold circuit 160b is initialized to Vcc / 2. The hold voltage stored in the peak hold circuit 160p and the bottom hold circuit 160b is fixed at Vcc / 2 until the offset voltage Voff is adjusted and the voltage Vm amplified at the maximum amplification rate becomes Vcc / 2. The amplified voltage Vm is input to the peak hold circuit 160p and the bottom hold circuit 160b. When the amplified voltage Vm matches Vcc / 2, the peak hold circuit 160p starts the peak hold voltage update process, and the bottom hold circuit 160b starts the bottom hold voltage update process.
While the post-amplification voltage Vm rises, an increase width from the minimum value (minimum value after the update process is started) is calculated, and the increase width is input to the change width determination unit 145. When the increase width exceeds the predetermined width, the change width determination unit 145 reduces the amplification factor of the amplifier circuit 120 by one step. While the post-amplification voltage Vm decreases, a decrease width from the maximum value (maximum value after the update process is started) is calculated, and the decrease width is input to the change width determination unit 145. The change width determination unit 145 reduces the amplification factor of the amplifier circuit 120 by one step when the descending width exceeds a predetermined width.
In the present embodiment, when the amplified voltage Vm rises from the minimum value Vb beyond a predetermined width, the amplified voltage Vm exceeds the peak hold voltage Vp so far. That is, while the peak hold voltage Vp is updated following the increase in the amplified voltage Vm, the amplified voltage Vm increases from the minimum value Vb beyond a predetermined width. At this time, the amplified voltage Vm = the peak hold voltage Vp. Therefore, in this embodiment, whether or not the difference between the peak hold voltage Vp and the bottom hold voltage Vb exceeds the predetermined width in order to determine whether or not the increase width of the amplified voltage Vm from the minimum value Vb exceeds the predetermined width. Judgment is made depending on
Similarly, when the amplified voltage Vm drops from the maximum value Vp beyond a predetermined width, the amplified voltage Vm is lower than the bottom hold voltage Vb. That is, while the bottom hold voltage Vb is updated following the decrease in the amplified voltage Vm, the amplified voltage Vm decreases from the maximum value Vp beyond a predetermined width. At this time, the amplified voltage Vm = bottom hold voltage Vb. Therefore, in this embodiment, whether or not the difference between the peak hold voltage Vp and the bottom hold voltage Vb exceeds a predetermined width in order to determine whether or not the descending width of the amplified voltage Vm from the maximum value Vp exceeds a predetermined width. Judgment is made depending on
Since the increase width from the minimum value or the decrease width from the maximum value (in this embodiment, the difference between the peak hold voltage Vp and the bottom hold voltage Vb) exceeds a predetermined width, the amplification factor adjustment circuit 140 causes the amplification circuit 120 to The peak hold voltage Vp and the bottom hold voltage Vb need to be corrected to the maximum value and the minimum value of the amplified voltage Vm based on the new gain. When the correction is made, the difference between the peak hold voltage Vp and the bottom hold voltage Vb is increased from the minimum value of the amplified voltage Vm by the new amplification factor or decreased from the maximum value of the amplified voltage Vm by the new amplification factor. Will be equal.
By repeating the above processing, the amplified voltage Vm is reduced to a gain that does not exceed a predetermined width of the minimum value or the change width from the maximum value. Since the amplification factor is reduced in order, eventually, the amplification factor is adjusted to the maximum amplification factor that satisfies the constraint that the variation range from the minimum value or the maximum value of the amplified voltage Vm does not exceed the predetermined range.

  When the peak hold circuit 160p and the bottom hold circuit 160b start the hold voltage update process, the amplified voltage Vm is Vcc / 2, the peak hold voltage Vp is also Vcc / 2, and the bottom hold voltage Vb is also Vcc / 2. It is. In this state, the peak hold circuit 160p and the bottom hold circuit 160b start the hold voltage update process. Therefore, if the amplified voltage Vm subsequently increases, the peak hold voltage Vp also follows and increases, and then the amplified voltage Vm. If the voltage falls, the bottom hold voltage Vb also follows and falls. The peak hold circuit 160p and the bottom hold circuit 160b store the maximum value and the minimum value after the time when the offset voltage Voff is adjusted and the amplified voltage Vm becomes Vcc / 2.

When the amplification factor is switched, the amplified voltage Vm changes. On the other hand, the hold voltage of the peak hold circuit 160p and the bottom hold circuit 160b is an extreme value of the amplified voltage Vm in the case of the amplification factor before switching. Therefore, simply calculating the difference between the amplified voltage Vm and the hold voltage does not result in a variation from the extreme value of the amplified voltage Vm. In order to cope with this problem, when the amplification factor is switched and the amplified voltage Vm changes, the hold voltages of the peak hold circuit 160p and the bottom hold circuit 160b are also switched to the extreme values when amplified with the new amplification factor. When the processing is performed, even after the amplification factor is switched, the difference from the extreme value of the amplified voltage Vm can be obtained by calculating the difference between the amplified voltage Vm and the hold voltage. In this embodiment, the difference between the peak hold voltage Vp and the bottom hold voltage Vb becomes equal to the rise from the minimum value or the fall from the maximum value of the amplified voltage Vm due to the new amplification factor.
In this processing circuit, it is found that the amplification factor is excessive, and when the adjustment circuit 400 outputs the adjustment signal S for reducing the amplification factor to the amplification circuit 120, the extreme value is given to the extreme value storage circuit 160. The storage circuit 160 outputs a signal for correcting the hold voltage stored. Specifically, the adjustment circuit 400 outputs a signal for correcting the peak hold voltage Vp to the peak hold circuit 160p, and outputs a signal for correcting the bottom hold voltage Vb to the bottom hold circuit 160b.
In this embodiment, when the adjustment circuit 400 outputs the adjustment signal S for reducing the amplification factor to the amplifier circuit 120, both the peak hold voltage Vp of the peak hold circuit 160p and the bottom hold voltage Vb of the bottom hold circuit 160b are obtained. The amplified voltage Vm after the amplification factor reduction is made equal.
In this case, as illustrated in FIG. 10 to be described later, the peak hold voltage Vp or the bottom hold voltage Vb is updated following the increase or decrease of the amplified voltage Vm after the amplification factor reduction, and the amplification after the amplification factor reduction is performed. It corresponds to the peak voltage or the bottom voltage of the rear voltage Vm. When the increase width from the minimum value of the amplified voltage Vm after the amplification factor reduction exceeds a predetermined width, or when the decrease width from the maximum value of the amplified voltage Vm after the amplification factor reduction exceeds a predetermined width, Prior to that, there has been a phenomenon in which the amplified voltage Vm after the amplification factor reduction increases and then increases or decreases. That is, when the increase width from the minimum value of the amplified voltage Vm after the amplification factor reduction exceeds a predetermined width, the bottom hold voltage Vb is updated to the minimum value of the amplified voltage Vm after the amplification factor reduction. Further, when the descending width from the maximum value of the amplified voltage Vm after the amplification factor reduction exceeds a predetermined width, the peak hold voltage Vp is updated to the maximum value of the amplified voltage Vm after the amplification factor reduction.
When the adjustment circuit 400 outputs the adjustment signal S for reducing the amplification factor to the amplifier circuit 120, both the peak hold voltage Vp of the peak hold circuit 160p and the bottom hold voltage Vb of the bottom hold circuit 160b are reduced. When equal to the amplified voltage Vm, when the variation width of the amplified voltage Vm after the amplification factor reduction exceeds a predetermined width, the minimum value of the amplified voltage Vm after the amplification factor reduction is stored in the bottom hold circuit 160b. The maximum value of the amplified voltage Vm after the amplification factor reduction can be stored in the peak hold circuit 160b.
During the period from when the above processing is performed until a phenomenon occurs in which the output voltage of the amplifier circuit changes beyond the maximum value or the minimum value stored in the extreme value storage circuit over a predetermined range, the peak used for the determination The hold voltage Vp and the bottom hold voltage Vb are corrected to be based on the amplification factor of the amplified voltage to be discriminated. According to this method, it is possible to determine whether the amplification factor is excessive or not based on the variation range from the maximum value or the minimum value of the amplified voltage.
Instead of the above, when it is determined that the amplification factor is excessive and the adjustment circuit 400 outputs the adjustment signal S for reducing the amplification factor to the amplification circuit 120, the old value stored in the extreme value storage circuit 160 A method of updating the maximum value and the old minimum value to the new maximum value and the new minimum value calculated by the following equations may be adopted.
New maximum value = (old maximum value−offset voltage) × (new gain / old gain) + offset voltage New minimum value = (old minimum value−offset voltage) × (new gain / old gain) + offset voltage Also in this method, when a phenomenon occurs in which the voltage after amplification due to the new amplification factor (reduction factor after reduction) changes beyond a predetermined width, the peak hold voltage and the bottom hold voltage stored in the extreme value storage circuit 160 are stored. Can be made to coincide with the maximum value and the minimum value of the amplified voltage Vm based on the new amplification factor. Further, it is possible to obtain a relationship of “a variation from the maximum value or the minimum value of the amplified voltage Vm due to the new amplification factor = the difference between the peak hold voltage Vp and the bottom hold voltage Vb”.

  The binarization processing unit 170 is generated by dividing the voltage difference between the peak hold voltage Vp stored in the peak hold circuit 160p and the bottom hold voltage Vb stored in the bottom hold circuit 160b by a ratio of 1/2. The amplified voltage Vm is binarized using the reference voltage Vref, and a digital signal Vout that is inverted when the amplified voltage Vm changes beyond the reference voltage Vref is generated. If the number of inversions per unit time of the digital signal Vout is counted, the rotational speed of the rotating body 10 can be determined.

  FIG. 3 shows a configuration of the preamplifier circuit 110, the amplifier circuit 120, the offset voltage adjustment circuit 130, and the amplification factor adjustment circuit 140.

The preamplifier circuit 110 is configured with the operational amplifier 121 as the center, the inverting input terminal is connected to the input terminal of the sensor voltage Vin via the resistor 1R, and the non-inverting terminal is connected to Vcc / 2. . A feedback resistor 50Rs is inserted between the output terminal and the inverting input terminal of the operational amplifier 121. The voltage at the output terminal of the operational amplifier 121 is expressed by the following equation.
-(50Rs / 1R) x (Vin-Vcc / 2) + Vcc / 2
That is, the offset voltage of the preamplifier circuit 110 is Vcc / 2, and the amplification factor is −50 Rs / 1R.

The sensor 11 has a characteristic that the amplitude of the sensor voltage Vin decreases as the temperature rises. Therefore, a resistor whose resistance value increases with temperature is used as the feedback resistor 50Rs. For the feedback resistor 50Rs, a material having a temperature coefficient of resistance satisfying the relationship that (the rate of decrease of the amplitude of the sensor voltage / unit temperature) is substantially equal to (the rate of increase of (resistor 50Rs / resistor 1R) / unit temperature) is selected. ing.
Due to the above relationship, the effect that the amplitude of the sensor voltage decreases when the temperature rises is canceled by the increase of the amplification factor of the preamplifier circuit 110 when the temperature rises, and is amplified by the preamplifier circuit 110 against temperature change. The amplitude of the sensor voltage can be maintained almost constant. In the present embodiment, the rate of change of the amplitude of the sensor voltage amplified by the preamplifier circuit 110 with respect to the temperature is suppressed to 1/10 or less when temperature compensation is not performed.
Since the preamplifier circuit 110 has a temperature compensation function, when the amplification factor of the amplifier circuit 120 is adjusted as described later, temperature compensation can be performed even if the amplification factor is fixed. ing.
Since the preamplifier circuit 110 uses Vcc / 2 as an offset voltage and the amplification factor is relatively small, the sensor voltage amplified by the preamplifier circuit 110 falls within 0 to Vcc.

The offset voltage adjustment circuit 130 includes a switch SW1, a counter 132, and a D / A conversion circuit 134. The output voltage of the D / A conversion circuit 134 is connected to the non-inverting input terminal of the operational amplifier 122 and determines the offset voltage of the operational amplifier 122.
The counter 132 includes a reset terminal, and a reset signal RST is applied when the power is turned on. Then, a value that becomes Vcc / 2 when converted by the D / A conversion circuit 134 is set in the counter 132. The offset adjustment circuit 130 sets the offset voltage of the operational amplifier 122 at power-on to Vcc / 2.

  The counter 132 includes a DOWN terminal and an UP terminal. When a pulse signal is input to the DOWN terminal, the count value decreases, and when the pulse signal is input to the UP terminal, the count value increases. The switch SW1 switches whether the pulse wave CLK that is inverted at a predetermined time interval is applied to the DOWN terminal or the UP terminal. If the first voltage determination unit 150 is connected to the switch SW1 and the output voltage Vm of the operational amplifier 122 is Vm> Vcc / 2, SW1 is connected to the DOWN terminal. As a result, the count value of the counter 132 decreases, the offset voltage of the operational amplifier 122 decreases, and the output voltage Vm of the operational amplifier 122 decreases to approach Vcc / 2. If the output voltage Vm of the operational amplifier 122 is Vm <Vcc / 2, SW1 is connected to the UP terminal. As a result, the count value of the counter 132 increases, the offset voltage of the operational amplifier 122 increases, and the output voltage Vm of the operational amplifier 122 increases to approach Vcc / 2. The offset voltage adjustment circuit 130 adjusts the offset voltage Voff until the output voltage Vm of the operational amplifier 122 becomes Vcc / 2 belonging to the intermediate band of the operating voltage range.

The inverting input terminal of the operational amplifier 122 is connected to the output terminal of the operational amplifier 121 through resistors 25R, 15R, and 10R. The output terminal of the operational amplifier 122 is connected to the inverting input terminal of the operational amplifier 122 through a feedback resistor 50Ra.
A switch terminal S1 is provided between the resistors 10R and 15R, a switch terminal S2 is provided between the resistors 15R and 25R, and a switch terminal S3 is provided between the resistor 25R and the inverting input terminal of the operational amplifier 122. ing. The switch SW2 connects the output terminal of the operational amplifier 122 to any one of the switch terminals S1, S2, and S3.
When the switch SW2 is in contact with the switch terminal S1, the amplification factor of the operational amplifier 121 is 50Ra / 10R, which is the maximum amplification factor. When the switch SW2 is in contact with the switch terminal S2, the amplification factor of the operational amplifier 122 is 50Ra / (10R + 15R), which is an intermediate amplification factor. When the switch SW2 is in contact with the switch terminal S3, the amplification factor of the operational amplifier 121 is 50 Ra / (10R + 15R + 25R), which is the minimum amplification factor.

As shown in FIG. 2, the amplification factor adjustment circuit 140 includes a reset terminal, and a reset signal RST is applied when the power is turned on. Then, the amplification factor adjustment circuit 140 sends an amplification factor adjustment signal S to the switch SW2, and switches the switch SW2 to a state where it is in contact with the switch terminal S1. Until the offset voltage Voff is adjusted and the amplified voltage Vm becomes Vcc / 2, the amplification factor of the operational amplifier 122 is maintained at the maximum value.
Until the amplified voltage Vm amplified at the maximum amplification factor of the operational amplifier 122 reaches Vcc / 2, the hold voltage stored in the peak hold circuit 160p and the bottom hold circuit 160b is fixed at Vcc / 2. The amplified voltage Vm is input to the peak hold circuit 160p and the bottom hold circuit 160b. When the amplified voltage Vm coincides with Vcc / 2, the peak hold circuit 160p starts updating the peak hold voltage Vp, and the bottom hold circuit 160b starts updating the bottom hold voltage Vb. While the amplified voltage Vm of the operational amplifier 122 first rises, the rise width from Vcc / 2 is calculated, and the rise width is input to the change width determination unit 145. When the increase width exceeds a predetermined width, the change width determination unit 145 sends an amplification factor adjustment signal S to the switch SW2, switches to a state where the switch SW2 is in contact with the switch terminal S2, and sets the amplification factor of the operational amplifier 122 to 1. Step down. While the post-amplification voltage Vm of the operational amplifier 122 first falls, the fall width from Vcc / 2 is calculated, and the fall width is input to the change width determination unit 145. When the fall width exceeds a predetermined width, the change width determination unit 145 sends an amplification factor adjustment signal S to the switch SW2, switches the switch SW2 to a state where it is in contact with the switch terminal S2, and sets the amplification factor of the operational amplifier 122 to 1. Step down.
In conjunction with the reduction of the amplification factor by one step, both the peak hold voltage Vp of the peak hold circuit 160p and the bottom hold voltage Vb of the bottom hold circuit 160b are made equal to the post-amplification voltage Vm after the amplification factor reduction.
The above processing is repeated after the switch SW2 is switched to the state where it is in contact with the switch terminal S2. When the rising width from the minimum value (corrected to the value corresponding to the gain of the switch terminal S2) exceeds a predetermined width, the gain adjustment signal S is sent to the switch SW2, and the switch SW2 comes into contact with the switch terminal S3. The gain of the operational amplifier 122 is further reduced by one step. In conjunction with this, both the peak hold voltage Vp of the peak hold circuit 160p and the bottom hold voltage Vb of the bottom hold circuit 160b are made equal to the amplified voltage Vm by the amplification factor corresponding to the switch terminal S3. When the descending width from the maximum value (corrected to the value corresponding to the amplification factor of the switch terminal S2) exceeds a predetermined width, the amplification factor adjustment signal S is sent to the switch SW2, and the switch SW2 contacts the switch terminal S3. The gain of the operational amplifier 122 is reduced by one step. In conjunction with this, both the peak hold voltage Vp of the peak hold circuit 160p and the bottom hold voltage Vb of the bottom hold circuit 160b are made equal to the amplified voltage Vm by the amplification factor corresponding to the switch terminal S3. The amplification factor of the operational amplifier 122 is adjusted to the maximum amplification factor that satisfies the constraint that the change width of the amplified voltage Vm of the operational amplifier 122 does not exceed a predetermined width.

FIG. 4 is an explanatory diagram showing the internal configuration of the peak hold circuit 160p and the bottom hold circuit 160b.
The peak hold circuit 160p includes a comparator 161, two AND circuits 162 and 163, a counter 164, and a D / A conversion circuit 165. The counter 164 includes a reset terminal, and a reset signal RST is applied when the power is turned on. Then, a value that becomes Vcc / 2 when converted by the D / A conversion circuit 165 is set in the counter 164. The peak hold circuit 160p sets the peak hold voltage when power is turned on to Vcc / 2.
The peak hold circuit 160p includes an amplified voltage Vm, two clock signals CLK1 and CLK2, a reset signal RST, a signal indicating the offset voltage Voff from the offset adjustment circuit 130, and an amplification from the amplification factor adjustment circuit 140. A signal indicating the rate is input.
The clock signal CLK1 is a short cycle clock signal, and the clock signal CLK2 is a long cycle clock signal. The clock signal CLK2 is obtained by processing the clock signal CLK1 with a frequency dividing circuit. The peak hold circuit 160p outputs a peak hold voltage Vp.

  The amplified voltage Vm is input to the non-inverting input terminal of the comparator 161. The peak hold voltage Vp is input to the inverting input terminal of the comparator 161. A high voltage is output to the output terminal of the comparator 161 when the amplified voltage Vm> the peak hold voltage Vp. The output voltage of the comparator 161 is input to one terminal of the AND circuit 162. The clock signal CLK1 is input to the other of the AND circuit 162. While the amplified voltage Vm> the peak hold voltage Vp is established, the clock signal CLK1 is output to the output terminal of the AND circuit 162. The output terminal of the AND circuit 162 is connected to the UP terminal of the counter 164. While the post-amplification voltage Vm> the peak hold voltage Vp is established, the count value of the counter 164 increases in a short cycle. The clock signal CLK1 is set to a short cycle that provides a relationship of increasing speed of count value> rising speed of the amplified voltage Vm. While the post-amplification voltage Vm> the peak hold voltage Vp is established, the count value of the counter 164 increases following the increase of the post-amplification voltage Vm. When the amplified voltage Vm rises, the peak hold voltage Vp also increases following it. When the amplified voltage Vm starts to drop, the clock signal CLK1 does not appear at the output terminal of the AND circuit 162, and the peak hold voltage Vp is held. As a result, the peak hold voltage Vp is obtained by storing the maximum value of the amplified voltage Vm.

FIG. 6 (1) shows a case where the amplified voltage Vm that periodically changes gradually decreases. When the environmental temperature changes, or when the rotating body 10 rotates eccentrically and the gap δ gradually increases following the rotation of the rotating body 10, a phenomenon in which the amplified voltage Vm gradually decreases occurs. There is.
In the case of FIG. 6, three maximum values p1, p2, and p3 are illustrated. p1>p2> p3. The normal peak hold circuit does not update the peak hold voltage Vp from p1 to p2 because it is smaller than the held maximum value p1 even if it takes the second maximum value p2. However, when the amplified voltage Vm that periodically changes is binarized based on the periodic change, it is necessary to update the maximum value and the minimum value at that time.

The peak hold circuit 160p has a function of updating the local maximum value to the local maximum value when the local maximum value decreases.
As shown in FIG. 4, the output terminal of the comparator 161 is inverted and then input to one terminal of the AND circuit 163. The clock signal CLK2 is input to the other terminal of the AND circuit 163. Since the output terminal of the comparator 161 becomes high when the amplified voltage Vm> the peak hold voltage Vp, the inverted signal becomes high when the amplified voltage Vm <the peak hold voltage Vp. When the amplified voltage Vm <the peak hold voltage Vp, the clock signal CLK2 is output to the output terminal of the AND circuit 163. The output terminal of the AND circuit 163 is connected to the DOWN terminal of the counter 164. While the amplified voltage Vm <the peak hold voltage Vp, the count value of the counter 164 decreases in a long cycle. The clock signal CLK2 is set to a long cycle in which the count value gradually decreases. While the amplified voltage Vm <the peak hold voltage Vp, the count value of the counter 164 gradually decreases, and the peak hold voltage Vp gradually decreases. However, the rate of decrease is slow. Even if the threshold voltage for binarizing the amplified voltage Vm is calculated from the peak hold voltage Vp, the peak hold voltage Vp gradually decreases so that the binarization result is not affected. Is set. The purpose of peak hold by the peak hold circuit 160p is obtained. However, as shown in FIG. 6 (1), when the amplified voltage Vm gradually decreases, a relationship smaller than the next maximum value is obtained. Therefore, when the local maximum value decreases for each period, the peak hold circuit 160p is updated to the local maximum value for each period.
The peak hold circuit 160p captures the maximum value of each cycle even when the rotating body 10 rotates eccentrically and the output voltage Vin of the sensor undulates.

The bottom hold circuit 160b includes a comparator 161a, two AND circuits 162 and 163, a counter 164a, and a D / A conversion circuit 165. The counter 164a has a reset terminal, and a reset signal RST is applied when the power is turned on. Then, a value which becomes Vcc / 2 when converted by the D / A conversion circuit 165 is set in the counter 164a. The bottom hold circuit 160b sets the bottom hold voltage Vb at power-on to Vcc / 2.
The bottom hold circuit 160 p includes an amplified voltage Vm, two clock signals CLK 1 and CLK 2, a reset signal RST, a signal indicating the offset voltage Voff from the offset adjustment circuit 130, and an amplification from the amplification factor adjustment circuit 140. A signal indicating the rate is input.

  The amplified voltage Vm is input to the inverting input terminal of the comparator 161a. The bottom hold voltage Vb is input to the non-inverting input terminal of the comparator 161a. A high voltage is output to the output terminal of the comparator 161a when the amplified voltage Vm <the bottom hold voltage Vb. The output voltage of the comparator 161 a is input to one terminal of the AND circuit 162. The clock signal CLK1 is input to the other of the AND circuit 162. While the amplified voltage Vm <the bottom hold voltage Vb, the clock signal CLK1 is output to the output terminal of the AND circuit 162. The output terminal of the AND circuit 162 is connected to the DOWN terminal of the counter 164a. While the amplified voltage Vm <the bottom hold voltage Vb, the count value of the counter 164a decreases in a short cycle. The clock signal CLK1 is set to have a short period in which the relationship of the decrease rate of the count value> the decrease rate of the amplified voltage Vm is obtained. While the amplified voltage Vm <the bottom hold voltage Vb, the count value decreases following the decrease of the amplified voltage Vm. When the amplified voltage Vm decreases, the bottom hold voltage Vb also follows and decreases. When the amplified voltage Vm starts to rise, the clock signal CLK1 does not appear at the output terminal of the AND circuit 162, and the bottom hold voltage Vb is held. As a result, the bottom hold voltage Vb is obtained by storing the minimum value of the amplified voltage Vm.

FIG. 6 (2) shows a case where the amplified voltage Vm that periodically changes gradually increases. When the environmental temperature changes, or when the rotating body 10 rotates eccentrically and the gap δ gradually narrows following the rotation of the rotating body 10, a phenomenon in which the amplified voltage Vm gradually increases occurs. There is.
In the case of FIG. 6, three minimum values b1, b2, and b3 are illustrated. b1 <b2 <b3. The normal bottom hold circuit does not update the bottom hold voltage Vb from b1 to b2 because it is larger than the held minimum value b1 even when the second minimum value b2 is reached. However, when the amplified voltage Vm that periodically changes is binarized based on the periodic change, it is necessary to update the maximum value and the minimum value at that time.

The bottom hold circuit 160b has a function of updating to a minimum value in each cycle when the minimum value increases.
As shown in FIG. 4, the output terminal of the comparator 161 a is inverted and then input to one terminal of the AND circuit 163. The clock signal CLK2 is input to the other terminal of the AND circuit 163. Since the output terminal of the comparator 161a becomes high when the amplified voltage Vm <the bottom hold voltage Vb, the inverted signal becomes high when the amplified voltage Vm> the bottom hold voltage Vb. When the amplified voltage Vm> bottom hold voltage Vb, the clock signal CLK2 is output to the output terminal of the AND circuit 163. The output terminal of the AND circuit 163 is connected to the UP terminal of the counter 164a. While the amplified voltage Vm> the bottom hold voltage Vb, the count value of the counter 164a increases in a long cycle. The clock signal CLK2 is set to a long cycle in which the count value rises gently. While the amplified voltage Vm> the bottom hold voltage Vb, the count value of the counter 164a gradually increases, and the bottom hold voltage Vb increases gently. However, the increase rate is slow, and even if the threshold voltage for binarizing the amplified voltage Vm is calculated from the bottom hold voltage Vb, the bottom hold voltage Vb gradually increases so that the binarization result is not affected. Is set. The purpose of bottom-holding by the bottom-hold circuit 160b is obtained. However, as shown in FIG. 6 (2), when the post-amplification voltage Vm rises gently, a relationship that becomes larger than the next minimum value is obtained. Therefore, when the minimum value increases every period, the bottom hold circuit 160b is updated to the minimum value of each period.
The bottom hold circuit 160b captures the minimum value of each cycle even when the rotating body 10 rotates eccentrically and the output voltage Vin of the sensor undulates.

Even when the maximum value is lowered by artificially decreasing the peak hold voltage Vp, the technique for capturing the maximum value of each cycle and the minimum value is increased by artificially increasing the bottom hold voltage Vb. Even in the case of going on, the technique described in Japanese Patent Application No. 2008-244369 may be used as a technique for capturing the minimum value of each cycle.
In this technique, as shown in FIG. 5, the peak hold voltage Vp is artificially reduced at a timing immediately before the next maximum value. Thereby, even when the local maximum value decreases, the local maximum value of each cycle can be captured. Note that the operation of binarizing the amplified voltage Vm by determining the threshold voltage from the maximum value and the minimum value is performed prior to artificially reducing the peak hold voltage Vp. Does not affect binarization.
Similarly, the bottom hold voltage Vb is artificially increased at the timing immediately before the next minimum value. Thereby, even when the local minimum value increases, the local minimum value of each cycle can be captured. Note that the operation of binarizing the amplified voltage Vm by determining the threshold voltage from the maximum value and the minimum value is performed prior to artificially increasing the bottom hold voltage Vb. Does not affect binarization.

  As shown in FIG. 2, the peak hold circuit 160p and the bottom hold circuit 160b receive a signal that instructs the offset voltage Voff from the offset voltage adjustment circuit 130. If the offset voltage adjustment circuit 130 corrects the offset voltage Voff of the amplifier circuit 120, the value of the amplified voltage Vm changes accordingly. If the peak hold circuit 160p and the bottom hold circuit 160b continue to hold the hold values so far, the peak hold voltage and the bottom hold voltage of the amplified voltage when using the new offset voltage Voff are shifted. Therefore, when a signal instructing the offset voltage Voff is input from the offset voltage adjustment circuit 130 to the peak hold circuit 160p and the bottom hold circuit 160b, the peak hold circuit 160p and the bottom hold circuit 160b Change the hold voltage to the value for the new offset voltage. The peak hold circuit 160p and the bottom hold circuit 160b include counters 164 and 164a, and the held values can be reset by signal processing from the outside.

  As shown in FIG. 2, the peak hold circuit 160p and the bottom hold circuit 160b are input with a signal indicating the amplification factor from the amplification factor adjustment circuit 140. If the amplification factor adjustment circuit 140 corrects the amplification factor of the amplification circuit 120, the value of the amplified voltage Vm changes accordingly. If the peak hold circuit 160p and the bottom hold circuit 160b continue to hold the hold values so far, the maximum value and the minimum value of the amplified voltage Vm when using the new amplification factor are shifted. Therefore, when a signal indicating the amplification factor is input from the amplification factor adjustment circuit 140 to the peak hold circuit 160p and the bottom hold circuit 160b, the peak hold circuit 160p and the bottom hold circuit 160b are connected to the current peak hold voltage and bottom hold circuit 160b. The voltage is matched with the voltage amplified by the new amplification factor. The peak hold circuit 160p and the bottom hold circuit 160b include counters 164 and 164a, and the held values can be reset by signal processing from the outside.

7 and 8 are flowcharts showing the contents of the processing routine executed by the sensor voltage processing circuit 100 of the first embodiment. 9 and 10 are diagrams for explaining a phenomenon caused by the processing.
7 and 8 are executed when the power is turned on. When the power is turned on, first, the amplification factor of the amplifier circuit 120 is set to the maximum state (S4). That is, the switch SW2 in FIG. 3 is switched to a state in which it is in contact with the switch terminal S1. Next, the hold voltage of the peak hold circuit 160p is set to Vcc / 2, and the update process is stopped (S6). Similarly, the hold voltage of the bottom hold circuit 160b is set to Vcc / 2, and the update process is stopped (S8). Then, the offset voltage of the amplifier circuit 120 is set to Vcc / 2 (S10). The above setting state is shown at timing t1 in FIG.

Next, the amplified voltage Vm is compared with Vcc / 2 (S12). If Vm> Vcc / 2, the offset voltage is treated as too high, and the offset voltage Voff is lowered by a predetermined width (S14). The process is repeated. If the initially set offset voltage of Vcc / 2 is too high, the processes of steps S12 and S14 are repeated, and the offset voltage Voff is lowered until the amplified voltage Vm drops to Vcc / 2.
If the initially set offset voltage of Vcc / 2 is too low, step S16 becomes yes. In this case, if the offset voltage is too low, the offset voltage Voff is increased by a predetermined width (S18). The process is repeated. If the initially set offset voltage of Vcc / 2 is too low, the processes of steps S16 and S18 are repeated and the offset voltage Voff is increased until the amplified voltage Vm rises to Vcc / 2.
FIG. 9 illustrates the case where the offset voltage of Vcc / 2 that was initially set is too high.
The case where it is corrected after that and adjusted to the offset voltage that realizes the relationship of the amplified voltage Vm = Vcc / 2 at timing t2 is illustrated. Thus, the initial adjustment of the offset voltage is completed.

When the offset voltage Voff is corrected and the amplified voltage Vm coincides with Vcc / 2 (timing t2 in FIG. 9), step S16 becomes no and the processing after step S20 is performed. In step S20, update processing of the voltage Vp held by the peak hold circuit 160p and update processing of the voltage Vb held by the bottom hold circuit 160b are started.
As shown in FIG. 9, until the timing t2, the peak hold circuit 160p and the bottom hold circuit 160b hold the voltage of Vcc / 2. If the amplified voltage Vm coincides with Vcc / 2 at timing t2 and then the amplified voltage Vm decreases, the bottom hold voltage Vb is updated and decreased. The peak hold voltage is held at Vcc / 2.
Although not shown, if the amplified voltage Vm coincides with Vcc / 2 at timing t2 and then the amplified voltage Vm increases, the peak hold voltage Vp is updated and increased. The bottom hold voltage is held at Vcc / 2.

In step S22, the change width from the peak hold voltage Vp or the bottom hold voltage Vb thus updated to the current post-amplification voltage Vm is compared with a predetermined width.
In this embodiment, the minimum value of the amplitude of the sensor voltage amplified by the preamplifier circuit 110 observed when the rotator 10 rotates is preamplified when the rotator 10 oscillates. The amplitude of the sensor voltage amplified by the circuit 110 is larger than the maximum value. ΔV1 included in the expression for determining the value to be compared in step S22 is smaller than the minimum value of the amplitude of the sensor voltage amplified by the preamplifier circuit 110 observed when the rotating body 10 rotates. The amplitude of the sensor voltage amplified by the preamplifier circuit 110 observed when the rotating body 10 vibrates is larger than the maximum value. If step S22 is YES, it can be said that rotational motion is detected, and if step S22 is NO, it can be said that rotational motion is not detected.
Since the amplification factor of the preamplifier circuit 110 is constant, the value of ΔV1 is constant. The post-amplification voltage Vm to be compared is amplified by the amplifier circuit 120. Therefore, in step S22, a comparison is made with a value obtained by multiplying ΔV1 by the amplification factor of the amplifier circuit 120 (in this case, the maximum amplification factor).

When a rotational motion is detected in step S22, binarization processing is started (S23). When the binarization process starts in step S23, the binarization process is continuously performed repeatedly at short time intervals thereafter.
While the binarized signal has not yet been inverted three times, the answer is no in step S24. The reason why the number of rotations is three times is to reliably determine that the rotating body 10 has started rotating. Until it is determined that the rotating body 10 has started rotating, the adjustment process of the amplification factor is performed.
In step S26, the change width from the updated peak hold voltage Vp or bottom hold voltage Vb to the current post-amplification voltage Vm is compared with a predetermined value. Here, it is determined whether or not a necessary change width is obtained in relation to the operating voltage range (0 to Vcc) of the circuit.
ΔV2 to be compared in step S26 is a value determined in relation to the operating voltage range (0 to Vcc) of the circuit and does not need to be multiplied by the amplification factor.

If the change width from the updated peak hold voltage Vp or bottom hold voltage Vb to the current post-amplification voltage Vm exceeds a predetermined width ΔV2 (in the case of YES in S26), it is treated as an amplification factor larger than necessary. The amplification factor is lowered by one step (S28). In this case, in accordance with the switching of the amplification factor, the peak hold circuit 160p and the bottom hold circuit 160b match the peak hold voltage Vp and the bottom hold voltage Vb with the voltage Vm amplified by the reduced amplification factor (S30). In step S20, the update process of the peak hold voltage Vp and the bottom hold voltage Vb is started, and the update process of the peak hold voltage Vp and the bottom hold voltage Vb is continued even after the execution of step S30. In the case of FIG. 9, step S26 is YES while the amplified voltage Vm is increasing, the amplification factor is reduced, and the amplified voltage Vm due to the reduced amplification factor is increased again. As a result, the peak hold voltage Vp is updated. When the amplified voltage Vm drops from the peak hold voltage Vp beyond a predetermined width, the amplified voltage Vm is lower than the bottom hold voltage Vb. That is, while the bottom hold voltage Vb is updated following the decrease in the amplified voltage Vm, the amplified voltage Vm decreases from the maximum value Vp beyond a predetermined width. At this time, the amplified voltage Vm = bottom hold voltage Vb. Although not shown in FIG. 9, when step S26 is YES and the amplification factor is reduced while the amplified voltage Vm is decreasing, the amplified voltage Vm due to the reduced amplification factor decreases again. As a result, the bottom hold voltage Vb is updated. When the amplified voltage Vm rises from the bottom hold voltage Vb beyond a predetermined width, the amplified voltage Vm exceeds the peak hold voltage Vp so far. That is, while the peak hold voltage Vp is updated following the increase of the amplified voltage Vm, the amplified voltage Vm increases from the minimum value Vb beyond a predetermined width. At this time, the amplified voltage Vm = the peak hold voltage Vp. In step S30, when the peak hold voltage Vp and the bottom hold voltage Vb are made to coincide with the voltage Vm amplified by the amplification factor after reduction, the peak hold voltage Vp and the bottom hold voltage Vb are reached before the required timing is reached. The voltage Vp is updated to the maximum value, and the bottom hold voltage Vb is updated to the minimum value.
Instead, the peak hold voltage p and the bottom hold voltage Vb may be updated by the method shown in claim 3.
After executing Steps S28 and S30, the process returns to Step S22. By proceeding to S22 again, it is possible to prevent an edge from being erroneously detected due to noise. The value of ΔV1 is set to a size that does not cause detection errors due to noise.

  In the case of FIG. 9, the case where the amplified voltage Vm takes the minimum value at the timing t3 and then increases is illustrated. The timing at which the increasing amplified voltage Vm is changed by a predetermined width ΔV2 from the immediately preceding minimum value at timing t4 is illustrated. In this case, the amplification factor is lowered by one step at timing t4, and the voltage Vm after amplification decreases accordingly, and the peak hold voltage Vp and the bottom hold voltage Vb are made to coincide with the voltage Vm after amplification following that. Show.

According to the process of FIG. 7, step S26 and step S28 are repeated, and step S24 becomes YES while the amplification factor is reduced from the maximum value one step at a time. If step S24 is YES, the amplification factor at that time is fixed, and thereafter, the amplification factor of the amplifier circuit 120 is not adjusted.
When step S24 becomes YES, the adjustment process of the offset voltage and amplification factor of the amplifier circuit 120 is completed.

  The process of FIG. 8 shows a process while the adjustment process of the offset voltage and the amplification factor of the amplifier circuit 120 is completed and the rotation is detected. Also during this time, the update process of the peak hold voltage Vp and the bottom hold voltage Vb started in step S20 and the binarization process started in step S23 are continued. The process of dividing the peak hold voltage Vp and the bottom hold voltage Vb of the amplified voltage Vm to obtain the threshold voltage Vref and binarizing the amplified voltage Vm from the magnitude relationship between the threshold voltage Vref and the amplified voltage Vm is as follows. This is described in Japanese Patent Application Laid-Open No. 2009-192529, and redundant description is omitted.

  In step S34, it is determined whether or not all of the updated peak hold voltage Vp, bottom hold voltage Vb, and amplified voltage Vm are within the operating voltage range (within 0 to Vcc). If it is within the operating voltage range, the binarization process is continued. If any of the amplified voltage Vm, the peak hold voltage Vp, and the bottom hold voltage Vb has reached the limit of the operating voltage range (0 to Vcc range), the offset voltage is adjusted by the offset voltage adjustment circuit 130 (S36). . If the upper limit of the operating voltage range is reached, the offset voltage is lowered, and if the lower limit of the operating voltage range is reached, the offset voltage is raised. The peak hold voltage Vp stored in the peak hold circuit 160p and the bottom hold voltage Vb stored in the bottom hold circuit 160b are corrected in accordance with the adjustment of the offset voltage. However, the offset voltage adjustment width, the peak hold voltage Vp adjustment width, and the bottom hold voltage Vb correction width do not match. This is because the adjustment width of the offset voltage amplified by the amplifier circuit 120 becomes the adjustment amount of the peak hold voltage Vp and the bottom hold voltage Vb.

  Since the offset voltage of the amplifier circuit 120 is adjusted, a wider voltage adjustment range can be secured as compared with the case where the amplified voltage of the amplifier circuit 120 is adjusted. In addition, a fine adjustment width is not required as compared with the case of adjusting the offset voltage of the preamplifier circuit 110, and a D / A converter with a small number of bits can be used.

FIG. 10 illustrates a phenomenon that occurs in the processing of FIGS. 7 and 8. The solid line in (a) shows the amplified voltage Vm, the solid line in (b) shows the peak hold voltage Vp, the broken line in (b) shows the bottom hold voltage Vb, and the broken line in (a) shows the peak hold voltage Vp. And (b) shows the binarization result, and (e) shows the change in the amplification factor.
At timings t0 to t1, the rotating body is not rotating, is slightly oscillating, and the amplitude of the amplified voltage Vm amplified at the maximum amplification factor Gmax is small.
The timing t1 illustrates the timing at which the fluctuation range of the amplified voltage Vm from the peak hold voltage Vp changes more than the maximum value of the amplitude of the amplified voltage that occurs during the oscillating motion of the rotating body. That is, the timing when a voltage fluctuation range that is so large that it cannot be observed unless the rotating body rotates is illustrated.
Timing T1 indicates the timing when the fluctuation range of the voltage Vm amplified at the amplification factor Gmax from the peak hold voltage Vp becomes larger than the predetermined width ΔV2, and the amplification factor is reduced from Gmax to G1. When both the bottom voltage and the peak voltage of the amplified voltage Vm when the amplification factor is Gmax are found and the amplitude at that time is found, the amplification factor can be reduced. The amplification factor is reduced from Gmax to G1 when the fluctuation width from the peak hold voltage Vp becomes the predetermined width ΔV2 without waiting for the amplitude when Gmax is equal to Gmax. The time until the amplification factor is adjusted to an appropriate value is shortened. At timing T1 when the amplification factor is reduced from Gmax to G1, the bottom hold voltage Vb and the peak hold voltage Vp are made to coincide with the voltage Vm amplified with the amplification factor of G1.
Timing T2 indicates a timing at which the fluctuation range of the voltage Vm amplified at the amplification factor G1 from the bottom hold voltage Vb becomes larger than the predetermined width ΔV2, and the amplification factor is reduced from G1 to G2. Without waiting for the amplitude of the amplified voltage Vm when the amplification factor is set to G1, the amplification factor is reduced from G1 to G2 when the fluctuation range from the bottom hold voltage Vp becomes a predetermined width ΔV2. . The time until the amplification factor is adjusted to an appropriate value is shortened. At timing T2, the bottom hold voltage Vb and the peak hold voltage Vp are made to coincide with the voltage Vm amplified with the amplification factor of G2, in conjunction with the reduction of the amplification factor.
Timings t2, t3,... Indicate the inversion timing of the binarized signal. After the amplified voltage Vm changes from the maximum value or the minimum value stored in the extreme value storage circuit 160 beyond the maximum value of the amplitude of the amplified voltage caused by the vibration phenomenon of the rotating body (timing t1). The amplification factor reduction process is continued until the output of the binarization circuit is inverted three times (until timing t4). If the output of the binarization circuit is inverted three times, the amplification factor at that time is fixed.
If the output of the binarization circuit is inverted three times after the start of the rotational motion, the amplified voltage changes from the maximum value to the minimum value during that time, so even if the amplification factor is not reduced further, It is guaranteed that the amplified voltage Vm with the amplification factor adjusted to be within the operating range. If the output of the binarization circuit is inverted three times, it can be said that further adjustment processing of the amplification factor is unnecessary.

After completion of the adjustment of the amplification factor, the amplified voltage Vm may reach the limit of the operating voltage range for some reason. Timing T3 illustrates the case where the amplified voltage Vm rises to the upper limit voltage Vcc of the operating voltage range for some reason. In this case, it has been found that the amplified voltage Vm can be returned to the operating voltage range simply by adjusting the offset voltage, and it has been found that there is no need to reduce the amplification factor. In this case, the peak hold voltage Vp stored in the peak hold circuit 160p and the bottom hold voltage Vb stored in the bottom hold circuit 160b may be corrected in accordance with the adjustment of the offset voltage Voff. The process of FIG. 8 implements this process.
At timing T1 when the fluctuation range of the amplified voltage Vm from the peak hold voltage Vp becomes larger than the predetermined width ΔV2, the amplified voltage Vm = bottom hold voltage Vb. Therefore, in this embodiment, instead of comparing the difference between the amplified voltage Vm and the peak hold voltage Vp with the predetermined width ΔV2, the difference between the peak hold voltage Vp and the bottom hold voltage Vb is compared with the predetermined width ΔV2. . At timing T2, the amplified voltage Vm = the peak hold voltage Vp. The same result can be obtained by comparing the difference between the peak hold voltage Vp and the bottom hold voltage Vb with the predetermined width ΔV2 instead of comparing the difference between the amplified voltage Vm and the bottom hold voltage Vb with the predetermined width ΔV2. it can. In step S26 of FIG. 7, Vp−Vb> ΔV2? It is good.

In this embodiment, the amplification factor is first set to the maximum value. When the change width of the amplified voltage Vm becomes equal to or larger than a predetermined width set in relation to the operating voltage range, the amplification factor is reduced. This process is repeated until a rotational motion is observed a predetermined number of times.
According to the present embodiment, it is not set to an amplification factor that amplifies a weak voltage change accompanying vibration of the rotating body until an appropriate amplitude is obtained. If the amplification factor is adjusted by a weak voltage change accompanying vibration, it will be set to an excessive amplification factor for the voltage change accompanying rotation, and it is necessary to adjust the amplification factor again at the stage when the rotational motion starts. It is necessary to adjust the amplification factor again if necessary. In this embodiment, the amplification factor is adjusted to an appropriate amplification factor when the rotating body starts rotating immediately after the power is turned on, and it is not necessary to determine whether or not readjustment is necessary. No readjustment is required.

FIG. 11 shows a modification of the processing procedure of FIG. The same processes as those in FIG. 7 are denoted by the same step numbers, and redundant description is omitted.
In the process of FIG. 11, step S26a is performed first, and step S22a is performed later. That is, in step S26a, the change width from the previous peak hold voltage or bottom hold voltage to the current amplified voltage Vm is compared with a predetermined width. If it is above, the amplification factor is lowered (S28a). Thereafter, the peak hold voltage Vp and the bottom hold voltage Vb are made to coincide with the voltage Vm amplified by the post-reduction amplification factor (S30a). Thereafter, it is determined whether or not a rotational motion is detected (S22a). The amplification factor adjustment process is repeated until the inversion phenomenon accompanying the rotational motion is detected three times. Even in this case, the amplification factor is adjusted to an appropriate value within a short time. The procedure of FIG. 11 deals with a case where the adjustment starts from the maximum amplification factor that is set excessively. If there is a possibility that the maximum amplification factor to be used first is an appropriate value, the process proceeds to the determination process in step S22a when NO is determined in step S26a.

B. Sensor voltage processing circuit according to the second embodiment of the present invention:
B-1. Configuration of sensor voltage processing circuit according to second embodiment of the present invention:
FIG. 12 shows a rotation detection system of the second embodiment, which includes a rotating body 10a, two sensors 11a and 11b, and a sensor voltage processing circuit 200.
The rotating body 10a can rotate forward and backward, and the sensor voltage processing circuit 200 can also detect the rotation direction. The two sensors 11a and 11b are arranged at positions shifted by an angle α with respect to the rotation center of the rotating body 10a. The angle α is different from the angle β that one tooth 10ta stretches. As shown in FIG. 13, when the rotating body 10a is rotating forward, the output voltage Va of the sensor 11a changes faster than the output voltage Vb of the sensor 11b. For example, the timing at which Va starts to increase from the minimum value is earlier than the timing at which Vb starts to increase from the minimum value. That is, if the binary signal of Va is high at the timing when the binary signal of Vb is inverted to high, it can be determined that the rotating body 10a is rotating forward. When the rotating body 10a rotates in the reverse direction, the output voltage Va of the sensor 11a changes later than the output voltage Vb of the sensor 11b. For example, the timing at which Va starts to increase from the minimum value is later than the timing at which Vb starts to increase from the minimum value. That is, if the signal that binarizes Va is low at the timing when the signal that binarizes Vb is inverted to high, it can be determined that the rotating body 10a is rotating in reverse.

  The sensor voltage processing circuit 200 includes two sensor voltage processing units 100a and 100b, a rotation direction determination circuit 180, and a ternary signal output circuit 190. Each of the two sensor voltage processing units 100a and 100b has the same configuration as the sensor voltage processing circuit 100 of the first embodiment. The offset voltage and amplification factor are adjusted in the same manner as in the first embodiment.

B-2. Operation of the sensor voltage processing circuit according to the second embodiment of the present invention:
FIG. 13B shows how the output voltage Va of the sensor 11a and the output voltage Vb of the sensor 11b change. The left half in the figure shows the case where the rotating body 10a is rotating forward, and the right half shows the case where it is rotating backward. As described above, when the rotating body 10a is rotating forward, the output voltage Va of the sensor 11a changes faster than the output voltage Vb of the sensor 11b. When the rotating body 10a rotates in the reverse direction, the output voltage Va of the sensor 11a changes later than the output voltage Vb of the sensor 11b.

  The sensor voltage processing unit 100a binarizes the sensor voltage Va of the sensor 11a based on the intermediate value between the maximum value and the minimum value of Va, and generates a binarized signal Sa (see (3)). The sensor voltage processing unit 100b binarizes the sensor voltage Vb of the sensor 11b based on an intermediate value between the maximum value and the minimum value of Vb, and generates a binarized signal Sb (see (4)). As can be seen from FIG. 13, the binarized signal Sa and the binarized signal Sb have a phase difference, and the sign of the phase difference varies depending on the rotation direction.

  The rotation direction determination circuit 180 determines the rotation direction based on the sign of the phase difference between the binarized signal Sa and the binarized signal Sb. Specifically, whether the binarized signal Sa is high or low is determined at the rising edge of the binarized signal Sb. If the binarized signal Sa is high at the rising edge of the binarized signal Sb, the rotation direction determining circuit 180 determines that the rotation is normal (see time T1a). If the binarized signal Sa is low at the rising edge of the binarized signal Sb, it is determined as reverse rotation (see time T2a).

  The rotation direction determination circuit 180 and the ternary signal output circuit 190 are connected by two signal lines. The binary signal Sa is output to Sa1 during forward rotation (see (5)) and binarized during reverse rotation. The signal Sa is output to Sa2 (see (6)). Hereinafter, Sa1 may be referred to as a forward rotation pulse, and Sa2 may be referred to as a reverse rotation pulse. When the positive rotation pulse Sa1 is input, the ternary signal output circuit 190 outputs an output voltage Vout that is 0 v while the positive rotation pulse Sa1 is high and Vcc while the low rotation pulse Sa1 is low. When the reverse rotation pulse Sa2 is input, the output voltage Vout is Vcc / 2 while the reverse rotation pulse Sa2 is high and Vcc while the low rotation pulse Sa2 is low (see (7)).

  In the rotation detection system of the second embodiment, it can be determined whether the rotating body 10a is rotating or oscillating according to the amplitude of the sensor voltage Va of the sensor 11a or the sensor voltage Vb of the sensor 11b. The offset voltage and the amplification factor are adjusted to be suitable for the sensor voltages Va and Vb during rotation. This is the same as in the first embodiment.

C. Sensor voltage processing circuit according to the third embodiment of the present invention:
C-1. Configuration of sensor voltage processing circuit according to third embodiment of the present invention:
FIG. 14 shows a rotation detection system of the third embodiment, which includes a rotating body 10a, two sensors 11a and 11b, and a sensor voltage processing circuit 400.
The rotating body 10a can be rotated forward and backward. The relationship between the rotating body 10a and the sensors 11a and 11b is the same as that in the second embodiment, and a duplicate description is omitted.
The rotating body 10a rotates in the forward and reverse directions, and the center of rotation slightly vibrates in the illustrated x direction, slightly vibrates in the y direction, or slightly vibrates in the rotating direction. The sensor voltages Va and Vb output from the sensors 11a and 11b also periodically change due to the vibration, and it is determined whether the rotating body 10a is rotating or vibrating only from the amplitudes of the sensor voltages Va and Vb. Can not.

When attention is paid to the phase difference between the sensor voltages Va and Vb, the phase difference when the rotating body 10a is rotating differs from the phase difference when it vibrates. Therefore, it can be determined from the phase difference whether the rotating body 10a is rotating or vibrating.
However, when the amplitudes of the sensor voltages Va and Vb are small, since the accuracy of binarization is low, the phase difference between the binarized signals Sa and Sb when rotating and 2 when vibrating. The phase difference between the digitized signals Sa and Sb cannot be distinguished. Therefore, when discriminating by the phase difference, it is necessary to greatly amplify the amplitudes of the sensor voltages Va and Vb (amplify them to a level that enables phase discrimination described later) to discriminate the phase difference. is there.
Note that the rotation and vibration discrimination technology described below is described in Japanese Patent Application Laid-Open No. 2009-192529, and detailed description thereof is omitted. Refer to the above-mentioned publication for detailed explanation.

In FIG. 16, the vertical axis represents the amplitude of the sensor voltages Va and Vb amplified by the amplifier circuit 120, and the horizontal axis represents the phase difference between the sensor voltages Va and Vb.
A range 194 indicates a range observed when the rotating body 10a is rotating. When the rotating body 10a is rotating, the amplitude becomes VT1 or more and the phase difference is around 70 °. The phase difference is in the range of 40 ° to 110 °.
A range 192 indicates one range observed when the rotating body 10a vibrates. The phase difference is almost 0 °. A range 196 shows another range observed when the rotating body 10a vibrates. The phase difference is approximately 180 °.
However, it cannot be said that the rotating body 10a is rotating because the magnitudes of the amplitudes of the sensor voltages Va and Vb are not less than VT1. This is because even when the rotating body 10a vibrates, the amplitudes of the sensor voltages Va and Vb may become VT1 or more. However, it can be said that the rotating body 10a is rotating if the amplitudes of the sensor voltages Va and Vb are not less than VT2. You may add the process sequence which discriminate | determines whether an amplitude is more than VT2 to the discrimination procedure of rotation and vibration.
Further, since the phase difference is in the range of 40 ° to 110 °, it cannot be said that the rotating body 10a is rotating. When the amplitude is VT1 or less, the phase difference may fall within the range of 40 ° to 110 ° even when the rotating body 10a vibrates.

  If the phase difference between the sensor voltages Va and Vb can be calculated easily, rotation and vibration can be discriminated using the map of FIG. In the present embodiment, instead, the determination result is obtained at a specific timing, thereby obtaining the same determination result as the determination result by the map of FIG.

FIG. 15 shows the internal configuration of the sensor voltage processing circuit 400 of the third embodiment. The sensor voltage processing circuit 400 includes two sensor voltage processing units 100c and 100d. The sensor voltage processing unit 100c has all the functions of the sensor voltage processing unit 100a of the second embodiment, and further has additional functions. The sensor voltage processing unit 100d has all the functions of the sensor voltage processing unit 100b of the second embodiment, and further has additional functions.
The sensor voltage processing unit 100c includes a rotation / vibration determination unit 300a, and the sensor voltage processing unit 100d includes a rotation / vibration determination unit 300b. It can also be said that the rotation / vibration determination units 300a and 300b constitute a rotation / vibration determination unit 300 as shown in FIG.

FIG. 17 shows a configuration for realizing additional functions of the two sensor voltage processing units 100c and 100d. The two sensor voltage processing units 100c and 100d have the same configuration and will be described below in common.
In FIG. 17, 160p stores the peak hold voltage Vp, and 160b stores the bottom hold voltage Vb. Four voltage dividing resistors R10, R20, R30, and R40 are connected between 160p and 160b. The resistance values of the voltage dividing resistors R10, R20, R30, and R40 are all equal. Then, the values of Vu, Vref and Vd shown in the figure are as follows.
Vu = Vb + 3/4 × (Vp−Vb)
Vref = Vb + 2/4 × (Vp−Vb)
Vd = Vb + 1/4 × (Vp−Vb)

Vu and Vref are input to the first hysteresis comparator 171u. The first hysteresis comparator 171u includes a switch 172u, a comparator 173u, and an inverter 174u. The amplified sensor voltage Vm is input to the non-inverting input terminal of the comparator 173u. Either Vu or Vref is input to the inverting input terminal of the comparator 173u.
The switch 172u connects Vref to the inverting input terminal when the output terminal of the comparator 173u is inverted from low to high, and connects Vu to the inverting input terminal when the output terminal of the comparator 173u is inverted from high to low.

Du in FIG. 18A indicates the voltage at the inverting input terminal of the comparator 173u. First, assume Du = Vu. Vma represents a voltage obtained by amplifying the output voltage of the sensor 11a by the amplifier circuit 120.
Timing t12 indicates when Vma> Vu and the output of the comparator 173u is inverted from low to high. At this time, the switch 172u switches to Du = Vref. Timing t13 shows the time when Vma <Vref and the output of the comparator 173u is inverted from high to low. At this time, the switch 172u switches to Du = Vu. The voltage used as a reference for comparison by the comparator 173u changes as indicated by Du in FIG. 18A, and the output Dur of the comparator 173u changes as indicated by (B).

Vref and Vd are input to the second hysteresis comparator 171d. The second hysteresis comparator 171d includes a switch 172d, a comparator 173d, and an inverter 174d. The amplified sensor voltage Vm is input to the non-inverting input terminal of the comparator 173d. Either Vd or Vref is input to the inverting input terminal of the comparator 173d.
The switch 172d connects Vd to the inverting input terminal when the output terminal of the comparator 173d is inverted from low to high, and connects Vref to the inverting input terminal when the output terminal of the comparator 173d is inverted from high to low.

Dr in FIG. 18A indicates the voltage at the inverting input terminal of the comparator 173d. First, it is assumed that Dr = Vref. Vma represents a voltage obtained by amplifying the output voltage of the sensor 11a by the amplifier circuit 120.
Timing t11 indicates when Vma> Vref and the output of the comparator 173d is inverted from low to high. At this time, the switch 172d switches to Dr = Vd. Timing t14 shows the time when Vma <Vd and the output of the comparator 173d is inverted from high to low. At this time, the switch 172d switches to Dr = Vref. The voltage used as a reference for comparison by the comparator 173d changes as indicated by Dr in FIG. 18A, and the output Ddr of the comparator 173d changes as indicated by (C).

The output voltage Dur of the comparator 173u is supplied to the set terminal S of the flip-flop circuit 176. The output voltage Dur of the comparator 173u is inverted by the inverter 174u and supplied to the reset terminal R of the flip-flop circuit 175.
The output voltage Ddr of the comparator 173d is supplied to the set terminal S of the flip-flop circuit 175. The output voltage Ddr of the comparator 173d is inverted by the inverter 174d and supplied to the reset terminal R of the flip-flop circuit 176.

  The flip-flop circuit 175 generates the binarized signal Sa based on the voltage obtained by inverting the output voltage Dur of the comparator 173u and the output voltage Ddr of the comparator 173d. In the flip-flop circuit 175, when the voltage Ddr of the set terminal S rises from low to high (timing t11, t15, etc.), the voltage of the output terminal Sa becomes high, and the voltage of the reset terminal R (voltage obtained by inverting Dur) When rising from low to high (timing t13, t17, etc.), the voltage at the output terminal Sa goes low. As a result, the flip-flop circuit 175 generates a binarized signal Sa shown in (D). The binarized signal Sa is a signal that is inverted when the amplified sensor voltage Vma exceeds Vref.

  The flip-flop circuit 176 generates the delayed binary signal Sad based on the output voltage Dur of the comparator 173u and the voltage obtained by inverting the output voltage Ddr of the comparator 173d. In the flip-flop circuit 176, when the voltage Dur at the set terminal S rises from low to high (timing t12, t16, etc.), the voltage at the output terminal Sad becomes high and the voltage at the reset terminal R (voltage obtained by inverting Ddr) When rising from low to high (timing t14, t18, etc.), the voltage at the output terminal Sad goes low. As a result, the flip-flop circuit 176 generates a delayed binary signal Sad shown in (E). The delayed binary signal Sad is a signal that is inverted when the amplified sensor voltage Vma rises above Vu and falls below Vd. Obviously, the delayed binarized signal Sad is inverted later than the binarized signal Sa.

As shown in FIG. 15, the binarization processing unit 170a of the circuit that processes the sensor voltage Vb of the sensor 11b also generates the same type of output.
Eventually, the binarized signal Sa for the sensor 11a, its delayed binarized signal Sad, the binarized signal Sb for the sensor 11b, and its delayed binarized signal Sbd are obtained.

  The four types of inversion signals Sa, Sad, Sb, and Sbd are input to the rotation / vibration determination units 300a and 300b.

FIG. 19 shows a circuit configuration of the rotation / vibration determination units 300a and 300b. The determination timing in FIG. 19B indicates the timing for determining rotation / vibration. The determination is based on the inversion timing of the delayed binary signal. Here, the upward arrow indicates the timing of reversing to high, and the downward arrow indicates the timing of reversing to low. The target signal indicates a binary signal to be inspected at that timing. It is determined whether one of the binary signals Sa and Sb is high or low.
(1) of FIG. 19 shows the relationship between the high and low of the target signal at the determination timing and the motion state of the rotating body 10a at that time. For example, if the rotating body 10a is rotating forward, the binarized signal Sb at the timing when the delayed binarized signal Sad is inverted to high is low, and the timing at which the delayed binarized signal Sbd is inverted to high. The binarized signal Sa is high, the binarized signal Sb at the timing when the delayed binarized signal Sad is inverted to low, and the binary signal Sbd at the timing when the delayed binarized signal Sbd is inverted to low. The value signal Sa is low. If the rotating body 10a rotates in the reverse direction, the binarized signal Sb at the timing when the delayed binarized signal Sad is inverted to high is high, and 2 at the timing at which the delayed binarized signal Sbd is inverted to high. The binarization signal Sa is low, the binarization signal Sb at the timing when the delayed binarization signal Sad is inverted to low, is low, and the binarization is performed at the timing when the delay binarization signal Sbd is inverted to low Signal Sa is high. When the rotating body 10a vibrates, it differs from the pattern at the time of forward rotation, and also differs from the pattern at the time of reverse rotation.

  The timing at which the delayed binary signal Sad is inverted to high, the timing at which the delayed binary signal Sbd is inverted to high, the timing at which the delayed binary signal Sad is inverted to low, and the delayed binary signal Sbd is inverted to low. From the determination result of the timing four times, it can be determined whether the rotating body 10a is rotating forward, rotating backward, or vibrating.

  The above determination relationship corresponds to the map of FIG. Instead of detecting the phase difference between Vma and Vmb, whether the signal is rotating or not is determined according to the map shown in FIG. 16 by determining whether the binary signal is high or low at the inversion timing of the delayed binary signal. It is possible to obtain the same determination result as determining whether or not it is not.

  The logical operation circuit of FIG. 19A shows a circuit for determining whether the rotating body 10a is rotating forward, reversely rotating, or vibrating from the four determination results. . If it is rotating forward, the AND circuit 198 outputs high. If it is rotating in the reverse direction, the AND circuit 197 outputs high. The OR circuit 199 outputs high to the terminal R if the rotating body 10a is rotating in both forward and reverse rotations. If the voltage at the output terminal R of the OR circuit 199 is high, the rotating body 10a is rotating. If the voltage at the output terminal R of the OR circuit 199 is low, the rotating body 10a is not rotating.

FIG. 20 shows a processing procedure performed by the sensor voltage processing circuit of the third embodiment. The same step number is used for the same processing in the processing procedure of the first embodiment shown in FIG.
Also in the circuit of the third embodiment, the post-amplification voltage Vm is adjusted to an offset voltage having a value (Vcc / 2 in the embodiment) within the intermediate band of the circuit operating voltage range. Also, the amplification factor of the amplification circuit 120 is set to the maximum value, and the amplification factor adjustment process is started.

  In step S22b, the process waits for the amplified sensor voltage Vm to change from the previous peak hold voltage Vp or bottom hold voltage Vb by more than amplification factor × ΔV1. Here, the lower limit value is a value corresponding to VT1 in FIG. 16, and is a value at which a further voltage change is observed whenever the rotating body 10a rotates. Since the initial amplification factor is set to the maximum value, if the rotating body 10a rotates, step S22b becomes yes while step S22b is repeatedly executed. However, clearly from the map of FIG. Even if the step S22b becomes YES, it does not always mean that it is rotating. This is because even if it vibrates, the amplitude may become large.

Therefore, the distinction between rotation and vibration is determined in step S24b. Here, the motion state of the rotating body 10a is determined by the method described in FIG. Specifically, the output of the OR circuit 199 is determined.
When the rotational motion of the rotating body 10a is not detected and the output of the OR circuit 199 is low, the amplification factor reduction processing after step S26b is executed. At the same time, the peak hold voltage Vp and the bottom hold voltage Vb stored in the extreme value storage circuit are also corrected. The above is the same as the gain adjustment process described in the first embodiment, and a duplicate description is omitted. Until the rotational motion is detected in step S24b, the amplification factor reduction processing after step S26b is repeatedly executed, and when the rotational motion is detected in step S24b, the amplification factor reduction processing after step S26b is not executed. Thereby, the sensor output at the time of rotation is adjusted to an amplification factor with an appropriate amplitude.

  In this embodiment, when the determination based on the map of FIG. 16 is performed, the amplification factor is excessive or an appropriate value, and a voltage of VT1 or higher is always obtained when the engine is rotating. Further, in this embodiment, the rotation and vibration can be obtained in a state where a post-amplification voltage (a voltage equal to or higher than the product of the maximum amplification factor and ΔV1 used in step S22b in FIG. 20) can be obtained based on the phase difference. Determine the vibration. The process of erroneously detecting a vibration motion as a rotational motion and reducing the amplification factor while the amplification factor is excessive is not stopped halfway.

D. Variations:
Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. For example, the following modifications are also possible. In the above embodiment, the intermediate value between the maximum value Vp and the minimum value Vb is compared with the amplified voltage Vm and binarized. Instead, the amplified voltage Vm is adjusted to increase or decrease so that the intermediate value between the maximum value Vp and the minimum value Vb becomes a predetermined value, and the amplified voltage Vm after the increase / decrease adjustment is compared with the predetermined value to be binarized. It may be. In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

DESCRIPTION OF SYMBOLS 10, 10a ... Rotating body 10R, 15R, 25R, 50Ra ... Resistance 50Rs ... Temperature compensation feedback resistor 11, 11a, 11b ... Sensor 100, 200, 400 ... Sensor voltage processing circuit 100a, 100b ... Sensor voltage processing part 120 ... Amplification Circuits 121, 122 ... Operational amplifier 130 ... Offset voltage adjustment circuit 140 ... Amplification factor adjustment circuit 160 ... Extreme value storage circuit 160b ... Bottom hold circuit 160p ... Peak hold circuit 161, 161a ... Comparator 164, 164a ... Counter 170, 170a, ... 2 Value processing unit 171d ... second hysteresis comparator 171u ... first hysteresis comparator 172d, 172u ... switch 173d, 173u ... comparator 174d, 174u ... inverter 175, 176 ... flip-flop circuit 180 ... rotation direction Judgment circuit 190... Trinary signal output circuit 200... Binary circuit 300.

Claims (9)

It is a circuit that processes sensor voltage that periodically changes following the rotation of the rotating body,
While outputting the voltage which amplified the sensor voltage on the basis of offset voltage, the amplifier circuit which can adjust offset voltage and an amplification factor,
An extreme value storage circuit for storing the maximum value and the minimum value of the output voltage of the amplifier circuit;
A binarization circuit that binarizes the output voltage of the amplifier circuit based on the maximum value and the minimum value stored in the extreme value storage circuit;
The offset voltage adjustment signal and the amplification factor adjustment signal are output to the amplification circuit based on the output voltage of the amplification circuit and the maximum value or the minimum value stored in the extreme value storage circuit, and It has an adjustment circuit that outputs a signal that corrects the extreme value stored in the extreme value storage circuit for the extreme value storage circuit,
The adjustment circuit is
During the initialization process,
(1) Output an adjustment signal that maximizes the amplification factor,
(2) outputting an adjustment signal for adjusting the offset voltage such that the output voltage of the amplifier circuit falls within an intermediate band of the operating voltage range;
(3) outputting a signal for making the maximum value and the minimum value stored in the extreme value storage circuit equal to the voltage in the intermediate band;
Then
(4) When the output voltage of the amplifier circuit changes from a maximum value or a minimum value stored in the extreme value storage circuit beyond a predetermined width, an adjustment signal for reducing the amplification factor is output, and Output a signal to correct the extreme value stored in the value storage circuit,
(5) The sensor voltage processing circuit, wherein the processing of (4) is repeated until the output voltage of the amplifier circuit shows a change pattern unique to the rotational motion of the rotating body.   The adjustment circuit makes both the maximum value and the minimum value stored in the extreme value storage circuit equal to the output voltage of the amplification circuit amplified with the reduced amplification factor during the processing of (4). The processing circuit according to claim 1. When the adjustment circuit performs the processing of (4), the old maximum value and the old minimum value stored in the extreme value storage circuit are expressed by the following formula:
New maximum value = (old maximum value−offset voltage) × (new gain / old gain) + offset voltage New minimum value = (old minimum value−offset voltage) × (new gain / old gain) + offset voltage The processing circuit according to claim 1, wherein the processing circuit corrects the new maximum value and the new minimum value calculated in step 1.   The change width is calculated from the maximum value or the minimum value of the output voltage of the amplifier circuit from the difference between the maximum value and the minimum value stored in the extreme value storage circuit. Processing circuit.   The adjustment circuit is configured such that the output voltage of the amplifier circuit exceeds the maximum value of the amplitude of the output voltage of the amplifier circuit caused by the vibration phenomenon of the rotating body from the maximum value or the minimum value stored in the extreme value storage circuit. 5. The processing circuit according to claim 1, wherein after the change, the processing of (4) is repeated until the output of the binarization circuit is inverted three times. A processing circuit used by connecting to a first sensor and a second sensor having different positional relationships with respect to the rotating body;
The amplifier circuit for processing the first sensor voltage, the extreme value storage circuit, the binarization circuit, and the adjustment circuit;
The amplifier circuit for processing a second sensor voltage, the extreme value storage circuit, the binarization circuit, and the adjustment circuit,
The process (4) is repeated until the phase difference between the processing result of the binarization circuit that processes the first sensor voltage and the processing result of the binarization circuit that processes the second sensor voltage falls within a predetermined range. The processing circuit according to claim 1, wherein the processing circuit is characterized in that:   7. The processing circuit according to claim 1, wherein the amplification circuit includes an offset voltage adjustment circuit configured by an analog / digital mixed circuit. 8.   The processing circuit according to claim 1, wherein the extreme value storage circuit is configured by an analog / digital mixed circuit. A preamplifier circuit is inserted between the sensor and the amplifier circuit;
9. The processing circuit according to claim 1, wherein the resistance value of the feedback resistor of the preamplifier circuit changes with temperature.

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