JP2011193016A - Trench gate semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a trench gate semiconductor device capable of accurately detecting a current up to a saturation current. <P>SOLUTION: In the trench gate semiconductor device, an active cell in which a channel is formed and a floating cell in which a channel is not formed are arranged alternately in a main IGBT region and a sense IGBT region, respectively, wherein a ratio of an active cell width to a floating cell width in the main IGBT region and the sense IGBT region is set at a predetermined value so that the main IGBT region and the sense IGBT region are controlled to have similar saturation current characteristics. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power semiconductor device, and more particularly to a trench gate type semiconductor device having a current detection function.

  A trench gate type IGBT (Insulated Bipolar Transistor) with low channel resistance and low loss is an exposure of a drift layer of a silicon substrate comprising a p-type collector layer, a low-resistance n-type buffer layer, and a high-resistance n-type drift layer. In the p-type base layer formed on the surface side, a plurality of grooves each having a stripe shape in plan view are dug. A trench gate electrode insulated from the silicon substrate is provided in the groove, and the side wall of the trench gate electrode is used as a MOS channel.

  Since the trench gate type IGBT has a large number of channels, the saturation current is large, and the element is easily destroyed by overcurrent. Therefore, it is necessary to quickly and accurately detect an overcurrent caused by a short circuit of the element and cut off the current. In JP-A-10-107282 (Patent Document 1), the saturation current of the sense IGBT is made smaller than the saturation current of the main IGBT, and the current of the sense IGBT is first saturated before the current of the main IGBT is saturated. A trench gate type IGBT is disclosed in which current is detected and heat generation of the sense IGBT is reduced to prevent a change in the sense ratio.

JP-A-10-107282

  The IGBT protection modes are roughly classified into a short-circuit mode and an overcurrent mode, and each operates differently. The prior art is suitable for a short-circuit protection mode in which a large current of 5 times or more of the rated current is detected in a short time. However, in the overcurrent mode, part of the load is short-circuited or the load is grounded and the current flowing through the IGBT gradually increases. Therefore, the current is detected with high accuracy, and it is twice to several times the rated current. Since it is necessary to operate the protection circuit accurately within a certain range, the prior art has the following problems. In the prior art, if the saturation current of the sense IGBT is reduced, the current of the sense IGBT is saturated first, so that an accurate current cannot be detected and the overcurrent mode cannot be protected. In addition, since the saturation current in the sense IGBT region is reduced in the prior art to suppress the heat generation in the sense IGBT region, there is a problem that the characteristics differ between the main IGBT region and the sense IGBT region, that is, the threshold of the IGBT when the temperature increases. Since the voltage decreases and the saturation current increases, if the temperature of the main IGBT rises, only the saturation current of the main IGBT increases and the saturation current of the sense IGBT does not increase. Therefore, a sense that is the current ratio of the main IGBT and the sense IGBT There was a problem that the ratio increased.

  An object of the present invention is to provide a trench gate type semiconductor device capable of accurately detecting even a saturation current.

  In the trench gate type semiconductor device of the present invention, an active cell in which a channel is formed and a floating cell in which a channel is not formed are alternately arranged in the main semiconductor device and the sense semiconductor device, respectively. The saturation current was controlled by setting the ratio of the active cell width to the floating cell width of the device to a predetermined value.

  In the trench gate type semiconductor device of the present invention, the second semiconductor layer stacked on the first semiconductor layer includes a main conductive region and a sub-conductive region, and the main conductive region is stacked on the second semiconductor layer. A plurality of insulated gates that penetrate the semiconductor layer to reach the second semiconductor layer, a region sandwiched between adjacent insulated gates, and a first region and a second region adjacent to each other, and a third semiconductor layer in the first region A fourth semiconductor layer in contact with the insulated gate, and a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer in the first region. A plurality of insulated gates that penetrate the fifth semiconductor layer adjacent to reach the second semiconductor layer, a third region and a fourth region that are adjacent to each other and are adjacent to each other, and a third region of the third region; A sixth semiconductor layer of the second conductivity type in contact with the insulated gate in the five semiconductor layers; Comprising a second electrode electrically connected to the second in the third region the fifth semiconductor layer and the sixth semiconductor layer, and a third electrode electrically connected to the first semiconductor layer.

  The outline | summary of the other invention shown in this application is as follows.

Item 1: A semiconductor substrate having three layers of a first conductivity type collector layer, a low resistance second conductivity type buffer layer, and a high resistance second conductivity type drift layer is stacked on the exposed surface side of the drift layer. In a trench gate type semiconductor device comprising an insulated gate electrode arranged in a plurality of stripes having a planar shape formed in a first conductivity type base layer,
The semiconductor device comprises a main semiconductor region and a current detection semiconductor region,
An active cell region in which the main semiconductor region and the current detection semiconductor region are each sandwiched between the stripe-shaped grooves, and an active cell region having a narrow groove interval between the stripe-shaped grooves; A trench gate type semiconductor device, wherein a floating cell region having a larger groove interval than the active cell region is disposed, and a second conductivity type emitter layer is disposed in the active cell region.

Item 2: Stacked on the exposed surface side of the drift layer of a semiconductor substrate having three layers of a first conductivity type collector layer, a low resistance second conductivity type buffer layer, and a high resistance second conductivity type drift layer. In a trench gate type semiconductor device comprising an insulated gate electrode arranged in a plurality of stripes having a planar shape formed in a first conductivity type base layer,
The semiconductor device comprises a main semiconductor region and a current detection semiconductor region,
An active cell region in which the main conductive region and the current detection semiconductor region are each sandwiched between the stripe-shaped grooves and the second conductive type emitter layer is disposed in a narrow groove interval; and the active cell region It has a floating cell region with a wider groove interval,
A trench gate type semiconductor device, wherein the main semiconductor region and the current detection semiconductor region are arranged via a blocking cell in which the interval between the stripe-shaped grooves is wider than the interval between the floating cell grooves.

  According to the present invention, since accurate current detection can be performed from several times the rated current of the trench gate type IGBT to the saturation current, highly accurate short-circuit protection and overcurrent protection can be achieved.

1 is a cross-sectional view of an IGBT according to Example 1. FIG. 3 is an explanatory diagram of a planar structure of the IGBT of Example 1. FIG. 6 is an explanatory diagram of a planar structure of an IGBT according to Example 2. FIG. It is explanatory drawing of the gate wiring and gate electrode of IGBT of Example 2. 6 is a cross-sectional view of an IGBT according to Example 3. FIG. FIG. 10 is an equivalent circuit diagram for explaining the operation of the IGBT according to the third embodiment. 6 is a cross-sectional view of an IGBT according to Example 4. FIG. FIG. 10 is an equivalent circuit diagram of the three-phase inverter according to the fifth embodiment.

  Details of embodiments of the present invention will be described with reference to the drawings. Hereinafter, an embodiment in which the present invention is applied to an IGBT will be described. Similarly, the present invention can be similarly applied to a MOSFET having an insulated gate of a trench gate, a MOSFET control thyristor and the like.

Example 1
FIG. 1 shows a cross-sectional structure of the IGBT of this embodiment, and FIG. 2 shows a planar structure. 1 corresponds to a cross section taken along the line AB of FIG. As shown in FIG. 1, a silicon semiconductor substrate including an n-type buffer layer 102 and an n-type drift layer 103 deposited on a p-type collector layer 101 by an epitaxial method or the like is formed by using a main IGBT region and a sense IGBT. In the main IGBT region, a floating layer 104 mainly formed by injecting p-type impurities such as boron into the main IGBT region by thermal diffusion, a p base layer 114, and the p base layer 114 There are a trench (groove) that reaches the drift layer 103 through the gate, and a gate electrode 108 that is mainly formed of polycrystalline silicon or the like through the gate insulating film 107 in the trench. This trench arrangement includes a region having a narrow interval (active cell: width La) and a region having a trench arrangement interval wider than the active cell (floating cell: width Lb). The active cell includes an n-type. The emitter layer 105 and the p-type contact layer 106 are formed.

  The emitter layer 105, the p base layer 114, and the drift layer 103 form an n-channel MOSFET. The contact layer 106 is provided to make ohmic contact with the emitter electrode 111 formed on the surface. In order to obtain a better contact, the contact portion is preferably processed into a recessed shape as shown in FIG. A p-type floating layer 104 that is in an electrically floating state is formed in the floating cell. Similarly to the main IGBT region, active cells and floating cells are also formed in the sense IGBT region. The active cell in the sense IGBT region is connected to the sense electrode 112.

  FIG. 2 shows a planar structure of the present embodiment. In FIG. 2, the left side is the main IGBT region, the right side is the sense IGBT region, and a plurality of striped cells are arranged. As described in FIG. 1, the gate electrodes 108 are arranged at different intervals to form active cells and floating cells. The emitter layers 105 are arranged at regular intervals in order to reduce the saturation current.

  The contact layer 106 described with reference to FIG. 1 is formed by thermal diffusion after impurity implantation from the emitter contact 400. The emitter electrode 111 is indicated by an emitter electrode boundary 404 in FIG. A region in the emitter electrode boundary 404 indicated by an arrow in FIG. 2 becomes an emitter electrode. The emitter electrode 111 is connected to the contact layer 106 through the emitter contact 400.

  The p base layer 114 and the floating layer 104 are formed in the lower region of FIG. 2 from the p base layer boundary 406. In the region on the upper side in FIG. 4 from the p base layer boundary 406, a well layer 402 is formed after forming a trench until the drift layer 103 is partially exposed. The well layer 402 is formed deeper than the p base layer 114, the floating layer 104, and the gate electrode. The function of the well layer 402 is to alleviate the electric field at the terminal end of the gate electrode and discharge excess carriers (particularly holes) at the terminal end of the cell. A well contact 401 is formed in the well layer 402 and is connected to the emitter electrode 111 via this contact. A terminal portion of the gate electrode 108 is covered with a polycrystalline silicon layer 403 for gate contact. A configuration in which all the trenches are connected by the polysilicon layer 403 for gate contact in the lateral direction of FIG. 4 is also preferable. The gate contact polycrystalline silicon layer 403 is in electrical contact with the gate electrode 108, extends to the upper side in FIG. 4, and is in contact with the gate wiring 300 through the gate wiring contact 407. The sense electrode 112 is a region below the sense electrode boundary 405 and is in contact with the contact layer through an emitter contact.

  In the present embodiment, in order to reduce the saturation current, active cells having a channel (La portion in FIG. 1) and floating cells not forming a channel (Lb portion in FIG. 1) are alternately arranged, Saturation currents in both the main IGBT region and the sense IGBT region were reduced. At this time, it is desirable that the width of the active cell and the floating cell satisfy La ≦ Lb. Increasing the ratio of La: Lb can reduce the saturation current, and this ratio is preferably set to 1: 3 or more. For example, when La = 4 μm is set, Lb = 12 μm or more is preferable.

  In this embodiment, the La: Lb ratio is adjusted so that the saturation current is about 10 times the rated current, so that instantaneous breakdown of the GBT when the load is short-circuited can be prevented. In this embodiment, since the IGBT does not break instantaneously when the load is short-circuited, it is not necessary to saturate the current in the sense IGBT region before the current in the main IGBT region, and the same cell structure as the main IGBT region is formed in the sense IGBT region. The current can be accurately detected in the overcurrent mode.

  Further, in the present embodiment, since the current flows in the same way in the main IGBT region and the sense IGBT region, the heat generation is also the same, and the same characteristic variation (threshold voltage variation) is exhibited, so the sense ratio variation is small. Further, in this embodiment, since no special blocking region is provided between the main IGBT region and the sense IGBT region, the main IGBT region and the sense IGBT region are adjacent to each other through the floating cell. Cells can be arranged regularly. For this reason, a current flows uniformly in the main IGBT region and the sense IGBT region, and a part of the main current can be accurately extracted in the sense IGBT region.

(Example 2)
FIG. 3 and FIG. 4 are plan structural views of this embodiment. FIG. 3 shows a chip appearance of the trench gate type IGBT of this embodiment, and is a view of the chip as seen from the emitter surface. A breakdown voltage holding region 200 is formed in the peripheral portion of the chip, and the electric field in the peripheral portion of the chip is relaxed. Inside the withstand voltage holding region 200, there is a gate wiring 201 that extends over the entire chip and is electrically connected to the gate pad 204. A bonding wire having a diameter of 100 μm to 500 μm is driven into the gate pad 204 and is electrically connected to an external circuit. The temperature detection pads 202 and 203 are connected to a temperature detection element (not shown) such as a diode formed of polycrystalline silicon so that the temperature can be detected. The emitter sense pad 205 is provided for detecting the potential of the emitter electrode 111 and connecting the ground of the gate circuit. The main IGBT region 208 is disposed on the entire chip, and most of the surface thereof may be used as an emitter pad. A plurality of wires having a diameter of 300 μm to 500 μm are connected to the emitter pad, and a main current is applied. The sense IGBT region 206 is disposed adjacent to the sense pad 207.

  Details of the sense IGBT region 206 surrounded by a dotted line in FIG. 3 will be described with reference to FIG. FIG. 4 is an enlarged schematic view of the sense IGBT region 206 of FIG. 3, and the emitter electrode 111 and the sense electrode 112 are omitted for convenience of expression. The main IGBT cell is shown on the upper side of FIG. 4, and the sense IGBT cell is shown on the lower side.

  In this embodiment, the sense IGBT region 206 is arranged between the cell with the fastest and the slowest turn-on of the IGBT. When the sense IGBT is turned on at the same time as the cell with the fastest turn-on, a large inrush current flows and a spike occurs in the current waveform. If the sense IGBT is arranged to turn on at the same time as the cell with the slowest turn-on, the period until the sense IGBT is turned on becomes a dead zone for current detection, and the current may increase during this time, leading to destruction.

  According to the study by the inventors, the signal applied to the gate wiring 300 in FIG. 4 can delay the turn-on timing of the sense IGBT region by at least about 5% from the turn-on timing of the fastest turn-on cell in the main IGBT region. It was found that no spikes occurred and there was almost no detection time delay. Specifically, as shown in the arrangement of FIG. 4, L3 expressed by the formula (1) from the distance L1 between the cell and the gate line 300 with the earliest turn-on and the distance L2 between the cell and the gate line 300 with the latest turn-on. It is only necessary to dispose the emitter layer 105 in the sense IGBT region at a distance from the gate wiring 300.

L3 ≧ (L2−L1) × 0.05 + L1 (Equation 1)
For example, if L1 is 50 μm and L2 is 380 μm, L3 ≧ 66.5 μm may be satisfied, and among the combinations satisfying the formula (1), L3 shown in the formula (2) is particularly preferable.

L3 = (L2−L1) / 2 + L1 (Expression 2)
For example, when L1 is 50 μm and L2 is 380 μm, L3 = 215 μm. With the arrangement as described above, it is possible to realize a sense IGBT without detection delay while preventing a spike at the time of turn-on, and to realize highly reliable current detection.

(Example 3)
FIG. 5 shows a cross-sectional structure of this embodiment. In FIG. 5, the same components as those in FIGS. The present embodiment is different from the first and second embodiments in that the sense IGBT region 206 and the main IGBT region 208 are arranged via a blocking cell.

As shown in the equivalent circuit of FIG. 6, a sense resistor 600 is connected to the sense electrode 112. When the sense resistor 600 is connected to the sense electrode 112 as shown in FIG. 6, a sense current I _{S that} is about one hundredth to several thousandth of the main current I _{M in} the main IGBT region flows to the sense resistor 600, A sense voltage Vs is generated. The main current I _M is detected from the sense voltage Vs. However, when the sense voltage Vs is generated, the potential of the sense electrode 112 rises, and the potential of the sense IGBT region 206, specifically, the potential of the p base layer 114 of the active cell in the sense IGBT region 206 becomes the potential of the main IGBT region 208. Specifically, it becomes higher than the potential of the p base layer 114 of the active cell in the main IGBT region. Then, current leaks from the sense IGBT region 206 to the main IGBT region 208 due to this potential difference, and the linearity of the current in the main IGBT region 208 and the sense IGBT region 206 deteriorates.

  In this embodiment, the blocking cell width Lc is set larger than the floating cell width Lb of the main IGBT region 208 to reduce the leakage current between the sense IGBT region 206 and the main IGBT region 208. In this example, when La = 4 μm and Lb = 12 μm, the width Lc of the cutoff cell was set to 12 μm or more. The width Lc of the blocking cell may be set to 24 μm, which is twice as large as Lb.

  According to this embodiment, accurate current detection is possible, and overcurrent protection can be performed with high accuracy. This embodiment is highly effective when the detection voltage is set high, particularly when the sense voltage Vs is 0.5 V to 1.0 V.

(Example 4)
FIG. 7 shows a cross-sectional structure of this embodiment. 7, the same components as those in FIGS. 1 to 6 are denoted by the same reference numerals. In FIG. 7, reference numeral 700 denotes a dummy gate.

  This embodiment is different from the first to third embodiments in that the sense IGBT region 206 and the main IGBT region 208 are arranged adjacent to each other via a dummy cell that is a blocking cell. As described in the third embodiment, when the sense voltage Vs is increased, the leakage current between the main IGBT region 208 and the detection cell is increased, and the linearity is deteriorated.

  In this embodiment, when the sense voltage Vs is set high (Vs> 1.0 V), that is, when Lc in FIG. 7 is widened, a dummy cell is arranged between the sense IGBT region 206 and the main IGBT region 208, and the trench The influence of the variation in shape processing on the sense voltage Vs is suppressed. In this embodiment, the dummy gate 700 of the dummy cell is made floating. This is because an accumulation layer is formed on the surface of the trench gate electrode that is not floating, and it is easy for electricity to flow, so that the effect of reducing the leakage current is reduced even if a dummy cell is provided. In the present embodiment, an example in which one dummy cell is arranged has been described. However, it is also preferable to arrange a plurality of dummy cells to further increase the width Lc of the cutoff cell in FIG.

(Example 5)
FIG. 8 shows a three-phase inverter of this embodiment. In FIG. 8, reference numeral 800 is a gate driver with a protection circuit, 801 and 802 are DC input terminals, 803 is an IGBT, 804 is a freewheeling diode, 805 to 807 are AC output terminals, and 600 is a sense resistor. In the three-phase inverter of this example, the trench gate type IGBT chip described in Examples 1 to 4 was applied to the inverter. In the three-phase inverter of this embodiment, accurate current detection can be performed simply by connecting a detection resistor to the sense electrode of the trench gate type IGBT, so that a current transformer and a current probe for current measurement are not required, and the inverter circuit is simplified. Can be. In addition, since the current value can be extracted as a voltage, the configuration of the gate driver with a protection circuit can be simplified.

  The present invention is suitable for application to, for example, a power semiconductor device.

100 collector electrode 101 collector layer 102 buffer layer 103 drift layer 104 floating layer 105 emitter layer 106 contact layer,
107 Gate insulating film 108 Gate electrode 109 Insulating film 110 Interlayer insulating film 111 Emitter electrode 112 Sense electrode 113 Surface protection film 114 p Base layer 200 Withstand voltage holding region 201, 300 Gate wiring 202, 203 Temperature detection pad 204 Gate pad 205 Emitter sense Pad 206 Sense IGBT region 207 Sense pad 208 Main IGBT region 400 Emitter contact 401 Well contact 402 Well layer 403 Gate contact polycrystalline silicon layer 404 Emitter electrode boundary 405 Sense electrode boundary 406 p base layer boundary 407 Gate wiring contact 600 Sense resistor 700 Dummy gate 800 Gate drivers 801 and 802 with protection circuit DC input terminal 803 IGBT
804 Freewheeling diode 805, 806, 807 AC output terminal

Claims (9)

A first conductive type first semiconductor layer; and a second conductive type second semiconductor layer stacked on the first semiconductor layer, wherein the second semiconductor layer includes a main conductive region and a sub-conductive region. ,
The second energization region of the second semiconductor layer is separated from the third semiconductor layer through the third semiconductor layer and the third semiconductor layer of the first conductivity type stacked on the second semiconductor layer. A plurality of insulated gates reaching the semiconductor layer, and a region between the neighboring insulated gates, the first region and the second region adjacent to each other, and the insulation in the third semiconductor layer of the first region A second conductivity type fourth semiconductor layer in contact with the gate; and a first electrode electrically connected to the third semiconductor layer and the fourth semiconductor layer in the first region;
The second energization region of the second semiconductor layer is separated from the fifth semiconductor layer through the fifth semiconductor layer and the fifth semiconductor layer of the first conductivity type adjacent to the second semiconductor layer. A plurality of insulated gates that reach the semiconductor layer; and a third region and a fourth region that are adjacent to each other and that are adjacent to each other, and in the fifth semiconductor layer of the third region A second conductive type sixth semiconductor layer in contact with the insulated gate; and a second electrode electrically connected to the fifth semiconductor layer and the sixth semiconductor layer in the third region;
A third electrode electrically connected to the first semiconductor layer;
A trench gate type semiconductor device, wherein a width of the first region of the main energization region is narrower than a width of the second region.   2. The trench gate type semiconductor device according to claim 1, wherein the width of the third region of the sub-conduction region is narrower than the width of the fourth region of the sub-conduction region.   2. The trench gate type semiconductor device according to claim 1, wherein the main conduction region is a main IGBT region, the sub-conduction region is a sense IGBT region, and is electrically connected to the insulated gate of the main IGBT region. A gate line and a gate line electrically connected to the insulated gate in the sense IGBT region, the fourth semiconductor layer being closest to a contact point between the gate line and the insulated gate in the main IGBT region; The distance between the contact points is L1, the distance between the fourth semiconductor layer farthest from the contact point between the gate wiring in the main IGBT region and the insulated gate and the contact point is L2, and the gate wiring in the sense IGBT region When the distance between the sixth semiconductor layer closest to the contact point of the insulated gate and the contact point is L3, L3 ≧ (L2−L1) × 0.05 + L Trench gate type semiconductor device, characterized in that it.   2. The trench gate type semiconductor device according to claim 1, wherein the main conduction region and the sub conduction region are adjacent to each other via a fifth region sandwiched between the insulating gates. apparatus.   5. The trench gate type semiconductor device according to claim 4, wherein one or a plurality of the fifth regions located between the main energization region and the sub energization region are arranged.   5. The trench gate type semiconductor device according to claim 4, wherein a width of the fifth region disposed between the main energization region and the sub-energization region is wider than a width of the second region. Gate type semiconductor device.   5. The trench gate type semiconductor device according to claim 4, wherein a width of the fifth region disposed between the main energization region and the sub-energization region is wider than a width of the fourth region. Gate type semiconductor device.   2. The trench gate type semiconductor device according to claim 1, wherein the width of the first region of the main conduction region and the width of the third region of the sub conduction region are the same.   2. The trench gate type semiconductor device according to claim 1, wherein the width of the second region of the main conduction region and the width of the fourth region of the sub conduction region are the same.

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