JP2011191192A - Semiconductor device and testing device of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decide whether an over current protection value of a main current is within a normal range without a special test facility. <P>SOLUTION: The semiconductor device 1 includes a main transistor 11 for making the main current I11 flow, a sub-transistor 21 for making the sub-current I21 flow, a control circuit 60 generating a drive signal IN_H common to both the transistors 11 and 21, an overcurrent protection circuit 70 comparing the sub-current I21 with a sub-current threshold and generating an overcurrent protection signal Socp to output it to the controlling circuit 60, and a drive circuit (circuit block group expressed by 41a, 41b, 50, 81 and 91) deciding whether on/off-operations should be applied to both the transistors 11 and 21 according to the drive signal IN_H, or after setting the transistor 11 to be turned off independently of the drive signal IN_H, whether on/off-operations are sould be applied to only the transistor 21 based on a switching signal TEST. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device provided with an overcurrent protection circuit and a test apparatus therefor.

  FIG. 9 is a circuit block diagram showing a conventional example of a semiconductor device provided with an overcurrent protection circuit. In the semiconductor device 100 of the conventional example, the overcurrent protection circuit 70 uses the sub-currents I21 and I22 flowing through the sub-transistors 21 and 22 whose gates are shared with the main transistors 11 and 12, respectively, to sense resistors 31 and 32. Are used to detect large main currents I11 and I12 flowing in the main transistors 11 and 12, respectively (where I11 = α × I21, I12 = β × I22, α and β are mirror ratios (eg, 1,000)). It was set as the structure which detects indirectly.

  That is, the overcurrent protection circuit 70 determines that the upper main current I11 also exceeds the upper main current threshold Ith1 (= α × Ith1 ′) when the upper subcurrent I21 exceeds the upper subcurrent threshold Ith1 ′. The overcurrent protection signal Socp is changed from the normal logic level to the abnormal logic level. The overcurrent protection circuit 70 also sets the lower main current I12 to the lower main current threshold Ith2 (= β × Ith2 ′) when the lower subcurrent I22 exceeds the lower subcurrent threshold Ith2 ′. Therefore, the overcurrent protection signal Socp is changed from the normal logic level to the abnormal logic level.

  Regarding the shipping test of such a semiconductor device 100, (1) the sub current thresholds Ith1 ′ and Ith2 ′ are measured, (2) the main current thresholds Ith1 and Ith2 are measured, or (3) There was an option to not test at shipping.

  If option (1) is selected, as shown in FIG. 9, test pads TP1 and TP2 (connected to one end of each of the sense resistors 31 and 32 (connection ends to the sub-transistors 21 and 22) ( It is necessary to prepare an EDS [Electrical Die Sorting] pad). When measuring the upper sub-current threshold Ith1 ′, the main transistors 11 and 12 and the sub-transistors 21 and 22 are both turned off, and the arbitrary value from the external terminal T1 toward the test pad TP1. And the current value of the test current Itest when the overcurrent protection operation is activated may be measured as the upper subcurrent threshold Ith1 ′. Further, when the lower sub-current threshold Ith2 ′ is measured, the test transistor TP2 is connected to the external terminal with the main transistors 11 and 12 and the sub-transistors 21 and 22 turned off, as described above. An arbitrary test current Itest directed to T3 may be supplied, and the current value of the test current Itest when the overcurrent protection operation is activated may be measured as the lower subcurrent threshold Ith2 ′.

  On the other hand, when the option (2) is selected, the above-described test pads TP1 and TP2 are not necessary. When measuring the upper main current threshold Ith1, the main transistor 11 and the sub-transistor 21 are both turned on, and the main transistor 12 and the sub-transistor 22 are both turned off. An arbitrary test current Itest directed to T2 may be supplied, and the current value of the test current Itest when the overcurrent protection operation is activated may be measured as the upper main current threshold value Ith1. When measuring the lower main current threshold Ith2, the main transistor 11 and the sub-transistor 21 are both turned off, and the main transistor 12 and the sub-transistor 22 are both turned on. An arbitrary test current Itest directed to the terminal T3 may be supplied, and the current value of the test current Itest when the overcurrent protection operation is activated may be measured as the lower main current threshold Ith2.

  As an example of the related art related to the above, Patent Document 1 can be cited.

JP 2006-287399 A

  However, the conventional semiconductor device 100 has a problem when any of the previous options (1) to (3) is selected for the shipping test.

  When the option (1) is selected, the test pads TP1 and TP2 described above are required for each output, leading to an increase in the chip area, leading to an increase in chip cost. Further, since the test pads TP1 and TP2 are hidden pads that are not wire-bonded to the lead frame, the sub-current thresholds Ith1 'and Ith2' cannot be measured after the semiconductor device 100 is packaged. Further, even if the sub-current thresholds Ith1 ′ and Ith2 ′ are measured, the main-current thresholds Ith1 and Ith2 are not directly measured. Therefore, the mirror ratio α between the main transistors 11 and 12 and the sub-transistors 21 and 22 and When β varies from product to product, the main current thresholds Ith1 and Ith2 cannot be guaranteed.

  When the option (2) is selected, the main current thresholds Ith1 and Ith2 can be directly measured. However, in order to activate the intentional overcurrent protection operation, a very large test current Itest is used. Therefore, a test facility that can withstand the measurement of a large current is required, which in turn increases the cost of testing at the time of shipment.

  In addition, when option (3) is selected, the semiconductor device 100 is not tested at the time of shipment, so it can contribute to the cost reduction of the product, but the deterioration in quality (increase in the initial defect rate) is avoided. I didn't get it.

  In view of the above problems, the present invention provides a semiconductor device capable of determining whether an overcurrent protection value of a main current flowing through a main transistor is within a normal range without requiring a special test facility, and An object is to provide the test apparatus.

  In order to achieve the above object, a semiconductor device according to the present invention is connected between a first external terminal; a second external terminal; the first external terminal and the second external terminal, and allows a main current to flow. A main transistor for connecting; a sub-transistor connected between the first external terminal and the second external terminal for flowing a sub-current exhibiting the same behavior as the main current; the main transistor and the sub-transistor A control circuit that generates a drive signal common to both of them; an overcurrent protection circuit that compares the subcurrent with a predetermined threshold for subcurrent to generate an overcurrent protection signal and outputs the signal to the control circuit; Both the main transistor and the sub transistor are turned on / off according to the drive signal, or the main transistor is turned off regardless of the drive signal, and the sub transistor It has a configuration having a (first configuration); or registers only turns on / off according to the drive signal, a drive circuit for determining based on a predetermined switching signal.

  In the semiconductor device having the first structure, the drive circuit outputs, based on the switching signal, one of the drive signal and a logic signal for turning off the main transistor; A configuration (second configuration) including: a main driver that drives the main transistor according to an output; and a sub-driver that drives the sub-transistor according to the drive signal.

  In the semiconductor device having the second configuration, the drive circuit includes a level shifter that converts the voltage level of the drive signal into a voltage level suitable for input to the main driver and the sub driver (third (Configuration).

  In the semiconductor device having the second or third configuration, the drive circuit gives a signal delay equivalent to a signal delay generated by the selector to the drive signal input to the sub-driver. (4th configuration).

  In the semiconductor device having any one of the second to fourth configurations, the main driver turns on the main transistor without delay when the input signal becomes a logic level for turning on the main transistor. When the input signal becomes a logic level for turning off the main transistor, the main transistor is turned off after a lapse of a predetermined time from that point, and the sub-driver is configured to turn on the sub transistor. When the level is reached, the sub-transistor is turned on after a lapse of a predetermined time from that point, while the sub-transistor is turned off without delay when the input signal becomes a logic level that turns off the sub-transistor 5 configuration).

  In the semiconductor device having any one of the first to fifth configurations, a signal path from the control circuit to the main transistor and a signal path from the control circuit to the sub-transistor are symmetrical to each other. It is good to use the structure (6th structure) currently laid.

  In the semiconductor device having any one of the first to sixth configurations, the drive circuit turns on the main transistor when turning on / off both the main transistor and the sub-transistor according to the drive signal. It is preferable that the sub-transistor is turned on after being turned on, and the main transistor is turned off after the sub-transistor is turned off (seventh configuration).

  In the semiconductor device having any one of the first to seventh configurations, the switching signal may be output from the control circuit (eighth configuration).

  In the semiconductor device having the eighth configuration, the control circuit turns on both the main transistor and the sub-transistor according to the drive signal based on a test command input from the outside of the semiconductor device. And the second step of turning off only the sub-transistor in response to the drive signal, and the second step of turning on only the sub-transistor in response to the drive signal. A configuration for generating a switching signal (a ninth configuration) is preferable.

  Further, the test apparatus according to the present invention outputs the test command to the semiconductor device having any one of the first to ninth configurations, and whether or not the threshold value of the overcurrent protection circuit is within a normal range. It is set as the structure (10th structure) which determines this.

  The test apparatus having the tenth configuration includes a current source for supplying an arbitrary test current between the first external terminal and the second external terminal; the first external terminal and the second external terminal; A test sequencer for generating the test command, driving control of the current source, obtaining a measurement value of the voltmeter, and calculating a threshold value of the overcurrent protection circuit. A configuration (eleventh configuration) is preferable.

  In the test apparatus having the eleventh configuration, the test sequencer sets the test current to an arbitrary current value while the control circuit is executing the first step. A resistance value of a main current path through which the main current flows is calculated by obtaining a measurement value of the meter; while the second step is executed by the control circuit, the test current is set to an arbitrary current value. The resistance value of the sub current path through which the sub current flows is calculated by acquiring the measured value of the voltmeter in the state set to, while the test current is gradually increased, and the overcurrent protection operation is activated. Current value of the test current at the time is obtained as the threshold value for the sub current; finally, the resistance value of the main current path, the resistance value of the sub current path, and the threshold value for the sub current Based on, or when the calculated main current threshold, which is to determine configure whether falls within the normal range (12 configuration).

  With the semiconductor device and its test device according to the present invention, it is possible to determine whether or not the overcurrent protection value of the main current flowing through the main transistor is within the normal range without requiring special test equipment. Become.

The figure which shows the example of 1 structure of the semiconductor device which concerns on this invention Diagram showing an example of external connection during upper test Diagram showing an example of external connection during the lower test Timing chart for explaining the upper test operation Timing chart for explaining the lower test operation Schematic diagram showing an example of element layout Circuit diagram showing one configuration example of driver Timing chart showing driver output operation The figure which shows the 1st usage example (use example as a synchronous rectification type | mold step-down DC / DC controller) of the semiconductor device 1. The figure which shows the 2nd usage example (use example as an asynchronous rectification type | mold step-down DC / DC controller) of the semiconductor device 1. The figure which shows the 3rd usage example (use example as an asynchronous rectification type | mold boost DC / DC controller) of the semiconductor device 1. The figure which shows the 4th usage example (use example as a motor driver) of the semiconductor device 1. The figure which shows one prior art example of the semiconductor device provided with the overcurrent protection circuit

  FIG. 1 is a diagram showing a configuration example of a semiconductor device according to the present invention. As shown in FIG. 1, the semiconductor device 1 of this configuration example includes transistors 11 and 12, transistors 21 and 22, sense resistors 31 and 32, drivers 41a and 42a, drivers 41b and 42b, A level shifter 50, a control circuit 60, an overcurrent protection circuit 70, selectors 81 and 82, and delay circuits 91 and 92 are included.

  Further, the semiconductor device 1 has external terminals T1 to T5 as means for establishing an electrical connection with the outside, and the test device 2 is connected at the time of the shipping test (FIG. 2A and FIG. 2). 2B, details will be described later), and appropriate discrete components are connected depending on the application during use (see FIGS. 8A to 8D, details will be described later).

  The transistor 11 is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) connected between the external terminal T1 and the external terminal T2, and functions as an upper main transistor for flowing the upper main current I11. The source of the transistor 11 is connected to the external terminal T1. The drain of the transistor 11 is connected to the external terminal T2. The gate of the transistor 11 is connected to the application terminal of the gate signal G11 (the output terminal of the driver 41a).

  The transistor 12 is an N-channel MOSFET connected between the external terminal T2 and the external terminal T3, and functions as a lower main transistor for flowing the lower main current I12. The source of the transistor 12 is connected to the external terminal T3. The drain of the transistor 12 is connected to the external terminal T2. The gate of the transistor 12 is connected to the application terminal of the gate signal G12 (the output terminal of the driver 42a).

  Thus, the transistors 11 and 12 are a pair of switch elements forming a so-called totem pole type output stage. During normal operation of the semiconductor device 1, the transistors 11 and 12 are complementarily (exclusively) turned on / off. Controlled off.

  Note that the expression “complementary (exclusively)” used in this specification is not only when the transistors 11 and 12 are turned on / off completely, but also from the viewpoint of preventing through current. And a case where a predetermined delay is given to the on / off transition timing of 12.

  The transistor 21 is a P-channel MOSFET connected between the external terminal T1 and the external terminal T2, and functions as an upper sub-transistor for flowing an upper sub-current I21 that exhibits the same behavior as the upper main current I11. The source of the transistor 21 is connected to the external terminal T1 through the sense resistor 31. The drain of the transistor 21 is connected to the external terminal T2. The gate of the transistor 21 is connected to the application terminal of the gate signal G21 (the output terminal of the driver 41b).

  The transistor 22 is an N-channel MOSFET connected between the external terminal T2 and the external terminal T3, and serves as a lower sub-transistor for flowing a lower sub-current I22 that exhibits the same behavior as the lower main current I12. Function. The source of the transistor 22 is connected to the external terminal T3 through the sense resistor 32. The drain of the transistor 22 is connected to the external terminal T2. The gate of the transistor 22 is connected to the application terminal of the gate signal G22 (the output terminal of the driver 42b).

  The mirror ratio α of the upper main current I11 with respect to the upper subcurrent I21 (ie, I11 = α × I21) and the mirror ratio β of the lower main current I12 with respect to the lower subcurrent I22 (ie, I12 = β × I22) are Each may be set to about 1,000. For this purpose, for example, the gate areas of the transistors 21 and 22 may be designed to be about 1/1000 of the gate areas of the transistors 11 and 12.

  The sense resistors 31 and 32 convert the upper subcurrent I21 and the lower subcurrent I22 into voltage signals and output the voltage signals to the overcurrent protection circuit 70, respectively.

  The driver 41a functions as an upper main driver that generates a gate signal G11 for driving the transistor 11 in accordance with the output of the selector 81.

  The driver 42a functions as a lower main driver that generates a gate signal G12 for driving the transistor 12 in accordance with the output of the selector 82.

  The driver 41b functions as an upper sub-driver that generates a gate signal G21 for driving the transistor 21 in accordance with the output of the delay circuit 91.

  The driver 42b functions as a lower sub-driver that generates a gate signal G22 for driving the transistor 22 in accordance with the output of the delay circuit 92.

  The level shifter 50 selects the voltage levels of the upper drive signal IN_H, the lower drive signal IN_L, and the switching signal TEST output from the control circuit 80 by selectors 81 and 82 (and thus drivers 41a and 42a), and a delay circuit. 91 and 92 (and thus drivers 41b and 42b) are converted to voltage levels suitable for input.

  The control circuit 60 generates an upper drive signal IN_H common to both transistors 11 and 21, a lower drive signal IN_L common to both transistors 12 and 22, and a switching signal TEST common to both selectors 81 and 82. Logic circuit.

  Note that the control circuit 60 pulse-drives the upper drive signal IN_H and the lower drive signal IN_L complementarily (exclusively) as necessary while maintaining the switching signal TEST at a low level during the normal operation of the semiconductor device 1. To do.

  On the other hand, the control circuit 60 performs an upper test command or a lower test command input from the outside of the semiconductor device 1 via the external terminal T5 during a shipping test of the semiconductor device 1 (see FIGS. 2A to 2B). Based on the above, the upper drive signal IN_H, the lower drive signal IN_L, and the switching signal TEST are appropriately generated in accordance with a pre-programmed test sequence so as to execute a predetermined test operation. This will be described in detail later.

  The control circuit 60 determines whether to forcibly turn off the transistors 11 and 12 and the transistors 21 and 22 based on the overcurrent protection signal Socp input from the overcurrent protection circuit 70. More specifically, the control circuit 60 forcibly turns off the transistors 11 and 12 and the transistors 21 and 22 when the overcurrent protection signal Socp is at a high level (logic level at the time of abnormality). With such a configuration, it is possible to perform an overcurrent protection operation by the semiconductor device 1 alone without waiting for shutdown control from a microcomputer or the like.

  The overcurrent protection circuit 70 compares the upper subcurrent I21 with a predetermined upper subcurrent threshold Ith1 ′, and the lower subcurrent I22 with a predetermined lower subcurrent threshold Ith2 ′, respectively, to detect an overcurrent protection signal Socp. Is output to the control circuit 60.

  More specifically, the overcurrent protection circuit 70 has a predetermined upper limit value (upper subcurrent threshold Ith1 ′ or lower subcurrent threshold Ith2 ′) in either one of the upper subcurrent I21 and the lower subcurrent I22. ), It is determined that an overcurrent state has occurred, and the overcurrent protection signal Socp is set to a high level (logical level at the time of abnormality).

  That is, the overcurrent protection circuit 70 determines that the upper main current I11 also exceeds the upper main current threshold Ith1 (= α × Ith1 ′) when the upper subcurrent I21 exceeds the upper subcurrent threshold Ith1 ′. The overcurrent protection signal Socp is changed from the normal logic level to the abnormal logic level. The overcurrent protection circuit 70 also sets the lower main current I12 to the lower main current threshold Ith2 (= β × Ith2 ′) when the lower subcurrent I22 exceeds the lower subcurrent threshold Ith2 ′. Therefore, the overcurrent protection signal Socp is changed from the normal logic level to the abnormal logic level.

  Further, the overcurrent protection circuit 70 is configured to output an overcurrent protection signal Socp to the outside of the semiconductor device 1 through the external terminal T4. With such a configuration, the microcomputer that has received the input of the overcurrent protection signal Socp can notify the user that an abnormality has occurred in the semiconductor device 1 or can forcibly shut down the operation of the semiconductor device 1. Can do.

  The selector 81 outputs one of the upper drive signal IN_H and a logic signal (high level signal) for turning off the transistor 11 based on the switching signal TEST. More specifically, the selector 81 outputs the upper drive signal IN_H when the switching signal TEST is at the low level, and the logic for turning off the transistor 11 when the switching signal TEST is at the high level. A signal (high level signal) is output.

  The selector 82 outputs one of a lower drive signal IN_L and a logic signal (low level signal) for turning off the transistor 12 based on the switching signal TEST. More specifically, the selector 82 outputs the lower drive signal IN_L when the switching signal TEST is at a low level, and turns off the transistor 12 when the switching signal TEST is at a high level. A logic signal (low level signal) is output.

  The delay circuit 91 gives a signal delay equivalent to the signal delay generated in the selector 81 to the upper drive signal IN_H input to the driver 41b.

  The delay circuit 92 gives a signal delay equivalent to the signal delay generated by the selector 82 to the lower drive signal IN_L input to the driver 42b.

  In the semiconductor device 1 configured as described above, the drivers 41a and 41b, the level shifter 50, the selector 81, and the delay circuit 91 turn on / off both the transistors 11 and 21 in accordance with the upper drive signal IN_H, or This corresponds to a component of the upper drive circuit that determines whether the transistor 11 is turned off regardless of the upper drive signal IN_H and only the transistor 21 is turned on / off according to the upper drive signal IN_H based on the switching signal TEST.

  In the semiconductor device 1 having the above configuration, the drivers 42a and 42b, the level shifter 50, the selector 82, and the delay circuit 92 turn on / off both the transistors 12 and 22 according to the lower drive signal IN_L. Alternatively, a component of the lower drive circuit that determines whether the transistor 12 is turned off regardless of the lower drive signal IN_L and only the transistor 22 is turned on / off according to the lower drive signal IN_L based on the switching signal TEST. Equivalent to.

  FIG. 2A is a diagram illustrating an example of an external connection during an upper test of the semiconductor device 1 (a test for calculating an upper main current threshold Ith1 and determining whether or not this is within a normal range). FIG. 6 is a diagram illustrating an example of external connection during a lower test of a semiconductor device 1 (a test for calculating a lower main current threshold Ith2 and determining whether or not this is within a normal range).

  As shown in FIGS. 2A and 2B, when performing an upper test or a lower test of the semiconductor device 1, the test device 2 is externally connected to the semiconductor device 1. The test apparatus 2 outputs the upper test command and the lower test command as serial-type logic signals to the semiconductor device 1, and sets the thresholds of the overcurrent protection circuit 70 (upper main current threshold Ith1 and lower main current threshold). It is a device that determines whether or not Ith2) is within the normal range, and includes a current source X1, a voltmeter X2, and a test sequencer X3.

  The current source X1 flows an arbitrary test current Itest between the first external terminal and the second external terminal based on an instruction from the test sequencer X3. In the upper test of the semiconductor device 1, as shown in FIG. 2A, the external terminal T1 is selected as the first external terminal, and the external terminal T2 is selected as the second external terminal. Therefore, the test current Itest flows into the transistors 11 to 21. On the other hand, during the lower test of the semiconductor device 1, as shown in FIG. 2B, the external terminal T2 is selected as the first external terminal, and the external terminal T3 is selected as the second external terminal. Therefore, the test current Itest flows into the transistors 12 to 22.

  The voltmeter X2 measures the potential difference between the first external terminal and the second external terminal, and outputs the measured voltage Vtest to the test sequencer X3. In the upper test of the semiconductor device 1, as described above, the external terminal T1 is selected as the first external terminal, and the external terminal T2 is selected as the second external terminal. Therefore, the voltmeter X2 measures the potential difference between the external terminal T1 and the external terminal T2. On the other hand, during the lower test of the semiconductor device 1, as described above, the external terminal T2 is selected as the first external terminal, and the external terminal T3 is selected as the second external terminal. Therefore, the voltmeter X2 measures the potential difference between the external terminal T2 and the external terminal T3.

  The test sequencer X3 generates an upper test command and a lower test command to be output to the external terminal T5 of the semiconductor device 1, drive control of the current source X1, acquisition of a measured value of the voltmeter X2, and a threshold value of the overcurrent protection circuit 70 This is a logic circuit that performs calculation (calculation of the upper main current threshold Ith1 and the lower main current threshold Ith2).

  FIG. 3 is a timing chart for explaining the upper side test operation. In order from the top, the switching signal TEST, the upper side drive signal IN_H, the gate signal G11, the gate signal G21, the lower side drive signal IN_L, the gate signal G21, and the gate signal. G22, test current Itest, measurement voltage Vtest, and overcurrent protection signal Socp are shown.

  Upon receiving the upper test command from the test apparatus 2, the control circuit 60 first sets the upper drive signal IN_H to the low level over a predetermined period in a state where the switching signal TEST is set to the low level in order to execute the first step of the upper test operation. To fall. Thereby, the control circuit 60 turns on both the transistors 11 and 21 in accordance with the upper drive signal IN_H. Therefore, almost all of the test current Itest flowing from the current source X1 flows as the upper main current I11. During the upper test operation, the lower drive signal IN_L is always maintained at a low level, and both the transistors 12 and 22 are turned off.

On the other hand, while the test sequencer X3 is executing the first step of the upper test operation by the control circuit 60, the test sequencer X3 sets the test current Itest to an arbitrary current value I (0), and the voltage value of the measurement voltage Vtest. By obtaining V (0), the resistance value R11 of the upper main current path (current path from the external terminal T1 to the external terminal T2 through the transistor 11) through which the upper main current I11 flows is calculated. The equation for calculating the resistance value R11 is the following equation (1). Note that the resistance value R11 is substantially equal to the on-resistance value of the transistor 11.

  At this time, the current value I (0) of the test current Itest is a current value that does not activate the overcurrent protection operation, and is set to a current value that is large enough to correctly calculate the resistance value R11. It is desirable.

  Next, the control circuit 60 lowers the upper drive signal IN_H to a low level for a predetermined period in a state where the switching signal TEST is raised to a high level in order to execute the second step in the upper test operation. Thereby, the control circuit 60 turns off the transistor 11 regardless of the upper drive signal IN_H, and turns on only the transistor 21 according to the upper drive signal IN_H. Therefore, all the test currents Itest flowing from the current source X1 flow as the upper subcurrent I21. As described above, during the upper test operation, the lower drive signal IN_L is always maintained at a low level, and the transistors 12 and 22 are both turned off.

On the other hand, the test sequencer X3 sets the test current Itest to an arbitrary current value I (k) while the control circuit 60 executes the second step of the upper test operation, and the voltage value of the measurement voltage Vtest. By obtaining V (k), the resistance value R21 of the upper subcurrent path (current path from the external terminal T1 to the external terminal T2 through the sense resistor 31 and the transistor 21) through which the upper subcurrent I21 flows is calculated. The equation for calculating the resistance value R21 is the following equation (2). The resistance value R21 is substantially equal to the sum of the on-resistance value of the transistor 21 and the resistance value of the sense resistor 31.

  At this time, the current value I (k) of the test current Itest is a current value that does not activate the overcurrent protection operation, and is set to a current value that is large enough to correctly calculate the resistance value R21. It is desirable. For example, as will be described later, when current variable control is performed in which the current value I (k) of the test current Itest is gradually increased, an appropriate timing (for example, overcurrent protection operation is performed). The resistance value R21 may be calculated immediately before activation, that is, in a state where the test current Itest is set to the current value I (n-1).

  The test sequencer X3 gradually increased the current value I (k) of the test current Itest while the control circuit 60 was executing the second step of the upper test operation, and the overcurrent protection operation was activated. Current value I (n) of the test current Itest is obtained as the upper subcurrent threshold Ith1 ′.

  Then, the test sequencer X3 finally has the upper main current path resistance value R11, the upper sub current path resistance value R21, and the upper sub current threshold value Ith1 acquired in the first step and the second step. Based on ', the upper main current threshold Ith1 is calculated, and it is determined whether or not it is within the normal range. The calculation formula for the upper main current threshold Ith1 is the following formula (3).

  FIG. 4 is a timing chart for explaining the lower side test operation. In order from the top, the switching signal TEST, the upper side drive signal IN_H, the gate signal G11, the gate signal G21, the lower side drive signal IN_L, the gate signal G21, and the gate A signal G22, a test current Itest, a measurement voltage Vtest, and an overcurrent protection signal Socp are shown.

  The control circuit 60 that has received the lower test command from the test apparatus 2 first sets the lower drive signal IN_L for a predetermined period in a state where the switching signal TEST is at the low level in order to execute the first step of the lower test operation. To a high level. As a result, the control circuit 60 turns on both the transistors 12 and 22 in accordance with the lower drive signal IN_L. Therefore, almost all of the test current Itest flowing from the current source X1 flows as the lower main current I12. During the lower test operation, the upper drive signal IN_H is always maintained at a high level, and both the transistors 11 and 21 are turned off.

On the other hand, while the test sequencer X3 is executing the first step of the lower test operation in the control circuit 60, the test sequencer X3 sets the test current Itest to an arbitrary current value I (0) and sets the voltage of the measurement voltage Vtest. By obtaining the value V (0), the resistance value R12 of the lower main current path (current path from the external terminal T2 to the external terminal T3 through the transistor 12) through which the lower main current I12 flows is calculated. The equation for calculating the resistance value R12 is the following equation (4). Note that the resistance value R12 is substantially equal to the on-resistance value of the transistor 12.

  At this time, the current value I (0) of the test current Itest is a current value that does not activate the overcurrent protection operation, and is set to a current value that is large enough to correctly calculate the resistance value R12. It is desirable.

  Next, the control circuit 60 raises the lower drive signal IN_L to a high level for a predetermined period in a state where the switching signal TEST is raised to a high level in order to execute the second step in the lower test operation. Accordingly, the control circuit 60 turns off the transistor 12 regardless of the lower drive signal IN_L, and turns on only the transistor 22 according to the lower drive signal IN_L. Therefore, all the test currents Itest flowing from the current source X1 flow as the lower sub-current I22. As described above, during the lower test operation, the upper drive signal IN_H is always maintained at the high level, and the transistors 11 and 21 are both turned off.

On the other hand, while the test sequencer X3 is executing the second step of the lower test operation by the control circuit 60, the test sequencer X3 sets the test current Itest to an arbitrary current value I (k) and sets the voltage of the measurement voltage Vtest. By obtaining the value V (k), the resistance value R22 of the lower subcurrent path (current path from the external terminal T2 to the external terminal T3 through the transistor 22 and the sense resistor 32) through which the lower subcurrent I22 flows is obtained. calculate. The equation for calculating the resistance value R22 is the following equation (5). The resistance value R22 is substantially equal to the sum of the on-resistance value of the transistor 22 and the resistance value of the sense resistor 32.

  At this time, the current value I (k) of the test current Itest is a current value that does not activate the overcurrent protection operation, and is set to a current value that is large enough to correctly calculate the resistance value R22. It is desirable. For example, as will be described later, when current variable control is performed in which the current value I (k) of the test current Itest is gradually increased, an appropriate timing (for example, overcurrent protection operation is performed). The resistance value R22 may be calculated immediately before activation, that is, in a state where the test current Itest is set to the current value I (n-1).

  The test sequencer X3 gradually increases the current value I (k) of the test current Itest while the control circuit 60 executes the second step of the lower test operation, and the overcurrent protection operation is activated. The current value I (n) of the test current Itest at that time is acquired as the lower subcurrent threshold Ith2 ′.

  Then, the test sequencer X3 finally obtains the resistance value R12 of the lower main current path, the resistance value R22 of the lower sub current path, and the lower sub current acquired in the first step and the second step. Based on the threshold value Ith2 ′, the lower main current threshold value Ith2 is calculated, and it is determined whether or not this is within the normal range. The formula for calculating the lower main current threshold Ith2 is the following formula (6).

  As described above, the semiconductor device 1 of this configuration example is configured such that the transistors 21 to 22 can be driven independently of the transistors 11 to 12, so that only the transistors 21 to 22 are turned on when the semiconductor device 1 is tested. Thus, the resistance value R21 and the upper subcurrent threshold value Ith1 ′ of the upper subcurrent path, or the resistance value R22 of the lower subcurrent path and the threshold value Ith2 ′ of the lower subcurrent path can be measured.

  Therefore, in the case of the semiconductor device 1 of this configuration example, without passing an excessive test current Itest exceeding the main current thresholds Ith1 and Ith2, based on the above formulas (3) and (6), It is possible to calculate the main current thresholds Ith1 and Ith2 and determine whether they are within the normal range. As a result, special test equipment that can withstand the measurement of large currents is not necessary, so that it is possible to reduce the cost of the test at the time of shipment. It is possible to improve the quality (reducing the initial defect rate).

  In the semiconductor device 1 of this configuration example, not only the measurement results of the sub-current thresholds Ith1 ′ and Ith2 ′ but also the resistance values R11 and R12 of the main current path and the resistance values R21 and R22 of the sub-current path are obtained. Since the main current threshold values Ith1 and Ith2 are calculated separately and calculated based on the above-described equations (3) and (6), the mirror ratio α between the transistors 11 and 12 and the transistors 21 and 22 is obtained. And β vary from product to product, it is possible to correctly calculate the main current thresholds Ith1 and Ith2 and to ensure that the set values are within the normal range.

  Further, in the semiconductor device 1 of this configuration example, the resistance values R21 and R22 of the sub current path and the sub current thresholds Ith1 ′ and Ith2 are not required without using the test pads TP1 and TP2 shown in FIG. Since 'can be measured, it is possible to reduce the chip area, and it is possible to reduce the chip cost.

  In the semiconductor device 1 of this configuration example, a series of test sequences can be executed by inputting a test command from the external terminal T5 to the control circuit 60. Tests can be performed.

  3 and 4, the resistance values R11 and R12 of the main current path are calculated (first step) first, followed by the calculation of the resistance values R21 and R22 of the sub current path, Although the test sequence for executing the measurement of the current threshold values Ith1 ′ and Ith2 ′ (second step) is illustrated, the order of the first step and the second step may be reversed.

  Next, during normal operation of the semiconductor device 1, both the transistors 11 and 21 are simultaneously turned on / off according to the upper drive signal IN_H, and both the transistors 12 and 22 are simultaneously turned on according to the lower drive signal IN_L. A device for turning on / off will be described.

  In the semiconductor device 100 having the conventional configuration shown in FIG. 9, the gates of the transistor 11 and the transistor 21 are common to each other, so that both the transistors 11 and 21 are always turned on at the same time in accordance with the upper drive signal IN_H. / It was off. Similarly, in the semiconductor device 100 having the conventional configuration, the gates of the transistor 12 and the transistor 22 are also common to each other. Therefore, both the transistors 12 and 22 are always turned on / off simultaneously according to the lower drive signal IN_L. It was.

  On the other hand, in the semiconductor device 1 of this configuration example, the gates of the transistor 11 and the transistor 21 are separated from each other so that the transistor 21 can be driven independently of the transistor 11. Therefore, when an unintended phase difference occurs between the gate signal G11 and the gate signal G21, the on / off timing of the transistors 11 and 21 with respect to one upper drive signal IN_H may be shifted. Similarly, in the semiconductor device 1 of this configuration example, the gates of the transistor 12 and the transistor 22 are separated from each other so that the transistor 22 can be driven independently of the transistor 12. Therefore, when an unintended phase difference occurs between the gate signal G12 and the gate signal G22, the on / off timing of the transistors 12 and 22 with respect to the one lower drive signal IN_L may be shifted.

  Therefore, in the semiconductor device 1 of this configuration example, the signal path from the control circuit 60 to the transistors 11 to 12 and the signal path from the control circuit 60 to the transistors 21 to 22 are shown in FIG. As shown in a schematic diagram showing an example of an element layout, the layers are laid with symmetry.

  By adopting such an element layout, the wiring length of the signal path from the control circuit 60 to the transistors 11 to 12 and the signal path from the control circuit 60 to the transistors 21 to 22 can be matched as much as possible. It is possible to reduce the phase difference generated between the gate signal G11 and the gate signal G21 or the phase difference generated between the gate signal G12 and the gate signal G22. It is possible to reduce the ON / OFF timing shift of the transistors 11 and 21 or the ON / OFF timing shift of the transistors 12 and 22 with respect to one lower drive signal IN_L.

  In addition, as described above, the semiconductor device 1 of this configuration example has the signals generated by the selectors 81 and 82 with respect to the upper drive signal IN_H and the lower drive signal IN_L respectively input to the drivers 41b and 42b. The delay circuit 91 and the delay circuit 92 provide a signal delay equivalent to the delay. By adopting such a configuration, the signal delays respectively generated in the selectors 81 and 82 can be canceled by the signal delays generated in the delay circuits 91 and 92, respectively, so that they occur between the gate signal G11 and the gate signal G21. It is possible to reduce the phase difference or the phase difference generated between the gate signal G12 and the gate signal G22. As a result, the on / off timing shift of the transistors 11 and 21 with respect to one upper drive signal IN_H, Alternatively, it is possible to reduce a deviation in the on / off timing of the transistors 12 and 22 with respect to one lower drive signal IN_L.

  However, even if the above-described device is elaborated, the on / off timing shift of the transistors 11 and 21 with respect to one upper drive signal IN_H or the on / off timing shift of the transistors 12 and 22 with respect to one lower drive signal IN_L. In some cases, the problem cannot be resolved completely. In particular, when the transistor 21 is turned on while the transistor 11 is turned off, a current that should flow through the transistor 11 as the main current I11 flows into the sense resistor 31, and the overcurrent protection circuit 70 may malfunction. There is. Further, when the transistor 22 is turned on while the transistor 12 is turned off, a current that should flow through the transistor 12 as the main current I12 flows into the sense resistor 32, and the overcurrent protection circuit 70 may malfunction. There is.

  Therefore, in the semiconductor device 1 of this configuration example, in order to solve the above-described problem, the driver 41a turns on the transistor 11 without delay when the input signal becomes a logic level (low level) that turns on the transistor 11. On the other hand, when the input signal becomes a logic level (high level) for turning off the transistor 11, the gate signal G11 is generated so that the transistor 11 is turned off after a predetermined time d11 elapses from that point. ing. Further, when the input signal becomes a logic level (low level) for turning on the transistor 21, the driver 41b turns on the transistor 21 after a predetermined time d21 has elapsed from that point, while the input signal turns on the transistor 21. The gate signal G21 is generated so that the transistor 21 is turned off without delay when the logic level is turned off (high level).

  Similarly, the driver 42a turns on the transistor 12 without delay when the input signal becomes a logic level (high level) that turns on the transistor 12, while the driver 42a turns on the logic level (low level) that turns off the transistor 12. (Level), the gate signal G12 is generated so that the transistor 12 is turned off after a predetermined time d12 has elapsed. Further, when the input signal becomes a logic level (high level) for turning on the transistor 22, the driver 42b turns on the transistor 22 after a lapse of a predetermined time d22 from that time, while the input signal turns on the transistor 22. The gate signal G22 is generated so that the transistor 22 is turned off without delay when the logic level (low level) is turned off.

  FIG. 6 is a circuit diagram showing a configuration example of the drivers 41a, 41b, 42a, and 42b.

  The driver 41a includes a P-channel MOS field effect transistor P1a, an N-channel MOS field effect transistor N1a, a resistor R1a, and an inverter INV1a. The source of the transistor P1a is connected to the power supply terminal. The drain of the transistor P1a is connected to the input terminal of the inverter INV1a. The gate of the transistor P1a is connected to the output terminal of the selector 81. The source of the transistor N1a is connected to the ground terminal. The drain of the transistor N1a is connected to the input terminal of the inverter INV1a via the resistor R1a. The gate of the transistor N1a is connected to the output terminal of the selector 81. The output terminal of the inverter INV1a is connected to the gate of the transistor 11.

  The driver 41b includes a P-channel MOS field effect transistor P1b, an N-channel MOS field effect transistor N1b, a resistor R1b, and an inverter INV1b. The source of the transistor P1b is connected to the power supply terminal. The drain of the transistor P1b is connected to the input terminal of the inverter INV1b via the resistor R1b. The gate of the transistor P1b is connected to the output terminal of the delay circuit 91. The source of the transistor N1b is connected to the ground terminal. The drain of the transistor N1b is connected to the input terminal of the inverter INV1b. The gate of the transistor N1b is connected to the output terminal of the delay circuit 91. The output terminal of the inverter INV1b is connected to the gate of the transistor 21.

  The driver 42a includes a P-channel MOS field effect transistor P2a, an N-channel MOS field effect transistor N2a, a resistor R2a, and an inverter INV2a. The source of the transistor P2a is connected to the power supply terminal. The drain of the transistor P2a is connected to the input terminal of the inverter INV2a via the resistor R2a. The gate of the transistor P2a is connected to the output terminal of the selector 82. The source of the transistor N2a is connected to the ground terminal. The drain of the transistor N2a is connected to the input terminal of the inverter INV2a. The gate of the transistor N2a is connected to the output terminal of the selector 82. The output terminal of the inverter INV2a is connected to the gate of the transistor 12.

  The driver 42b includes a P-channel MOS field effect transistor P2b, an N-channel MOS field effect transistor N2b, a resistor R2b, and an inverter INV2b. The source of the transistor P2b is connected to the power supply terminal. The drain of the transistor P2b is connected to the input terminal of the inverter INV2b. The gate of the transistor P2b is connected to the output terminal of the delay circuit 92. The source of the transistor N2b is connected to the ground terminal. The drain of the transistor N2b is connected to the input terminal of the inverter INV2b via the resistor R2b. The gate of the transistor N2b is connected to the output terminal of the delay circuit 92. The output terminal of the inverter INV2b is connected to the gate of the transistor 22.

  In the driver 41a configured as described above, when the input signal (upper drive signal IN_H) from the selector 81 becomes a low level, the transistor P1a is turned on and the transistor N1a is turned off. At this time, the voltage applied to the input terminal of the inverter INV1a immediately becomes high level via the transistor P1a, and the gate signal G11 output from the output terminal of the inverter INV1a immediately becomes low level. Therefore, when the input signal from the selector 81 becomes low level, the transistor 11 is turned on without delay.

  On the other hand, in the driver 41a configured as described above, when the input signal from the selector 81 becomes high level, the transistor P1a is turned off and the transistor N1a is turned on. At this time, the voltage applied to the input terminal of the inverter INV1a gently falls to a low level via the resistor R1a and the transistor N1a, and the gate signal G11 output from the output terminal of the inverter INV1a has a predetermined delay. Become high level. Therefore, when the input signal from the selector 81 becomes high level, the transistor 11 is turned off after a predetermined time d11 has elapsed since that time.

  In the driver 41b configured as described above, when the input signal (upper drive signal IN_H) from the delay circuit 91 becomes low level, the transistor P1b is turned on and the transistor N1b is turned off. At this time, the voltage applied to the input terminal of the inverter INV1b gradually rises to a high level via the resistor R1b and the transistor P1b, and the gate signal G21 output from the output terminal of the inverter INV1b has a predetermined delay. Become low level. Therefore, when the input signal from the delay circuit 91 becomes low level, the transistor 21 is turned on after a predetermined time d21 has elapsed since that time.

  On the other hand, in the driver 41b having the above configuration, when the input signal from the delay circuit 91 becomes high level, the transistor P1b is turned off and the transistor N1b is turned on. At this time, the voltage applied to the input terminal of the inverter INV1b immediately becomes low level via the transistor N1b, and the gate signal G11 output from the output terminal of the inverter INV1b immediately becomes high level. Therefore, when the input signal from the delay circuit 91 becomes high level, the transistor 21 is turned off without delay.

  Further, in the driver 42a configured as described above, when the input signal (lower drive signal IN_L) from the selector 82 becomes low level, the transistor P2a is turned on and the transistor N2a is turned off. At this time, the voltage applied to the input terminal of the inverter INV2a gradually rises to a high level via the resistor R2a and the transistor P2a, and the gate signal G12 output from the output terminal of the inverter INV2a has a predetermined delay. Become low level. Therefore, when the input signal from the selector 82 becomes a low level, the transistor 12 is turned off after a predetermined time d12 has elapsed since that time.

  On the other hand, in the driver 42a configured as described above, when the input signal from the selector 82 becomes high level, the transistor P2a is turned off and the transistor N2a is turned on. At this time, the voltage applied to the input terminal of the inverter INV2a immediately becomes low level via the transistor N2a, and the gate signal G12 output from the output terminal of the inverter INV2a immediately becomes high level. Therefore, when the input signal from the selector 82 becomes high level, the transistor 12 is turned on without delay.

  In the driver 42b having the above-described configuration, when the input signal (lower drive signal IN_H) from the delay circuit 92 becomes low level, the transistor P2b is turned on and the transistor N2b is turned off. At this time, the voltage applied to the input terminal of the inverter INV2b immediately becomes high level via the transistor P2b, and the gate signal G22 output from the output terminal of the inverter INV2b immediately becomes low level. Therefore, when the input signal from the delay circuit 92 becomes low level, the transistor 22 is turned off without delay.

  On the other hand, in the driver 42b having the above configuration, when the input signal from the delay circuit 92 becomes high level, the transistor P2b is turned off and the transistor N2b is turned on. At this time, the voltage applied to the input terminal of the inverter INV2b gently falls to a low level via the resistor R2b and the transistor N2b, and the gate signal G22 output from the output terminal of the inverter INV2b has a predetermined delay. Become high level. Accordingly, when the input signal from the delay circuit 92 becomes a high level, the transistor 22 is turned on after a predetermined time d22 has elapsed since that time.

  FIG. 7 is a timing chart showing the output operations of the drivers 41a, 41b, 42a, and 42b described above. From the top, the upper drive signal IN_H, the gate signal G11, the gate signal G21, the lower drive signal IN_L, A gate signal G12 and a gate signal G22 are shown.

  As clearly shown in the timing chart of FIG. 7, in the semiconductor device 1 of this configuration example, the upper drive circuit including the drivers 41a and 42a turns both the transistor 11 and the transistor 21 on / off according to the upper drive signal IN_H. When turning off, the transistor 11 is turned on and then the transistor 21 is turned on, and the transistor 21 is turned off and then the transistor 11 is turned off. The lower drive circuit including the drivers 41b and 42b turns on the transistor 22 after turning on the transistor 12 when turning on / off both the transistor 12 and the transistor 22 according to the lower drive signal IN_L. In addition, the transistor 12 is turned off after the transistor 22 is turned off.

  With such a configuration, a shift in the on / off timing of the transistors 11 and 21 with respect to one upper drive signal IN_H or a shift in the on / off timing of the transistors 12 and 22 with respect to one lower drive signal IN_L. Even if it is not completely eliminated, a situation in which the transistors 21 to 22 are turned on in a state where the transistors 11 to 11 are turned off cannot occur, so that the malfunction of the overcurrent protection circuit 70 can be avoided.

  Finally, usage examples of the semiconductor device 1 will be described with reference to FIGS. 8A to 8D.

  FIG. 8A is a diagram illustrating a first usage example (usage example as a synchronous rectification step-down DC / DC controller) of the semiconductor device 1. In this first usage example, the external terminal T1 is connected to the input terminal of the input voltage Vin. The external terminal T2 is connected to the first end of the coil L1. The external terminal T3 is connected to the ground terminal. The second end of the coil L1 is connected to the output end of the output voltage Vout. The first end of the capacitor C1 is connected to the output end of the output voltage Vout. The second end of the capacitor C1 is connected to the ground end. Although not shown in the figure, in order to maintain the output voltage Vout at a predetermined target value, it is necessary to perform output feedback control using the control circuit 60, and a known technique is applied to this. A detailed explanation is omitted because it is sufficient.

  FIG. 8B is a diagram illustrating a second usage example (usage example as an asynchronous rectification step-down DC / DC controller) of the semiconductor device 1. In this second usage example, the external terminal T1 is connected to the input terminal of the input voltage Vin. The external terminal T2 is connected to the first end of the coil L2 and the cathode of the diode D1. The external terminal T3 is connected to the ground terminal and the anode of the diode D1. The second end of the coil L2 is connected to the output end of the output voltage Vout. The first end of the capacitor C2 is connected to the output end of the output voltage Vout. The second end of the capacitor C2 is connected to the ground end. In the second usage example of the semiconductor device 1, the transistor 12 and related circuit elements (the transistor 22, the drivers 42 a and 42 b, the selector 82, and the delay circuit 92) are unnecessary. In addition, as in the first usage example described above, in order to maintain the output voltage Vout at a predetermined target value, it is necessary to perform output feedback control using the control circuit 60. For this, a known technique is applied. Detailed explanation is omitted.

  FIG. 8C is a diagram illustrating a third usage example of the semiconductor device 1 (usage example as an asynchronous rectification step-up DC / DC controller). In the third usage example, the external terminal T1 is connected to the input end of the input voltage Vin and the first end of the coil L3. The external terminal T2 is connected to the second end of the coil L3 and the anode of the diode D2. The external terminal T3 is connected to the ground terminal. The cathode of the diode D2 is connected to the output terminal of the output voltage Vout. A first terminal of the capacitor C3 is connected to an output terminal of the output voltage Vout. The second end of the capacitor C3 is connected to the ground end. In the third usage example of the semiconductor device 1, the transistor 11 and circuit elements related thereto (transistor 21, drivers 41 a and 41 b, selector 81, and delay circuit 91) are not necessary. Further, as in the first usage example and the second usage example described above, in order to maintain the output voltage Vout at a predetermined target value, it is necessary to perform output feedback control using the control circuit 60. Since it is sufficient to apply a known technique, a detailed description is omitted.

  FIG. 8D is a diagram illustrating a fourth usage example (usage example as a DC motor driver) of the semiconductor device 1. When the semiconductor device 1 is used as a DC motor driver, two external terminals T2x and T2y to which both ends of the motor coil L4 are respectively connected are prepared for the semiconductor device 1 as shown in FIG. In the semiconductor device 1, an output stage (transistors 11x and 12x and transistors 11y and 12y) connected to the motor coil L4 in an H-bridge type may be incorporated. That is, in the fourth usage example of the semiconductor device 1, the two circuit terminals shown in FIG. 1 are basically required for the two external terminals T2x and T2y. However, the sense resistors 31 and 32, the level shifter 50, the control circuit 60, and the overcurrent protection circuit 70 may be provided in common in both systems.

  The first to fourth usage examples described above are merely examples, and the use of the semiconductor device 1 is not limited to the above. Various circuit configurations of the semiconductor device 1 can be used depending on the use. It goes without saying that the deformation of can be added.

  That is, the configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the spirit of the invention. As described above, the above embodiments are examples in all respects and should not be considered to be restrictive, and the technical scope of the present invention is not the description of the above embodiments, but the claims. It is to be understood that all changes that come within the scope of the claims, are equivalent in meaning to the claims, and fall within the scope of the claims.

  The present invention can be used, for example, in a semiconductor device (such as a switching regulator IC or a motor driver IC) provided with an overcurrent protection circuit.

1 Semiconductor device 11, 11x, 11y Upper main transistor (PMOSFET)
12, 12x, 12y Lower main transistor (NMOSFET)
21 Upper sub-transistor (PMOSFET)
22 Lower sub-transistor (NMOSFET)
31, 32 Sense resistor 41a Upper main driver 41b Lower main driver 42a Upper sub driver 42b Lower sub driver 50 Level shifter 60 Control circuit (logic circuit)
70 Overcurrent protection circuit 81, 82 Selector 91, 92 Delay circuit T1 to T5, T2x, T2y External terminal 2 Test device X1 Current source X2 Voltmeter X3 Test sequencer P1a, P1b, P2a, P2b PMOSFET
N1a, N1b, N2a, N2b NMOSFET
R1a, R1b, R2a, R2b Resistor INV1a, INV1b, INV2a, INV2b Inverter L1, L2, L3, L4 Coil C1, C2, C3 Capacitor D1, D2 Diode

Claims (12)

A first external terminal;
A second external terminal;
A main transistor connected between the first external terminal and the second external terminal for flowing a main current;
A sub-transistor connected between the first external terminal and the second external terminal for passing a sub-current that exhibits the same behavior as the main current;
A control circuit for generating a drive signal common to both the main transistor and the sub-transistor;
An overcurrent protection circuit that compares the subcurrent with a predetermined threshold for subcurrent to generate an overcurrent protection signal and outputs the signal to the control circuit;
Both the main transistor and the sub-transistor are turned on / off according to the drive signal, or the main transistor is turned off regardless of the drive signal, and only the sub-transistor is turned on / off according to the drive signal. A driving circuit for determining whether or not based on a predetermined switching signal;
A semiconductor device comprising: The drive circuit is
A selector that outputs one of the drive signal and a logic signal for turning off the main transistor based on the switching signal;
A main driver for driving the main transistor in accordance with the output of the selector;
A sub-driver for driving the sub-transistor in response to the drive signal;
The semiconductor device according to claim 1, comprising:   The semiconductor device according to claim 2, wherein the drive circuit includes a level shifter that converts a voltage level of the drive signal into a voltage level suitable for input to the main driver and the sub driver.   4. The delay circuit according to claim 2, wherein the drive circuit includes a delay circuit that gives a signal delay equivalent to a signal delay generated by the selector to the drive signal input to the sub-driver. Semiconductor device. The main driver turns on the main transistor without delay when the input signal becomes a logic level for turning on the main transistor, while the input signal becomes a logic level for turning off the main transistor. The main transistor is turned off after a lapse of a predetermined time from that point,
When the input signal becomes a logic level for turning on the sub-transistor, the sub-driver turns on the sub-transistor after a lapse of a predetermined time from that point, while the input signal turns off the sub-transistor. When the logic level is reached, the sub-transistor is turned off without delay.
The semiconductor device according to claim 2, wherein:   6. The signal path from the control circuit to the main transistor and the signal path from the control circuit to the sub-transistor are laid with symmetry to each other. A semiconductor device according to claim 1.   The drive circuit turns on the sub-transistor after turning on the main transistor and turns off the sub-transistor when turning on / off both the main transistor and the sub-transistor according to the drive signal. The semiconductor device according to claim 1, wherein the main transistor is turned off after that.   The semiconductor device according to claim 1, wherein the switching signal is output from the control circuit. The control circuit includes:
Based on a test command input from the outside of the semiconductor device,
A first step of turning on both the main transistor and the sub-transistor according to the drive signal;
A second step of turning off the main transistor regardless of the drive signal and turning on only the sub-transistor according to the drive signal;
The semiconductor device according to claim 8, wherein the drive signal and the switching signal are generated so as to be executed in any order.   10. A test comprising: outputting the test command to the semiconductor device according to claim 1 to determine whether or not a threshold value of the overcurrent protection circuit is within a normal range. apparatus. A current source for supplying an arbitrary test current between the first external terminal and the second external terminal;
A voltmeter for measuring a potential difference between the first external terminal and the second external terminal;
A test sequencer for generating the test command, driving control of the current source, obtaining a measurement value of the voltmeter, and calculating a threshold value of the overcurrent protection circuit;
The test apparatus according to claim 10, further comprising: The test sequencer
While the first step is executed by the control circuit, a main current path through which the main current flows is obtained by acquiring a measurement value of the voltmeter in a state where the test current is set to an arbitrary current value. Calculate the resistance value of
While the second step is executed by the control circuit, a sub current path through which the sub current flows is obtained by acquiring a measurement value of the voltmeter in a state where the test current is set to an arbitrary current value. While gradually increasing the test current to obtain the current value of the test current when the overcurrent protection operation is activated as the sub-current threshold value;
Finally, the main current threshold value is calculated based on the resistance value of the main current path, the resistance value of the sub current path, and the threshold value for the sub current, and whether or not this is within the normal range. The test apparatus according to claim 11, wherein:

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