CN109521350B

CN109521350B - Measuring apparatus and measuring method

Info

Publication number: CN109521350B
Application number: CN201710843624.3A
Authority: CN
Inventors: 蔡佳宏; 林富仓; 林亚民
Original assignee: King Yuan Electronics Co Ltd
Current assignee: King Yuan Electronics Co Ltd
Priority date: 2017-09-19
Filing date: 2017-09-19
Publication date: 2021-05-07
Anticipated expiration: 2037-09-19
Also published as: CN109521350A

Abstract

The present invention provides a measuring apparatus comprising: n comparators and M channels, each for connecting with one of a plurality of consecutive pins of an object to be tested, and each channel respectively connected with one of the comparators, wherein each channel has a switch; the channels are divided into a group by N in sequence to form at least one channel subgroup, and the channels in each channel subgroup are connected with the 1 st to N comparators in sequence.

Description

Measuring apparatus and measuring method

Technical Field

The present invention relates to a measuring apparatus and a measuring method thereof, and more particularly, to a measuring apparatus and a measuring method thereof suitable for measuring a pin of an integrated circuit.

Background

In the conventional Integrated Circuit (IC) measurement device, in order to allow a user to arbitrarily arrange the positions of ICs to be tested, a comparator is connected to each Channel (Channel) for connecting IC pins on the measurement device, so as to facilitate writing of a test program. However, in practical applications, only a part of the comparators are used, and the unused comparators remain idle. Therefore, the design often causes the cost of the measuring equipment to be increased, the size of the measuring equipment to be increased, and the resource waste to be doubtful.

The present invention provides a measuring apparatus and a measuring method to solve the above problems.

Disclosure of Invention

An object of the present invention is to provide a measuring apparatus, comprising: n comparators, wherein N is a positive integer more than 1; and M channels, M is a positive integer greater than N, each channel is used for connecting with one of a plurality of continuous pins of an object to be detected, and each channel is respectively connected with one of the comparators, wherein each channel is provided with a switch; the channels are divided into a group by N in sequence to form at least one channel subgroup, and the channels in each channel subgroup are connected with the 1 st to N comparators in sequence.

In one embodiment, the channels are divided into a group of N in sequence, and then have a remaining channels, and the a channels are sequentially connected with the 1 st to a th comparators, wherein a is a positive integer smaller than N.

In one embodiment, when the dut has i consecutive pins and is connected to i channels of the channels, the switches on the i channels are turned on, respectively, so that the comparators connected to the i channels measure the pins during the period when the corresponding switches are turned on, where i is a positive integer not greater than M.

In one embodiment, the switches on these i channels are turned on sequentially.

Another objective of the present invention is to provide a measurement method implemented in a measurement apparatus, the measurement apparatus includes N comparators and M channels, each channel is configured to be connected to one of a plurality of consecutive pins of an object to be measured, each channel is respectively connected to one of the comparators, and each channel has a switch thereon, the channels are sequentially grouped into a group by N to form at least one channel subgroup, and the channels in each channel subgroup are sequentially connected to the 1 st to N comparators, where N is a positive integer greater than 1, and M is greater than N, the measurement method includes the following steps: connecting a plurality of continuous pins of the object to be detected to one of the channels respectively; and controlling switches on the channels to enable the comparator to measure a plurality of continuous pins of the object to be measured.

In one embodiment, the channels are divided into a group of N in sequence and have a remaining channels, and the a channels are sequentially connected with the 1 st to a th comparators, wherein a is less than a positive integer of N.

In one embodiment, the measuring method further comprises the steps of: when the object to be measured has i continuous pins and is respectively connected with i channels of the channels, the switches on the i channels are respectively conducted, so that the comparators connected with the i channels conduct the measurement of the pins in the period when the corresponding switches are conducted, wherein i is a positive integer not more than M.

In one embodiment, the measuring method further comprises the steps of: when the 1 st pin of the object to be tested corresponds to the b th comparator, switches corresponding to the b th to N comparators are respectively conducted, wherein b is a positive integer not greater than N.

In one embodiment, the measuring method further comprises the steps of: when the switches corresponding to the b-th to N-th comparators are turned on, the switches corresponding to the continuous pins of the object to be measured are turned on respectively.

In one embodiment, the measuring method further comprises the steps of: the switches on the b-th to N-th channels are conducted in sequence, and the switches corresponding to the continuous pins of the object to be measured which are not measured are conducted in sequence.

Drawings

Fig. 1 is a schematic diagram of a basic architecture of a measurement device according to an embodiment of the present invention.

Fig. 2(a) is a schematic circuit diagram of a measurement apparatus according to an embodiment of the present invention.

Fig. 2(B) is a schematic diagram of a partial circuit structure of a measurement apparatus according to an embodiment of the present invention.

Fig. 3(a) is a schematic diagram illustrating a connection manner between a measurement device and an object to be measured according to an embodiment of the invention.

Fig. 3(B) is a schematic view illustrating another connection mode between the measurement apparatus and the object according to an embodiment of the invention.

Fig. 4 is a flowchart illustrating a basic operation method of a measurement apparatus according to an embodiment of the present invention.

Fig. 5(a) is a schematic diagram of an operation situation of the measurement apparatus according to an embodiment of the present invention.

Fig. 5(B) is a flowchart of a partial operation method corresponding to fig. 5 (a).

Fig. 6(a) is a schematic diagram of an operation situation of a measurement apparatus according to another embodiment of the present invention.

Fig. 6(B) is a flowchart of a partial operation method corresponding to fig. 6 (a).

Fig. 6(C) is a schematic diagram of an operation situation of a measurement apparatus according to yet another embodiment of the present invention.

Fig. 6(D) is a flowchart of a partial operation method corresponding to fig. 6 (C).

[ notation ] to show

10 measuring device

20 channel unit

30 switch unit

40 comparison unit

50 IC to be tested

DP1-DPM channel

SW1-SWM switch

CP1-CPN comparator

SDP1-SDP2 channel subgroup

PIN1-PINi PIN

S41-S45 steps

S51-S54 steps

S61-S64 steps

S61' -S64

Detailed Description

The following description will explain the implementation and operation principle of the measuring device according to the present invention by using several embodiments. Those skilled in the art can appreciate that the features and effects of the present invention from the above-described embodiments can be combined, modified, replaced or converted based on the spirit of the present invention.

The term "coupled" as used herein includes direct coupling or indirect coupling, and is not intended to be limiting. The term "when …", "…" as used herein means "when, before or after", and is not intended to be limiting.

Fig. 1 is a schematic diagram of a basic architecture of a measurement apparatus 10 according to an embodiment of the present invention. The measurement apparatus 10 includes a channel unit 20, a switch unit 30, and a comparison unit 40. The channel unit 20 is used to connect with an object 50 to be tested (e.g. an IC to be tested), and the comparison unit 40 is used to measure the object 50 to be tested. The switch unit 30 is disposed on the channel unit 20 to control whether the comparison unit 40 performs measurement.

Fig. 2(a) is a schematic circuit diagram of a measurement apparatus 10 according to an embodiment of the present invention, and please refer to fig. 1. The channel unit 20 includes M channels (DP1-DPM), where M is a positive integer of 2 or more. The switch unit 30 includes M switches (SW1-SWM), and each switch (SW1-SWM) is disposed on one channel (DP 1-DPM). The comparison unit 40 includes N comparators (CP1-CPN), where N is a positive integer greater than 1 and N is less than M.

In one embodiment, each channel includes a switch, i.e., channel DP1 is provided with switch SW1, channel DP2 is provided with switch SW2, and so on, but is not limited thereto. Furthermore, the channel (DP1-DPM) is connected to a comparator (CP 1-CPN). Since M is greater than N, one comparator may be connected to more than 2 channels.

When a pin of the dut 50 is connected to one of the channels (DP1-DPM), the comparator connected to the channel will measure the pin as long as the switch on the channel is turned on. In one embodiment, the comparator compares the voltage of the pin with a predetermined range to determine whether the pin is normal, but the invention is not limited thereto.

In addition, the switches (SW1-SWM) can be turned on or off by various methods, such as an external controller, etc., and the detailed description is omitted because how to control the switches (SW1-SWM) to be turned on belongs to the prior art of the ordinary skill in the art and is not the focus of the present invention. In addition, the switches (SW1-SWM) may be transistors or other electronic devices that can be used as switches, or may be mechanical switches, and the type of the switches (SW1-SWM) is not critical to the present invention and is not described in detail herein.

The position of the switch on the channel can be replaced, for example, at the channel connection pin, or between the channel and the comparator, and the invention is not limited in particular.

In one embodiment, the conduction periods of each switch on the channels (DP1-DPM) do not overlap. In other embodiments, however, the conduction periods of the N switches on the channel (DP1-DPM) may overlap, but the comparators connected to the N switches are different.

In one embodiment, the lanes (DP1-DPM) are grouped into N in sequence to form at least one lane subgroup, and the lanes in each lane subgroup are connected to the 1 st to N comparators in sequence. In addition, if there are a remaining channels after N channels (DP1-DP (M)) are sequentially grouped into a group, the a channels are sequentially connected to the 1 st to a th comparators, wherein a is a positive integer less than N.

The following will explain a partial circuit structure of the present invention.

Fig. 2(B) is a schematic diagram of a circuit partial structure of the measurement apparatus 10 according to an embodiment of the present invention, and please refer to fig. 1 to 2 (B). This embodiment is described with N being 128 and M being 259. Since the circuit structure of this embodiment is similar to that of fig. 2(a), some duplicated elements are not described here and are not labeled in fig. 2 (B).

In this embodiment, the channels (DP1-DP230) are sequentially grouped into 128 channels to form 2 channel subgroups (SDP1-SDP2), and the channels in each channel subgroup (SDP1-SDP2) are sequentially connected to the 1 st to 128 comparators, for example, the channels (DP1-DP128) in the 1 st channel subgroup (SDP1) are respectively connected to the 1 st to 128 comparators (CP1-CP128) through switches, and the channels (DP129-DP256) in the 2 nd channel subgroup (SDP2) are respectively connected to the 1 st to 128 comparators (CP1-CP128) through switches.

In addition, since the remaining 3 lanes (DP257-DP259) are not sufficient to form a lane subgroup after the lanes (DP1-DP256) are sequentially grouped into 128 lanes, the lanes (DP257-DP259) are sequentially connected to the 1 st to 3 rd comparators (CP1-CP 3).

The connection between the channels (DP1-DP259) and the comparators (CP1-CP128) is exemplary only and not intended to be limiting.

The following description will be made with respect to various connection modes of the analyte 50.

Fig. 3(a) is a schematic view of a connection manner between the measurement apparatus 10 and the object 50 according to an embodiment of the invention, and please refer to fig. 1 to fig. 2 (B). In this embodiment, the DUT 50 has i consecutive PINs (PIN1-PINi), where i is a positive integer greater than 1 and i is less than or equal to M. When the PIN (PIN1-PINi) of the dut 50 is to be connected to the channel (DP1-DPM), the 1 st PIN (PIN1) of the dut 50 may be connected to the 1 st channel (DP1), and so on, i.e., the ith PIN (PINi) is connected to the ith channel (DPi).

Fig. 3(B) is a schematic view of another connection mode between the measurement apparatus 10 and the object 50 according to an embodiment of the invention, and please refer to fig. 1 to 3(a) at the same time. In this embodiment, when the PINs (PIN1-PINi) of the dut 50 are to be connected to the lanes (DP1-DPM), the PINs (PIN1-PINi) of the dut 50 are arbitrarily connected to i consecutive lanes on the lanes (DP1-DPM), such that the 1 st PIN is connected to the b-th lane, b being a positive integer greater than 1 and not greater than N. As shown in fig. 3(B), in this embodiment, B is 3, i.e., the 1 st PIN (PIN1) of the dut 50 can be connected to the 3 rd channel (DP3), and so on, so that the ith PIN (PINi) is connected to the (3+ i) th channel (DP (3+ i)).

The connection between the PIN (PIN1-PINi) and the channel (DP1-DPM) of the DUT 50 is only an example and is not a limitation of the present invention.

Fig. 4 is a flowchart of a basic operation method of the measurement apparatus 10 according to an embodiment of the present invention, and please refer to fig. 1 to fig. 3 (B). First, step S41 is executed, i consecutive PINs (PIN1-PINi) of the dut 50 are connected to i consecutive channels of the channels (DP1-DPM), respectively. Then, step S42 is executed to turn on the switches on the i channels respectively, and the pins corresponding to the switches are measured during the turn-on periods of the switches on the i channels through the comparators connected to the i channels, wherein the "turn-on respectively" may be sequential or non-sequential. Thereafter, step S43 is executed, and when the measurement of all the pins is completed, the measuring apparatus 10 outputs the measurement result of each pin, and since the data output belongs to the prior art of the person skilled in the art and is not the focus of the present invention, the detailed description is omitted.

When the number of PINs (PIN1-PINi) of the dut 50 is different and/or the connection method is different, the partial flow of the method of fig. 4 is also different. The following will describe a partial operation flow of the measurement device 10 to be measured.

Fig. 5(a) is a schematic diagram of an operation of the measuring apparatus 10 according to an embodiment of the invention, and fig. 5(B) is a flowchart of a partial operation method corresponding to fig. 5 (a). FIGS. 5(A) and 5(B) illustrate the operation when the number of pins of the DUT is less than or equal to the number of comparators (i.e., i ≦ N). In this embodiment, the number of comparators is illustrated as 6 (N-6), the number of channels is illustrated as 15 (M-15), the number of pins of the dut 50 is illustrated as 4 (i-4), and the number of channel subgroups is illustrated as 2 (i.e., SDP1, SDP 2).

In this embodiment, the 1 st PIN (PIN1) of the dut 50 is connected to the 2 nd channel (DP2), i.e., b is 2, so the PINs (PIN1-PIN4) of the dut 50 correspond to the comparators (CP2-CP5), respectively.

Fig. 5(B) is a flowchart of a partial operation method corresponding to fig. 5(a), and please refer to fig. 4 at the same time. First, step S51 is executed, i consecutive PINs of the test IC50 are connected to i channels of the channels (DP1-DP15), respectively, i.e., the PINs (PIN1-PIN4) of the dut 50 are connected to the 2 nd to 5 th channels (DP2-DP5), respectively.

Thereafter, step S52 is executed to turn on the switches on the i channels, respectively. In this embodiment, switches (SW2-SW5) on channels 2-5 (DP2-DP5) are turned on, respectively, and comparators 2-5 (CP2-CP5) measure PINs (PIN1-PIN4) during the turn-on of switches (SW2-SW5), respectively, i.e., when switch 2 SW2 is turned on, comparator 2 (CP2) measures PIN1 (PIN1), and so on. The switches SW2-SW5 may be turned on sequentially or not sequentially.

Thereafter, step S53 is executed, and when the measurement of the PIN (PIN1-PIN4) is completed, the measurement apparatus 10 outputs the measurement result.

According to the above operation, since the number of the PINs of the object 50 is not greater than the number of the comparators (i.e. i is not greater than N), no matter how the PINs of the object 50 are connected to the channel (for example, no matter whether the 1 st PIN (PIN1) is connected to the 1 st channel (DP 1)), each comparator only needs to perform one measurement, and thus the measurement of all the PINs of the object 50 can be completed.

Fig. 6(a) is a schematic diagram of an operation situation of the measurement apparatus 10 according to another embodiment of the present invention, and fig. 6(B) is a flowchart of a partial operation method corresponding to fig. 6 (a). Fig. 6(a) and 6(B) illustrate an operation when the pin number of the dut 50 is greater than the number of comparators (i > N).

In the embodiment of fig. 6(a) to 6(D), the number of comparators is illustrated as 6(N ═ 6), the number of channels is illustrated as 15(M ═ 15), the number of pins of the dut 50 is illustrated as 8(i ═ 8), and the number of channel subgroups is illustrated as 2(SDP1, SDP 2).

In the embodiment of fig. 6(a), the 1 st PIN (PIN1) of the object 50 is connected to the 1 st channel (DP1), further connected to the 1 st comparator (CP1), and so on, i.e., the PINs (PIN1-PIN6) of the object 50 are connected to the 1 st to 6 th channels (DP1-DP 6). In addition, the remaining PINs (PIN7, PIN8) of the DUT 50 are sequentially reconnected to the 1 st to 2 nd channels (DP1-DP2) and further connected to the 1 st to 2 nd comparators (CP1-CP 2).

Fig. 6(B) is a flowchart of a partial operation method corresponding to fig. 6(a), and please refer to fig. 4 at the same time. First, step S61 is executed, i consecutive PINs of the test IC50 are respectively connected to i of the channels (DP1-DP15), and the 1 st PIN (PIN1) corresponds to the 1 st channel (DP1), i.e., the PINs (PIN1-PIN6) of the object 50 are respectively connected to the 1 st to 6 th channels (DP1-DP6), and the remaining PINs (PIN7-PIN8) of the object 50 are respectively connected to the 1 st to 2 nd channels (DP1-DP 2).

Thereafter, step S62 is performed, in which the switches (SW1-SWN) on the channels (DP1-DPN) to which the 1 st to N-th PINs (PIN1-PINN) are connected are turned on, respectively, so that the 1 st to N-th comparators (CP1-CPN) measure the corresponding PINs (PIN1-PINN) during the on periods of the corresponding switches (SW1-SWN), that is, the switches (SW1-SW6) on the channels (DP1-DP6) are turned on, respectively, and the comparators (CP1-CP6) measure the PINs (PIN1-PIN6) during the on periods of the switches (SW1-SW6), respectively. The switches SW1-SW6 may be turned on sequentially or not sequentially.

Thereafter, step S63 is executed to turn on the switches (SW (N +1) -SWi) of the channels (DP (N +1) -DPi) to which the remaining PINs (PIN (N +1) -PINi) are connected, so that the comparators corresponding to the remaining PINs (PIN (N +1) -PINi) measure the PINs (PIN (N +1) -PINi) during the turn-on periods of the corresponding switches (SW (N +1) -SWi), that is, the switches (SW7-SW8) of the channels (DP7-DP8) are turned on, respectively, and the comparators (CP1-CP2) measure the PINs (PIN7-PIN8) during the turn-on periods of the switches (SW7-SW8), respectively. The switches SW7-SW8 may be turned on sequentially or not sequentially.

It should be noted that in this embodiment, the number of remaining pins is only 2, but in other embodiments, the number of remaining pins may be larger. If the remaining pins are more than N, before performing step S63, step S621 is performed to turn on the switches corresponding to the 1 st to N th pins in the remaining pins, so that the 1 st to N th pins in the remaining pins are measured and repeatedly performed until the number of the remaining pins is less than N, and then step S63 is performed. In other words, after the step S62 is executed, if the remaining pins are less than N, the process proceeds to step S63 directly.

Thereafter, step S64 is executed, and when the measurement of all the pins is completed, the measurement apparatus 10 outputs the measurement result.

Next, description will be made with respect to the embodiment of fig. 6 (C).

Fig. 6(C) is a schematic diagram of an operation of the measuring apparatus 10 according to yet another embodiment of the present invention, and fig. 6(D) is a flowchart of a partial operation method corresponding to fig. 6 (C). Fig. 6(C) and 6(D) illustrate another operation when the pin number of the dut 50 is greater than the number of comparators (i > N).

In the embodiment of fig. 6(C), the 1 st PIN (PIN1) of the object 50 is connected to the 4 th channel (DP4), further connected to the 4 th comparator (CP4), and so on, i.e., the 1 st to 3 rd PINs (PIN1-PIN3) of the object 50 are respectively connected to the 4 th to 6 th channels (DP4-DP 6). In addition, the 4 th to 8 th PINs (PIN4-PIN8) of the DUT 50 are sequentially connected to the 7 th to 12 th channels (DP7-DP12) and further connected to the 1 st to 5 th comparators (CP1-CP 5).

Fig. 6(D) is a flowchart of a partial operation method corresponding to fig. 6(C), and please refer to fig. 4 at the same time. First, step S61' is executed, i consecutive PINs of the object 50 to be tested are respectively connected to i channels of the channels (DP1-DP15), wherein the 1 st PIN (PIN1) corresponds to the b-th channel (DPb), i.e. the PINs (PIN1-PIN3) of the object 50 to be tested are respectively connected to the channels (DP4-DP6), and the remaining PINs (PIN4-PIN8) of the object 50 to be tested are sequentially connected to the channels (DP7-DP12), and further connected to the comparators (CP1-CP 5).

Thereafter, step S62' is performed, the switches (SWb-SWN) on the channels (DPb-DPN) to which the 1 st to (N-b +1) th PINs (PIN1-PIN (N-b +1)) are connected are turned on, respectively, so that the b th to N th comparators (CPb-CPN) measure the corresponding PINs (PIN1-PIN (N-b +1)) during the turn-on period of the corresponding switches (SWb-SWN), that is, the switches (SW4-SW6) on the channels (DP4-DP6) are turned on, respectively, and the comparators (CP4-CP6) measure the PINs (PIN1-PIN3) during the turn-on period of the switches (SW4-SW6), respectively. The switches SW4-SW6 may be turned on sequentially or not sequentially.

Thereafter, step S63' is executed to turn on the switches (SW (N +1) -SWi) on the channels (DP (N +1) -DPi) to which the remaining PINs (PIN (N-b +2) -PINi) are connected, so that the comparators corresponding to the remaining PINs (PIN (N-b +2) -PINi) measure the PINs (PIN (N-b +2) -PINi) during the turn-on periods of the corresponding switches (SW (N +1) -SWi), i.e., the switches (SW7-SW12) on the channels (DP7-DP12) are turned on, respectively, and the comparators (CP1-CP5) measure the PINs (PIN5-PIN8) during the turn-on periods of the switches (SW7-SW12), respectively. The switches SW7-SW12 may be turned on sequentially or not sequentially.

It should be noted that, in this embodiment, the number of the remaining pins is only 5, but in other embodiments, the number of the remaining pins may be more, if the remaining pins are more than N, step S621 ' is performed before step S63 ', the switches corresponding to the 1 st to N th pins in the remaining pins are turned on respectively, so that the 1 st to N th pins in the remaining pins are measured and repeatedly performed until the number of the remaining pins is less than N, and then step S63 ' is performed. In other words, after the step S62 ', if the remaining pins are less than N, the process proceeds to step S63'.

Thereafter, step S64' is performed, and when the measurement of all the pins is completed, the measurement apparatus 10 outputs the measurement result.

The number of pins, the number of channels, the number of switches, and the number of comparators of the dut in the above embodiment are only examples, and actually there may be more pins. In addition, the measurement sequence of each pin can be changed by controlling the conduction of the switch, and the present invention is not limited to the above embodiment.

Therefore, the invention can connect the continuous pins of the object to be measured to any channel of the measuring equipment, reduce the number of the comparators, reduce the overall cost and avoid waste caused by too many idle elements. In addition, the invention can also reduce the whole volume of the measuring equipment, reduce the use space of a dust-free room and improve the utilization rate of production energy.

The above-described embodiments are merely exemplary for convenience in explanation, and the scope of the claims of the present invention should be determined by the claims rather than by the limitations of the above-described embodiments.

Claims

1. A measurement device, comprising:

n comparators, wherein N is a positive integer more than 1; and

m channels, M is a positive integer larger than N, each channel is used for being connected with one of a plurality of continuous pins of an object to be detected, and each channel is respectively connected with one of the comparators, wherein each channel is provided with a switch;

the channels are divided into a group by N in sequence to form at least one channel subgroup, the channels in each channel subgroup are sequentially connected with the 1 st to N comparators, the adjacent channels are connected with the adjacent pins of the object to be tested, and the adjacent pins are connected with different comparators.

2. The measurement apparatus of claim 1, wherein the channels are grouped into N in sequence with a remaining channels, the a channels being connected to the 1 st to a th comparators in sequence, wherein a is a positive integer less than N.

3. The measurement apparatus according to claim 2, wherein when the dut has i consecutive pins and is connected to i channels of the channels, the switches on the i channels are turned on, respectively, so that the comparators connected to the i channels perform the measurement of the pins during a period in which their corresponding switches are turned on, where i is a positive integer not greater than M.

4. The measurement device as claimed in claim 3 wherein the switches on the i channels are turned on sequentially.

5. A measuring method is executed on a measuring device, the measuring device comprises N comparators and M channels, each channel is used for being connected with one of a plurality of continuous pins of an object to be measured, each channel is respectively connected with one of the comparators, each channel is provided with a switch, the channels are sequentially divided into a group by N to form at least one channel subgroup, and the channels in each channel subgroup are sequentially connected with the 1 st comparator to the N comparators, wherein N is a positive integer more than 1, and M is more than the positive integer of N, the measuring method comprises the following steps:

connecting a plurality of continuous pins of the object to be detected to one of the channels respectively; and

and controlling the switches on the channels to enable the comparators to measure a plurality of continuous pins of the object to be measured, wherein the adjacent channels are connected with the adjacent pins of the object to be measured, and the adjacent pins are connected with different comparators.

6. The method of claim 5, wherein the plurality of channels are grouped into N in sequence with a remaining plurality of channels, the a plurality of channels are connected to the 1 st to a th comparators in sequence, wherein a is less than a positive integer of N.

7. The measuring method of claim 6, further comprising the steps of: when the object to be measured has i continuous pins and is respectively connected with i continuous channels of the channels, switches on the i channels are respectively conducted, so that the comparators connected with the i channels conduct the measurement of the pins in the period when the switches corresponding to the i channels are conducted, wherein i is a positive integer not larger than M.

8. The measuring method of claim 7, further comprising the steps of: when the 1 st pin of the object to be measured corresponds to the b th comparator, switches corresponding to the 1 st to (N-b +1) th pins are respectively switched on, so that the b th to N th comparators measure the 1 st to (N-b +1) th pins, wherein b is a positive integer greater than 0 and not greater than N.

9. The measuring method of claim 8, further comprising the steps of: when the switches corresponding to the b-th to N-th comparators are turned on, the switches corresponding to the continuous pins of the object to be measured are turned on respectively.

10. The method of claim 9, wherein the switches of the b-th to N-th channels are turned on sequentially, and the switches corresponding to the successive pins of the dut that have not been measured are turned on sequentially.