JP2011188309A - Frequency synthesizer, and adjustment method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer etc. for improving phase noise and for stably operating. <P>SOLUTION: When a frequency synthesizer for adjusting a control voltage of a voltage controlled oscillator unit is started up based on phase difference between both frequency signals which are acquired by performing an orthogonal detection about a difference signal acquired by amplifying difference between a frequency signal outputted from the voltage controlled oscillation unit and a frequency signal outputted from a frequency setting unit with a detection signal which is orthogonal with the frequency signal outputted from the frequency setting unit, a phase of the detection signal is corrected by a previously determined correction amount by a first phase correction unit in a state in which the voltage controlled oscillator unit is separated from a differential amplifier for acquiring the difference signal. A timing from a time point when a digital frequency signal is outputted from the frequency setting unit until the difference signal is acquired, and a timing until the detection signal is acquired are justified after outputting the detection signal by a second correction unit after delaying by a clock unit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a frequency synthesizer.

As a frequency synthesizer, the output signal of the voltage controlled oscillator is A / D converted (analog / digital converted), the obtained digital signal is processed, and the processing result is input to the voltage controlled oscillator, thereby making a PLL (Phase Locked Loop) Are known. For example, in Patent Document 1, an output signal of a voltage controlled oscillator is A / D converted (analog / digital converted), and a sine wave signal created from the digital signal is subjected to quadrature detection and used for the sine wave signal and detection. The rotation vector that rotates at the difference frequency from the sine wave signal is extracted, and the difference velocity between this rotation vector and the rotation vector that rotates in the opposite direction to the rotation vector and rotates at the frequency corresponding to the set frequency is integrated. A frequency synthesizer is described that serves as the input voltage of a voltage controlled oscillator.
However, there is a problem that phase noise exists in the PLL, and therefore phase noise is generated at the output of the frequency synthesizer.

  Therefore, in order to solve such a phase noise problem, the applicant of the present application uses an analog frequency signal from a voltage controlled oscillator (hereinafter referred to as VCO) and a direct digital synthesizer (hereinafter referred to as DDS). The digital frequency signal output from the digital frequency oscillator such as) is amplified by taking the difference from the signal obtained by digital / analog conversion (D / A conversion), and the amplified difference signal is converted to A / D. After conversion, quadrature detection is performed using the detection signal, the phase difference between both frequency signals is extracted and integrated, and the voltage corresponding to the integration value is supplied to the voltage controlled oscillation unit to adjust the frequency of the analog frequency signal. A new PLL is being developed.

By amplifying the output signal after taking the difference with the differential amplifier, the quantization error that occurs when the signal is converted from analog to digital can be kept relatively low with respect to the amplitude of the difference signal. Thus, it is possible to improve the phase noise caused by such a quantization error.
Here, as the detection signal orthogonally detected with the differential signal, a signal in which the phase of the digital frequency signal output from the DDS is shifted by 90 ° is used, and the frequency output from the DDS in the differential signal and the differential signal is used. Since the signal component is orthogonal, the phase shift on the analog frequency signal side can be accurately extracted.

  However, in a circuit such as a D / A converter used for obtaining a digitized difference signal, a time from when a signal is input to the circuit every time the circuit is started up until an operation result is output (hereinafter, referred to as a “D / A converter”). It turns out that there is something that changes the latency). If the latency fluctuates in this way, there is a problem that accurate quadrature detection cannot be performed and the accuracy of VCO frequency adjustment is reduced.

  Here, in Patent Document 2, a sample reproduction signal such as a frequency signal is sampled in synchronization with the sample clock output from the VCO, and the phase difference between the sample clock and the target clock is determined by comparing the sampling value with the target value. A technique for providing a variable delay circuit between the VCO and the error correction circuit in a conventional PLL that detects the error in the error correction circuit and feeds back this phase difference to the VCO to adjust the frequency of the sampling clock is described. ing. In this delay circuit, the phase difference detected by the error correction circuit in the subsequent stage is fed back, and by increasing / decreasing the delay amount according to the magnitude of the phase difference, the phase difference at the initial startup of the PLL is canceled, Although the sample clock can be synchronized with the target clock in a short time, there is no disclosure of a technique for eliminating the influence of the latency variation of the circuit in the PLL.

JP 2007-74291 A: Claim 1, paragraphs 0017 to 0021, FIG. JP-A-11-214990: Claim 1, paragraphs 0023 to 0025, FIG.

  The present invention has been made under such circumstances, and an object of the present invention is to provide a frequency synthesizer capable of highly accurate frequency adjustment and a stable operation, and a method for adjusting the frequency synthesizer. .

The frequency synthesizer according to the present invention includes a frequency signal output from the voltage-controlled oscillation unit, an analog frequency signal obtained from the digital frequency signal of the set frequency output from the frequency setting unit via the digital / analog conversion unit, and , And a digital frequency signal obtained through an analog / digital conversion unit, and a digital frequency output from the frequency setting unit. The detection signal obtained by shifting the phase of the signal by 90 ° is subjected to quadrature detection by the phase difference detection unit to extract the phase difference between both frequency signals, and the voltage corresponding to the integrated value is obtained by integrating the phase difference and the voltage controlled oscillation. A frequency synthesizer for supplying a control voltage to the unit,
A switch unit provided between the voltage controlled oscillation unit and the differential amplifier;
The timing from when the digital frequency signal is output from the frequency setting unit to the time when the frequency signal derived from the frequency setting unit included in the differential signal is input to the phase detection unit, and the detection from the output point A first phase correction unit that corrects the phase of the detection signal by a predetermined correction amount in order to align the timing until the signal is input to the phase detection unit;
A second phase correction unit for delaying and outputting the detection signal in units of clocks in order to eliminate the inconvenience that the conversion time of the signal of the digital / analog conversion unit is different every time the frequency synthesizer is started;
A frequency signal for testing is output from the digital signal oscillation unit in a state where the voltage control oscillation unit is disconnected from the differential amplifier by the switch unit, and the number of clocks of delay in the second phase correction unit is sequentially changed, And a control unit that sets the second phase correction unit so that the delay amount is the number of clocks with which the phase difference obtained by the phase detection unit is minimized.

The frequency synthesizer may have the following characteristics.
(A) When the control unit inputs the test frequency signal to the differential amplifier, the control unit sets the differential gain of the differential amplifier or the signal level of the digital frequency signal output from the frequency setting unit. Make it smaller than normal use.
(B) The second phase correction unit is constituted by a shift register.
(C) The frequency setting unit is a direct digital synthesizer.

In addition, the frequency synthesizer adjustment method according to another aspect of the invention obtains the frequency signal output from the voltage controlled oscillation unit and the digital frequency signal of the set frequency output from the frequency setting unit via the digital / analog conversion unit. The analog frequency signal is input to the differential amplifier, the analog differential signal obtained by the differential amplifier is obtained from the digital frequency signal via the analog / digital conversion unit, and the frequency setting unit The detection signal obtained by shifting the phase of the output digital frequency signal by 90 ° is orthogonally detected by the phase difference detection unit to extract the phase difference between the two frequency signals, and the phase difference is integrated to correspond to the integrated value. A voltage is supplied as a control voltage to the voltage controlled oscillation unit, and a switch unit provided between the voltage controlled oscillation unit and the differential amplifier, and the frequency setting unit In order to align the timing from when the digital frequency signal is output until the differential signal is obtained with the timing from when the digital signal is output until the detection signal is obtained, the detection signal is corrected by a predetermined correction amount. In order to eliminate the disadvantage that the conversion time of the signal of the first phase correction unit for correcting the phase and the digital / analog conversion unit differs every time the frequency synthesizer is started up, the detection signal is delayed and output in units of clocks. A frequency synthesizer adjustment method comprising: a second phase correction unit that:
A step of outputting a test frequency signal from the digital signal oscillating unit in a state where the voltage controlled oscillating unit is separated from the differential amplifier by the switch unit at the time of starting up the frequency synthesizer;
Changing the number of delay clocks in the second phase correction unit in sequence, and setting the second phase correction unit so that the number of clocks that minimizes the phase difference obtained by the phase detection unit is the delay amount; , Including.

  The frequency synthesizer according to the present invention detects a phase difference between the frequency signal output from the voltage controlled oscillation unit and the frequency signal output from the frequency setting unit and a detection signal obtained by shifting the phase of the frequency signal by 90 °. When the two signals are input to the phase detection unit through different paths and used for quadrature detection, the first phase correction unit and the second phase correction unit for aligning the timings at which these two signals are input to the phase detection unit And a phase correction unit. The first phase correction unit corrects the phase of the detection signal by a predetermined amount, while the second phase correction unit can delay the timing of outputting the detection signal in units of clocks. As a result, even if the conversion time of the signal of the digital / analog conversion unit provided in the path through which the frequency signal output from the frequency setting unit passes differs every time the frequency synthesizer is started up, Since the output timing of the detection signal is delayed according to the change and the phase difference between the frequency signal and the detection signal output simultaneously from the frequency setting unit can be reduced, each frequency signal of the voltage controlled oscillation unit and the frequency setting unit Therefore, it is possible to accurately grasp the phase difference and to perform high-precision frequency adjustment.

It is a block diagram of the frequency synthesizer concerning an embodiment. It is a block diagram of the integration circuit provided in the said frequency synthesizer. It is a block diagram of the latency adjustment part provided in the said frequency synthesizer. It is a timing chart which shows the operation | movement of the frequency synthesizer at the time of the said starting. It is explanatory drawing which shows typically the intensity | strength of the signal output from a phase detection part at the time of the said starting. It is a flowchart which shows the flow of operation | movement at the time of starting of the said frequency synthesizer.

  The configuration of the frequency synthesizer according to the present embodiment will be described below with reference to the block diagram shown in FIG. The frequency synthesizer according to this example uses the frequency signal output from the VCO 11 that is a voltage-controlled oscillation unit as a feedback signal, compares the phase with the frequency signal output from the DDS 21 (Direct Digital Synthesizer), and determines the level of these frequencies. A PLL (Phased Lock Loop) circuit that integrates the voltage corresponding to the phase difference and supplies the voltage to the input side of the VCO 11 is formed. When the frequency difference between these signals becomes zero, the PLL is locked, and the output frequency of the VCO 11 is locked to the set frequency. The DDS 21 corresponds to a frequency setting unit in the claims.

In FIG. 1, the _{VCO 11} serves to output an analog frequency signal that is a sine wave having a frequency f _VCO corresponding to the supply voltage. The frequency divider 12 provided at the subsequent stage of the VCO 11 has a function of dividing the frequency signal output from the VCO 11 into 1 / N (N is an integer) and setting the frequency to (f _VCO / N).

The mixer 13 multiplies the frequency signal output from the frequency divider 12 by a fixed frequency signal having a frequency f _MIX , and a signal having two frequencies “(f _VCO / N) ± fMIX” obtained by the heterodyne principle. Among them, a signal having a low frequency “(f _VCO / N) −f _MIX ” can be extracted. The frequency signal output from the mixer 13 is input to the differential amplifier 14 at the subsequent stage.

  In addition to the frequency signal from the VCO 11 side, a frequency signal for phase comparison with this signal is input to the differential amplifier 14 from the DDS 21 side, so the DDS 21 will be described first. The DDS 21 stores, for example, sinusoidal amplitude data in association with phase data in a waveform table (not shown), and accumulates phase width data set in advance at each input timing of a clock signal from the system clock 201 described later. It has a function of outputting a digital frequency signal having a set frequency by reading amplitude data based on the phase data obtained by the addition. A clock generation source serving as a reference for the system clock 201 is constituted by, for example, a crystal oscillator.

  In the DDS 21, by increasing the value of the phase width data, the waveform data stored in the waveform table is skipped according to the size of the phase width data, and the frequency is adjusted accordingly. That is, a signal having a higher frequency can be output as the value of the phase width data is increased. The DDS 21 in this example can simultaneously output, for example, a frequency signal of cos (ωt) (ω is an angular velocity [rad / sec]) and a detection signal sin (ωt) in which the phase of the frequency signal is shifted by 90 °. The DDS 21 can increase or decrease the signal levels (signal strength) of these frequency signals and detection signals independently. However, as will be described later, the level of the frequency signal from the DDS 21 may be adjusted by the D / A converter 22.

In this example, for example, the phase width data for determining the set frequency is set from the computer unit 20 that forms the control unit of the frequency synthesizer to the DDS 21. For example, when the set frequency of the frequency synthesizer is f _s , the frequency f _DDS of the signal output from the _DDS 21 is the same as that of the signal output from the mixer 13 when the frequency signal output from the VCO 11 is locked to the set frequency. It is set to coincide with the frequency “(f _S / N) −f _MIX ”, and the phase width data is set based on this value. The frequency signal output from the DDS 21 is converted into an analog frequency signal via the D / A converter 22 and input to the differential amplifier 14 described above. The D / A converter 22 corresponds to a digital / analog converter in the claims.

  The differential amplifier 14 calculates a difference value between the frequency signal input from the mixer 13 on the VCO 11 side and the frequency signal input from the DDS 21 side, amplifies this result, and then passes to the A / D converter 15 in the subsequent stage. Play a role to output. In this way, the differential amplifier 14 is provided, and the difference signal amplified by taking the difference between the frequency signals output from both the VCO 11 and the DDS 21 is output, whereby the difference signal from the analog signal in the A / D converter 15 in the subsequent stage is output. The generation of phase noise that occurs when the digital signal is rounded to a predetermined number of bits during sampling is reduced.

  The present inventor compares the simulation result of an ideal frequency synthesizer without phase noise degradation in the A / D converter and the output of the actual frequency synthesizer, so that the amount of phase noise degradation in the A / D converter is It is understood that the size is about 10 dB at the maximum. Therefore, the differential amplifier 14 amplifies the difference value of the two frequency signals by 10 dB or more, for example, 26 dB (amplifies by 20 times), thereby canceling (cancelling) the deterioration of the phase noise generated in the A / D converter 15. The frequency synthesizer according to the present embodiment has a configuration including the differential amplifier 14 based on such a concept.

As described above, when the frequency signal output from the DDS 21 is cos (ωt) and the frequency signal at the mixer 13 exit from the VCO 11 side is cos (ω′t) (ω ′ is an angular velocity [rad / sec]). In the state immediately before the output frequency f _{VCO of the VCO 11} is sufficiently close to the set frequency f _s and the PLL is locked, ω≈ω ′ = ω + Δω (Δω << 1), so the frequency signal at the outlet of the mixer 13 is cos ( ωt + Δωt). Under the condition of Δω << 1, the value of Δωt hardly changes with time, and can be expressed as a phase shift Δθ.

That is, in a state immediately before the PLL is locked, the frequency signal input to the differential amplifier 14 from the DDS 21 side is cos (ωt), and the frequency signal input from the mixer 13 to the differential amplifier 14 is cos (ωt + Δθ). The differential amplifier 14 outputs a frequency signal represented by the following equation (1).
20 {cos (ωt + Δθ) −cos (ωt)} (1)

The A / D converter 15 provided in the subsequent stage of the differential amplifier 14 plays a role of converting the signal represented by the equation (1) into a digital signal. The frequency signal output from the DDS 21 is D / D A time delay occurs when analog conversion is performed by the A converter 22, a differential signal is acquired by the differential amplifier 14, and processing is performed when the differential signal is converted into a digital signal by the A / D converter 15. Causes a time delay. When this time delay is represented by Δt and t ′ = t + Δt, the output signal from the A / D converter 15 can be represented by the following equation (1) ′. Here, the time delay due to the processing of the D / A converter 22 with respect to the output of the mixer 13 can be included in the phase difference Δθ of both frequency signals.
20 {cos (ωt ′ + Δθ) −cos (ωt ′)} (1) ′

  A phase detection unit 16 that is a quadrature detection unit for detecting the phase difference Δθ between the two frequency signals is provided after the A / D converter 15. The phase detection unit 16 detects a detection signal sin () orthogonal to cos (ωt ′) included in the equation (1) ′ as an output signal from the preceding stage A / D converter 15 expressed by equation (1) ′. (ωt ′) and a function of performing preprocessing for extracting a phase difference component.

As described above, the DDS 21 can output the frequency signal (cos (ωt)) input to the differential amplifier 14 and the detection signal (sin (ωt)) orthogonal thereto in parallel. Phase correction for canceling the time delay Δt generated in the D / A converter 22, the differential amplifier 14, and the A / D converter 15 is performed on the detection signal by the phase correction unit 31 and the latency adjustment unit 4. The detection signal sin (ωt ′) thus corrected in phase is input to the phase detector 16. When the calculations executed by the phase detector 16 are arranged, an output represented by the following equation (2) is obtained.
sin (ωt ′)
× [20 {cos (ωt ′ + Δθ) −cos (ωt ′)}]
= (20/2) sin (2ωt ′ + Δθ) + (20/2) sin (−Δθ)
+ (20/2) sin (2ωt ′) (2)

  A filter 17 is provided at the subsequent stage of the phase detection unit 16, and the AC component is removed from the output of the phase detection unit 16 expressed by the equation (2) to obtain a DC component (20/2) sin (− By extracting (Δθ) = − (20/2) sin (Δθ), the phase difference between the two frequency signals on the VCO 11 side and the DDS 21 side can be known.

  The integrating circuit 18 corresponds to a loop filter of the PLL circuit constituting the frequency synthesizer of this example, and the signal “− (20/2) sin (Δθ)” corresponding to the phase difference detected by the filter 17 is added to the PLL circuit. In this configuration, a coefficient for adjusting the loop gain is multiplied, and the signal is divided into an integral system and a direct system and then added.

  FIG. 2 shows a configuration example of the integrating circuit 18, in which 181 is a multiplication unit that multiplies the input signal by an adjustment coefficient, 182 is a cumulative addition unit that cumulatively adds the signals after multiplication, and 183 is a signal after multiplication ( (Additional system) and an output signal (integration system) from the cumulative adder 182. The integration circuit 18 plays a role of executing loop control of the PLL circuit so that the value of “− (20/2) sin (Δθ)” inputted becomes zero.

  A D / A converter 19 is provided at the subsequent stage of the integrating circuit 18, the output from the integrating circuit 18 is converted into an analog signal, and the output of the D / A converter 19 is input to the VCO 11 as a control voltage. Frequency adjustment by a PLL circuit can be executed.

  Here, reference numeral 32 shown in FIG. 1 denotes a frequency signal from the differential amplifier 14 in order to make the amplitude of the frequency signal on the DDS side input to the differential amplifier 14 and the frequency signal from the mixer 13 side, The amplitude of the analog signal output from the D / A converter 22 is adjusted based on the frequency signal from the DDS 21 (cos (ωt ′): the time delay Δt has been adjusted by the phase correction unit 31 and the latency adjustment unit 4). It is an amplitude adjustment part for doing.

  As described above, the phase correction unit 31 and the latency adjustment unit 4 are time delays generated by the processing of the D / A converter 22, the differential amplifier 14, and the A / D converter 15 in the subsequent stage. It plays a role to correct. However, as described in the background art, in these devices, the processing time (latency) fluctuates every time the circuit is started up. As a result, the frequency signal output from the DDS 21 is converted into the D / A converter 22 → the operational amplifier 14 → There may be a case where the time delay until the phase detector 16 is reached via the A / D converter 15 may fluctuate. When the time delay fluctuates in this way, it becomes difficult to accurately grasp the phase difference between the frequency signal from the VCO 11 side (mixer 13) and the frequency signal from the DDS 21 side described using the equation (2). The control accuracy of the PLL circuit is lowered.

  Therefore, the frequency synthesizer according to the present embodiment is provided with two types of circuits, that is, the phase correction unit 31 and the latency adjustment unit 4, and thereby the D / A converter 22, the operational amplifier 14, and the A / D converter. The configuration is such that the phase of the detection signal is corrected so that the time delay generated in each of the 15 devices is accurately offset.

  In this example, among the three circuits (D / A converter 22, operational amplifier 14, and A / D converter 15) described above in which a time delay occurs, for example, every time the latency of the D / A converter 22 rises. A case of fluctuation will be described. At this time, the phase correction unit 31 cannot be adjusted by the latency adjustment unit 4 among the time delay of a certain time in the operational amplifier 14 and the A / D converter 15 and the time delay generated in the D / A converter 22. In order to adjust a short time delay, it plays the role of correcting the phase of the detection signal by a predetermined correction amount. As the phase correction unit 31, a known pulse delay circuit including an inverter and a capacitor is used. The phase correction unit 31 corresponds to the first phase correction unit of the present embodiment.

  On the other hand, the latency adjustment unit 4 outputs a detection signal in order to eliminate the inconvenience that the processing time (conversion time) required for the D / A conversion in the D / A converter 22 differs every time the frequency synthesizer is started up. The timing can be delayed and the timing (delay amount) to be delayed can be changed. The latency adjustment unit 4 corresponds to the second phase correction unit of the present embodiment.

  FIG. 3 shows a configuration example of the latency adjustment unit 4 according to the present embodiment. The latency adjustment unit 4 includes, for example, a known shift register, and delays the signal input from the phase correction unit 31 in units of clocks in synchronization with the input timing of the clock signal from the system clock 201. Can be output.

  For example, the latency adjustment unit 4 illustrated in FIG. 3 includes a plurality of, for example, three register units 41 a to 41 c that can store data corresponding to the number of bits of the detection signal output from the DDS 21 or the phase correction unit 31 in series. A shift register is provided. Each register unit 41a to 41c outputs the data held at the timing when the clock signal from the system clock 201 is received to the subsequent stage, thereby delaying the output timing of the detection signal in units of clocks (correcting the phase). Can be output.

The outputs from the register units 41 a to 41 b are also output to the connection points S _{1 to} S ₃ side with the changeover switch 42, and are input to the phase detection unit 16 by selecting the connection destination of the changeover switch 42. The delay amount (phase correction amount) of the detection signal can be changed. Further to the changeover switch 42 according to the present embodiment, the contact S ₀ to directly output without delaying the output timing of the phase correction unit 31 is provided.

A method for obtaining an optimum delay amount by the latency adjusting unit 4 having the above-described configuration will be described. For example, a time delay that occurs until the frequency signal cos (ωt) output from the DDS 21 is input to the phase detector 16 via the D / A converter 22 → the differential amplifier 14 → the A / D converter 15 is Δt _1. Similarly, let Δt ₂ be the amount of phase correction performed until the detection signal sin (ωt) output from the DDS 21 is input to the phase detection unit 16 via the phase correction unit 31 → the latency adjustment unit 4.

At this time, when the input of the frequency signal from the VCO 11 side (mixer 13) to the differential amplifier 14 is cut off and the gain of the differential amplifier 14 is set to 1, the phase detection unit 16 performs the calculation of the following equation (3). Executed.
sin (ω (t + Δt ₂ )) × cos (ω (t + Δt ₁ ))
= (1/2) sin (ω (2t + Δt ₂ + Δt ₁ ))
+ (1/2) sin (ω (Δt ₂ −Δt ₁ )) (3)
If the AC component is also removed from the calculation result of equation (3), a signal corresponding to (1/2) sin (ω (Δt ₂ −Δt ₁ )) is extracted, and the value of Δt ₂ approaches Δt _1. , (1/2) sin (ω (Δt ₂ −Δt ₁ )) approaches 0.

Therefore, the connection destination of the changeover switch 42 in the latency adjustment unit 4 shown in FIG. 3 is changed to the contacts S _{0 to} S ₃ to sequentially change Δt ₂ , and (1/2) sin (ω (Δt ₂ −Δt ₁ By selecting the contact whose value of)) is closest to 0, it is possible to determine the correction amount of the phase of the detection signal that cancels the delay time of the D / A converter 22 at the time of startup.

  In order to make it possible to execute the delay amount determination (hereinafter referred to as latency adjustment) by the latency adjustment unit 4 by the method described above, the frequency synthesizer according to the present embodiment performs the latency adjustment on the VCO 11 side (mixer 13). ) Is provided to cut off the input of the frequency signal from. By opening the switch unit 5, the frequency signal output from the DDS 21 is input to the phase detection unit 16 as a test signal.

  Further, since there is no input from the VCO 11 side, the frequency signal of the DDS 21 converted into analog is amplified and output as it is from the differential amplifier 14, but the frequency signal not taking the difference is amplified and detected. When quadrature detection with a signal is performed, the difference in amplitude between the detected signals is too large, which causes a reduction in detection accuracy. Thus, for example, the DDS 21 outputs a frequency signal by lowering its signal level when adjusting the latency.

Further, the output of the phase detection unit 16 is output to, for example, the computer unit 20, a process for removing the AC component is performed in the computer unit 20, and data representing the difference between the time delay Δt ₂ and the correction amount Δt _1. Can be stored. The computer unit 20 stores data representing the difference between Δt ₂ and Δt _{1 in} association with the switching state of the changeover switch 42 to the contacts S _{0 to} S ₃ , and the absolute value of the data is minimized. The contact can be selected as a contact corresponding to an optimum correction amount in the latency adjustment operation at that time.

A method for determining an optimum delay amount in the latency adjustment unit 4 having the above configuration will be described with reference to FIGS. FIG. 4 is a simplified timing chart showing signals input to and output from each circuit based on the clock signal from the system clock 201 in the operation of adjusting the latency. Each chart is input to the phase detection unit 16 from the clock signal, the frequency signal input to the phase detection unit 16 via the differential amplifier 14 and the contacts S _{0 to} S _{3 of} the changeover switch 42 in order from the top. The detection signal and the signal output from the phase detector 16 are shown.

  From the DDS 21, for example, a frequency signal (cos (ωt1) to cos (ωt7)) and a detection signal (sin (ωt1) to sin (ωt7)) for one cycle are repeatedly output during 8 clocks of ωt0 to ωt7. The For convenience of illustration, these frequency signals and detection signals are collectively shown as “e ^ (jωt0) to e ^ (jωt7)” in the output chart of the DDS 21 in FIG.

In the example of the chart illustrated in FIG. 4, the frequency signal output from the DDS 21 is input to the phase detection unit 16 after 4 clocks via the differential amplifier 14 and the like. On the other hand, the output from the contact S ₀ where the delay amount in the latency adjustment unit is zero is input to the phase detection unit 16 two clocks after the DDS 21 output. From this, it can be seen that in this example, the phase correction unit 31 performs correction to delay the phase of the detection signal output from the DDS 21 by two clocks of the clock signal. The contacts S _{1 to} S ₃ output a signal obtained by delaying the timing of outputting the detection signal by one clock unit with respect to the detection signal after the phase correction by the phase correction unit 31.

Here now, at the timing shown in FIG. 4, the selector switch 42 to connect to the contact S _0, at the timing after one clock has elapsed from the input of the phase detector 16 for example, a frequency signal and a detection signal ( 3) The result of executing the calculation of the equation is output to the computer unit 20. In addition, when the contact of the changeover switch 42 is switched at the timings indicated by S ₁ , S ₂ ,... In FIG. 4, the above calculation result is output after one clock of the input timing of the frequency signal and the detection signal. The

Therefore, in the computer unit 20, the latency adjustment unit 4 can send a detection signal by storing the switching timing of the contact of the changeover switch 42 and its connection destination in association with the data acquired from the phase detection unit 16. Thus, the relationship between the number of clocks to be output and the degree of coincidence of the phase between the frequency signal and the detection signal (the previously described (1/2) sin (ω (Δt ₂ −Δt ₁ )) can be grasped.

According to FIG. 4, for example, the output A3 from the phase detection unit 16 immediately after connecting the changeover switch 42 to the contact S ₀ (delay amount 0 clock) becomes “cos (ωt6) × (sin (ωt0))”, and the latency is increased. Since the output from the adjustment unit 4 is advanced by two clocks, a result in which the phase between the frequency signal and the detection signal coincides cannot be obtained. On the other hand, the output A3 from the phase detector 16 immediately after connecting the changeover switch 42 to the contact S ₂ (delay amount 2 clocks) is “cos (ωt2) × (sin (ωt2))”, and the phases of both signals are the same. You can see what you are doing.

For convenience of explanation, FIG. 4 shows a case where the changeover switch 42 is changed every two clocks. However, in actuality, for example, about several hundred milliseconds to several seconds, the connection destination of the changeover switch 42 every preset time. For example, S ₀ → S ₁ → S ₂ → S ₃ are switched. As a result, the computer unit 20 stores the value of “(½) sin (ω (Δt ₂ −Δt ₁ ))” in association with each contact point along the time axis as shown in FIG. In FIG. 5, the absolute value is shown). The contact having the smallest value is selected as the contact corresponding to the delay amount that cancels the latency of the D / A converter 22 in the current start-up operation.

The operation of the frequency synthesizer having the configuration described above will be described with reference to the flowchart of FIG. Start the launch of the frequency synthesizer (start) When the power is turned on (step S1), the delay amount of the detection signal by connecting the switch 42 of the latency adjustment unit 4 to the contact S ₀ to "0 Clock" Set (step S2). Further, the switch unit 5 is opened to disconnect the VCO 11 from the differential amplifier 14 (step S3), and the frequency of the frequency signal (and detection signal) of the DDS 21 and the signal level of the digital signal output from the DDS 21 to the operational amplifier 14 Are respectively set to predetermined values (step S4). Here, for example, the signal level of the digital signal output from the DDS 21 to the operational amplifier 14 is set to a level that is 1/20 of that during normal operation, while the digital signal output to the phase correction unit 31 as the detection signal is normally set. Set to the level during operation.

  When the output of the frequency signal and the detection signal is started from the DDS 21 (step S5), the calculation result output from the phase detection unit 16 is processed by the computer unit 20, and data indicating the phase difference between the frequency signal and the detection signal. (Step S6). When the preset time has elapsed in this way, the connection destination of the changeover switch 42 is switched, and the delay amount of the latency adjustment unit 4 is incremented by one clock (step S7).

  As a result, if the amount of delay does not exceed 3 clocks (step S8; NO), there is a changeover destination of the changeover switch 42. Therefore, the phase difference between both signals is detected for a predetermined time in that state, and the result is obtained. After storing (step S7), the operation of incrementing the delay amount of the latency adjusting unit 4 by one clock is repeated (step S8). When the delay amount exceeds 3 clocks and becomes 4 clocks, and there is no longer any contact that increases the number of clocks (step S8; YES), the optimum delay is based on the concept described with reference to FIGS. The amount is selected, and the connection destination of the changeover switch 42 is switched to a contact corresponding to this delay amount (step S9).

  As a result, the delay amount that cancels out the latency of the D / A converter 22 in the current start-up operation is selected by the latency adjustment unit 4, so the switch unit 5 is closed and the differential amplifier 14 is connected to the VCO 11 side. The signal level of the digital signal output from the DDS 21 to the operational amplifier 14 is returned to the level during normal operation (step S10). Thus, the latency adjustment operation is finished (end), and the entire PLL circuit is activated. Start up a frequency synthesizer.

The subsequent operation of starting up the frequency synthesizer will be briefly described. In this example, each set value set frequency of the frequency synthesizer is set to f _s = 8755.5 MHz, the frequency divider 12 is set to N = 104, and the fixed frequency signal f _MIX of the mixer 13 is set to 80 MHz. The frequency synthesizer is provided with a frequency drawing mechanism (not shown), and can draw the output frequency of the VCO 11 to the vicinity of the set frequency when the frequency synthesizer is started up.

When the output frequency of the VCO 11 is pulled to the vicinity of the set frequency by the action of the frequency pulling mechanism, the PLL circuit is actuated, and the output from the VCO 11 is divided by the frequency divider 12 into a frequency of 1/104, and the mixer 13 Is multiplied by a fixed frequency of 80 MHz and output to the differential amplifier 14. _Here, when it becomes the _f VCO = _{f s} would frequency signal 8755.5 × 106 / 104-80 × 106 = 4187500Hz is output from the mixer 13.

On the other hand, in the _DDS 21, the setting is made from the computer unit 20 so that the output frequency f _DDS becomes the above-mentioned 4187500 Hz, and the amplitude of the frequency signal having this output frequency is adjusted by the D / A converter 22. Thereafter, it is input to the differential amplifier 14. As a result, the differential amplifier 14 outputs a differential signal obtained by amplifying the difference between the frequency signal on the VCO 11 side output from the mixer 13 and the frequency signal on the DDS 21 side by 20 times. Is subjected to quadrature detection and an operation for detecting the phase difference Δθ between the two frequency signals is performed. Here, as described above, when the frequency synthesizer is started up, the phase of the frequency signal input from the DDS 21 to the phase detection unit 16 and the detection signal are in good agreement, so that the level of the frequency signal on the VCO 11 side is the same. The phase difference Δθ can be detected with high accuracy.

  Then, the signal shown in the above-described equation (2) is output from the phase detector 16, and the signal “− (20/2) sin (Δθ)” corresponding to the phase difference is extracted by the filter 17. The signal extracted by the filter 17 is integrated and added by the integration circuit 18 and converted to analog data by the D / A converter 19 and then applied to the VCO 11 as a control voltage. The loop control is executed by this PLL circuit so that “− (20/2) sin (Δθ) = 0”, that is, Δθ = 0, and when Δθ = 0, the output frequency fVCO of the VCO 11 becomes the set frequency fs. In addition to being locked, the frequency signal output from the mixer 13 is synchronized with the output from the DDS 21.

  The frequency synthesizer described above has the following effects. The frequency synthesizer detects the phase difference from the frequency signal output from the VCO 11, and the frequency signal output from the DDS 21 and the detection signal obtained by shifting the phase of this frequency signal by 90 ° are phased through different paths. A phase correction unit 31 and a latency adjustment unit 4 are provided for aligning the timing at which these two signals are input to the phase detection unit when input to the detection unit 16 and used for quadrature detection. The phase correction unit 31 corrects the phase of the detection signal by a predetermined amount, while the latency adjustment unit 4 can delay the timing of outputting the detection signal in units of clocks. As a result, even if the conversion time of the signal of the D / A converter 22 provided in the path through which the frequency signal output from the DDS 21 passes differs every time the frequency synthesizer is started up, Since the detection signal output timing is delayed according to the change and the phase difference between the frequency signal and the detection signal output simultaneously from the DDS 21 can be reduced, the phase difference between the frequency signals of the VCO 11 and the DDS 21 can be accurately grasped. Thus, highly accurate frequency adjustment can be performed.

  Here, the order of correcting the detection signals is not limited to the order of the phase correction unit 31 → latency adjustment unit 4 as shown in FIG. 1, and this order may be changed. In this example, the D / A converter 22 is used as an example of a circuit that converts the processing time each time the frequency synthesizer is started up. However, the differential amplifier 14 and the A / D converter 15 in the subsequent stage are also used. Even when the same phenomenon occurs, the phase correction unit 31 corrects the phase by a preset correction amount with respect to the detection signal, and the latency to correct the phase by outputting the detection signal delayed by the clock unit. Combining with the adjustment unit 4 can eliminate the disadvantages associated with the occurrence of the phenomenon.

Further, the number of register units provided in the shift register constituting the latency adjustment unit 4 is not limited to the three examples shown in FIG. 3, and may be 3 if two or more connection points having different adjustment amounts are provided. It may be less than the number or more. Further contacts S ₀ which does not pass through the register unit may not be provided. In addition, the optimum adjustment amount is not limited to the case of determining using the computer unit 20, and the connection point of the changeover switch 42 may be manually switched based on the signal output from the phase detection unit, for example. Further, the latency adjusting unit 4 is not limited to the case where a shift register is used as shown in FIG. 3, and for example, a delay element may be used.

  And the switch part which interrupts | blocks the input of the frequency signal from the VOC11 side at the time of latency adjustment is not limited to when the said switch part 5 is physically provided in a circuit as shown in FIG. For example, the output of the frequency divider 12 can be stopped based on an instruction from the computer unit 20, and the output from the frequency divider 12 is stopped at the time of latency adjustment, so that the operational amplifier 14 is connected from the VOC 11 side. The input of the frequency signal may be cut off. In this case, the frequency divider 12 also serves as a switch unit.

  In addition, when adjusting the latency, the gain on the side of the differential amplifier 14 may be reduced in place of the technique of reducing the output level of the frequency signal output from the DDS 21 to the operational amplifier 14 as compared with the normal use. For example, the differential amplifier 14 can change the gain under the control of the computer unit 20 and increases the gain by 20 times during normal operation of the frequency synthesizer, while detecting the frequency signal and detection signal input to the phase detection unit 16 during latency adjustment. In order to substantially match the amplitude with the signal, a configuration in which the gain is switched so that the gain of the differential amplifier 14 is 1 can be considered.

11 Voltage controlled oscillator (VCO)
14 differential amplifier 15 A / D converter 16 phase detector 20 computer 21 DDS
22 D / A converter 31 Phase correction unit 4 Latency adjustment units 41a to 41c
Register section 42 selector switch 5 switch section

Claims (5)

The frequency signal output from the voltage-controlled oscillation unit and the analog frequency signal obtained from the digital frequency signal of the set frequency output from the frequency setting unit via the digital / analog conversion unit are input to the differential amplifier. The phase of the digital frequency signal obtained from the analog differential signal obtained by the differential amplifier via the analog / digital conversion unit and the phase of the digital frequency signal output from the frequency setting unit are shifted by 90 °. The detection signal is quadrature detected by the phase difference detection unit to extract the phase difference between the two frequency signals, and the phase difference is integrated and a voltage corresponding to the integration value is supplied to the voltage controlled oscillation unit as a control voltage. A synthesizer,
A switch unit provided between the voltage controlled oscillation unit and the differential amplifier;
The timing from when the digital frequency signal is output from the frequency setting unit to the time when the frequency signal derived from the frequency setting unit included in the differential signal is input to the phase detection unit, and the detection from the output point A first phase correction unit that corrects the phase of the detection signal by a predetermined correction amount in order to align the timing until the signal is input to the phase detection unit;
A second phase correction unit for delaying and outputting the detection signal in units of clocks in order to eliminate the inconvenience that the conversion time of the signal of the digital / analog conversion unit is different every time the frequency synthesizer is started;
A frequency signal for testing is output from the digital signal oscillation unit in a state where the voltage control oscillation unit is disconnected from the differential amplifier by the switch unit, and the number of clocks of delay in the second phase correction unit is sequentially changed, A frequency synthesizer comprising: a control unit that sets the second phase correction unit so that the delay amount is the number of clocks that minimizes the phase difference obtained by the phase detection unit.   When the control unit inputs the test frequency signal to the differential amplifier, the differential gain of the differential amplifier or the signal level of the digital frequency signal output from the frequency setting unit is normally used. The frequency synthesizer according to claim 1, wherein the frequency synthesizer is made smaller.   The frequency synthesizer according to claim 1, wherein the second phase correction unit is configured by a shift register.   4. The frequency synthesizer according to claim 1, wherein the frequency setting unit is a direct digital synthesizer. The frequency signal output from the voltage-controlled oscillation unit and the analog frequency signal obtained from the digital frequency signal of the set frequency output from the frequency setting unit via the digital / analog conversion unit are input to the differential amplifier. The phase of the digital frequency signal obtained from the analog differential signal obtained by the differential amplifier via the analog / digital conversion unit and the phase of the digital frequency signal output from the frequency setting unit are shifted by 90 °. The detection signal is quadrature detected by the phase difference detection unit to extract the phase difference between the two frequency signals, the phase difference is integrated, and a voltage corresponding to the integration value is supplied as a control voltage to the voltage controlled oscillation unit, The switch unit provided between the voltage controlled oscillation unit and the differential amplifier, and the difference from the time point when the digital frequency signal is output from the frequency setting unit To align the timing until the frequency signal derived from the frequency setting unit included in the signal is input to the phase detection unit and the timing from the time when the signal is output until the detection signal is input to the phase detection unit In order to eliminate the disadvantage that the conversion time of the signal of the first phase correction unit that corrects the phase of the detection signal by a predetermined correction amount and the digital / analog conversion unit each time the frequency synthesizer is started A frequency synthesizer adjustment method comprising: a second phase correction unit that delays and outputs the detection signal in clock units,
A step of outputting a test frequency signal from the digital signal oscillating unit in a state where the voltage controlled oscillating unit is separated from the differential amplifier by the switch unit at the time of starting up the frequency synthesizer;
Changing the number of delay clocks in the second phase correction unit in sequence, and setting the second phase correction unit so that the number of clocks that minimizes the phase difference obtained by the phase detection unit is the delay amount; And a method of adjusting a frequency synthesizer.

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