JP2011188268A - Receiver - Google Patents

Receiver Download PDF

Info

Publication number
JP2011188268A
JP2011188268A JP2010051809A JP2010051809A JP2011188268A JP 2011188268 A JP2011188268 A JP 2011188268A JP 2010051809 A JP2010051809 A JP 2010051809A JP 2010051809 A JP2010051809 A JP 2010051809A JP 2011188268 A JP2011188268 A JP 2011188268A
Authority
JP
Japan
Prior art keywords
analog
signal
field strength
gain control
received
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010051809A
Other languages
Japanese (ja)
Inventor
Kosuke Shinmei
康介 新明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2010051809A priority Critical patent/JP2011188268A/en
Publication of JP2011188268A publication Critical patent/JP2011188268A/en
Pending legal-status Critical Current

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To solve the following problems of a receiver which performs intermittent reception and uses amplitude modulation: high-speed AGC is required in an initial stage immediately after start-up, and low-speed AGC is required in a steady state, however, large CPU load and power consumption are required for achieving the high-speed AGC only by digital processing. <P>SOLUTION: In the high-speed AGC that tracks a transient received electric field level in the stage immediately after start-up, the receiver performs automatic gain control using an analogue RSSI obtained by envelope detection in analogue processing. In the low-speed AGC performs stable gain control in the steady state even under a fading environment, the receiver performs automatic gain control using digital RSSI (average power, peak power) obtained by the digital processing. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、間欠受信時に受信電界レベルに応じて利得を自動的に制御する(自動利得制御 Automatic Gain Control)受信装置に関する。   The present invention relates to a receiver that automatically controls gain according to a received electric field level during intermittent reception (automatic gain control).

復調時に振幅の線形性を必要とする変調方式を用いる通信装置は、受信するとき、受信電界レベルのダイナミックレンジを確保するため、受信レベルに応じて自立的に利得を変化させる自動利得制御(AGC)を行っている。無線通信環境下において、受信装置が受信する信号のレベルは伝播路特性により変動する。受信装置は、伝播路の入力信号レベルが変動しても復調器に入力する信号レベルを一定に保つよう自動利得制御を行う。自動利得制御は、入力する受信信号を対数増幅し包絡線検波して得た受信電界強度(Received Signal Strength Indicator RSSI)信号を用いて可変増幅器の増幅率や減衰率を変更することにより受信信号のレベルを調整する。   A communication device that uses a modulation method that requires linearity of amplitude during demodulation, when receiving, automatic gain control (AGC) that autonomously changes the gain according to the reception level in order to secure a dynamic range of the reception electric field level. )It is carried out. Under a wireless communication environment, the level of a signal received by the receiving apparatus varies depending on propagation path characteristics. The receiver performs automatic gain control so that the signal level input to the demodulator is kept constant even if the input signal level of the propagation path varies. In automatic gain control, received signal strength indicator RSSI signals obtained by logarithmically amplifying an incoming received signal and detecting envelopes are used to change the gain and attenuation rate of the variable amplifier. Adjust the level.

消費電力の削減を目的として、受信装置は間欠受信を行う。受信開始直後、信号波形の立ち上がり直後においては、過渡期的な受信電界レベルに追従させるため、自動利得制御を瞬時に行う必要がある。以下の説明では、短い処理時間で実行する自動利得制御を「高速AGC」と記載する。また、信号波形が立ち上がった定常状態においては、フェージング環境下でも安定的に利得制御を行うため自動利得制御を行っている。このときの自動利得制御は先の「高速AGC」ほどの即応性は要求されない。以下の説明では、この状態の自動利得制御を「低速AGC」と記載する。高速AGCを実現するため、高速に応答するデジタル処理で受信電界強度を求めるデジタルRSSIを用いたり、アナログ回路によって検波した電圧に応じた制御をアナログ処理のみによって行うAGCを使用するといったことが考えられている。   For the purpose of reducing power consumption, the receiving apparatus performs intermittent reception. Immediately after the start of reception and immediately after the rise of the signal waveform, automatic gain control needs to be performed instantaneously in order to follow the transient received electric field level. In the following description, automatic gain control executed in a short processing time is referred to as “high-speed AGC”. In a steady state where the signal waveform has risen, automatic gain control is performed in order to stably perform gain control even under a fading environment. The automatic gain control at this time is not required to be as responsive as the “high-speed AGC”. In the following description, the automatic gain control in this state is described as “low speed AGC”. In order to realize high-speed AGC, it is conceivable to use digital RSSI that obtains the received electric field strength by digital processing that responds at high speed, or use AGC that performs control according to the voltage detected by the analog circuit only by analog processing. ing.

特許文献1では、短周期で入力信号の電力計算を行う高速電力計算回路と、通常周期で電力計算を行う通常電力計算回路と、高速電力計算回路または通常電力計算回路の電力計算結果を入力しフィードバック増幅器を計算する回路によって、高速電力計算回路の電力計算結果と予め定めたターゲットとする受信電力との差の値に応じて高速電力計算回路と通常電力計算回路を切り替える受信装置が開示されている。   In Patent Document 1, a high-speed power calculation circuit that calculates power of an input signal in a short cycle, a normal power calculation circuit that calculates power in a normal cycle, and a power calculation result of the high-speed power calculation circuit or the normal power calculation circuit are input. A receiving device that switches between a high-speed power calculation circuit and a normal power calculation circuit according to a value of a difference between a power calculation result of the high-speed power calculation circuit and a predetermined target reception power by a circuit that calculates a feedback amplifier is disclosed. Yes.

特許文献2では、高速AGCを実施する必要がある受信信号レベル立ち上がり時の検出方法として、RSSI信号の瞬時値と長区間の差信号を閾値と比較し、差信号が閾値を越えた場合に受信信号レベルの立ち上がりと判断し、AGCの制御を高速に引き込んでいる。デジタル処理により得られるデジタルRSSI値によって、受信信号の立ち上がりを検出している。   In Patent Document 2, as a detection method at the time of reception signal level rise where high-speed AGC needs to be performed, an instantaneous value of an RSSI signal and a difference signal of a long section are compared with a threshold value, and reception is performed when the difference signal exceeds the threshold value. It is determined that the signal level has risen, and AGC control is pulled in at high speed. The rising edge of the received signal is detected by a digital RSSI value obtained by digital processing.

特開2002−135346JP 2002-135346 A

特開2006−197654JP 2006-197654 A

例えば、振幅変調やQPSK(Quadrature Phase-Shift Keying)、π/4QPSKといった位相偏移変調においても送信ダイバーシチを行う場合は、復調時に振幅の線形性を必要とする。間欠受信を行い、かつ復調時に振幅の線形性を必要とする受信装置は、立ち上がり直後の初期段階では高速AGCを、定常状態においては低速AGCを実施することが必要である。しかし、高速AGCをデジタル処理のみで実現するためには、きわめて短い時間でデジタルRSSIを算出するため、高速なデジタル処理が必要不可欠となる。これは、消費電力の削減が重要となる受信装置においては、大きな課題の一つとなる。また、シンボルレートが遅い通信においてはオーバーサンプル数の増大により、高速なサンプリング処理が必要となり、これもまた消費電力増大の要因となる。本発明は上記課題を解決するためになされたものであり、CPUの負荷軽減や低消費電力化を削減しながら、高速に自動利得制御を行うことができる受信装置を提供することを目的とする。   For example, when transmission diversity is performed even in phase shift keying such as amplitude modulation, QPSK (Quadrature Phase-Shift Keying), and π / 4 QPSK, linearity of amplitude is required at the time of demodulation. A receiving apparatus that performs intermittent reception and requires linearity of amplitude at the time of demodulation needs to perform high-speed AGC at an initial stage immediately after rising and low-speed AGC in a steady state. However, in order to realize high-speed AGC only by digital processing, high-speed digital processing is indispensable because digital RSSI is calculated in a very short time. This is one of the major problems in a receiving apparatus in which reduction of power consumption is important. Further, in communication with a low symbol rate, an increase in the number of oversamples requires high-speed sampling processing, which also causes an increase in power consumption. The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a receiving apparatus capable of performing automatic gain control at high speed while reducing the load on the CPU and reducing power consumption. .

本発明に係る受信装置は、所定の時間間隔で基地局より送信されたデータフレームを含む受信アナログ信号をデジタル信号に変換して復調するとともに、受信電界強度を測定してデジタル受信電界強度信号を出力する受信部と、受信アナログ信号を包絡線検波し、受信電界強度を測定するとともにアナログ受信電界強度信号を出力するアナログ検波部と、外部からの利得制御信号に基づいて受信アナログ信号の増幅率ないし減衰率を変更する自動利得制御部と、所望のデータフレームを受信する所定時間前に受信部への電源供給を開始するとともに、アナログ検波部から出力されたアナログ受信電界強度信号に基づいて利得制御信号を生成し、データフレームを受信していて、かつ、受信電界強度が安定している場合に、受信部から出力されたデジタル受信電界強度信号に基づいて利得制御信号を生成する制御部とを設けたものである。   A receiving apparatus according to the present invention converts a received analog signal including a data frame transmitted from a base station at a predetermined time interval into a digital signal and demodulates it, and measures a received electric field strength to obtain a digital received electric field strength signal. Output receiver, envelope detection of received analog signal, measurement of received field strength and output of analog received field strength signal, and gain of received analog signal based on external gain control signal In addition, the automatic gain control unit that changes the attenuation factor and the power supply to the receiving unit start a predetermined time before receiving the desired data frame, and the gain is based on the analog received electric field strength signal output from the analog detection unit. When the control signal is generated, the data frame is received, and the received electric field strength is stable, it is output from the receiver. Based on the digital reception electric field intensity signal is provided with a control unit for generating a gain control signal.

本発明に係る受信装置は、所定の時間間隔で基地局より送信されたデータフレームを含む受信アナログ信号をデジタル信号に変換して復調するとともに、受信電界強度を測定してデジタル受信電界強度信号を出力する受信部と、受信アナログ信号を包絡線検波し、受信電界強度を測定するとともにアナログ受信電界強度信号を出力するアナログ検波部と、外部からの利得制御信号に基づいて受信アナログ信号の増幅率ないし減衰率を変更する自動利得制御部と、所望のデータフレームを受信する所定時間前に受信部への電源供給を開始するとともに、アナログ検波部から出力されたアナログ受信電界強度信号に基づいて利得制御信号を生成し、データフレームを受信していて、かつ、受信電界強度が安定している場合に、受信部から出力されたデジタル受信電界強度信号に基づいて利得制御信号を生成する制御部とを設けたので、CPUの負荷軽減や低消費電力化を削減しながら、高速に自動利得制御を行うことができる。   A receiving apparatus according to the present invention converts a received analog signal including a data frame transmitted from a base station at a predetermined time interval into a digital signal and demodulates it, and measures a received electric field strength to obtain a digital received electric field strength signal. Output receiver, envelope detection of received analog signal, measurement of received field strength and output of analog received field strength signal, and gain of received analog signal based on external gain control signal In addition, the automatic gain control unit that changes the attenuation factor and the power supply to the receiving unit start a predetermined time before receiving the desired data frame, and the gain is based on the analog received electric field strength signal output from the analog detection unit. When the control signal is generated, the data frame is received, and the received electric field strength is stable, it is output from the receiver. Since there is provided a control unit for generating a gain control signal based on the digital received signal strength signal, while reducing the load reduction and low power consumption of the CPU, it is possible to perform automatic gain control at a high speed.

本発明の実施の形態1に係る受信装置の構成を示すブロック図である。It is a block diagram which shows the structure of the receiver which concerns on Embodiment 1 of this invention. 本発明の実施の形態2に係る受信装置の構成を示すブロック図である。It is a block diagram which shows the structure of the receiver which concerns on Embodiment 2 of this invention. 間欠受信の同期モードの様子を示す説明図である。It is explanatory drawing which shows the mode of the synchronous mode of intermittent reception.

実施の形態1.
図1は、本発明の実施の形態1に係る受信装置の構成を示すブロック図である。本発明における構成は、無線通信におけるデジタル携帯通信機(スーパーヘテロダイン受信機)を想定しており、アンテナ部1、RF(Radio Frequency)部2、周波数変換を行うミキサー3、ローカル信号生成部4、IF(Intermediate Frequency)部5、復調用A/D(アナログ/デジタル)変換器6、高速RSSI測定用のA/D変換器7、デジタル処理部8である。デジタル処理部8は、主に復調処理を行うDEM(DEModulator)9と、自動利得制御(AGC)などの無線機制御を行うCPU(Central Processing Unit)10から構成される。システム上、要求される受信装置のダイナミックレンジがA/D変換器6のダイナミックレンジによって、制約される場合、RF部2によって、プリアンプのON/OFF制御やATT(Attenuator)のON/OFF制御のような自動利得制御(AGC)が必要となる。
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 1 of the present invention. The configuration of the present invention assumes a digital portable communication device (superheterodyne receiver) in wireless communication, and includes an antenna unit 1, an RF (Radio Frequency) unit 2, a mixer 3 for performing frequency conversion, a local signal generating unit 4, An IF (Intermediate Frequency) unit 5, a demodulation A / D (analog / digital) converter 6, an A / D converter 7 for high-speed RSSI measurement, and a digital processing unit 8. The digital processing unit 8 mainly includes a DEM (DEModulator) 9 that performs demodulation processing and a CPU (Central Processing Unit) 10 that performs radio control such as automatic gain control (AGC). When the required dynamic range of the receiving device is restricted by the dynamic range of the A / D converter 6 in the system, the RF unit 2 performs preamplifier ON / OFF control and ATT (Attenuator) ON / OFF control. Such automatic gain control (AGC) is required.

立ち上がり直後の初期段階において過渡期的な受信電界レベルに追従させる高速AGCを実施する場合の動作を説明する。本発明に係る受信装置は、低消費電力化のため以下二つのモードで動作する。「圏外モード」は十分な電界が得られていないときの受信装置の動作モードであり、「同期モード」は十分な電界が得られているときの受信装置の動作モードを示す。受信装置は「圏外モード」では、数秒周期で受信電源のオン/オフを繰り返し、受信電源をオンした後に、アナログRSSIのレベルに応じて高速AGCを実行する。また、受信装置は「同期モード」では、既知の時間間隔で送信されるデータフレームに対し、受信したいフレームのタイミングが分かっているので、受信したいデータフレームの数十ms前に受信電源をオンし、その後、アナログRSSIのレベルに応じて高速AGCを実行する。   The operation in the case of implementing high-speed AGC for tracking the received electric field level in the transition period in the initial stage immediately after the rising will be described. The receiving apparatus according to the present invention operates in the following two modes to reduce power consumption. “Out-of-service mode” is an operation mode of the receiving apparatus when a sufficient electric field is not obtained, and “synchronous mode” indicates an operation mode of the receiving apparatus when a sufficient electric field is obtained. In the “out-of-service mode”, the receiving device repeatedly turns on / off the receiving power at a cycle of several seconds, and after turning on the receiving power, executes high-speed AGC according to the level of analog RSSI. In the “synchronous mode”, the receiving device knows the timing of the frame to be received with respect to the data frame transmitted at a known time interval. Thereafter, high-speed AGC is executed in accordance with the level of analog RSSI.

また、定常状態においてフェージング環境下でも安定的に利得制御を行う低速AGCを実施する場合の動作を説明する。定常状態とは、受信装置が上記説明の同期モードに入っていて、受信電源がオンされており、かつフレームを受信している状態を示す。受信装置は、高速AGCを実施した後、LSIからCPUに対する受信割り込み(LSIが受信フレーム単位でCPUに入れる)を検知すると、低速AGCを実施する。   An operation in a case where low-speed AGC that stably performs gain control in a steady state even under a fading environment will be described. The steady state indicates a state in which the receiving apparatus is in the synchronous mode described above, the receiving power is turned on, and a frame is received. When the receiving apparatus detects a reception interrupt from the LSI to the CPU after the high-speed AGC is performed (the LSI enters the CPU in units of received frames), the receiving apparatus performs the low-speed AGC.

図3は、間欠受信の同期モードの様子を示す説明図である。対象の受信装置は基地局から連続的に送信されるデータを受信する。データはフレーム長が40msのフレームが16個を1セットとし、640ms長のスーパーフレームを構成している。基地局は、スーパーフレームを周期的に送信する。各フレームは、同期を確立するためのシンクワード(Sync- Word)、誤り訂正符号、汎用のデータ等から構成されている。受信装置は、図3に示す0〜15のフレームのうち、1つ以上のフレームを受信する。図3では、フレーム番号1のみを受信する場合の様子を示している。この場合、図中符号1〜4に示すデータを受信する必要がある。符号1のデータは高速AGC用受信、符号2はプリアンブル、符号3は受信したいフレーム、符号4はプリアンブルを示す。受信装置は、符号1の区間では高速AGCを実施しており、CPU10は、アナログ処理による包絡線検波によって得られるアナログRSSIを用いて自動利得制御信号を生成し、RF部2に出力して自動利得制御を行う。そして、符号2の区間ではDEM部9のデジタル処理によって検出可能な平均RSSI値とピークRSSI値を用いて自動利得制御信号を生成し、RF部2に出力して自動利得制御を行う。CPU10は、符号1から符号2の区間に移行したときにDEM9から受信割り込み信号を受ける。この受信割り込み信号を契機にCPU10は高速AGCから低速AGCに遷移する。   FIG. 3 is an explanatory diagram showing a state of the intermittent reception synchronous mode. The target receiving apparatus receives data continuously transmitted from the base station. The data consists of 16 frames each having a frame length of 40 ms, forming a super frame having a length of 640 ms. The base station periodically transmits a super frame. Each frame includes a sync word for establishing synchronization, an error correction code, general-purpose data, and the like. The receiving apparatus receives one or more frames among 0 to 15 frames shown in FIG. FIG. 3 shows a state in which only frame number 1 is received. In this case, it is necessary to receive data indicated by reference numerals 1 to 4 in the figure. Data of code 1 indicates reception for high-speed AGC, code 2 indicates a preamble, code 3 indicates a frame to be received, and code 4 indicates a preamble. The receiving apparatus performs high-speed AGC in the section denoted by reference numeral 1, and the CPU 10 generates an automatic gain control signal using analog RSSI obtained by envelope detection by analog processing, and outputs it to the RF unit 2 to automatically Gain control is performed. Then, in the section of reference numeral 2, an automatic gain control signal is generated using an average RSSI value and a peak RSSI value that can be detected by digital processing of the DEM unit 9, and is output to the RF unit 2 to perform automatic gain control. The CPU 10 receives a reception interrupt signal from the DEM 9 when transitioning from the reference numeral 1 to the reference numeral 2. In response to this reception interrupt signal, the CPU 10 transitions from high-speed AGC to low-speed AGC.

高速AGCにおいて、アナログ包絡線検波を行うため、単一の検波ICを用いることが一般的であるが、ダイオードを使用して検波回路を構成することも可能である。一方、低速AGCにおいては、デジタル処理によって得られるデジタルRSSI(平均電力、ピーク電力)を用いた自動利得制御を行う。すなわち、ベースバンド信号であるI、Q信号の振幅より、フレーム単位で平均化した平均電力と最大電力を算出し、得られる各電力を変換テーブルによりデジベル単位に変換する。高速AGCに使用するアナログRSSIの検出はRF部2による伝播遅延のみに依存し、μsecオーダーの自動利得制御が可能となり、バースト単位で完結する制御を行うことができる。   In high-speed AGC, it is common to use a single detection IC to perform analog envelope detection, but it is also possible to configure a detection circuit using a diode. On the other hand, in low speed AGC, automatic gain control using digital RSSI (average power, peak power) obtained by digital processing is performed. That is, average power and maximum power averaged in frame units are calculated from the amplitudes of the I and Q signals that are baseband signals, and each obtained power is converted into decibel units using a conversion table. The detection of the analog RSSI used for the high-speed AGC depends only on the propagation delay by the RF unit 2, enables automatic gain control on the order of μsec, and complete control in units of bursts.

一方、低速AGCに使用するデジタルRSSIの検出はフレーム単位でのデジタル処理でよく、DEM部9とCPU10とのアクセス頻度の低減を図ることにより、CPU10の負荷軽減や消費電力の低減を実現することができることが特長である。   On the other hand, the digital RSSI used for the low-speed AGC may be detected by digital processing in units of frames. By reducing the access frequency between the DEM unit 9 and the CPU 10, the load on the CPU 10 and the power consumption can be reduced. The feature is that it can.

上記説明のように、本発明に係る受信装置は、立ち上がり直後の初期段階において過渡期的な受信電界レベルに追従させる高速AGCにおいては、アナログ処理による包絡線検波によって得られるアナログRSSIを用いた自動利得制御を行い、定常状態においてフェージング環境下でも安定的に利得制御を行う低速AGCにおいては、デジタル処理によって得られるデジタルRSSI(平均電力、ピーク電力)を用いた自動利得制御を行う。   As described above, the receiving apparatus according to the present invention is an automatic processor that uses analog RSSI obtained by envelope detection by analog processing in high-speed AGC that follows a transient received electric field level in an initial stage immediately after rising. In low-speed AGC that performs gain control and stably performs gain control in a steady state even under a fading environment, automatic gain control using digital RSSI (average power, peak power) obtained by digital processing is performed.

したがって、本発明により、間欠受信を行う無線通信において、通信のビットレートによらず、立ち上がり直後に、μsecオーダーで高速に追従可能である高速AGCが実現可能であり、デジタル処理の軽減を図ることが可能である。また、定常状態においては、デジタルRSSI(平均電力、ピーク電力)を用いた低速AGCを行うことにより、間欠受信を行う携帯機においても安定的な無線通信を実現することが可能となる。また、バーストごとに独立して受信電力に応じた自動利得制御が可能である。CPUの負荷軽減や低消費電力化を削減しながら、高速に自動利得制御を行うことができる。   Therefore, according to the present invention, in wireless communication that performs intermittent reception, it is possible to realize a high-speed AGC that can follow at a high speed on the order of μsec immediately after the start-up, regardless of the bit rate of communication, and reduce digital processing. Is possible. In a steady state, by performing low-speed AGC using digital RSSI (average power, peak power), it is possible to realize stable wireless communication even in a portable device that performs intermittent reception. Also, automatic gain control according to received power can be performed independently for each burst. Automatic gain control can be performed at high speed while reducing CPU load reduction and low power consumption.

なお、上記説明は、スーパーヘテロダイン方式の受信装置について説明したが、ダブルスーパーヘテロダイン方式の受信装置にも適用可能である。   Although the above description has been given of a superheterodyne receiver, it can also be applied to a double superheterodyne receiver.

実施の形態2.
図2は、本発明の実施の形態2に係る受信装置の構成を示すブロック図である。本発明における構成は、無線通信におけるデジタル携帯機(スーパーヘテロダイン受信機)を想定している。図2において、構成要素としては、アンテナ部1、RF(Radio Frequency)部2、周波数変換を行うミキサー3、ローカル信号生成部4、IF(Intermediate Frequency)部5、復調用のA/D(アナログ/デジタル)変換器6、高速RSSI用のA/D(アナログ/デジタル)変換器7、デジタル処理部8である。デジタル処理部8は、主に復調処理を行うDEM(DEModulator)9と、自動利得制御(AGC)などの無線機制御を行うCPU(Central Processing Unit)10から構成される。
Embodiment 2. FIG.
FIG. 2 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 2 of the present invention. The configuration of the present invention assumes a digital portable device (superheterodyne receiver) in wireless communication. In FIG. 2, the components include an antenna unit 1, an RF (Radio Frequency) unit 2, a mixer 3 that performs frequency conversion, a local signal generation unit 4, an IF (Intermediate Frequency) unit 5, and an A / D (analog) for demodulation. / Digital) converter 6, high-speed RSSI A / D (analog / digital) converter 7, and digital processing unit 8. The digital processing unit 8 mainly includes a DEM (DEModulator) 9 that performs demodulation processing and a CPU (Central Processing Unit) 10 that performs radio control such as automatic gain control (AGC).

システム上、要求される受信装置のダイナミックレンジがデジタル処理におけるビット幅によるダイナミックレンジによって、制約される場合、ビットシフトを行うビット最適化による自動利得制御(AGC)が必要となる。自動利得制御(AGC)では、通常、受信装置内部で検出するRSSI値に基づいて、利得制御を行う。本発明ではIF部5のアナログ処理による包絡線検波によって得られるアナログRSSIと、DEM部9のデジタル処理によって検出可能な平均RSSI値とピークRSSI値を用いて、CPU10がDEM部9のビット最適化を行うことによって、デジタル自動利得制御(AGC)を実現する。このとき、立ち上がり直後の初期段階において過渡期的な受信電界レベルに追従させる高速AGCにおいては、アナログ処理による包絡線検波によって得られるアナログRSSIを用いた自動利得制御を行い、定常状態においてフェージング環境下でも、安定的に利得制御を行う低速AGCにおいてはデジタル処理によって得られるデジタルRSSI(平均電力、ピーク電力)を用いた自動利得制御を行う。   When the required dynamic range of the receiving apparatus is restricted by the dynamic range due to the bit width in digital processing, automatic gain control (AGC) by bit optimization that performs bit shift is required. In automatic gain control (AGC), gain control is normally performed based on an RSSI value detected within the receiving apparatus. In the present invention, the CPU 10 optimizes the bit of the DEM unit 9 using the analog RSSI obtained by the envelope detection by the analog processing of the IF unit 5 and the average RSSI value and the peak RSSI value detectable by the digital processing of the DEM unit 9. To realize digital automatic gain control (AGC). At this time, in high-speed AGC that follows the transient received electric field level in the initial stage immediately after the rising, automatic gain control using analog RSSI obtained by envelope detection by analog processing is performed, and in a steady state under fading environment However, in low-speed AGC that stably performs gain control, automatic gain control using digital RSSI (average power, peak power) obtained by digital processing is performed.

高速AGCに使用するアナログRSSIの検出はRF部2による伝播遅延のみにより、μsecオーダーの自動利得制御が可能となり、バースト単位で完結する制御を行うことができる。一方、低速AGCに使用するデジタルRSSIの検出はフレーム単位でのデジタル処理でよく、DEM部9とCPU10とのアクセス頻度の低減を図ることにより、CPU10の負荷軽減や消費電力の低減を実現することが特長である。   The detection of the analog RSSI used for the high-speed AGC enables automatic gain control on the order of μsec only by the propagation delay by the RF unit 2, and complete control can be performed in burst units. On the other hand, the digital RSSI used for the low-speed AGC may be detected by digital processing in units of frames. By reducing the access frequency between the DEM unit 9 and the CPU 10, the load on the CPU 10 and the power consumption can be reduced. Is a feature.

実施の形態1では、受信装置はIF部5のアナログ処理による包絡線検波によって得られるアナログRSSIと、DEM部9のデジタル処理によって検出可能な平均RSSI値とピークRSSI値を用いて、CPU10がRF部2のゲイン制御を行っていたが、実施の形態2では、IF部5のアナログ処理による包絡線検波によって得られるアナログRSSIと、DEM部9のデジタル処理によって検出可能な平均RSSI値とピークRSSI値を用いて、CPU10がDEM部9のビット最適化を行うことでゲイン制御を行っている。両者はともに、間欠受信を行う無線通信においても安定的な無線通信を実現することが可能であり、バーストごとに独立して受信電力に応じた自動利得制御が可能であるという効果を奏する。   In the first embodiment, the reception device uses the analog RSSI obtained by envelope detection by analog processing of the IF unit 5 and the average RSSI value and the peak RSSI value that can be detected by digital processing of the DEM unit 9, and the CPU 10 performs RF Although the gain control of the unit 2 is performed, in the second embodiment, the analog RSSI obtained by the envelope detection by the analog processing of the IF unit 5, the average RSSI value and the peak RSSI that can be detected by the digital processing of the DEM unit 9 The CPU 10 performs gain control by performing bit optimization of the DEM unit 9 using the values. Both of them can realize stable wireless communication even in wireless communication that performs intermittent reception, and have an effect that automatic gain control according to received power can be performed independently for each burst.

1:アンテナ部、2:RF部、3:ミキサー、4:ローカル信号生成部、5:IF部、
6:A/D(アナログ/デジタル)変換器(復調用)、
7:A/D(アナログ/デジタル)変換器(高速RSSI用)、
8:デジタル処理部、9:DEM部、10:CPU
1: antenna unit, 2: RF unit, 3: mixer, 4: local signal generation unit, 5: IF unit,
6: A / D (analog / digital) converter (for demodulation),
7: A / D (analog / digital) converter (for high-speed RSSI),
8: Digital processing unit, 9: DEM unit, 10: CPU

Claims (2)

所定の時間間隔で基地局より送信されたデータフレームを含む受信アナログ信号をデジタル信号に変換して復調するとともに、受信電界強度を測定してデジタル受信電界強度信号を出力する受信部と、
前記受信アナログ信号を包絡線検波し、受信電界強度を測定するとともにアナログ受信電界強度信号を出力するアナログ検波部と、
外部からの利得制御信号に基づいて前記受信アナログ信号の増幅率ないし減衰率を変更する自動利得制御部と、
所望のデータフレームを受信する所定時間前に前記受信部への電源供給を開始するとともに、前記アナログ検波部から出力されたアナログ受信電界強度信号に基づいて前記利得制御信号を生成し、前記データフレームを受信していて、かつ、前記受信電界強度が安定している場合に、前記受信部から出力されたデジタル受信電界強度信号に基づいて前記利得制御信号を生成する制御部とを設けたことを特徴とする受信装置。
A receiving unit that converts a received analog signal including a data frame transmitted from a base station at a predetermined time interval into a digital signal and demodulates it, measures a received electric field strength, and outputs a digital received electric field strength signal;
Envelope detection of the received analog signal, an analog detector for measuring the received electric field strength and outputting an analog received electric field strength signal;
An automatic gain control unit that changes the amplification factor or attenuation factor of the received analog signal based on an external gain control signal;
The power supply to the receiving unit is started a predetermined time before receiving a desired data frame, and the gain control signal is generated based on the analog received electric field strength signal output from the analog detecting unit, and the data frame And a control unit that generates the gain control signal based on the digital reception field strength signal output from the reception unit when the reception field strength is stable. A receiving device.
所定の時間間隔で基地局より送信されたデータフレームを含む受信アナログ信号をデジタル信号に変換して復調するとともに、受信電界強度を測定してデジタル受信電界強度信号を出力する受信部と、
前記受信アナログ信号を包絡線検波し、受信電界強度を測定するとともにアナログ受信電界強度信号を出力するアナログ検波部と、
所望のデータフレームを受信する所定時間前に前記受信部への電源供給を開始するとともに、前記アナログ検波部から出力されたアナログ受信電界強度信号に基づいて前記利得制御信号を生成し、前記データフレームを受信していて、かつ、前記受信電界強度が安定している場合に、前記受信部から出力されたデジタル受信電界強度信号に基づいて前記利得制御信号を生成することを特徴とする制御部とを備え、
前記受信部は、前記制御部から出力された前記利得制御信号に応じて、前期デジタル信号のビット列を補正することを特徴とする受信装置。
A receiving unit that converts a received analog signal including a data frame transmitted from a base station at a predetermined time interval into a digital signal and demodulates it, measures a received electric field strength, and outputs a digital received electric field strength signal;
Envelope detection of the received analog signal, an analog detector for measuring the received electric field strength and outputting an analog received electric field strength signal;
The power supply to the receiving unit is started a predetermined time before receiving a desired data frame, and the gain control signal is generated based on the analog received electric field strength signal output from the analog detecting unit, and the data frame And the gain control signal is generated based on the digital received field strength signal output from the receiver when the received field strength is stable and With
The receiving device corrects a bit string of a previous digital signal according to the gain control signal output from the control unit.
JP2010051809A 2010-03-09 2010-03-09 Receiver Pending JP2011188268A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010051809A JP2011188268A (en) 2010-03-09 2010-03-09 Receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010051809A JP2011188268A (en) 2010-03-09 2010-03-09 Receiver

Publications (1)

Publication Number Publication Date
JP2011188268A true JP2011188268A (en) 2011-09-22

Family

ID=44794010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010051809A Pending JP2011188268A (en) 2010-03-09 2010-03-09 Receiver

Country Status (1)

Country Link
JP (1) JP2011188268A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11632721B2 (en) 2020-02-26 2023-04-18 Samsung Electronics Co., Ltd. Apparatus and method for controlling power consumption in wireless communication

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003008676A (en) * 2001-06-25 2003-01-10 Sony Corp Automatic gain control circuit, its method, and demodulator using them
JP2009188898A (en) * 2008-02-08 2009-08-20 Ricoh Co Ltd Radio communication apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003008676A (en) * 2001-06-25 2003-01-10 Sony Corp Automatic gain control circuit, its method, and demodulator using them
JP2009188898A (en) * 2008-02-08 2009-08-20 Ricoh Co Ltd Radio communication apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11632721B2 (en) 2020-02-26 2023-04-18 Samsung Electronics Co., Ltd. Apparatus and method for controlling power consumption in wireless communication

Similar Documents

Publication Publication Date Title
KR100532266B1 (en) Direct conversion receiver and dc offset reducing method
JP2004328494A (en) Radio receiver and radio signal processing method
US8909183B2 (en) Automatic gain control device
CA2232754A1 (en) Gain control method and receiver
TW200931813A (en) ADC use with multiple signal modes
JP4168393B2 (en) AGC control method for radio communication mobile station
JP2001024454A (en) Automatic gain controller and its method and radio communication apparatus having automatic gain control function
CN107147368B (en) Gain adjusting method and device for gain amplifier
US10594280B2 (en) Method and device for generating received signal strength indication
JP2011188268A (en) Receiver
JP2006197654A (en) Agc method, and agc circuit
JP4506343B2 (en) Wireless receiver
KR100651493B1 (en) Apparatus and method for controllin gain in receiver
JP2008172568A (en) Receiver
JP2002141832A (en) Spread spectrum communication system receiver
JP2001244861A (en) Device and method for radio reception
JP4644823B2 (en) Automatic gain control circuit
JP2004221663A (en) Radio communication equipment
JPH11355376A (en) Receiver and reception method
JP2007312187A (en) Radio lan integrated-circuit device, radio lan system, and mobile telephone set
JP4942674B2 (en) Reception device and reception control method
JP2007266853A (en) Automatic gain controller
KR100606688B1 (en) Apparatus for controlling power in code division multiple access system
KR100257930B1 (en) Reference frequency control apparatus and method of a tranceiver
CN116743100A (en) Automatic gain control circuit, control method and device and storage medium

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130206

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20130823

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130903

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140107