JP2011187814A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a MOS transistor of high breakdown voltage, by suppressing the number of hot-carriers trapped at an end portion of a gate insulating film, and by suppressing increase in the area. <P>SOLUTION: With a mask pattern 9 formed on a first conductive type semiconductor substrate 1 as a mask, a pair of first low-concentration diffusion regions 4 of second conductive type and a pair of second low-concentration diffusion regions 3 of a second conductive type which is deeper than the first low-concentration diffusion region 4 and of high concentration are formed. Then, a gate insulating film 5 is formed from over one first low-concentration diffusion region 4, among the pair of first low-concentration diffusion regions 4 to over the other first low-concentration diffusion region 4, and a gate electrode 6 is formed on the gate insulating film 5. With the gate electrode 6 as a mask, a pair of high-concentration diffusion region 8 of a second conductive type which is higher in concentration than the second low-concentration diffusion region 3 is formed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Insulated gate MOS transistors have a problem of deterioration of element characteristics caused by trapping hot carriers (hot electrons) at the end of the gate insulating film. This problem is particularly noticeable with N-channel transistors.

As a method for manufacturing an insulated gate MOS transistor, there is one disclosed in Patent Document 1.
The manufacturing method of patent document 1 is performed as follows. First, a gate insulating film is formed on a first conductivity type semiconductor substrate. Next, a gate electrode is formed on the gate insulating film. Next, using the gate electrode as a mask, a second conductivity type impurity is ion-implanted deeply into the semiconductor substrate at a first ion beam tilt angle to form a first low-concentration drain layer. Next, using the gate electrode as a mask, a second conductivity type impurity is shallowly ion-implanted into the semiconductor substrate at a second ion beam tilt angle smaller than the first ion beam tilt angle, and the first low-concentration drain layer is formed. Increase the surface concentration.

  However, in the manufacturing method of Patent Document 1, due to the influence of ion beam implantation obliquely, the impurity along the outermost surface of the semiconductor substrate as shown in FIG. A depression is generated in the concentration profile. This depression promotes hot carrier injection into the end portion of the gate insulating film, and becomes a factor of fluctuation of the saturation current.

  For this reason, in the manufacturing method disclosed in Patent Document 1, the second conductivity type impurity (arsenic) is ion-implanted into the semiconductor substrate at the third ion beam tilt angle using the gate electrode as a mask, and the first low concentration A second low-concentration drain layer having a low impurity concentration and shallower than the drain layer is formed. In Patent Document 1, by forming the second low-concentration drain layer in this way, the profile of the impurity concentration along the outermost surface of the semiconductor substrate can be made smooth as shown in FIG. There is a statement to that effect.

Japanese Patent Application Laid-Open No. 2005-116892

  However, in the technique of Patent Document 1, a low concentration diffusion region is formed by implanting an ion beam obliquely using a gate electrode as a mask, that is, a low concentration diffusion region is formed by ion implantation after forming a gate insulating film. To do. For this reason, since the gate insulating film is damaged by ion implantation, it is difficult to manufacture a high breakdown voltage MOS transistor as required by a display driver or the like. Therefore, when creating a high breakdown voltage MOS transistor, in order to sufficiently ensure electric field relaxation from the end of the gate electrode to the high concentration diffusion region, the high concentration diffusion is sufficiently separated from the end of the gate electrode. A region needs to be formed. As a result, the area of the MOS transistor becomes large.

  As described above, it has been difficult to manufacture a high-breakdown-voltage MOS transistor while suppressing the number of hot carriers trapped at the end of the gate insulating film and suppressing area expansion.

The present invention uses a mask pattern formed on a first conductivity type semiconductor substrate as a mask, a pair of first low concentration diffusion regions of a second conductivity type, and a deeper and higher concentration than the first low concentration diffusion regions. Forming a pair of second low-concentration diffusion regions of the second conductivity type;
A gate insulating film is formed from one first low concentration diffusion region of the pair of first low concentration diffusion regions to the other first low concentration diffusion region, and a gate electrode is formed on the gate insulating film. Forming, and
Forming a pair of high-concentration diffusion regions of the second conductivity type having a higher concentration than the second low-concentration diffusion region using the gate electrode as a mask;
A method for manufacturing a semiconductor device is provided.

  According to this method for manufacturing a semiconductor device, since the second low-concentration diffusion region that is deeper and higher in concentration than the first low-concentration diffusion region is formed, the low-concentration diffusion region including the first and second low-concentration diffusion regions The depth becomes low resistance. As a result, the current flows mainly in the deep portion of the low concentration diffusion region, and the number of hot carriers injected into the gate insulating film is suppressed. In addition, since the low concentration diffusion region is formed so that it also exists below the gate insulating film, the high concentration diffusion region is not formed far from the end of the gate electrode (the MOS transistor area is increased). It is possible to manufacture a high-breakdown-voltage MOS transistor required by a display driver or the like.

  According to the present invention, it is possible to manufacture a high-breakdown-voltage MOS transistor while suppressing the number of hot carriers trapped at the end of the gate insulating film and suppressing the area expansion.

It is sectional drawing which shows a series of processes of the manufacturing method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows a series of processes of the manufacturing method of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the structure of the semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on embodiment. It is a figure which shows the profile of the impurity concentration along the outermost surface of the semiconductor substrate of the semiconductor device manufactured by the manufacturing method of the semiconductor device which concerns on embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  1 and 2 are cross-sectional views showing a series of steps in the method for manufacturing a semiconductor device according to the embodiment.

  In the method for manufacturing a semiconductor device according to this embodiment, the following steps are performed. First, using the mask pattern 9 formed on the semiconductor substrate 1 of the first conductivity type as a mask, the pair of first low concentration diffusion regions 4 of the second conductivity type and deeper and higher concentration than the first low concentration diffusion regions 4. And a pair of second low-concentration diffusion regions 3 of the second conductivity type. Next, a gate insulating film 5 is formed from one first low-concentration diffusion region 4 to the other first low-concentration diffusion region 4 of the pair of first low-concentration diffusion regions 4. A gate electrode 6 is formed on the film 5. Next, using the gate electrode 6 as a mask, a pair of high concentration diffusion regions 8 of the second conductivity type having a higher concentration than the second low concentration diffusion region 3 are formed. Details will be described below.

As shown in FIG. 1A, an element isolation region 2 is formed on the surface layer of a first conductivity type (for example, P type) semiconductor substrate 1 (hereinafter referred to as substrate 1), and the element formation region 10 is separated from other regions. Separate. For this purpose, first, a mask pattern (not shown) is formed on a portion of the substrate 1 other than where the element isolation region 2 is formed. Next, the surface layer of the substrate 1 is etched using this mask pattern as a mask. Thereby, the surface layer of the substrate 1 is selectively removed, and the groove 2a for forming the element isolation region 2 is formed. Next, an oxide film (SiO ₂ ) is formed on the surface of the substrate 1 so as to fill the groove 2a. Next, the surface of the substrate 1 is polished so that the oxide film remains in the groove 2a while being removed from the substrate 1 other than the groove 2a, thereby forming the element isolation region 2.

  Next, as shown in FIG. 1A, a mask pattern 9 is formed on the substrate 1. Next, using this mask pattern 9 as a mask, an ion beam tilt angle with respect to the substrate 1 is set to 0 degree, and a second conductivity type (for example, N-type) impurity (for example, phosphorus) is ion-implanted. As a result, a pair of second low-concentration diffusion regions 3 are formed in the element formation region 10.

  Next, as shown in FIG. 1B, the tilt angle of the ion beam with respect to the substrate 1 is set to 0 degree using the same mask pattern 9 as that used for forming the second low-concentration diffusion region 3 as a mask. A second conductivity type (for example, N-type) impurity (for example, phosphorus) is ion-implanted. As a result, the first low concentration diffusion region 4 is formed above each of the second low concentration diffusion regions 3. That is, the pair of first low concentration diffusion regions 4 are formed in the element formation region 10. Here, the first low-concentration diffusion region 4 is formed to have a lower concentration and shallower than the second low-concentration diffusion region 3. Next, the mask pattern 9 is removed.

  Next, as shown in FIG. 1C, the gate extends from one first low concentration diffusion region 4 to the other first low concentration diffusion region 4 in the pair of first low concentration diffusion regions 4. An insulating film 5 is formed, and a gate electrode 6 is formed on the gate insulating film 5. For this purpose, for example, an oxide film (not shown) is first formed on the substrate 1 by thermal oxidation or CVD (Chemical Vapor Deposition). Next, a polysilicon film (not shown) is formed on the oxide film. Next, a mask pattern (not shown) is formed on a portion that becomes the gate electrode 6 in the polysilicon film. Next, the polysilicon film is etched into the shape of the gate electrode 6 by etching the polysilicon film using this mask pattern as a mask. Next, the oxide film is etched into the shape of the gate insulating film 5 by etching the oxide film using this mask pattern as a mask. Next, this mask pattern is removed.

  Next, as shown in FIG. 2A, an oxide film is formed on the entire surface by, for example, CVD, and then etched back, thereby forming sidewalls 7 on the side surfaces of the gate electrode 6 and the gate insulating film 5. .

Next, as shown in FIG. 2B, the first conductivity type (for example, N-type) impurity (for example, phosphorus) is ion-implanted using the gate electrode 6 and the sidewalls 7 as a mask, thereby Then, the high concentration diffusion region 8 having a higher concentration than the second low concentration diffusion regions 3 and 4 is formed.
Thus, the semiconductor device 100 can be manufactured.

  Next, the operation will be described.

  When a gate voltage is applied to the gate electrode 6 with one high-concentration diffusion region 8 connected to the source potential and the other high-concentration diffusion region 8 connected to the drain potential, the substrate 1 below the gate electrode 6 is Thus, a current flows from one high concentration diffusion region 8 to the other high concentration diffusion region 8.

  FIG. 3 is a cross-sectional view showing a configuration of a semiconductor device 100 manufactured by the method for manufacturing a semiconductor device according to the embodiment. As shown in FIG. 3, the portion from the lower portion of the gate electrode 6 to the high concentration diffusion region 8 in the substrate 1 is equivalent to a circuit in which the first and second resistors R1 and R2 are connected in parallel. That is, the portion from the lower portion of the gate electrode 6 in the substrate 1 to the high concentration diffusion region 8 via the first low concentration diffusion region 4 becomes the first resistance R1, and the lower portion of the gate electrode 6 in the substrate 1 is formed. A portion from the portion to the high concentration diffusion region 8 via the second low concentration diffusion region 3 becomes the second resistance R2. Of the first and second low-concentration diffusion regions 4 and 3 of the low-concentration diffusion region 11, the deeper second low-concentration diffusion region 4 has a higher impurity concentration, so the low-concentration diffusion region 11 is lower than the upper portion. Becomes lower resistance. That is, the second resistor R2 has a lower resistance than the first resistor R1. For this reason, the current mainly flows under the low concentration diffusion region 11, and the number of hot carriers injected into the gate insulating film 5 is suppressed.

  FIG. 4 is a diagram showing a profile of impurity concentration along the outermost surface of the substrate 1 of the semiconductor device 100. In the present embodiment, the tilt angle of the ion beam is set to 0 degree. For this reason, since ions are uniformly implanted into the substrate 1, the profile shown in FIG. 4 does not have a dent as shown in FIG. Therefore, it is possible to suppress deterioration of element characteristics due to hot carriers without additional implantation of arsenic ions.

  Further, by forming the low concentration diffusion region 11 by setting the tilt angle of the ion beam to 0 degree before forming the gate insulating film 5, the low concentration diffusion region 11 extending to the lower side of the gate insulating film 5 is formed. Can be formed. Therefore, since the electric field from the end of the gate electrode 6 to the high concentration diffusion region 8 is sufficiently relaxed, the high concentration diffusion region 8 does not have to be formed sufficiently separated from the end of the gate electrode 6 (MOS transistor). This makes it possible to manufacture a high-breakdown-voltage MOS transistor required by a display driver or the like.

  According to the embodiment as described above, the second low-concentration diffusion region 3 that is deeper and higher in concentration than the first low-concentration diffusion region 4 is formed, and thus includes the first and second low-concentration diffusion regions 3 and 4. The lower part of the low concentration diffusion region 11 has a low resistance. As a result, the current mainly flows under the low concentration diffusion region 11 and the number of hot carriers injected into the gate insulating film 5 is suppressed. In addition, since the low concentration diffusion region 11 is formed so as to exist also under the gate insulating film 5, the high concentration diffusion region 8 does not have to be formed sufficiently separated from the end portion of the gate electrode 6 (in the MOS transistor). Even without increasing the area, a high-breakdown-voltage MOS transistor required by a display driver or the like can be manufactured.

  Further, since the low concentration diffusion region 11 is formed before the gate insulating film 5 is formed, the low concentration diffusion region 11 extending to the lower side of the gate insulating film 5 is formed even if the inclination angle of the ion beam is 0 degree. It becomes possible. As a result, the impurity concentration profile can be smoothed to suppress the deterioration of element characteristics due to hot carriers, and the breakdown voltage can be increased without increasing the area of the MOS transistor. Further, damage to the gate insulating film 5 due to the ion beam for forming the low concentration diffusion region 11 can be avoided.

  In addition, since the low concentration diffusion region 11 is formed by setting the inclination angle of the ion beam to 0 degree, the low concentration diffusion region 11 can be uniformly formed on the substrate 1. Therefore, the profile of the impurity concentration becomes smooth as shown in FIG. 4 without additional implantation of arsenic ions. In addition, since the profile of the impurity concentration becomes smooth as described above, the concentration of hot carriers at the end of the gate insulating film 5 can be controlled, so that deterioration of element characteristics can be suppressed.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 2a Groove 3 2nd low concentration diffusion region 4 1st low concentration diffusion region 5 Gate insulating film 6 Gate electrode 7 Side wall 8 High concentration diffusion region 9 Mask pattern 10 Element formation region 11 Low concentration diffusion region 100 Semiconductor device R1 First resistor R2 Second resistor

Claims (2)

Using a mask pattern formed on the first conductivity type semiconductor substrate as a mask, a pair of first low concentration diffusion regions of the second conductivity type and a second conductivity type deeper and higher in concentration than the first low concentration diffusion regions. Forming a pair of second low-concentration diffusion regions,
A gate insulating film is formed from one first low concentration diffusion region of the pair of first low concentration diffusion regions to the other first low concentration diffusion region, and a gate electrode is formed on the gate insulating film. Forming, and
Forming a pair of high-concentration diffusion regions of the second conductivity type having a higher concentration than the second low-concentration diffusion region using the gate electrode as a mask;
A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the first and second low-concentration diffusion regions, ion implantation is performed with an inclination angle of an ion beam with respect to the semiconductor substrate being 0 degree. .

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