JP2011187751A - Solid-state image sensing device, method for manufacturing the same, and electronic information equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a simple method to substantially reduce a parasitic capacity of an output unit, and to achieve dramatically higher sensitivity than that of conventional structures. <P>SOLUTION: A solid-state image sensing device has a space unit 15 which is formed by hollowing out an element isolation region between an FD unit 3 for extracting a signal existing at the termination portion of a charge transfer region 2 and a first stage transistor 6a of an output circuit 6 to which a contact 13 from the FD unit 3 is connected, and substantially reduced dielectric constant to approximately one-third by changing the conventional insulating film to an airspace. Therefore, parasitic capacitance between a gate electrode 11 at a portion from the FD unit 3 towards the output circuit 6 and a substrate is substantially reduced, thus significantly enhancing the sensitivity characteristics of the solid-state image sensing device 1 compared with that of conventional structures. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device such as a CCD (Charge Coupled Device) image sensor composed of a semiconductor element that photoelectrically converts image light from a subject and images the same, a manufacturing method thereof, and the solid-state imaging device as an image input device. The present invention relates to an electronic information device such as a digital camera such as a digital video camera and a digital still camera used for an imaging unit, an image input camera such as a surveillance camera, a scanner device, a facsimile device, a television phone device, and a camera-equipped mobile phone device.

  Conventional solid-state image sensors using semiconductor elements such as CCD image sensors are used in various applications such as digital cameras, scanner devices, digital copying machines, and facsimile machines. Further, along with the widespread use, not only requests for downsizing and cost reduction, but also higher functions and higher performance, such as an increase in the number of pixels and an improvement in light receiving sensitivity, are increasing.

  The CCD type solid-state imaging device includes a plurality of photoelectric conversion elements composed of photodiodes arranged vertically and horizontally on a light receiving surface, and a plurality of vertical CCDs respectively disposed along respective arrays in the vertical direction of these photoelectric conversion elements, A horizontal CCD disposed at the end of a plurality of vertical CCDs, and a signal output unit disposed at the end of the horizontal CCD for converting the signal charge from the horizontal CCD into a voltage signal for amplification output. .

  As the configuration of the signal output unit of such a CCD type solid-state imaging device, an FDA (Floating Diffusion Amplifier) type is generally widely used.

  FIG. 11 is a plan view showing a configuration example of a main part of a signal output unit of a conventional solid-state imaging device, and FIG. 12 is a cross-sectional view taken along line AA ′ of FIG. 11.

  As shown in FIGS. 11 and 12, the signal output unit 100 of the conventional solid-state imaging device accumulates the signal charge transferred from the charge transfer region 101, holds a potential corresponding to the signal charge, and then An FD unit 102 that repeats an operation to become a reset potential by a reset operation, a horizontal output transistor 103 that controls transfer of signal charges from the charge transfer region 101 to the FD unit 102, a reset transistor 104 that controls the reset operation, And an output circuit 105 that outputs an imaging signal by converting and amplifying the displacement of the signal charge of the FD unit 102 into a potential signal.

  The output circuit 105 is configured by a source follower circuit having a plurality of stages (2 to 3 stages), and the first stage transistor 105 a constituting the output circuit 105 is formed in the P-type well region 107 on the semiconductor substrate 106. Impurity diffusion region 108 and gate electrode 110 arranged on impurity diffusion region 108 with gate insulating film 109 interposed therebetween are included. The gate electrode 110 is embedded with an interlayer insulating film 111. The FD portion 102 and the gate electrode 110 are connected by a contact 112 formed on the interlayer insulating film 111, and a wiring 113 formed on the interlayer insulating film 111. The FD portion 102 and the gate electrode 110 are connected to each other. A field oxide film 114 is buried between the FD portion 102 and the impurity diffusion region 108.

  A horizontal output transistor 103 that controls the transfer of signal charges from the charge transfer region 101 to the FD unit 102 is disposed at the end of the charge transfer region 101. The horizontal output transistor 103 has a gate electrode 115 disposed via a gate insulating film 109. A reset transistor 104 is disposed on the opposite side of the FD portion 102 from the charge transfer region 101. The reset transistor 104 has a gate electrode 116 and a reset drain region 117 which are arranged with a gate insulating film 109 interposed therebetween.

  In the CCD solid-state imaging device 100 having such a configuration, signal charges generated by a plurality of photoelectric conversion elements are transferred to the charge transfer region 101 of the horizontal CCD by the plurality of vertical CCDs and transferred to the charge transfer region 101. The signal charges are further transferred by the charge transfer region 101 to the FD unit 102 via the horizontal output transistor gate 115 at the end thereof. As a result, the signal charge is accumulated in the FD unit 102. Then, the FD unit 102 holds a potential corresponding to the accumulated signal charge, and this potential is amplified by the output circuit 105 and is output from the output circuit 105 as an imaging signal. The signal charge converted into a voltage signal by the FD unit 102 is discharged from the FD unit 102 to the reset drain region 117 by the reset transistor gate 116.

  Here, the equation of dV = Qsig / Cp is established for the conversion of the charge voltage at the output section. Where dV is the amount of voltage change in the floating diffusion region (FD unit 102), Qsig is the amount of signal charge transferred to the floating diffusion region (FD unit 102), and Cp is the pickup capacitance. Specifically, the pickup capacitance Cp includes a capacitance (junction capacitance) between the floating diffusion region (FD portion 102) and the semiconductor substrate 106, and an output MOS transistor (connected to the floating diffusion region (FD portion 102)). The capacitance is between the gate electrode 110 side of the first stage transistor 105a) and the ground (P-type well 107 formed on the surface portion of the N-type semiconductor substrate 106).

  Therefore, in order to increase the conversion efficiency of the output portion, it is necessary to reduce the pickup capacitance Cp. To this end, the junction capacitance between the floating diffusion region (FD portion 102) and the semiconductor substrate 106 side must be reduced. Is effective.

  On the other hand, in Patent Document 1, a single element in which an output extraction unit that terminates a charge transfer unit and an MOS transistor in an output unit to which wiring from the output extraction unit is connected are surrounded by the same element isolation region. By forming in the formation region, the polysilicon layer that becomes the gate electrode of the MOS transistor does not need to be wired up and down the slope of the tapered portion at the end of the field oxide film. Parasitic capacitance can be reduced.

  In Patent Document 2, as shown in FIG. 13, the CCD solid-state imaging device 200 is low between the floating diffusion region 202 on the terminal side of the charge transfer region 201 and the channel stop regions 203 on both sides in the width direction. The parasitic capacitance is reduced by providing each of the siliconization regions 204 for capacitance. Reference numeral 205 denotes a reset drain.

Japanese Patent Laid-Open No. 3-116840 JP-A-11-297982

  However, in the above-described conventional configuration, the field oxide film 114 is embedded between the FD portion 102 and the impurity diffusion region 108 of the first stage transistor 105a constituting the output circuit 105 to isolate the element, so that the parasitic capacitance is large. There has been a problem that the voltage conversion efficiency is lowered and the sensitivity characteristic is deteriorated.

  In Patent Document 1, since the field oxide film is eliminated, the wiring length is shortened, but there is a problem that the parasitic capacitance is increased due to the thin film thickness.

  In Patent Document 2, there is a problem that the effect of reducing the parasitic capacitance is small because it is difficult to reduce the dielectric constant of the silicon oxide film despite the increase in the number of steps.

  The present invention has been made in view of the above-described conventional problems. A solid-state imaging device capable of significantly reducing the parasitic capacitance of the output unit by a simple method and significantly higher sensitivity than the conventional structure, and its manufacture It is an object of the present invention to provide a method and an electronic information device such as a camera-equipped mobile phone device using the solid-state imaging device as an image input device in an imaging unit.

  The solid-state imaging device of the present invention is a floating diffusion unit that sequentially accumulates each signal charge that has been transferred through a charge transfer region from a plurality of light receiving units that photoelectrically convert incident light from a subject and captures an image. And a signal output circuit that outputs an image pickup signal after being amplified according to a detection voltage detected by the floating diffusion portion, and a transistor constituting the signal output circuit connected to the floating diffusion portion. A part of the gate electrode has a space portion between the gate electrode and the semiconductor substrate, whereby the above object is achieved.

  Preferably, a space forming layer is provided to cover the space portion in the solid-state imaging device of the present invention.

  Further preferably, in the space forming layer in the solid-state imaging device of the present invention, the gate electrode is constituted by kenyoushiteiruka or a film other than the gate electrode.

  Further preferably, the space forming layer in the solid-state imaging device of the present invention has a plurality of openings for forming the space, and the plurality of openings are formed in a matrix in a plan view. And at least one of a plurality of quadrangles, a plurality of circles, and a slit shape formed in one or a plurality of rows.

  Still preferably, in the solid-state imaging device of the present invention, the space portion is formed as an element isolation insulating layer on the substrate surface portion between the floating diffusion portion and the impurity diffusion region of the transistor.

  Further preferably, the gate electrode of the transistor in the solid-state imaging device of the present invention is made of a polysilicon wiring material.

  Further preferably, the contact means electrically connected to the surface portion of the floating diffusion portion in the solid-state imaging device of the present invention is electrically connected to the end portion extending from the portion functioning as the gate electrode of the transistor. Has been.

  The solid-state imaging device manufacturing method of the present invention is a solid-state imaging device manufacturing method including the solid-state imaging device manufacturing process for manufacturing the solid-state imaging device of the present invention, and the solid-state imaging device manufacturing process is performed on the semiconductor substrate. A space forming layer is formed on the gate electrode, and a part of the gate electrode is formed thereon, or the gate electrode also serves as the space forming layer, and a plurality of openings are formed in the space forming layer or the gate electrode. The semiconductor substrate or the underlying layer formed on the semiconductor substrate is etched through the plurality of openings using the space forming layer or the gate electrode in which the plurality of openings are formed as a mask, and the semiconductor substrate The above-mentioned object is achieved by forming the space portion.

  The solid-state imaging device manufacturing process in the method for manufacturing a solid-state imaging device according to the present invention includes a step of depositing a film to be a space forming layer on a substrate in which an impurity diffusion region to be the floating diffusion portion is formed on the semiconductor substrate A step of forming a plurality of openings in a part of the film to be the space forming layer, and a part of the semiconductor substrate as a mask using the space forming layer in which the plurality of openings are formed as a mask. Forming a space portion by etching through the openings, and a space blocking layer depositing step of depositing a film serving as a space blocking layer for closing the plurality of openings on the space forming layer And after the formation of the gate insulating film, the space forming layer and the space blocking layer forming step of etching and removing the film to be the space forming layer and the space blocking layer in the region for forming the gate insulating film, A gate electrode forming step of forming a gate electrode on the gate insulating film and the space blocking layer; an interlayer insulating film forming step of forming an interlayer insulating film on the gate insulating film and the gate electrode; and And a contact means forming step of forming contact means that is electrically connected to the surface of the floating diffusion portion and is electrically connected to an end extending from the gate electrode.

Further preferably, the space forming layer in the method for manufacturing a solid-state imaging device of the present invention is made of a SiO ₂ material or a SiN material.

Further preferably, the space portion in the method of manufacturing a solid-state imaging device of the present invention is formed by isotropically etching a part of the semiconductor substrate through the opening with a gas containing SF ₆ gas in an ionized plasma state. .

  Further preferably, the size of the opening and the material of the space blocking layer are set so that the space blocking layer in the method for manufacturing a solid-state imaging device of the present invention does not enter the plurality of spaces.

  Further, in the solid-state imaging device manufacturing process of the solid-state imaging device manufacturing method of the present invention, after forming a field oxide film of the element isolation region on the semiconductor substrate, an impurity diffusion region to be the floating diffusion portion is formed, A step of depositing a gate insulating film on the substrate on which the field oxide film and the impurity diffusion region are formed; a gate electrode forming step of forming a gate electrode on a predetermined region of the gate insulating film; An opening forming step for forming an opening; and the gate electrode formed with the plurality of openings is used as a mask to etch a part of the field oxide film or the semiconductor substrate under the gate electrode to form the space Forming a space portion, forming an interlayer insulating film on the gate insulating film and the gate electrode, and forming the interlayer The edge membrane, and a contact unit forming step of forming a contact means for electrically connecting the end portion extending from the gate electrode as well as connected to the surface of the floating diffusion portion.

Preferably, the space portion in the method for manufacturing a solid-state imaging device according to the present invention is formed by isotropically etching a part of the semiconductor substrate through the opening with a gas containing SF ₄ gas in an ionized plasma state. .

  Further preferably, the space portion in the method for manufacturing a solid-state imaging device of the present invention is formed by isotropically etching the field oxide film by immersing the HF through the opening.

Further preferably, in the method for manufacturing a solid-state imaging device of the present invention, the field oxide film and the gate insulating film are made of a SiO ₂ material.

  The electronic information device of the present invention uses the solid-state imaging device of the present invention as an image input device in an imaging unit, and thereby achieves the above object.

  With the above configuration, the operation of the present invention will be described below.

  In the present invention, a floating diffusion unit that sequentially accumulates each signal charge transferred through a charge transfer region from a plurality of light-receiving units that photoelectrically convert incident light from a subject and picks up an image, and a floating detection unit. In a solid-state imaging device having a signal output circuit that outputs an imaging signal after amplification according to a detection voltage detected in the diffusion portion, a part of a gate electrode of a transistor that constitutes a signal output circuit connected to the floating diffusion portion A space is provided between the semiconductor substrate and the semiconductor substrate. A space portion is formed as an element isolation insulating layer in the substrate between the floating diffusion portion and the impurity diffusion region of the transistor.

  As a result, the element isolation region between the floating diffusion portion, which is the signal output extraction portion at the end of the charge transfer region, and the transistor of the signal output circuit to which the wiring from the output extraction portion is connected is hollowed out. Since the dielectric constant is greatly reduced to about 1/3 or more from the conventional insulating oxide film by air from the conventional insulating oxide film, the gate electrode and the substrate in the portion from the floating diffusion portion to the signal output circuit by a simple method It is possible to significantly reduce the parasitic capacitance between the two, and the sensitivity characteristics of the solid-state imaging device can be greatly enhanced as compared with the conventional structure.

  As described above, according to the present invention, since a part of the gate electrode of the transistor constituting the signal output circuit connected to the floating diffusion portion has a space portion between the semiconductor substrate and the conventional insulating oxide By replacing the membrane with an air layer and reducing the dielectric constant to about 1/3, the parasitic capacitance in the floating diffusion region can be greatly reduced, and the conversion efficiency of the signal output circuit is increased. The sensitivity characteristics of the solid-state imaging device can be remarkably increased.

It is a top view which shows the principal part structural example of the signal output part of the solid-state image sensor in Embodiment 1 of this invention. FIG. 2 is a sectional view taken along line BB ′ in FIG. 1. (A)-(c) is a top view which shows typically the some opening part formed in the space formation layer on the cavity part of FIG. 2, respectively. (A)-(c) is a longitudinal cross-sectional view which shows typically each process (the 1) of the manufacturing method of the solid-state image sensor of FIG. 1 and FIG. 2, respectively. (A)-(c) is a longitudinal cross-sectional view which shows typically each process (the 2) of the manufacturing method of the solid-state image sensor of FIG. 1 and FIG. It is a top view which shows the principal part structural example of the signal output part of the solid-state image sensor in Embodiment 2 of this invention. It is CC 'sectional view taken on the line of FIG. (A) And (b) is a longitudinal cross-sectional view which shows typically each process (the 1) of the manufacturing method of the solid-state image sensor of FIG. 6 and FIG. 7, respectively. (A)-(c) is a longitudinal cross-sectional view which shows typically each process (the 2) of the manufacturing method of the solid-state image sensor of FIG. 6 and FIG. 7, respectively. It is a block diagram which shows the schematic structural example of the electronic information apparatus which used the solid-state image sensor of any one of Embodiment 1, 2 of this invention for the imaging part as Embodiment 3 of this invention. It is a top view which shows the principal part structural example of the signal output part of the conventional solid-state image sensor. It is AA 'line sectional drawing of FIG. It is a top view which shows the principal part structural example of the signal output part of the conventional solid-state image sensor currently disclosed by patent document 2. FIG.

  Embodiments 1 and 2 of the solid-state imaging device and manufacturing method thereof according to the present invention, and a mobile phone device with a camera, for example, using any one of Embodiments 1 and 2 of the solid-state imaging device as an image input device in an imaging unit A third embodiment of the electronic information device will be described in detail with reference to the drawings. In addition, each thickness, length, etc. of the structural member in each figure are not limited to the structure to illustrate from a viewpoint on drawing preparation.

(Embodiment 1)
FIG. 1 is a plan view illustrating an exemplary configuration of a main part of a signal output unit of a solid-state imaging device according to Embodiment 1 of the present invention, and FIG. 2 is a cross-sectional view taken along line BB ′ of FIG.

  1 and 2, the solid-state imaging device 1 according to the first embodiment accumulates signal charges transferred from the charge transfer region 2, holds a potential corresponding to the signal charges, and then performs a reset operation. The floating diffusion section 3 (FD section 3), which is a charge detection region that repeats the operation to become the reset potential, the horizontal output transistor 4 that controls the transfer of signal charges from the charge transfer region 2 to the FD section 3, and the reset operation thereof And an output circuit 6 that outputs an imaging signal by converting the displacement of the signal charge of the FD unit 3 into a potential signal and amplifying it.

  The output circuit 6 is composed of a plurality of (two to three stages) source follower circuits, and amplifies and outputs an image pickup signal corresponding to the potential fluctuation of the signal charge of the FD section 3. The first stage transistor 6a constituting the output circuit 6 includes an impurity diffusion region 9 formed in a P-type well region 8 on a semiconductor substrate 7, and a gate disposed on the impurity diffusion region 9 via a gate insulating film 10. And an electrode 11. The gate electrode 11 is embedded with an interlayer insulating film 12, and the FD portion 3 and the gate electrode 11 are connected and formed on the interlayer insulating film 12 by a contact 13 as a contact means formed on the interlayer insulating film 12. The FD portion 3 and the gate electrode 11 are connected to the formed wiring 14. In other words, the contact 13 electrically connected to the surface portion of the FD portion 3 is electrically connected to the end portion extending from the portion functioning as the gate electrode 11 of the first stage transistor 6.

  A low dielectric constant cavity (or space) 15 is formed between the substrate of the FD portion 3 and the impurity diffusion region 9 instead of the thick film of the field oxide film. That is, a cavity in which the element isolation region between the FD portion 3 as the signal output extraction portion at the terminal end of the charge transfer region 2 and the transistor of the signal output circuit to which the wiring from the FD portion 3 is connected is hollowed out A part (or space part) 15 is formed.

  A gate 11 of the output first stage transistor 6 a is connected to the impurity diffusion layer of the FD portion 3 through a contact 13. The cavity 15 is provided under the gate electrode 11 and on the substrate between the FD portion 3 for accumulating signal charges and the impurity diffusion region 9 of the output first stage transistor 6a. A cavity 15 is formed under the gate electrode 11 of the output first stage transistor 6a in a state of being blocked by the space blocking layer 21 and further via a space forming layer 22 therebelow. A plurality of openings 23 are formed in the space forming layer 22 on the cavity 15.

  As for the arrangement and shape of the plurality of openings 23, first, as shown in FIG. 3A, the plurality of openings 23a are quadrangular and are arranged in a matrix. Next, as shown in FIG.3 (b), as the some opening part 23b, opening shape is circular and this is multiply arranged by the matrix form. Further, as shown in FIG. 3 (c), a plurality of openings 23c having a slit shape and a plurality of openings 23c are arranged.

  A horizontal output transistor 4 that controls the transfer of signal charges from the charge transfer region 2 to the FD unit 3 is disposed at the end of the charge transfer region 2. The horizontal output transistor 4 has a gate electrode 16 disposed through a gate insulating film 10. A reset transistor 5 is disposed on the opposite side of the charge transfer region 2 with respect to the FD portion 3. The reset transistor 5 includes a gate electrode 17 and a reset drain region 18 that are disposed with the gate insulating film 10 interposed therebetween.

  With the above configuration, signal charges generated in the plurality of photoelectric conversion elements are transferred to the charge transfer region 2 of the horizontal CCD by the plurality of vertical CCDs, and the signal charge transferred to the charge transfer region 2 is further transferred to the charge transfer region. 2, charges are transferred to the FD unit 3 through the horizontal output transistor gate 16 at the end. As a result, the signal charge is accumulated in the FD unit 3.

  Next, the FD section 3 holds a potential corresponding to the accumulated signal charge, and this potential is transmitted from the FD section 3 to the gate electrode 11 of the first-stage transistor 6a through the contact 13, and the first-stage transistor 6a is connected to the output circuit 6 by the output circuit 6. Amplified and output from the output circuit 6 as an imaging signal.

  Thereafter, the signal charge converted into a voltage signal by the FD unit 3 is discharged from the FD unit 3 to the reset drain region 18 by the gate 17 of the reset transistor 5, and the potential of the FD unit 3 is reset to a predetermined potential.

  In the first embodiment, the semiconductor substrate 7 is a Si substrate. However, the semiconductor substrate 7 is not limited to this, and various substrates that can be used as the semiconductor substrate 7 such as a GaAs substrate can be used.

  Here, a method for manufacturing the solid-state imaging device 1 of the first embodiment having the above-described configuration will be described with reference to FIGS. 4 and 5.

  4 (a) to 4 (c) and FIGS. 5 (a) to 5 (c) are longitudinal sectional views schematically showing the respective steps of the method for manufacturing the solid-state imaging device 1 of FIGS. It is.

First, as shown in FIG. 4A, after forming a P-type well region 8 on a semiconductor substrate 7, a field oxide film 19 as an element isolation region is formed. The field oxide film 19 may be a thermal oxide film formed by a LOCOS method or a CVD oxide film (SiO ₂ film) formed by using an STI method (Shallow Trench Isolation). Thereafter, an N-type impurity diffusion region 3a to be a floating diffusion portion (FD portion 3) for accumulating signal charges is formed. Subsequently, for example, a SiO ₂ film 22a to be the first space forming layer 22 is formed by depositing a film thickness of 2000 to 4000 angstroms.

Next, as shown in FIG. 4B, a part of, for example, the SiO ₂ film 22a to be the first space forming layer 22 is formed on the photoresist 24 having a plurality of openings 23 as a mask, with a thickness of 0.1 to 0.1. A plurality of slit-like openings 23c having a width of 0.3 μm are formed to form the SiO ₂ film 22b.

Thereafter, as shown in FIG. 4C, the photoresist 24 is removed, and a plurality of slit-shaped openings are formed using the first space forming layer 22b in which the plurality of slit-shaped openings 23c are formed as a mask. Through the surface 23c, the surface portion of the P-type well region 8 and the end portion of the N-type impurity diffusion region 3a of the semiconductor substrate 7 are etched to form the cavity 15 (or space). This cavity 15 (or space) is formed by isotropically etching the silicon material of the semiconductor substrate 7 in an ionized plasma state with SF ₆ gas. The position of the cavity portion 15 (or space portion) is a substrate between the FD portion 3 and the impurity diffusion region 9, and is a position below the gate electrode 11 of the first-stage transistor 6a. The element is separated by the cavity (or space) 15.

Furthermore, depositing a SiO ₂ film serving as the spatial occlusion layer 21 having a thickness of 2000 to 5000 angstroms in order to close the opening 23c of the SiO ₂ film 22b. In this case, a film with poor coverage is selected as the deposited film, and the entry of the deposited film into the cavity 15 (or the space) is suppressed. In other words, the opening 23c needs to have such a size that the SiO ₂ film to be the space blocking layer 21 passes through the opening 23c and does not enter the cavity 15 (or the space).

Subsequently, as shown in FIG. 5A, the first space forming layer 22b and the SiO ₂ film to be the space blocking layer 21 in the region where the gate insulating film for forming the transistor is formed are masked with the photoresist 25. Etching is removed. In order to suppress the level difference, the etching in this case is preferably isotropic etching.

  Next, as shown in FIG. 5B, the photoresist 25 is removed, and a gate insulating film 10 having a thickness of 100 to 500 angstroms is formed by oxidation or deposition. Thereafter, a polysilicon film having a thickness of 1000 to 5000 angstroms is deposited thereon, and the gate electrode 11 of the first-stage transistor 6a in the output circuit 6 is formed by performing polysilicon etching into a desired shape using a photolithography technique. can do.

  Subsequently, as shown in FIG. 5C, an interlayer insulating film 12 made of a BPSG film covering the substrate on which the gate insulating film 10 and the gate electrode 11 of the first stage transistor 6a are formed is formed, and this is reflowed. To process. Thereafter, a contact hole reaching the surface of the FD portion 3 is formed in the interlayer insulating film 12 by a reactive ion etching (RIE) method or the like, and a metal material such as tungsten or aluminum is formed so as to fill the contact hole. .

  Finally, as shown in FIG. 5C, unnecessary portions of the deposited metal material are removed by etching, so that the gate electrode 11 of the first-stage transistor 6 and the N-type impurity diffusion region (FD portion) are removed. A wiring 14 made of a metal material that is electrically connected to 3) via a contact 13 is formed.

  That is, the manufacturing method of the solid-state imaging device 1 according to the first embodiment includes a step of depositing a film 22a to be the space forming layer 22 on the substrate in which the impurity diffusion region 9 to be the FD portion 3 is formed on the semiconductor substrate 7. An opening forming step of forming a plurality of openings 23 in a part of the film 22a to be the space forming layer 22, and a part of the semiconductor substrate 7 as a mask using the space forming layer 22 in which the plurality of openings 23 are formed as a mask. A space forming step of etching through the plurality of openings 23 to form the space 15, and a space blocking for depositing a film to be the space blocking layer 21 for closing the plurality of openings 23 on the space forming layer 33. After forming the gate insulating film 10, the layer deposition step, the space forming layer 22 and the space blocking layer forming step of etching and removing the film that becomes the space forming layer 22 and the space blocking layer 21 in the region where the gate insulating film 10 is formed, Game A gate electrode forming step of forming the gate electrode 11 on the insulating film 10 and the space blocking layer 21; an interlayer insulating film forming step of forming the interlayer insulating film 12 on the gate insulating film 10 and the gate electrode 11; And a contact means forming step of forming a contact 13 which is electrically connected to the surface of the FD portion 3 and electrically connected to the gate electrode 11.

  As described above, according to the first embodiment, the first-stage transistor 6a of the output circuit 6 to which the FD unit 3 as the signal output extraction unit at the terminal end of the charge transfer region 2 and the contact 13 from the FD unit 3 are connected. Since the space portion 15 in which the element isolation region is made hollow is formed, the dielectric constant is greatly reduced to about 1/3 from the conventional insulating oxide film to the air layer. 3 can greatly reduce the parasitic capacitance with the substrate between the gate electrode 11 in the portion from 3 to the output circuit 6, and the sensitivity characteristics of the solid-state imaging device 1 can be made much higher than the conventional structure. it can.

(Embodiment 2)
FIG. 6 is a plan view showing a configuration example of a main part of a signal output unit of a solid-state imaging device according to Embodiment 2 of the present invention, and FIG. 7 is a cross-sectional view taken along line CC ′ of FIG. 6 and 7, members having the same functions and effects as those of the constituent members used in FIGS. 1 and 2 are described with the same reference numerals.

  6 and 7, the solid-state imaging device 1A of the second embodiment includes an FD unit 3 that accumulates signal charges transferred from the charge transfer region 2, a horizontal output transistor 4 that is in front of the FD unit 3, It has a reset transistor 5 that resets the potential of the FD unit 3 to a predetermined potential, and an output circuit 6 that amplifies the displacement of the FD unit 3 as a control voltage and outputs an imaging signal.

  The first stage transistor 6 a of the plurality of stages constituting the output circuit 6 includes an impurity diffusion region 9 formed in a P-type well region 8 on a semiconductor substrate 7, and a gate insulating film 10 on the impurity diffusion region 9. And a gate electrode 11A arranged therebetween. The gate electrode 11 </ b> A is embedded with the interlayer insulating film 12, and the FD portion 3 and the gate electrode 11 </ b> A are connected by the contact 13 formed in the interlayer insulating film 12 and the wiring formed on the interlayer insulating film 12. 14 is connected to the FD section 3 and the gate electrode 11A. A low dielectric constant cavity (or space) 15 is formed between the substrate of the FD portion 3 and the impurity diffusion region 9 instead of the thick film of the field oxide film. In this case, the gate electrode 11A covers the cavity (or space) 15 and also serves as a space forming layer. Further, the interlayer insulating film 12 covering the gate electrode 11 </ b> A also functions as the space blocking layer 21. These greatly simplify the manufacturing process.

  The cavity 15 is below the row of openings 23d formed in the gate electrode 11A, and the substrate surface between the FD portion 3 for accumulating signal charges and the impurity diffusion region 9 of the output first stage transistor 6a. Provided in the department.

  Here, a method for manufacturing the solid-state imaging device 1 of the first embodiment having the above-described configuration will be described with reference to FIGS. 4 and 5.

  8 (a), FIG. 8 (b), and FIG. 9 (a) to FIG. 9 (c) are longitudinal sections schematically showing respective steps of the manufacturing method of the solid-state imaging device 1A of FIG. 6 and FIG. FIG.

First, as shown in FIG. 8A, after forming a P-type well region 8 on a semiconductor substrate 7, a field oxide film 19 as an element isolation region is formed. The field oxide film 19 may be a thermal oxide film formed by a LOCOS method or a CVD oxide film (SiO ₂ film) formed by using an STI method (Shallow Trench Isolation). Thereafter, an N-type impurity diffusion region 3 that forms a floating diffusion portion (FD portion 3) for accumulating signal charges is formed. Subsequently, a gate insulating film 10 having a thickness of 100 to 500 angstroms is formed by oxidation or deposition.

  Next, as shown in FIG. 8B, a polysilicon film having a thickness of 1000 to 5000 angstroms is deposited on the gate insulating film 10, and the photoresist 26 is used as a mask by a photolithography technique. By etching the silicon film, the outer shape of the gate electrode 11 of the first-stage transistor 6a is formed in a desired shape.

  Subsequently, as shown in FIG. 9A, a part of the gate electrode 11 of the first-stage transistor 6a is removed by etching using the photoresist 27 patterned into a predetermined shape using a photolithography technique as a mask. A plurality of openings 23d having a width of 1 to 0.3 μm are formed in a line. As described above, the gate electrode 11 of the first-stage transistor 6a is directly patterned to form the gate electrode 11A, which can also serve as the second space forming layer.

Further, the photoresist 27 is removed and, as shown in FIG. 9A, the field oxide film 19 under the region of the plurality of openings 23d in a row is etched away using the gate electrode 11A of the first stage transistor 6a as a mask. Thus, the cavity 15 (or space) is formed. This cavity 15 (or space) is formed by isotropic etching of SiO ₂ of silicon material by immersion in HF. The position of the cavity portion 15 (or space portion) is a substrate between the FD portion 3 and the impurity diffusion region 9, and is a position below the gate electrode 11A of the first-stage transistor 6a. The element is separated by the cavity (or space) 15.

  Thereafter, as shown in FIG. 9B, an interlayer insulating film 12 made of a BPSG film or the like is formed so as to cover the substrate on which the gate insulating film 10 and the gate electrode 11A of the first stage transistor 6a are formed. Reflow process. The interlayer insulating film 12 blocks the plurality of openings 23d in a row from above while maintaining the space of the cavity (or space) 15.

  Further, a contact hole reaching the surface of the FD portion 3 is formed in the interlayer insulating film 12 by a reactive ion etching (RIE) method or the like, and a metal material such as tungsten or aluminum is formed so as to fill the contact hole. .

  Finally, as shown in FIG. 9B, unnecessary portions of the deposited metal material are removed by etching, whereby the gate electrode 11A of the first-stage transistor 6 and the N-type impurity diffusion region (FD portion) are removed. A wiring 14 made of a metal material that is electrically connected to 3) via a contact 13 is formed.

  That is, in the method of manufacturing the solid-state imaging device 1A of the second embodiment, after forming the field oxide film 19 of the element isolation region on the semiconductor substrate 7, the impurity diffusion region to be the FD portion 3 is formed, and the field oxide film 19 is formed. And a step of depositing the gate insulating film 10 on the substrate on which the impurity diffusion region to be the FD portion 3 is formed, a gate electrode forming step of forming the gate electrode 11 on the predetermined region of the gate insulating film 10, and the gate electrode 11 The step of forming a plurality of openings 23d in the gate electrode 11A and the field oxide film 19 (under the regions of the plurality of openings 23d of the gate electrode 11A using the gate electrode 11A formed with the plurality of openings 23d as a mask) In the absence of the field oxide film 19, a part of the semiconductor substrate 7 is etched to form the space part 15A, and the gate insulating film 10 and the gate insulating film 10 An interlayer insulating film forming step of forming an interlayer insulating film 12 on the first electrode 11A, and a contact means forming step of forming a contact 13 connected to the surface portion of the FD portion 3 and to the gate electrode 11A on the interlayer insulating film 12 And have.

  As described above, according to the second embodiment, in addition to the effects of the first embodiment, since the gate electrode 11A of the first-stage transistor 6 is also used as a space forming layer, the lower portion of the plurality of openings 23d in one row of the gate electrode 11A is used. Only the cavity (or space) 15A can be selectively formed, and the manufacturing process can be greatly simplified.

  In the second embodiment, as shown in FIG. 9A, all of the field oxide film 19 under the region of the plurality of openings 23d in a row is removed by etching using the gate electrode 11A of the first-stage transistor 6a as a mask. Thus, the cavity 15 (or space) is formed. However, the present invention is not limited to this, and as shown in FIG. 9C, a region of a plurality of openings 23d in a row using the gate electrode 11A of the first-stage transistor 6a as a mask. Even if the underlying field oxide film 19 is etched to leave about 1/2 or 1/3, the parasitic capacitance between the gate electrode 11 and the substrate can be greatly reduced by the space portion 15B. In addition, the sensitivity characteristics of the solid-state imaging device 1 can be significantly improved. In this case, the etching time is shortened by the amount of the field oxide film 19A remaining, and the field oxide film 19A to the extent that exists between the FD portion 3 and the impurity diffusion region 9 of the first stage transistor 6a remains. As a result, the element isolation layer function is enhanced.

(Embodiment 3)
FIG. 10 is a block diagram illustrating a schematic configuration example of an electronic information device using the solid-state imaging device according to any of Embodiments 1 and 2 of the present invention as an imaging unit as Embodiment 3 of the present invention.

  In FIG. 10, an electronic information device 90 according to the third embodiment includes a solid-state imaging device 91 that obtains a color image signal by performing predetermined signal processing on the imaging signal from the solid-state imaging device 1 or 1A according to the first and second embodiments. The memory unit 92 such as a recording medium that can record data after performing predetermined signal processing (for example, data compression processing) on the color image signal from the solid-state imaging device 91 and the color image from the solid-state imaging device 91 A display means 93 such as a liquid crystal display device that can display a signal on a display screen such as a liquid crystal display screen after processing the signal for a predetermined signal for display, and a color image signal from the solid-state image pickup device 91 for communication The communication means 94 such as a transmission / reception device that can perform communication processing after signal processing and the color image signal from the solid-state imaging device 91 are subjected to predetermined print signal processing for printing. And an image output means 95 such as a printer which allows printing later. The electronic information device 90 is not limited to this, but in addition to the solid-state imaging device 91, at least one of a memory unit 92, a display unit 93, a communication unit 94, and an image output unit 95 such as a printer. You may have.

  As described above, the electronic information device 90 includes, for example, a digital camera such as a digital video camera and a digital still camera, an in-vehicle camera such as a surveillance camera, a door phone camera, and an in-vehicle rear surveillance camera, and a video phone camera. An electronic device having an image input device such as an image input camera, a scanner device, a facsimile device, a camera-equipped mobile phone device, and a portable terminal device (PDA) is conceivable.

  Therefore, according to the third embodiment, on the basis of the color image signal from the solid-state imaging device 91, the image is displayed on the display screen, or the image is output by the image output means 95 on the paper. (Printing), communicating this as communication data in a wired or wireless manner, performing a predetermined data compression process in the memory unit 92 and storing it in a good manner, or performing various data processings satisfactorily Can do.

  Although not particularly described in the first embodiment, the solid-state image sensor manufacturing process for manufacturing the space portion 23 as a method for manufacturing the solid-state image sensor including the solid-state image sensor manufacturing process for manufacturing the solid-state image sensor 1 or 1A. However, the space forming layer 22 is formed on the semiconductor substrate 7 and a part of the gate electrode 11 is formed thereon, or the gate electrode 11 also serves as the space forming layer 22 like the gate electrode 11A. A plurality of openings 23 are formed in the space forming layer 22 or the gate electrode 11A, and the semiconductor substrate 7 or the semiconductor substrate 7 through the plurality of openings 23 using the space forming layer 22 or the gate electrode 11A in which the plurality of openings 23 are formed as a mask. Even when the space layer 23 is formed in the semiconductor substrate 7 by partially or entirely etching the base layer (field oxide film 19) formed on the semiconductor substrate 7, If a part of the gate electrode 11 or 11A of the first stage transistor 6a constituting the signal output circuit 6 connected to the D portion 3 has the space portion 23 between the semiconductor substrate 7, the output is performed in a simple manner. The parasitic capacitance of the portion (FD portion 3 and the signal output circuit 6 connected thereto) can be greatly reduced, and the object of the present invention can be achieved which can make the sensitivity much higher than that of the conventional structure.

  As described above, the present invention has been exemplified using the preferred first to third embodiments of the present invention, but the present invention should not be construed as being limited to the first to third embodiments. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments 1 to 3 of the present invention. Patents, patent applications, and documents cited in this specification should be incorporated by reference in their entirety, as if the contents themselves were specifically described in the present specification. Understood.

  The present invention relates to a solid-state imaging device such as a CCD (charge coupled device) image sensor composed of a semiconductor device that photoelectrically converts image light from a subject and images the same, a manufacturing method thereof, and the solid-state imaging device as an image input device. Fields of electronic information equipment such as digital video cameras and digital still cameras used in the imaging unit, image input cameras such as surveillance cameras, scanner devices, facsimile devices, television telephone devices, camera-equipped mobile phone devices, etc. In this case, a part of the gate electrode of the transistor constituting the signal output circuit connected to the floating diffusion portion has a space portion with the semiconductor substrate, so that the conventional insulating oxide film is replaced with an air layer. By significantly reducing the dielectric constant to about 1/3 Thus, the parasitic capacitance parasitic to the floating diffusion region can be greatly reduced, the conversion efficiency of the signal output circuit can be increased, and the sensitivity characteristics of the solid-state imaging device can be remarkably increased.

DESCRIPTION OF SYMBOLS 1, 1A Solid-state image sensor 2 Charge transfer area 3 Floating diffusion part (FD part)
4 Horizontal output transistor 5 Reset transistor 6 Output circuit 6a First stage transistor 7 Semiconductor substrate 8 P-type well region 9 Impurity diffusion region 10 Gate insulating film 11, 11A, 16, 17 Gate electrode 12 Interlayer insulating film 13 Contact 14 Wiring 15, 15A Cavity Part (or space part)
DESCRIPTION OF SYMBOLS 18 Reset drain area | region 19 Field oxide film 21 Space blockage layer 22 Space formation layer 23, 23a, 23b, 23c, 23d Opening 90 Electronic information equipment 91 Solid-state imaging device 92 Memory part 93 Display means 94 Communication means 95 Image output means

Claims (17)

A floating diffusion unit that sequentially accumulates each signal charge transferred through a charge transfer region from a plurality of light receiving units that photoelectrically convert incident light from a subject and picks up an image, and a detection by the floating diffusion unit In a solid-state imaging device having a signal output circuit that amplifies according to the detected voltage and outputs an imaging signal,
A solid-state imaging device in which a part of a gate electrode of a transistor constituting the signal output circuit connected to the floating diffusion portion has a space portion between the semiconductor substrate.   The solid-state imaging device according to claim 1, further comprising a space forming layer that covers the space portion.   3. The solid-state imaging device according to claim 2, wherein the space forming layer is shared by the gate electrode or is formed of a film other than the gate electrode.   4. The solid-state imaging device according to claim 3, wherein the space forming layer includes a plurality of openings for forming the space, and the openings are formed in a matrix in a plan view. A solid-state imaging device having at least one of a plurality of squares, a plurality of circles, and a slit shape formed in one or a plurality of rows.   The solid-state imaging device according to claim 1, wherein the space portion is formed as an element isolation insulating layer on a substrate surface portion between the floating diffusion portion and the impurity diffusion region of the transistor.   2. The solid-state image pickup device according to claim 1, wherein the gate electrode of the transistor is made of a polysilicon wiring material.   2. The solid-state imaging device according to claim 1, wherein the contact means electrically connected to the surface portion of the floating diffusion portion is electrically connected to an end portion extending from a portion functioning as a gate electrode of the transistor. Solid-state imaging device. A method for manufacturing a solid-state imaging device comprising a solid-state imaging device manufacturing process for manufacturing the solid-state imaging device according to claim 1,
The solid-state imaging device manufacturing process includes:
A space forming layer is formed on the semiconductor substrate and a part of the gate electrode is formed thereon, or the gate electrode also serves as the space forming layer;
A plurality of openings are formed in the space forming layer or the gate electrode, and the semiconductor substrate or the semiconductor substrate is formed through the plurality of openings using the space forming layer or the gate electrode in which the plurality of openings are formed as a mask. A method of manufacturing a solid-state imaging device, wherein the space layer is formed in the semiconductor substrate by etching the underlying layer. It is a manufacturing method of the solid-state image sensing device according to claim 8,
The solid-state imaging device manufacturing process includes:
Depositing a film to be a space forming layer on a substrate in which an impurity diffusion region to be the floating diffusion portion is formed on the semiconductor substrate;
An opening forming step of forming a plurality of openings in a part of the film to be the space forming layer;
Using the space forming layer in which the plurality of openings are formed as a mask, a space forming step of forming a part of the semiconductor substrate by etching a part of the semiconductor substrate through the plurality of openings;
A space blocking layer depositing step of depositing a film to be a space blocking layer for closing the plurality of openings on the space forming layer;
A space forming layer and a space blocking layer forming step of etching and removing the space forming layer in the region for forming the gate insulating film and the film to be the space blocking layer;
A gate electrode forming step of forming a gate electrode on the gate insulating film and the space blocking layer after forming the gate insulating film;
An interlayer insulating film forming step of forming an interlayer insulating film on the gate insulating film and the gate electrode;
A solid-state imaging device having a contact means forming step for forming contact means electrically connected to the surface of the floating diffusion portion and electrically connected to an end portion extending from the gate electrode on the interlayer insulating film Manufacturing method. 10. The method for manufacturing a solid-state imaging device according to claim 9, wherein the space forming layer is made of a SiO ₂ material or a SiN material. 10. The method of manufacturing a solid-state imaging device according to claim 9, wherein the space portion is formed by isotropically etching a part of the semiconductor substrate through the opening with a gas containing SF ₆ gas in an ionized plasma state. Manufacturing method of solid-state image sensor.   The method for manufacturing a solid-state imaging device according to claim 9, wherein the size of the opening and the material of the space blocking layer are set so that the space blocking layer does not enter the plurality of spaces. . It is a manufacturing method of the solid-state image sensing device according to claim 8,
The solid-state imaging device manufacturing process includes:
After forming a field oxide film of an element isolation region on the semiconductor substrate, an impurity diffusion region to be the floating diffusion portion is formed, and a gate insulating film is formed on the substrate on which the field oxide film and the impurity diffusion region are formed. Depositing, and
Forming a gate electrode on a predetermined region of the gate insulating film; and
An opening forming step of forming a plurality of openings in the gate electrode;
Using the gate electrode in which the plurality of openings are formed as a mask, etching the field oxide film or a part of the semiconductor substrate under the gate electrode to form the space portion; and
An interlayer insulating film forming step of forming an interlayer insulating film on the gate insulating film and the gate electrode;
A solid-state imaging device manufacturing method comprising: a contact means forming step for forming contact means connected to the surface of the floating diffusion portion and electrically connected to an end extending from the gate electrode on the interlayer insulating film .   14. The method for manufacturing a solid-state imaging device according to claim 13, wherein the space is formed by isotropically etching the field oxide film by immersing the space in HF through the opening. In the method for manufacturing a solid-state imaging device according to claim 13, the space through the opening, formed by isotropically etching a portion of said semiconductor substrate a gas containing SF ₄ gas ionized plasma state Manufacturing method of solid-state image sensor. In the method for manufacturing a solid-state imaging device according to claim 13, wherein the field oxide film and the gate insulating film manufacturing method of the solid-state imaging device and a SiO ₂ material.   The electronic information apparatus which used the solid-state image sensor in any one of Claims 1-7 as an image input device for the imaging part.

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