JP2011182245A - Solid-state imaging element, method of driving the same, and camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element, a method of driving the element which can reduce only a smear component while maintaining a total handling electric charge quantity and can improve an image quality by relatively reducing a smear signal, and to provide a camera using the element. <P>SOLUTION: The solid-state imaging element includes: a plurality of sensors 11 of a photoelectric conversion function arranged in a matrix; a plurality of vertical transmitting parts 12 arranged in association with columns of the sensors for transmitting signal electric charges read out from the sensors in a row array direction; a horizontal transmitting part 15 for transmitting the signal electric charges transmitted from the vertical transmitting parts in a column array direction; a charge discharging part 40 formed in the units of a plurality of columns of the vertical transmitting parts for selectively discharging the signal electric charges from the vertical transmitting parts to the horizontal transmitting parts; and a drive system for exerting control to change a saturation signal quantity of an image when the signal electric charges are discharged by the charge discharging part. Electrode pitches of the horizontal transmitting parts include a plurality of vertical transmitting part lines. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device, a driving method thereof, and a camera, and in particular, a solid-state imaging using a CCD (Charge Coupled Device) type solid-state imaging device (hereinafter referred to as a CCD imaging device) having an overflow drain (OFD) structure. The present invention relates to an element, a driving method thereof, and a camera.

Taking an n-type semiconductor substrate as an example, the imaging region of the CCD solid-state imaging device is formed with a p-type well region on the n-type semiconductor substrate, and an n-type photoelectric conversion unit, that is, a light receiving unit on the surface of the well region Is formed.
The imaging region is configured by arranging the light receiving parts in a plurality of matrix shapes.

  In such a CCD solid-state imaging device, an allowable amount of signal charge e accumulated in the light receiving portion upon incidence of light, that is, a charge amount handled by the light receiving portion will be described with reference to FIG.

FIGS. 1A and 1B are diagrams showing a potential distribution of a light receiving unit that performs photoelectric conversion of a solid-state imaging device having a general vertical overflow drain structure.
FIG. 1A is a potential distribution diagram before the substrate bias voltage Vsub is adjusted, and FIG. 1B is a potential distribution diagram after the substrate bias voltage Vsub is adjusted.

As shown in the potential distribution diagram of FIG. 1, the amount of charge handled by the so-called light receiving portion is determined by the height of the potential barrier φa of the overflow barrier OFB formed of the p-type well region.
That is, when the signal charge e accumulated in the light receiving unit exceeds the handling charge amount, the excess charge exceeds the potential barrier φa of the overflow barrier and overflows to the n-type substrate constituting the overflow drain OFD. Thrown away.
Note that the symbol a in FIG. 1 indicates an oxide film on the light receiving portion.

The amount of charge handled by the light receiving unit, that is, the height of the potential barrier φa of the overflow barrier OFB is controlled by a bias voltage applied to the substrate serving as the overflow drain, that is, a so-called substrate bias voltage Vsub.
However, in this structure, the height of the potential barrier φ of the overflow barrier OFB varies from chip to chip as shown by a broken line in FIG.
In the solid-state imaging device, the maximum amount of signal charge (saturation signal amount) accumulated in the light receiving unit needs to be equal to or greater than a certain specification value for quality control.
For this reason, the substrate bias voltage Vsub of a certain chip is set to the substrate bias voltage Vsub so that all the light receiving parts in the chip have a saturation signal amount satisfying the above specifications.

For example, Patent Documents 1 and 2 disclose solid-state imaging devices in which an overflow drain, which is a region for discharging signal charges, is formed in the vicinity of a vertical transfer unit and a horizontal transfer unit.
For example, Patent Document 3 discloses a technique related to a substrate bias circuit.

  By the way, moving image shooting of a digital still camera using a CCD solid-state imaging device and a major drawback of a digital movie camera include smear during high-luminance subject imaging.

2A and 2B are diagrams for explaining smear. FIG. 2A shows a smear image example, and FIG. 2B shows a simplified cross section of a pixel in the horizontal direction.
In FIG. 2, 1 is a high-luminance object, 2 is a light receiving region (photodiode portion), 3 is a vertical transfer register, 4 is a transfer electrode, 5 is an oxide film, and 6 is a light shielding film. Yes.

As shown in FIG. 2, such as the sun or a car headlight, when a high-luminance subject 1 is imaged, light cannot be captured by the original light receiving region (photodiode portion) 2.
As a result, the streak of light in the vertical direction of the screen generated by light overcoming the potential area or directly leaking into the vertical transfer register 3 is smear.
This is determined by the ratio of the background sensitivity signal to the smear signal (smear = smear signal / sensitivity signal).

As an example for improving this smear, the following two methods can be considered.
The first method lowers the gain at the subsequent stage of the CCD such as a signal processing circuit, reduces the smear signal, and further reduces the smear signal while maintaining the sensitivity signal by combining the electronic shutter speed reduction. It is a method to improve.
The second method increases the saturation signal amount of a single pixel to suppress the adverse effect of lowering the dynamic range (D range) of the camera, while lowering the gain at the subsequent stage of the CCD, such as a signal processing circuit, and further Combine shutter speed reduction. The second method is a method of improving the image quality by relatively reducing the smear signal while maintaining the sensitivity signal.

JP 2008-193050 A JP 2006-310655 A Japanese Patent No. 4306701

In the case of the first method described above, the sensitivity signal can be maintained (returned to the original value) at a low electronic shutter speed as shown in FIG.
However, in the first method, since the saturation signal amount remains decreased due to the gain reduction, as shown in FIG. 3, the D range of the camera is reduced.

Also, in the second method described above, when the saturation signal amount increases too much, there is a problem of insufficient D range in the pixel signal transfer process such as a vertical register, a horizontal register, and a floating diffusion unit.
Furthermore, the second method has a problem that the absolute maximum rating is exceeded due to the large output signal amplitude (peak-to-peak including reset feedthrough) in the signal processing circuit in the latter stage of the CCD. Is not a preferred technique.

In the moving image mode, a method of adding a plurality of single pixel signals is also used for the purpose of securing the number of sensitive electrons.
For this reason, the increase in the saturation signal amount becomes more remarkable, and there arises a problem that the D range is insufficient in the pixel signal transfer process such as the vertical register, the horizontal register, and the floating diffusion unit.
Also in signal processing circuits, the output signal amplitude (peak-to-peak with reset feedthrough) increases, causing a problem of absolute maximum rating over, which makes it more difficult to adopt in practice. .

  The present invention provides a solid-state imaging device capable of reducing only smear components while maintaining the total amount of charge handled, and capable of improving image quality by relatively reducing smear signals, and a driving method thereof And providing a camera.

  A solid-state imaging device according to a first aspect of the present invention is arranged corresponding to a plurality of sensor units including photoelectric conversion functions arranged in a matrix and a column arrangement of the plurality of sensor units, and is read from the sensor unit. A plurality of vertical transfer units that transfer the signal charges output in the row arrangement direction, a horizontal transfer unit that transfers the signal charges transferred from the vertical transfer units in the column arrangement direction, and a plurality of columns of the vertical transfer units. And a charge discharging unit that can selectively discharge signal charges from the vertical transfer unit to the horizontal transfer unit, and a control that varies the saturation signal amount of the image when the signal charges are discharged by the charge discharging unit. And a drive system for performing

  According to a second aspect of the present invention, there is provided a driving method for a solid-state imaging device, which is arranged corresponding to a plurality of sensor units including photoelectric conversion functions arranged in a matrix and a column arrangement of the plurality of sensor units. A plurality of vertical transfer units that transfer the signal charges read from the unit in the row arrangement direction, a horizontal transfer unit that transfers the signal charges transferred from the vertical transfer unit in the column arrangement direction, and a plurality of the vertical transfer units When driving a solid-state imaging device including a charge discharging unit that is formed in units of columns and that can selectively discharge a signal charge from the vertical transfer unit to the horizontal transfer unit, the signal charge in the charge discharging unit Is controlled to vary the saturation signal amount of the image.

  A camera according to a third aspect of the present invention includes a solid-state imaging device, an optical system that guides incident light to a light receiving region of the solid-state imaging device, and a signal processing circuit that performs predetermined processing on an image by the solid-state imaging device. The solid-state imaging device is arranged in correspondence with a plurality of sensor units including photoelectric conversion functions arranged in a matrix and a column arrangement of the plurality of sensor units, and is read from the sensor unit A plurality of vertical transfer units that transfer signal charges in the row arrangement direction, a horizontal transfer unit that transfers signal charges transferred from the vertical transfer units in the column arrangement direction, and a plurality of columns of the vertical transfer units, A charge discharging unit that can selectively discharge signal charges from the vertical transfer unit to the horizontal transfer unit, and a drive that controls the amount of saturation signal of an image when the signal charge is discharged by the charge discharging unit. And the system.

  According to the present invention, it is possible to reduce only the smear component while maintaining the total amount of charge handled (effective pixel signal), and it is possible to improve the image quality by relatively reducing the smear signal.

It is a figure which shows the potential distribution of the light-receiving part which performs photoelectric conversion of the solid-state image sensor with a general vertical overflow drain structure. It is a figure for demonstrating a smear. It is a figure for demonstrating the relationship between exposure time and a signal output. It is a figure which shows the structural example of the solid-state image sensor which concerns on embodiment of this invention. It is a figure which shows the structural example of an electrode when the horizontal transfer register as a horizontal transfer part is a two-phase drive, and the vertical transfer register as four adjacent vertical transfer parts is made into one group. It is a figure which shows the structural example of an electrode when the horizontal transfer register as a horizontal transfer part is a two-phase drive, and the vertical transfer register as three adjacent vertical transfer parts is made into one group. It is a figure which shows the example of the output signal at the time of horizontal image 1/2 thinning drive. It is a figure which shows the drive timing chart at the time of the transfer in the operation mode of FIG. 5 and FIG. It is a figure which shows the transfer image of the output pixel in the operation mode of FIG. 5 and FIG. It is a figure which shows the example of the output signal at the time of the horizontal image 1/3 thinning drive. It is a figure which shows the example of the output signal at the time of the horizontal image 2/3 thinning drive. It is a figure which shows the drive timing chart at the time of the transfer in the operation mode of FIG. 6 and FIG. It is a figure which shows the transfer image of the output pixel in the operation mode of FIG. 6 and FIG. FIG. 12 is a diagram showing a drive timing chart at the time of transfer in the operation modes of FIGS. 6 and 11. It is a figure which shows the transfer image of the output pixel in the operation mode of FIG. 6 and FIG. It is a figure which shows the potential state of the overflow drain vicinity when barrier electric potential (phi) 2 of an overflow drain part is higher than electric potential (phi) 1 of a hold gate. It is a figure which shows the potential state of the overflow drain vicinity when barrier electric potential (phi) 2 of an overflow drain part is lower than electric potential (phi) 1 of a hold gate. It is a figure which shows the malfunction example by a local potential defect. It is a figure which shows the example of adjustment of the saturation signal amount by the substrate bias modulation which concerns on this embodiment. 1 is a schematic configuration diagram of a camera according to an embodiment of the present invention in which a solid-state imaging device according to the present embodiment is used as an imaging device.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
The description will be given in the following order.
1. 1. Configuration example of solid-state imaging device 2. Configuration example of substrate bias switching circuit 3. Characteristic configuration and function of the solid-state imaging device Specific description of characteristic configuration and function of the solid-state imaging device

<1. Configuration Example of Solid-State Image Sensor>
FIG. 4 is a diagram illustrating a configuration example of the solid-state imaging device according to the embodiment of the present invention.

The solid-state imaging device 10 of FIG. 4 is arranged in a matrix in a row (vertical) direction and a column (horizontal) direction, and converts a plurality of sensors that convert incident light into signal charges having a charge amount corresponding to the amount of light. Part (photoelectric conversion element) 11.
The solid-state imaging device 10 is provided for each vertical column of the sensor units 11 and includes a plurality of vertical transfer registers 13 that vertically transfer signal charges read from the sensor units 11 via the read gate unit 12.
In the solid-state imaging device 10, an imaging area 14 is configured by the sensor unit 11 and the vertical transfer register 13.

In the imaging area 14, the sensor unit 11 is composed of a PN junction photodiode, for example.
The signal charges accumulated in the sensor unit 11 are read out to the vertical register via the read gate unit 12 when a read pulse is applied.
The vertical transfer register 13 is driven to transfer by, for example, eight-phase vertical transfer clocks φV1 to φV8, and the read signal charges are sequentially arranged in portions corresponding to one scanning line (one line) in a part of the horizontal blanking period. Transfer vertically.

A horizontal transfer register 15 is disposed below the imaging area 14 in the drawing. Signal charges corresponding to one line are sequentially transferred from the plurality of vertical transfer registers 13 to the horizontal transfer register 15.
The horizontal transfer register 15 is driven to transfer by, for example, two-phase horizontal transfer clocks φH1 and φH2, and the signal charge for one line transferred from the plurality of vertical transfer registers 13 is transferred in the horizontal scanning period after the horizontal blanking period. Transfer sequentially in the horizontal direction.

At the transfer destination end of the horizontal transfer register 15, for example, a charge-voltage converter 16 having a floating diffusion amplifier configuration is disposed.
The charge-voltage converter 16 sequentially converts the signal charges transferred horizontally by the horizontal transfer register 15 into voltage signals and outputs the voltage signals.
This voltage signal passes through an output circuit (not shown), and then is output to the outside from the output terminal 17 as a CCD output OUT corresponding to the amount of incident light from the subject.

The sensor unit 11, the read gate unit 12, the vertical transfer register 13, the horizontal transfer register 15, the charge voltage conversion unit 16, and the like described above are formed on a semiconductor substrate (hereinafter simply referred to as a substrate) 18 to form the CCD image sensor 10 IMG. Is done.
Further, as will be described later, an overflow drain OFD as a charge discharging portion is formed in the vicinity (charge transfer region) of the connection portion between the vertical transfer register 13 and the horizontal transfer register 15.
In this embodiment, the electrode pitch of the horizontal transfer register 15 is formed as an electrode configuration including a plurality of lines of vertical transfer registers 13.

The solid-state imaging device 10 of this embodiment is a drive control system for the CCD imaging device 10 IMG, and includes a timing generation circuit 19 and a substrate bias switching circuit 20.
Furthermore, the solid-state imaging device 10 of the present embodiment is provided with a signal processing circuit (PRC) 30 that performs signal processing on the readout signal of the CCD imaging device 10IMG.

  In the solid-state imaging device 10, eight-phase vertical transfer clocks φV 1 to φV 8 and two-phase horizontal transfer clocks φH 1 and φH 2 for driving transfer reading in the vertical direction and the horizontal direction are generated from the timing generation circuit 19.

The 8-phase vertical transfer clocks φV1 to φV8 are supplied to the vertical transfer register 13 via terminals (pads) 21-1 to 21-8 formed on the substrate 18.
Various transfer timing signals φST1, φST2, φVHLD1, φVHLD2, φLV, and φVOG are supplied to the vertical transfer register 13 via terminals 22-1 to 22-6.
The two-phase horizontal transfer clocks φH1 and φH2 are supplied to the horizontal transfer register 15 via terminals 23-1 and 23-2.
Further, the timing generation circuit 19 generates substrate bias control signals Vsub Cont1 and Vsub Cont 2 for controlling the substrate bias switching process in the substrate bias switching circuit 20.

φV1 to φV8 are signals for driving the vertical transfer electrodes V1 to V8.
φST1 and φST2 are signals for driving the storage gates ST1 and ST2.
φVHLD1 and φVHLD2 are signals for driving the hold gate HLD.
φLV is a signal for driving the final vertical transfer electrode LV.
φVOG is a signal for driving the gate of the charge accumulation control electrode VOG.
φH1 and φH2 are signals for driving the horizontal transfer electrodes H1 and H2.
The arrangement of these electrodes and gates will be described later.

A bias voltage (hereinafter referred to as substrate bias) Vsub for biasing the substrate 18 is applied on the substrate 18. The circuit GVS for generating the substrate bias is formed on the substrate 18.
A substrate bias switching circuit 20 that switches the substrate bias in order to modulate the substrate bias Vsub is connected to the substrate 18 via a terminal 24.

<2. Configuration example of substrate bias switching circuit>
The substrate bias switching circuit 20 includes npn transistors Q1, Q2, resistance elements R1, R2, R3, R4, signal terminals 25-1, 25-2, and a node ND1.
In the substrate bias switching circuit 20, the node ND <b> 1 is connected to the terminal 24 of the substrate 18.
The collector of the transistor Q1 is connected to one end of the resistor element R1, and the other end of the resistor element R1 is connected to the node ND1. The emitter of the transistor Q1 is grounded, the gate is connected to one end of the resistor element R3, and the other end of the resistor element R3 is connected to the terminal 25-1 to which the first substrate bias control signal Vsub Cont1 is supplied.
The collector of the transistor Q2 is connected to one end of the resistance element R2, and the other end of the resistance element R2 is connected to the node ND1. The emitter of the transistor Q2 is grounded, the gate is connected to one end of the resistor element R4, and the other end of the resistor element R4 is connected to the terminal 25-2 to which the second substrate bias control signal Vsub Cont2 is supplied.

In the substrate bias switching circuit 20, the transistors Q1 and Q2 are individually controlled to be turned on and off by the first substrate bias control signal Vsub Cont1 and the second substrate bias control signal Vsub Cont2 supplied from the timing generation circuit 19.
As a result, the substrate bias Vsub of the substrate 18 is modulated.

  In FIG. 4, an example of substrate bias modulation is shown in the block of the substrate bias switching circuit 20 together with the circuit configuration.

In the example of FIG. 4, first, the first substrate bias control signal Vsub Cont1 and the second substrate bias control signal Vsub Cont2 are supplied to the bases of the transistors Q1 and Q2 at a high level.
In this case, the two transistors Q1 and Q2 are both held off.
As a result, the substrate bias Vsub is not modulated and is maintained at the reference setting.

Next, the first substrate bias control signal Vsub Cont1 is supplied to the bases of the transistors Q1 and Q2 at the high level and the second substrate bias control signal Vsub Cont2 is at the low level.
In this case, the transistor Q1 is turned on (ON), and the transistor Q2 is held off (OFF).
As a result, the substrate bias Vsub is modulated so as to increase by one step, and the saturation signal amount is controlled to increase by one step.

Next, the first substrate bias control signal Vsub Cont1 is supplied to the bases of the transistors Q1 and Q2 at the low level and the second substrate bias control signal Vsub Cont2 is at the high level.
In this case, the transistor Q1 is turned off (OFF) and the transistor Q2 is turned on (ON).
As a result, the substrate bias Vsub is modulated to be further increased by one step, and the saturation signal amount is controlled to be further decreased by one step.

Such modulation control is performed when the signal of a certain vertical line is swept out to the overflow drain OFD and the saturation signal amount of the pixel is varied simultaneously in parallel.
Note that it is also possible to individually control the drive by increasing the number of transistors that are driven in parallel, and thereby, it is possible to realize finer modulation control.

  In the present embodiment, the drive system includes at least a timing generation circuit 19 and a substrate bias switching circuit 20.

<3. Characteristic configuration and function of the solid-state image sensor>
The solid-state imaging device 10 having the above configuration has the following characteristics.
As described above, the solid-state imaging device 10 has the overflow drain OFD in the vicinity of the connection portion between the vertical transfer register 13 and the horizontal transfer register 15, and the electrode pitch of the horizontal transfer register 15 includes the plurality of lines of the vertical transfer register 13. It has a configuration.
The solid-state imaging device 10 has a drive system that performs control to sweep a signal of a certain vertical line to the overflow drain and vary the saturation signal amount of the pixel.
This drive system includes a timing generation circuit 19, a substrate bias switching circuit 20, and a control system (not shown).

  The solid-state imaging device 10 discharges (sweeps) the signal charges of the vertical line to the overflow drain OFD (the pixel thinning rate in the horizontal direction) according to the subject or the saturation signal amount of the selectable pixel. Has a function to select.

The solid-state imaging device 10 is configured such that the potential of the hold gate during the horizontal pixel thinning operation is shallower than the barrier potential of the overflow drain portion that is a charge discharging portion.
Further, the solid-state imaging device 10 has a function of varying the horizontal thinning drive, the electronic shutter speed, and the saturation signal amount of the pixel according to the brightness of the subject.

  The solid-state imaging device 10 has a function of “no” horizontal thinning when imaging a low-luminance subject and “existing” horizontal thinning when imaging a high-luminance subject.

  The solid-state imaging device 10 has a function of changing the saturation signal amount by the substrate bias switching circuit 20 and changing the gain setting of the signal processing circuit 30 when performing horizontal thinning driving.

  The solid-state imaging device 10 has a function of detecting subject information, in this case, whether the brightness is low or high by feeding back information on ND ON / OFF and shutter speed obtained by following the brightness. Have

  The solid-state imaging device 10 has a function of changing the digital gain during the substrate bias modulation period when the drive mode is switched.

  The solid-state imaging device 10 has a function of holding independent color reproduction parameters, reflecting parameters adapted to the modes, and adjusting white balance for each mode, for example.

The solid-state imaging device 10 according to the present embodiment including such a feature combines the total pixel charge (effective pixel signal) by combining horizontal pixel thinning, single pixel saturation signal amount increase, and electronic shutter speed reduction. While maintaining, reduce only the smear component.
That is, the solid-state imaging device 10 is configured to improve image quality by relatively reducing the smear signal.
As a result, the solid-state imaging device 10 prevents the dynamic range from being insufficient in the pixel signal transfer process, such as the vertical transfer register 13, the horizontal transfer register 15, and the floating diffusion unit.
Further, the solid-state imaging device 10 prevents the absolute maximum rating from being exceeded due to the large output signal amplitude (peak to peak including reset feedthrough) in the signal processing circuit 30 subsequent to the CCD imaging device 10IMG. ing.
As a result, only the smear signal amount can be reduced, and the image quality can be improved.
In addition, when performing horizontal pixel thinning driving, there may be a case where insufficient sensitivity during low-illuminance subject imaging becomes a problem.
In such a case, the solid-state imaging device 10 switches whether or not the horizontal pixels are thinned out according to the brightness of the subject as necessary.
For example, when high luminance is used, horizontal pixel thinning is “present” to reduce smear to improve image quality, and for low luminance, horizontal pixel thinning is “no” to ensure sensitivity.
The solid-state imaging device 10 having such a control function can also provide optimum image quality according to the brightness of the subject.

<4. Specific description of characteristic configuration and function of the solid-state imaging device>
Hereinafter, the characteristic configuration and function of the solid-state imaging device 10 of the present embodiment described above will be specifically described.

[Horizontal pixel decimation method]
First, a horizontal pixel thinning method will be described.
As a method of sweeping out pixel signals and smear signals in units of columns, a method of providing a vertical transfer register 13 as a vertical transfer unit and a region (overflow drain) for discharging signal charges in the vicinity of the horizontal transfer register 15 as a horizontal transfer unit is adopted. Is possible.
FIG. 5 and FIG. 6 show electrode configuration examples of the vertical transfer register 13 as a vertical transfer unit provided with the overflow drain and the horizontal transfer register 15 as a horizontal transfer unit.
In these examples, the horizontal transfer register 15 has an electrode configuration in which the electrode pitch includes a plurality of lines of the vertical transfer register 13.

FIG. 5 shows a configuration example of electrodes when the horizontal transfer register 15 as a horizontal transfer unit is two-phase driven and the vertical transfer registers 13 as four adjacent vertical transfer units are grouped.
FIG. 6 shows a configuration example of electrodes when the horizontal transfer register 15 as the horizontal transfer unit is two-phase driven and the vertical transfer registers 13 as three adjacent vertical transfer units are grouped into one group.
The horizontal transfer unit uses two-phase driving as an example, but there is no restriction on the number of horizontal driving phases.

5 and 6, reference numeral 40 denotes an overflow drain part as a charge discharging part.
5 and 6, the region indicated by R, G, and B is the sensor unit 11.
V7 represents the seventh vertical transfer electrode.
V8 represents the eighth vertical transfer electrode (the final stage of the 8-phase drive).
ST, ST1, ST2 indicate storage gates.
HLD indicates a hold gate.
Reference numerals LV, LV1 and LV2 denote final vertical transfer electrodes.
VOG, VOG1, and VOG2 indicate charge accumulation control electrodes.
H1 and H2 indicate horizontal transfer electrodes.

When performing horizontal pixel thinning with the electrode configuration of FIG. 5, the following processing is performed.
FIG. 7 is a diagram illustrating an example of an output signal at the time of horizontal image 1/2 thinning driving.
FIG. 8 is a diagram showing a drive timing chart at the time of transfer in the operation modes of FIG. 5 and FIG.
FIG. 9 is a diagram illustrating a transfer image of output pixels in the operation modes of FIGS. 5 and 7. FIG. 9 shows only transfer points as points.

A fixed bias is applied to the gates of the final vertical transfer electrode LV2 and the charge accumulation control electrode VOG2 adjacent to the overflow drain part 40, and is kept at a constant potential.
As a result, all the signals of the column having the final vertical transfer electrode LV2 can be discharged to the overflow drain section 40 without being transferred to the horizontal transfer register 15, and the pixel signals can be thinned out to ½ in the horizontal direction and output. It becomes.
In this case, as shown in FIG. 7, it is possible to provide pixel signals that are output every two columns and pixel signals that are not output.

When performing horizontal pixel thinning with the electrode configuration of FIG. 6, the following processing is performed.
FIG. 10 is a diagram illustrating an example of an output signal at the time of horizontal image 1/3 thinning driving.
FIG. 11 is a diagram illustrating an example of an output signal at the time of horizontal image 2/3 thinning driving.
FIG. 12 is a diagram showing a drive timing chart at the time of transfer in the operation modes of FIG. 6 and FIG.
FIG. 13 is a diagram illustrating a transfer image of output pixels in the operation modes of FIGS. 6 and 10. FIG. 13 shows only transfer points as points.
FIG. 14 is a diagram showing a drive timing chart at the time of transfer in the operation modes of FIGS. 6 and 11.
FIG. 15 is a diagram showing a transfer image of output pixels in the operation modes of FIGS. 6 and 11. FIG. 15 shows only transfer points as points.

In FIG. 6, the vertical transfer registers 13 as three vertical transfer units are grouped into one group.
In this case, either driving or fixing the bias of the storage gates ST1 and ST2 adjacent to the overflow drain section 40 is selected.
When only the storage gate ST1 is driven, the storage gate ST2 is given a fixed bias, and all the signals in the column of the storage gate ST2 are swept away to the overflow drain section 40, the horizontal pixel decimation rate becomes 2/3.
When both the storage gates ST1 and ST2 are fixed with a bias and both columns are swept away to the overflow drain section 40, the pixel thinning rate in the horizontal direction becomes 1/3.
In this way, the thinning rate can be arbitrarily selected in the electrode configuration of FIG.
As a result, as shown in FIGS. 10 and 11, it is possible to provide pixel signals that are output and pixel signals that are not output.

FIG. 16 is a diagram showing a potential state in the vicinity of the overflow drain when the barrier potential φ2 of the overflow drain portion is higher than the potential φ1 of the hold gate.
FIG. 17 is a diagram illustrating a potential state in the vicinity of the overflow drain when the barrier potential φ2 of the overflow drain portion is lower than the potential φ1 of the hold gate.

As noted in the horizontal pixel thinning operation described above, as shown in FIG. 16, the horizontal pixel thinning operation is performed with respect to the barrier potential φ2 of the overflow drain portion 40 provided in the vicinity of the vertical transfer portion and the horizontal transfer portion. It is necessary to reduce the potential φ1 of the hold gate HLD.
On the other hand, as shown in FIG. 17, when the barrier potential relationship is reversed (φ1> φ2), signal charges that should not be output due to horizontal pixel thinning leak into the horizontal register or the like, and normal signals and Color mixing will be a problem.

FIG. 18 is a diagram illustrating a failure example due to a local potential defect.
19A and 19B are diagrams showing examples of adjusting the saturation signal amount by the substrate bias modulation according to the present embodiment.

Even if the normal pixel row is normal, even if the barrier potential relationship is locally reversed for one pixel with respect to the number of horizontal pixels of 1000 due to a potential defect or the like, color mixing with the normal signal causes As shown in FIG. 18, a problem arises because local vertical stripes are generated.
Therefore, it is necessary to design with careful attention to the relationship between the barrier potential of the overflow drain section 40 and the potential of the hold gate HLD during the horizontal pixel thinning operation.

When the horizontal pixel thinning rate is 1 / n as described above, the substrate bias is modulated and the saturation signal amount is set to n times as shown in FIG.
Further, by combining the substrate modulation with the speed reduction of the electronic shutter, it is possible to reduce only the smear component to 1 / n while maintaining the output signal amount (sensitivity) of the pixel.

Further, it is not necessary to limit the increase of the saturation signal amount to n times, and it is sufficient that the saturation signal amount of the pixel can be increased even if it is minute.
In this case, it is possible to improve the smear image quality by performing gain processing (increasing the gain by the necessary pixel signal amount) in the signal processing circuit 30 while improving the ratio of pixel signal: smear.
For example, in the case of FIG. 9 where the ratio of smear signal: saturation output signal is 1/2: 1 (or 1: 2), the smear is improved by 6 dB.
On the other hand, in the case of FIG. 13 where the ratio of smear signal: saturation output signal is 2/3: 1 (or 1: 1.5), the smear is improved by 3.5 dB.
However, even when the increase in the saturation signal amount of a single pixel in FIG. 13 can only increase by a factor of 1.2, the smear signal: saturation output signal ratio is 1: 1.2, so that the smear is 1.6 dB (1 .2).

  As described above, the smear improvement effect is expressed by the smear signal: saturation output signal because the sensitivity signal can be maintained (returned) by reducing the speed of the electronic shutter. .

As described above, the solid-state imaging device 10 prevents the dynamic range from being insufficient in the pixel signal transfer process such as the vertical transfer register 13, the horizontal transfer register 15, and the floating diffusion unit.
Further, the solid-state imaging device 10 prevents the absolute maximum rating from being exceeded due to the large output signal amplitude (peak to peak including reset feedthrough) in the signal processing circuit 30 subsequent to the CCD imaging device 10IMG. ing.
As a result, only the amount of smear signal can be reduced, and the image quality can be improved.

[Toggle horizontal pixel thinning]
Next, control according to the luminance information of the subject, and switching of horizontal pixel thinning presence / absence depending on the brightness of the subject (high luminance: horizontal pixel thinning “Yes” improves smear image quality, low luminance: horizontal pixel thinning “No” An application example in which “sensitivity is secured” will be described.

  FIG. 20 is a schematic configuration diagram of a camera using the solid-state imaging device according to the present embodiment as an imaging device.

The camera 100 includes the following components in addition to the CCD image sensor 10IMG, the substrate bias switching circuit 20, and the signal processing circuit 30 described above.
The camera 100 includes an optical system 50 including a lens 51 and a diaphragm 52, a CCD drive circuit 60 including a timing generation circuit 19, and an operation mode setting unit 70 on the light incident side of the CCD image sensor 10 IMG.
In the present embodiment, the drive system includes a CCD drive circuit 60 including the timing generation circuit 19 and an operation mode setting unit 70.

When horizontal pixel thinning driving is performed when the subject has low luminance (pixel output signal >> smear signal), the originally small amount of smear does not change substantially, the required pixel signal is greatly reduced, and S / N is reduced. It will result in deterioration.
For this reason, the operation mode setting unit 70 shown in FIG. 20 performs ON / OFF control of the horizontal pixel thinning drive according to the luminance information (high luminance or low luminance) of the subject.

  As a method of detecting this subject information, a method of feeding back information on ON / OFF of the ND filter, F value (aperture) of the lens, and shutter speed can be applied.

In this way, when sensing subject information and imaging a dark subject, the horizontal pixel thinning operation is “none” to ensure sensitivity, and when shooting a bright subject, horizontal pixel thinning is “present” and the substrate bias is applied. The saturation signal amount is increased by modulation.
In parallel with this, the operation mode setting unit 70 sets the electronic shutter speed according to the brightness of the subject, thereby securing the necessary signal amount.
The electronic shutter speed is set to a low speed when low luminance and horizontal pixel thinning are not set, and to a low speed when high luminance and horizontal pixel thinning are set.

Further, the mode switching as described above is mostly accompanied by substrate bias modulation.
However, if time is required for modulation of the substrate bias, if the output is performed in a state where the substrate bias is not sufficiently modulated (a state where a sufficient saturation signal amount is not reached), coloring associated with a low dynamic range may occur. There is sex.
Therefore, it is also effective to change the gain (set by the signal processing circuit 30) at the time of mode switching and prevent coloring.

  Also, since the spectral sensitivity characteristic changes during substrate bias modulation, an independent white reproduction parameter (set by the signal processing circuit 30) is held and reflected in accordance with the drive mode switching control, so that the optimum white balance adjustment can be performed. It becomes possible.

  By combining the above functions, it is possible to provide optimum image quality according to the brightness of the subject.

As described above, according to the present embodiment, the following effects can be obtained.
Simultaneously with the horizontal pixel thinning operation, the saturation signal amount of a single pixel is increased, and further, by combining a low-speed electronic shutter, only the smear signal can be reduced while maintaining the necessary pixel signal amount.
This can solve the problem of insufficient dynamic range in the pixel signal transfer process, such as a vertical register, a horizontal register, and a floating diffusion unit.
Also in the signal processing circuit at the rear stage of the CCD, the problem of the absolute maximum rating over does not occur due to the large output signal amplitude (peak to peak including reset feedthrough). Only the smear signal amount can be reduced, and the image quality can be improved.
It is also possible to provide optimum image quality for each subject brightness by switching the presence or absence of horizontal pixel thinning and the electronic shutter speed according to the subject brightness.
When time is required for substrate bias modulation when switching the drive mode, it is possible to prevent coloring by adjusting the digital gain.
When the spectral characteristics are different for each drive mode, an optimum white balance adjustment can be performed by holding independent color reproduction parameters and reflecting them in accordance with the drive mode.

  DESCRIPTION OF SYMBOLS 10 ... Solid-state imaging device, 10IMG ... CCD image sensor, 11 ... Sensor part, 12 ... Read-out gate part, 13 ... Vertical transfer register (vertical transfer part), 14 ... Imaging area , 15 ... Horizontal transfer register (horizontal transfer unit), 16 ... Charge voltage conversion unit, 18 ... Semiconductor substrate, 19 ... Timing generation circuit, 20 ... Substrate bias switching circuit, 30 ... Signal processing circuit, 40 ... overflow drain part (charge discharging part), 50 ... optical system, 60 ... CCD drive circuit, 70 ... operation mode setting part, 100 ... camera.

Claims (13)

A plurality of sensor units including photoelectric conversion functions arranged in a matrix;
A plurality of vertical transfer units arranged corresponding to the column arrangement of the plurality of sensor units, and transferring signal charges read from the sensor units in a row arrangement direction;
A horizontal transfer unit that transfers the signal charges transferred from the vertical transfer unit in a column arrangement direction;
A charge discharging unit formed in units of a plurality of columns of the vertical transfer unit and capable of selectively discharging signal charges from the vertical transfer unit to the horizontal transfer unit;
A solid-state imaging device having a drive system for performing control to vary a saturation signal amount of an image when the signal charge is discharged by the charge discharging unit. The solid-state imaging device according to claim 1, wherein the number of columns for discharging the signal of the vertical transfer unit line to the charge discharging unit is selected according to a subject. The solid-state imaging device according to claim 1, wherein the number of columns for discharging the signal of the vertical transfer unit line to the charge discharging unit is selected according to a saturation signal amount of a selectable pixel. The charge discharging part is
Including overflow drain,
4. The solid-state imaging device according to claim 1, wherein a potential of a hold gate during a horizontal pixel thinning operation is set lower than a barrier potential of the overflow drain portion. The drive system is
5. The solid-state imaging device according to claim 1, wherein the horizontal thinning drive, the electronic shutter speed, and the saturation signal amount of the pixel can be changed according to the brightness of the subject. The drive system is
The solid-state imaging device according to claim 5, wherein driving is performed such that no thinning is performed in the horizontal direction when imaging a low-luminance subject, and thinning out is performed in the horizontal direction when imaging a high-luminance subject. A signal processing circuit that performs at least gain processing on the signal transferred by the horizontal transfer unit;
The drive system is
The solid-state imaging device according to claim 5, wherein when performing horizontal thinning driving, the saturation signal amount is changed and the gain setting of the signal processing circuit is changed. The drive system is
The solid-state imaging device according to any one of claims 5 to 7, wherein the subject information is detected by feeding back information obtained by following the brightness. The sensor unit, the vertical transfer unit, the horizontal transfer unit, and the charge discharge unit are formed on a semiconductor substrate,
A substrate bias voltage is applied to the semiconductor substrate,
The drive system is
The solid-state imaging device according to claim 1, having a function of modulating the substrate bias voltage. A signal processing circuit that performs at least gain processing on the signal transferred by the horizontal transfer unit;
The solid-state imaging device according to claim 9, wherein the digital gain is changed during a substrate bias modulation period when the drive mode is switched. A signal processing circuit that performs signal processing on the signal transferred by the horizontal transfer unit;
The signal processing circuit is
The solid-state imaging device according to claim 1, wherein the solid-state imaging element has a function of holding independent color reproduction parameters and reflecting a parameter adapted to a mode. A plurality of sensor units including photoelectric conversion functions arranged in a matrix;
A plurality of vertical transfer units arranged corresponding to the column arrangement of the plurality of sensor units, and transferring signal charges read from the sensor units in a row arrangement direction;
A horizontal transfer unit that transfers the signal charges transferred from the vertical transfer unit in a column arrangement direction;
When driving a solid-state imaging device, including a charge discharging unit that is formed in units of a plurality of columns of the vertical transfer unit and can selectively discharge signal charges from the vertical transfer unit to the horizontal transfer unit,
A method for driving a solid-state imaging device that performs control to vary a saturation signal amount of an image when signal charges are discharged by the charge discharging unit. A solid-state image sensor;
An optical system for guiding incident light to the light receiving region of the solid-state imaging device;
A signal processing circuit that performs predetermined processing on an image by the solid-state imaging device,
The solid-state imaging device is
A plurality of sensor units including photoelectric conversion functions arranged in a matrix;
A plurality of vertical transfer units arranged corresponding to the column arrangement of the plurality of sensor units, and transferring signal charges read from the sensor units in a row arrangement direction;
A horizontal transfer unit that transfers the signal charges transferred from the vertical transfer unit in a column arrangement direction;
A charge discharging unit formed in units of a plurality of columns of the vertical transfer unit and capable of selectively discharging signal charges from the vertical transfer unit to the horizontal transfer unit;
A drive system that performs control to vary a saturation signal amount of the image when the signal charge is discharged by the charge discharging unit.