JP2011171432A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid over etching of the bottom of an upper layer wiring groove when a recessed part is formed on a surface of lower layer wiring through a connecting plug hole by etching, in manufacturing a wiring structure by a dual damascene process. <P>SOLUTION: A wiring groove 114 and a hole 115 are formed after a conductive film pattern 112 made of TaN or the like and having an opening corresponding to a connecting plug is formed between interlayer insulating films 111 and 113 made of SiOC or the like. Then, a laminated conductive film 116 made of TaN, Ta or the like is deposited, the laminated conductive film 116 at the bottom of the hole 115 is removed, and further etching to dig a Cu film 109 constituting lower layer wiring is performed. At this time, the interlayer insulating film 111 under the bottom of the wiring groove 114 can be prevented from being etched since there exists the conductive film pattern 112. Then, a conductive film 117 made of Cu or the like is embedded in the wiring groove 114 and the hole 115. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a wiring structure and a manufacturing method thereof capable of stably manufacturing a highly reliable wiring.

  In recent years, with the increase in the operation speed and the miniaturization of various element patterns constituting a circuit in a semiconductor integrated circuit device, a technique for forming a low resistance wiring for an integrated circuit is required, and Cu (copper) is a main means. Development and improvement of technology for forming wiring by the damascene method (single damascene method or dual damascene method) using wiring materials mainly made of copper is continued. However, with the progress of pattern miniaturization, in multi-layer wiring structures formed using the damascene method, wiring reliability such as electromigration and stress migration is particularly important in the region where the plug and wiring connecting the wiring layers are in contact. There is a concern that the quality will deteriorate. As a method for improving the wiring reliability, a connection hole for embedding the plug is formed by digging from the interlayer insulating film to a portion deeper than the surface of the lower wiring, and concentrated on the connection hole portion during the operation of the semiconductor integrated circuit. A technique (generally called a punch-through process) has been proposed that distributes the current to be distributed.

  Patent Document 1 describes a process example in which a copper wiring is formed by using the dual damascene method and applying the punch-through process. FIG. 16 is a process cross-sectional view illustrating a main process for forming a buried copper wiring described in Patent Document 1. As shown in FIG. 16A, an etching stopper film 16 and an interlayer insulating film 19 are formed on a barrier conductive film made of a tantalum nitride film or the like and a buried wiring 15 made of a copper film. Then, a wiring groove 28 is formed in the interlayer insulating film 19, and a connection hole 25 A is formed in the interlayer insulating film 19 and the etching stopper film 16 at the bottom of the wiring groove 28. Thereafter, a barrier conductive film 31A is deposited on the inner surfaces of the wiring groove 28 and the connection hole 25A.

  Next, as shown in FIG. 16B, the barrier conductive film 31A at the bottom of the connection hole 25A is completely removed by sputter etching, and one embedded wiring 15 below the barrier conductive film 31A in the connection hole 25A. Dig into the part. At the same time, the barrier conductive film 31A remains thinly on the bottom surface of the wiring trench 28. This process utilizes the property that the etching proceeds more deeply in the sputter etching method. Next, as shown in FIG. 16C, a tantalum film is deposited on the interlayer insulating film 19 including the inside of the wiring groove 28 and the connection hole 25A by a sputtering method to increase the thickness of the barrier conductive film 31A and to dig the digging portion. cover. Thereafter, although not shown, the wiring groove 28 and the connection hole 25A are filled with a copper film to form a plug and an upper-layer buried wiring.

  Thus, by digging a part of the lower buried wiring 15 and then integrally forming the buried wiring and the plug in the wiring groove 28 and the connection hole 25A, the contact area between the plug and the lower buried wiring 15 is increased. Can be made. With this structure, it is possible to improve the reliability of connection characteristics between the upper embedded wiring including the plug and the lower embedded wiring 15 with respect to electromigration and stress migration.

JP 2007-227709 A

  However, the conventional method for manufacturing a wiring structure by the dual damascene method as disclosed in Patent Document 1 has the following problems. That is, as shown in FIG. 16B, the conventional manufacturing method uses sputter etching to remove the barrier conductive film 31A from the bottom surface of the connection hole 25A and further dig the buried wiring 15 therebelow. On the other hand, the bottom surface of the wiring trench 28 is to be processed so that the barrier conductive film 31A remains even when subjected to the same sputter etching.

  However, in such a method, depending on the sputter etching conditions, all of the barrier conductive film 31A on the bottom surface of the wiring groove 28 is removed, and further, the underlying interlayer insulating film 19 is etched to change the depth of the wiring groove 28 itself. In addition, due to the non-uniformity of sputter etching, it is expected that a portion where the barrier conductive film 31A remains and a portion where the barrier conductive film 31A does not remain are generated on the bottom surface of the wiring groove 28 in the semiconductor substrate surface.

Furthermore, in recent miniaturized semiconductor integrated circuits, the wirings are arranged at very small intervals, resulting in an increase in parasitic capacitance between wirings, and an increase in parasitic capacitance between different wiring layers due to a reduction in interlayer insulation film thickness. As a countermeasure, a material having a relative dielectric constant smaller than that of the silicon oxide film (SiO ₂ ) (low dielectric constant material or low-k material) is adopted as a countermeasure. Yes. When a film made of a low dielectric constant material (low dielectric constant film) is used, the smaller the dielectric constant is, the more the wiring delay can be eliminated, but the density of the film becomes smaller. This means that the sputter etching rate of the low dielectric constant film is increased.

  Assuming that the low dielectric constant film is used as the interlayer insulating film 19 in the conventional method for manufacturing a wiring structure, when the barrier conductive film 31A on the bottom surface of the wiring groove 28 is removed by sputter etching, the interlayer insulating film 19 is exposed. The interlayer insulating film 19 is greatly etched and thinned. Further, even if the interlayer insulating film is not subjected to much etching, it receives a considerable amount of damage due to the impact of ions used for sputter etching and the ions being implanted into the film itself. Such damage can be said to be greater as the relative dielectric constant is smaller. For these reasons, a short circuit defect between the upper and lower embedded wirings and deterioration of the withstand voltage between the embedded wirings occur, which deteriorates the manufacturing yield and reliability of the wiring structure.

  In addition, it is preferable in terms of lowering the electrical resistance that the height of the connection hole is equal to or less than the height of the wiring, but if the height of the connection hole is smaller than the height of the wiring, the wiring bottom is easily etched, There is a problem that the above problem becomes more apparent.

  In view of the above, the present invention solves the above-described problems, and maintains a highly reliable wiring structure while maintaining high reliability against electromigration, stress migration, etc. in the connection region between the plug and the wiring layer. In particular, it is an object of the present invention to provide a semiconductor device that can be manufactured stably and with high yield using a dual damascene method, and a method for manufacturing the semiconductor device.

  In the present invention, it is not necessary to solve all the above-mentioned problems, and it is not necessary to achieve all the objects. It is sufficient to solve at least one problem and achieve at least one purpose.

  A first semiconductor device according to the present invention that can solve the above-described problems includes a lower layer wiring formed on a semiconductor substrate, an upper layer wiring formed on an upper layer of the lower layer wiring, the lower layer wiring, and the upper layer A plug electrically connecting the wiring; a pattern made of a film formed in contact with the bottom surface of the upper wiring; and formed under the upper wiring; and a conductive film formed on the side wall of the upper wiring and the side wall of the plug And a recess is formed on the upper surface of the lower layer wiring located immediately below the plug.

  According to the first semiconductor device of the present invention, since the film pattern is formed on the bottom surface of the upper layer wiring, the lower layer positioned immediately below the plug is formed before the upper layer wiring and the plug are formed. Even if the entire surface is etched to form a recess in the wiring, the interlayer insulating film under the pattern can be prevented from being excessively etched or damaged, and the wiring structure can be stably manufactured.

  In the first semiconductor device, the plug and the lower layer wiring can be in direct contact with each other. The upper layer wiring is preferably formed in an area inside the pattern.

  The upper layer wiring and the plug are formed by being embedded in an interlayer insulating film, and the relative dielectric constant of the interlayer insulating film can be 3.5 or less. In particular, when the interlayer insulating film is composed of a first interlayer insulating film and a second interlayer insulating film, the plug is embedded in the first interlayer insulating film, and the upper layer wiring is formed in the second interlayer insulating film. The relative dielectric constant of the embedded first interlayer insulating film can be 3.5 or less.

  The film constituting the pattern may be a conductive film or an insulating film.

  Next, a second semiconductor device according to the present invention electrically connects a lower layer wiring formed on a semiconductor substrate, an upper layer wiring formed on an upper layer of the lower layer wiring, and the lower layer wiring and the upper layer wiring. A plug to be formed, a coating film formed on the side wall and the bottom surface of the upper layer wiring, a second conductive film formed on the coating film formed on the side wall of the upper layer wiring and on the side wall of the plug And a recess is formed on the upper surface of the lower layer wiring located immediately below the plug.

  According to the second semiconductor device of the present invention, since the coating film is formed on the side wall and the bottom surface of the upper layer wiring, the upper layer wiring and the plug are formed immediately before the plug. Even if the entire surface of the lower wiring layer is etched to form a recess, the interlayer insulating film under the bottom surface of the upper wiring layer can be prevented from being excessively etched or damaged, and the wiring structure can be stably manufactured. Can do.

  In the second semiconductor device, the plug and the lower layer wiring can be in direct contact with each other. Further, the upper layer wiring and the plug are formed to be embedded in the interlayer insulating film, and the relative dielectric constant of the interlayer insulating film can be 3.5 or less. Further, the coating film can be a conductive film or an insulating film. In the first and second semiconductor devices, it is preferable that the height of the upper layer wiring is equal to or higher than the height of the plug.

  Next, a first method of manufacturing a semiconductor device according to the present invention for solving the above-described problem includes a step of forming a first interlayer insulating film on a lower layer wiring formed on a semiconductor substrate, and the first Forming a pattern made of a film having an opening at a position where an upper wiring on the interlayer insulating film is to be formed, and forming a second interlayer insulating film on the pattern and the first interlayer insulating film A step of selectively etching the second interlayer insulating film located on the pattern to expose the pattern to form a groove; and selecting the first interlayer insulating film using the pattern as a mask. Etching to form a hole reaching the lower wiring, forming a first conductive film on the groove and the inner surface of the hole, and the first conductive formed on the bottom surface of the hole Remove the sex membrane and before A step of exposing the surface of the lower layer wiring, a step of etching the exposed surface of the lower layer wiring to form a recess, a second conductive film embedded in the groove, the hole and the recess, Forming the upper layer wiring.

  According to the first method for manufacturing a semiconductor device of the present invention, a pattern made of a film having an opening is formed in advance at a position where an upper layer wiring on the first interlayer insulating film is to be formed. In the step of removing the first conductive film formed on the substrate and further etching the surface of the underlying lower layer wiring to form a recess, the first interlayer insulating film below the bottom surface of the groove is excessively etched. It can be prevented from being damaged or damaged, and the wiring structure can be manufactured stably.

  In the first method for manufacturing a semiconductor device according to the present invention, between the step of forming the recess and the step of embedding the second conductive film in the groove, the hole and the recess, the groove and the A step of forming a third conductive film inside the hole can be performed.

  The film constituting the pattern may be made of a conductive film or an insulating film, and when the insulating film is selected, the insulating film constituting the pattern for the first interlayer insulating film is etched. It is desirable that the speed is 2 or more. The relative dielectric constant of the first interlayer insulating film can be 3.5 or less.

  A second method for manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film on a lower layer wiring formed on a semiconductor substrate, and a step of selectively etching the interlayer insulating film to form a groove. And a step of forming a coating film on the inner surface of the groove, and selectively etching portions of the coating film and the interlayer insulating film located on the bottom surface of the groove sequentially to form holes reaching the lower layer wiring. Forming a first conductive film on the inner surface of the groove and the hole; removing the first conductive film formed on the bottom surface of the hole; A step of exposing, a step of etching the exposed surface of the lower layer wiring to form a recess, a second conductive film embedded in the groove, the hole and the recess, and forming an upper layer wiring in the groove Including the step of.

  According to the second method for manufacturing a semiconductor device of the present invention, since the coating film is formed in advance on the inner surface, particularly the bottom surface of the groove, the first conductive film formed on the bottom surface of the hole is removed. In addition, in the process of forming a recess by etching the surface of the underlying lower layer wiring, the interlayer insulating film under the bottom of the groove can be prevented from being excessively etched or damaged, and the wiring structure can be stably manufactured. can do.

  In the second method for manufacturing a semiconductor device, between the step of forming the recess and the step of embedding the second conductive film in the groove, the hole, and the recess, the interior of the groove and the hole is provided. A step of forming the third conductive film can be performed. Further, the coating film can be made of a conductive film or an insulating film.

  Furthermore, a third method for manufacturing a semiconductor device according to the present invention includes a step of forming an interlayer insulating film on a lower wiring formed on a semiconductor substrate, and forming a first coating film on the interlayer insulating film. A step of selectively etching the first coating film and the interlayer insulating film to form a groove, a step of forming a second coating film on the inner surface of the groove, and the second A step of sequentially etching a portion of the coating film and the interlayer insulating film located on the bottom surface of the groove to form a hole reaching the lower layer wiring; and a first surface on the inner surface of the groove and the hole Forming a conductive film; removing the first conductive film formed on the bottom surface of the hole to expose the surface of the lower wiring; and etching the exposed surface of the lower wiring. Forming the recess, and the groove and the hole. Embedding a second conductive film on the pre said recess, and a step of forming the upper wiring in the trench.

  According to the third method for manufacturing a semiconductor device, since the second coating film is formed in advance on the inner surface, particularly the bottom surface of the groove, the first conductive film formed on the bottom surface of the hole is removed. In addition, in the process of forming a recess by etching the surface of the underlying lower layer wiring, the interlayer insulating film under the bottom of the groove can be prevented from being excessively etched or damaged, and the wiring structure can be stably manufactured. can do. In this manufacturing method, since the interlayer insulating film can be selectively etched using the first coating film as a mask, the width of the groove is smaller than that of a general photoresist film as a mask, and the upper layer wiring There is also an advantage that a predetermined interval can be secured.

  In the third method of manufacturing a semiconductor device, the interior of the groove and the hole is formed between the step of forming the recess and the step of embedding the second conductive film in the groove, the hole and the recess. In addition, a step of forming a third conductive film can be performed. Further, the first coating film can be made of a conductive film or an insulating film, and the second coating film can also be made of a conductive film or an insulating film.

  In the first to third semiconductor device manufacturing methods according to the present invention, the dielectric constant of the interlayer insulating film can be 3.5 or less.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention suppress the excessive etching or damage to the interlayer insulating film under the upper layer wiring, thereby the upper layer and lower layer wiring. It is possible to stably manufacture the wiring structure by preventing the short circuit between them and the degradation of the wiring interlayer breakdown voltage. In addition, it is possible to provide a wiring structure having high reliability with respect to electromigration, stress migration, and the like at the connection portion between the plug and the wiring layer.

FIG. 6 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention. FIG. 6 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention. FIG. 6 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention. FIG. 6 is a process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention. Sectional drawing of the semiconductor device manufactured with the manufacturing method of the deformed semiconductor device based on 1st Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing of the semiconductor device manufactured with the manufacturing method of the deformed semiconductor device based on 2nd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment of this invention. Sectional drawing of the semiconductor device manufactured with the manufacturing method of the deformed semiconductor device based on 3rd Embodiment of this invention. Process sectional drawing which shows the principal part of the manufacturing method of the conventional semiconductor device.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings. In addition, the material, numerical value, etc. which are used by each embodiment are illustrations, Comprising: This invention is not limited to them. In addition, each embodiment can be appropriately changed without departing from the scope of the technical idea of the present invention, and combinations of the embodiments are also possible.

(Embodiment 1)
1 to 4 are process cross-sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention, and in particular, a buried wiring layer and wiring made of a material containing at least copper as a main component using a dual damascene method. A manufacturing method for forming plugs for connecting layers at once is illustrated. As shown in FIG. 1A, a source / drain region 103 is formed in a semiconductor substrate (silicon substrate) 101. Further, in a region on the semiconductor substrate 101 sandwiched between the source / drain regions 103, there is a gate 102 composed of a gate insulating film, a gate electrode, and sidewalls made of an insulating material formed on the left and right sides of the gate electrode. The source / drain regions 103 and the gate 102 constitute a MOS transistor.

  The interlayer insulating film 104 on the semiconductor substrate 101 includes a silicon oxide film, a silicon nitride film, and the like, and a plug 105 in which a refractory metal such as tungsten is buried in a contact hole reaching the source / drain region 103 is formed. An interlayer insulating film 106 is formed on the interlayer insulating film 104 and the plug 105. The interlayer insulating film 106 is formed by depositing a silicon oxide film (SiOC film) made of SiOC in which C (carbon) is added to silicon oxide (SiOx) to a thickness of about 200 nm by using, for example, a plasma CVD method. Obtainable. Strictly speaking, SiOC is SiOxCy, and films having various compositions of Si, O, and C can be formed depending on the deposition method and deposition conditions. In the following description, these are collectively referred to as SiOC films. Although described later, the SiOC film is a low dielectric constant film.

In the substrate having the above structure, as shown in FIG. 1B, the interlayer insulating film 106 is processed using the photolithography technique and the dry etching technique, and the wiring groove 107 is formed at a position where the upper surface of the plug 105 is exposed. Form. In FIG. 1B, the wiring groove 107 has a width of 100 nm and a depth of 200 nm, and extends linearly in a direction perpendicular to the paper surface. Subsequently, as shown in FIG. 1C, over the entire surface of the interlayer insulating film 106 and the wiring trench 107, for example, tantalum (Ta) is used as a target, and argon (Ar) / nitrogen (N ₂ ) mixed gas is used as a sputtering gas. A conductive film 108 made of tantalum nitride (TaN) is deposited to a thickness of about 10 nm using reactive sputtering. Next, for example, a Cu film or a Cu alloy film to be a copper plating seed film is deposited on the conductive film 108 by a sputtering method. The film thickness is set to be about 10 nm to 50 nm, preferably about 30 nm on the flat surface of the interlayer insulating film 106 other than the inside of the wiring trench 107.

Subsequently, a Cu plating film is deposited on the entire surface of the seed film so as to fill the wiring groove 107. The Cu plating film and the seed film are combined to form a conductive film 109. Accordingly, in FIG. 1C, the seed film and the Cu plating film are not distinguished from each other, and the laminated film of both is displayed as the conductive film 109. The same applies to the following description. The Cu plating film that fills the wiring trench 107 can be formed, for example, by electrolytic plating using the seed film as a growth base. As a plating solution for this purpose, for example, a mixed solution in which H ₂ SO ₄ (sulfuric acid) is added with 10% CuSO ₄ (copper sulfate) and an additive for improving the coverage of the Cu plating film in the step portion of the wiring groove 107 is used. Can be used. Subsequently, in order to obtain a high-quality Cu film, annealing treatment is performed at a predetermined temperature to relieve internal strain of the Cu plating film. Here, the TaN film as the conductive film 108 deposited prior to the formation of the conductive film 109 improves the adhesion of the Cu film, and the interlayer insulating films 104 and 106 in which Cu atoms exist around the wiring trench 107 It functions as a barrier that prevents diffusion into the semiconductor substrate 101.

  Next, as shown in FIG. 2A, an extra conductive film 108 and a conductive film 109 other than the inside of the wiring trench 107 deposited on the upper surface of the interlayer insulating film 107 are removed by a CMP method (chemical mechanical polishing method). The lower buried wiring made of the conductive film 109 is formed inside the wiring groove 107 by polishing and removing using the above. Next, as shown in FIG. 2B, a silicon carbide film (hereinafter referred to as a SiC film) or a silicon nitride carbide film (hereinafter referred to as a SiCN film) over the entire surface of the lower buried wiring and the interlayer insulating film 106. Is deposited to a thickness of about 50 nm using, for example, a plasma CVD method to form an etching stopper film 110.

Subsequently, an interlayer insulating film 111 made of a SiOC film having a low relative dielectric constant or the like is deposited on the surface of the etching stopper film 110 to a thickness of about 100 nm using, for example, a plasma CVD method. Next, as shown in FIG. 2C, a thin conductive film made of TaN, for example, is deposited on the interlayer insulating film 111 to a thickness of about 15 nm using a reactive sputtering method, and then a resist pattern by photolithography is used. Then, the conductive film pattern 112 is formed by patterning the conductive film using a dry etching technique. This conductive film pattern 112 has substantially the same shape and dimensions as the upper-layer buried wiring formed in the subsequent process, and has a hole-like shape in a predetermined portion located immediately above the lower-layer wiring made of the conductive film 109. An opening is formed. A damage layer is formed on the surface layer portion of the interlayer insulating film 111 by dry etching for forming the conductive pattern 112 and plasma ashing of the resist pattern after the dry etching. For example, HF: H ₂ O = 1: 100 It is desirable to remove the damaged layer by washing with dilute hydrofluoric acid.

  The conductive film pattern 112 may use an insulating film instead of the conductive film. In this case, it is necessary to select a material in which the underlying interlayer insulating film 111 is difficult to be etched when the film is patterned by etching, and the etching rate ratio with respect to the interlayer insulating film 111 is preferably 2 or more.

  Next, an interlayer insulating film 113 made of, for example, a SiOC film is deposited on the interlayer insulating film 111 and the conductive film pattern 112 to a thickness of about 300 nm by plasma CVD. At this time, the interlayer insulating film 113 is preferably made of a material having the same physical properties as the interlayer insulating film 111. Next, as shown in FIG. 3A, although not shown, a resist film pattern having an opening having the same shape as the upper-layer buried wiring is formed on the interlayer insulating film 113, and this is used as a mask. The interlayer insulating films 113 and 111 and the etching stopper film 110 are selectively etched sequentially. In this etching, a wiring groove 114 having a depth of 300 nm corresponding to the upper buried wiring is first formed in the interlayer insulating film 113, and the conductive pattern 112 is exposed at the bottom of the wiring groove. Since the etching rate of the conductive film pattern 112 is low, the etching is almost stopped. After the conductive film pattern 112 is exposed, etching of the interlayer insulating film 111 proceeds from the hole-shaped opening provided in the conductive film pattern 112 using the conductive film pattern 112 as a mask, and the etching stopper film 110 is exposed. Etching is stopped because the etching hardly proceeds.

Thereafter, the etching conditions are further changed, and the etching stopper film 110 is etched using the conductive film pattern 112 and the interlayer insulating film 111 as a mask to expose the conductive film (Cu plating film) 109. Thus, a hole 115 that reaches the conductive film 109 through the interlayer insulating film 111 and the etching stopper film 110 is formed. The interlayer insulating films 113 and 111 need to be performed under a condition where the etching rate selection ratio with respect to the conductive film pattern 112 is high. For example, a CF-based mixed gas such as CF ₄ + C ₄ F ₈ + Ar can be used. . 3A shows a portion where the wiring groove 114 wider than the width of the lower buried wiring is formed for the sake of convenience, a wiring groove 114 having a width of 100 nm which is the same as the lower wiring width is shown in a portion not shown in the drawing. Is also formed.

  Next, as shown in FIG. 3B, a laminated conductive film 116 in which, for example, TaN and Ta films are sequentially laminated from the lower layer on the sidewalls and bottom surfaces of the wiring grooves 114 and the holes 115 and the interlayer insulating film 113, has a thickness of about 15 nm. Sedimentation. The laminated conductive film 116 is preferably deposited using an ion metal plasma sputtering method (IMP method). In the IMP method, a substrate to be processed is placed on a stage, a target made of a film material to be deposited is opposed to the substrate to be processed, a DC voltage or a high-frequency voltage is applied to the target in a sputtering gas atmosphere, and simultaneously from the stage. In this method, a material film is sputter deposited on a substrate to be processed while applying a high frequency bias to the substrate to be processed. When a high-frequency bias is applied to the non-processed substrate, a negative potential due to sputtering gas plasma is generated near the non-processed substrate, and positive material ions from the target can be attracted toward the target substrate. By this and by adjusting the sputtering gas pressure, the film can be deposited on the inner surface of the wiring groove 114 and the hole 115 having a high aspect ratio with good step coverage. This method can also be used for the deposition of the conductive film 108 (TaN) in the step of FIG. 1C and the deposition of a seed film made of Cu or Cu alloy.

  Next, as shown in FIG. 4A, all of the laminated conductive film 116 deposited on the bottom of the hole 115 is removed by the sputter etching method, and the exposed portion of the underlying buried wiring (conductive film 109) is further removed. ) Is dug to about 15 nm to form a recess. At this time, the etching rate of the laminated conductive film 116 at the bottom of the wiring groove 114 is larger than that of the laminated conductive film 116 at the bottom of the hole 115 due to a difference in aspect ratio between the wiring groove 114 and the hole 115, and faster than that at the bottom of the hole 115. Since it is etched, it is not removed, and the conductive film pattern 112 below it is sputter etched. However, when the conductive film pattern 112 is dug by about 15 nm, the etching is finished when the conductive film pattern 112 is etched by about 7 nm, and the entire conductive film pattern 112 is not removed.

  This sputter etching treatment can be performed continuously in the deposition of the laminated conductive film 116 in the chamber of the ion metal plasma sputtering apparatus. For example, the sputtering apparatus is provided with a high-frequency coil and a DC coil so as to surround the space between the target and the stage described above, and after sputter etching introduces a rare gas such as Ar or an inert gas into the chamber, A DC voltage is applied to the target, a high frequency voltage is applied to the stage, a high frequency voltage is applied to the high frequency coil, and a DC voltage is applied to the DC coil. Etching is carried out by ion bombardment of the laminated conductive film 116 with sputter etching gas plasma such as Ar generated by high frequency discharge in this way. The values of each DC voltage and each high-frequency voltage can be set independently, and may be set so that plasma is in an etching mode with respect to the laminated conductive film 116.

  Next, as shown in FIG. 4B, Cu or Cu is formed on the entire surface including the wiring trench 114, the laminated conductive film 116 in the hole 115, the conductive film pattern 112, and the conductive film 109 on the bottom of the hole 115. A seed film made of a Cu alloy is deposited by using the IMP method, and then a Cu plating film is deposited by the electrolytic plating method. Thus, the conductive film 117 made of the seed film and the Cu plating film is embedded in the wiring groove 114 and the hole 115. Next, the upper-layer buried wiring structure constituted by the conductive film 117 is obtained by polishing and removing the conductive film 117 and the laminated conductive film 116 deposited on portions other than the inside of the wiring trench 114, the hole 115 by the CMP method. Form. Here, the portion embedded in the wiring groove 114 of the conductive film 117 becomes the upper layer embedded wiring, and the portion embedded in the hole 115 becomes the connection plug. In addition, the contact area between the lower buried wiring and the plug is increased by performing the etching of the conductive film 109 of the lower buried wiring in the process of FIG. 4A. Electromigration and stress migration in this portion are increased. The reliability of the equal connection characteristics can be improved.

  In this embodiment, the width of the conductive film pattern 112 may be the same as that of the wiring groove 114. However, when the wiring groove 114 is formed by etching in the process of FIG. Since the film has to be a film, for example, the dimension is made larger by about 10 nm on one side than the width of the wiring groove 114, and the wiring groove 114 or the entire upper-layer buried wiring is formed inside the region of the conductive film pattern 112. Is desirable. In this way, even if the resist pattern of the wiring groove 114 is misaligned with the conductive film pattern 112 in the photolithography process, a part of the wiring groove 114 is displaced from the conductive film 112, and the interlayer insulating film 111. Unnecessary portions are not etched. In addition, the SiC film or the SiCN film as the etching stopper film 110 employed in the present embodiment prevents the Cu constituting the conductive film 109 of the lower buried wiring from diffusing into the interlayer insulating films 111 and 113, thereby insulating them. It plays the role of maintaining sex. In the semiconductor device according to the present embodiment, since the interlayer insulating film 113 is thicker than the interlayer insulating film 111, the height of the upper buried wiring is higher than the height of the plug, but the heights of both may be the same. Thus, by making the height of the plug equal to or less than the height of the wiring, the electrical resistance can be further reduced and the effect of the present invention is further exhibited.

  The manufacturing method according to the first embodiment of the present invention may be modified as follows. FIG. 5 is a cross-sectional view of a semiconductor device formed by the modified manufacturing method. This semiconductor device manufacturing method is different in that, after the steps from FIG. 1A to FIG. 4A are completed, a conductive film 118 made of, for example, a Ta film is deposited by about 8 nm using the IMP method. After the deposition of the conductive film 118, a seed film or a Cu plating film made of Cu or a Cu alloy is deposited as in FIG. 4B, and the conductive films 116, 117, and 118 are embedded in the wiring trench 114 and the hole 115. Then, an upper layer embedded wiring is formed.

  With the structure manufactured by this method, it becomes possible to further improve the reliability of connection characteristics related to copper wiring, such as electromigration and stress migration, particularly in the connection portion between the plug portion of the upper buried wiring and the lower buried wiring. . In the method according to the present embodiment described first, the film thickness of the conductive film pattern 112 on the bottom surface of the wiring groove 114 is thinned by sputter etching (FIG. 4A), but in the modified method, the conductive film 118 is formed. Therefore, the barrier property against the thinned conductive film 112 can be ensured more reliably.

  In the manufacturing method according to the first embodiment of the present invention, a conductive film pattern 112 having essentially the same shape as the upper-layer buried wiring is formed in advance in the step of FIG. In this step, etching for digging the conductive film 109 of the lower buried wiring is performed. For this reason, even if the digging etching becomes excessive, the etching rate varies within the semiconductor substrate, and at least a part of the laminated conductive film 116 on the bottom surface of the wiring groove 114 is completely removed, the conductive film pattern 112 is not removed. As a result, the underlying interlayer insulating film 111 can be prevented from being etched and the interlayer insulating film 111 can be prevented from being damaged, and the wiring structure can be manufactured stably and with high yield by the dual damascene method. The thickness of the conductive film pattern 112 is such that when the laminated conductive film 116 at the bottom of the hole 115 is removed and the etching of the conductive film 109 of the lower buried wiring is completed, the conductive film pattern 112 itself remains. What is necessary is just to set to such a film thickness.

  From the above, according to the manufacturing method according to the first embodiment, reliability between buried wiring layers such as electromigration and stress migration can be ensured, and short circuit defects between upper and lower buried wiring layers and deterioration of breakdown voltage between buried wiring layers are suppressed. A highly reliable semiconductor device can be obtained.

(Embodiment 2)
6 to 9 are process sectional views showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention, and show a part of the semiconductor device in which a MOS transistor is formed on a semiconductor substrate. In this embodiment, first, the same steps as those in the first embodiment shown in FIGS. 1A to 1C and FIG. 2A are performed. Therefore, detailed description of this process part is omitted. 6 to 9, the same parts as those of the semiconductor device of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. After performing the step of FIG. 2C, as shown in FIG. 6A, the SiC film or the SiCN film is formed on the lower buried wiring and the interlayer insulating film 106 made of the conductive film 109 by using, for example, a plasma CVD method. An etching stopper film 110 made of is deposited to a thickness of about 50 nm, and then an interlayer insulating film 120 made of SiOC is deposited to a thickness of about 400 nm on the surface of the etching stopper film 110 using, for example, a plasma CVD method.

  Next, as shown in FIG. 6B, using a photolithography technique and a dry etching technique, a region overlapping with the lower layer wiring of the interlayer insulating film 120 is selectively etched to form a wiring trench 121 having a depth of 300 nm. To do. In FIG. 6B, the wiring groove 121 having a width larger than the width of the lower layer wiring is shown, but a wiring groove having a width of 100 nm is formed in other regions not shown in the drawing as in the case of the lower layer wiring. Next, the conductive film 122 made of TaN is formed to a thickness of about 10 nm under the same conditions as in the first embodiment by using, for example, the IMP method so as to cover the entire surface of the interlayer insulating film 120 including the wiring trench 121. accumulate.

  Next, as illustrated in FIG. 7A, a photoresist film 123 is formed so as to cover the wiring trench 121. This photoresist film 123 has an opening pattern with a diameter of 100 nm on the lower buried wiring. When patterning the photoresist film 123, if the photoresist film thickness becomes non-uniform due to the step (depth) of the wiring groove 121 and patterning failure occurs, dry etching or After removing the excess photoresist film 123 on the interlayer insulating film 120 by using the CMP method, leaving the photoresist film only in the wiring trench 121 to flatten the entire surface, and then applying the photoresist film again from above. Perform patterning. In this way, the photoresist film thickness at the portion to be patterned becomes uniform, and the aperture pattern can be formed accurately.

  Next, as shown in FIG. 7B, when the conductive film 122 and the interlayer insulating film 120 are selectively dry-etched using the photoresist film 123 as a mask and the surface of the etching stopper film 110 is exposed, the etching is almost advanced. Etching is stopped because it disappears. Although a conductive film is used as the film 122, an insulating film may be used. In this case, it is desirable that the underlying interlayer insulating film 120 can be selectively etched in this etching, so that the etching rate ratio of the film 122 to the interlayer insulating film 120 is desirably 2 or more. Next, the etching conditions are changed, and the etching stopper film is selectively etched using the interlayer insulating film 120 as a mask to form a hole 124 to expose the surface of the conductive film 109 made of Cu of the lower buried wiring.

  Next, as shown in FIG. 8A, a laminated conductive film 125 in which, for example, a TaN film and a Ta film are sequentially laminated from the lower layer is formed on the interlayer insulating film 120 including the side wall and bottom surface of the wiring trench 121 and the hole 124. Using this method, the film is deposited to a thickness of about 15 nm under the same conditions as in the first embodiment. Next, as shown in FIG. 8B, the stacked conductive film 125 deposited on the bottom of the hole 124 is removed by a sputter etching method using a rare gas such as Ar or an inert gas as a sputter etching gas, and the hole 124 is further removed. A portion of the conductive film 109 constituting the lower buried wiring exposed below is dug by about 15 nm. At this time, the laminated conductive film 125 at the bottom of the wiring groove 121 is removed at a higher etching rate than the laminated conductive film 125 at the bottom of the hole 124 due to the difference in aspect ratio between the cross sections of the wiring groove 121 and the hole 124. After the conductive film 125 is completely removed, a part of the lower conductive film 122 is also sputter etched. However, everything is not etched, and the conductive film 122 at the bottom of the wiring trench 121 is only etched by about 7 nm at the end of the digging sputter etching. This sputter etching process can be performed in the chamber of the ion metal plasma sputtering apparatus, under the same conditions as in the first embodiment, following the deposition of the laminated conductive film 125.

  Next, as shown in FIG. 9, Cu is formed on the entire surface including the conductive film 122 and the laminated conductive film 125 in the wiring trench 121, the laminated conductive film 125 in the hole 124, and the conductive film 109 on the bottom surface of the hole 124. Alternatively, a seed film made of a Cu alloy is deposited by using the IMP method, and then a Cu plating film is deposited by the electrolytic plating method. Thus, the conductive film 126 made of the seed film and the Cu plating film is embedded in the wiring groove 121 and the hole 124. Next, the upper layer embedded wiring constituted by the conductive film 126 by polishing and removing the conductive films 122 and 126 and the laminated conductive film 125 deposited in portions other than the inside of the wiring trench 121 and the hole 124 by the CMP method. Form a structure. A portion embedded in the wiring groove 121 of the conductive film 126 forms an upper layer embedded wiring, and a portion embedded in the hole 115 forms a connection plug. Further, the contact area between the lower layer wiring and the plug is increased by digging into the conductive film 109 of the lower layer embedded wiring in the step of FIG. 8B, and connection characteristics such as electromigration and stress migration in this portion. Reliability can be improved.

  Although the wiring groove 121 is formed deeper than the hole 124 and the height of the upper buried wiring is higher than the height of the plug, the height of both may be the same. Thus, by making the height of the plug equal to or less than the height of the wiring, the electrical resistance can be further reduced and the effect of the present invention is further exhibited.

  The manufacturing method according to the second embodiment of the present invention may be modified as follows. FIG. 10 is a cross-sectional view of a semiconductor device formed by the modified manufacturing method. This semiconductor device manufacturing method is different in that, after the steps up to FIG. 8B are completed in accordance with the manufacturing method according to the present embodiment, a conductive film 127 made of, for example, a Ta film is deposited by about 8 nm using the IMP method. . After deposition of the conductive film 127, a conductive film 126 made of both of these films is formed by depositing a seed film made of Cu or a Cu alloy and a Cu plating film inside the wiring groove 121 and the hole 124 as in FIG. Then, the conductive films 122, 126, 127 and the laminated conductive film 125 are embedded in the wiring trench 121 and the hole 124 to form an upper layer embedded wiring.

  The structure manufactured by this method can further improve the reliability of connection characteristics related to copper wiring, such as electromigration and stress migration, especially at the connection between the plug portion of the upper embedded wiring and the lower embedded wiring. It becomes. In the method according to the second embodiment described at the beginning, the film thickness of the conductive film 122 on the bottom surface of the wiring groove 121 is thinned by sputter etching (FIG. 8B), but in the modified method, the conductive film 127 is formed. Therefore, the barrier property against the thinned conductive film 122 can be more reliably ensured.

  In the manufacturing method according to the second embodiment of the present invention, the conductive film 122 is formed in advance in the step of FIG. 6B, and then the conductive film 109 of the lower buried wiring in the step of FIG. 8B. Etching to dig in. For this reason, even if the digging etching becomes excessive, the etching rate varies within the semiconductor substrate, and even if at least a part of the laminated conductive film 125 on the bottom surface of the wiring groove 121 is completely removed, the conductive film 122 is still below. As a result, the underlying interlayer insulating film 120 is etched and the interlayer insulating film 120 is prevented from being damaged, and the wiring structure can be manufactured stably and with high yield by the dual damascene method. The thickness of the conductive film 122 is such that when the laminated conductive film 125 at the bottom of the hole 124 is removed and the etching of the conductive film 109 of the lower buried wiring is completed, the conductive film is formed on the bottom surface of the wiring groove 121. The film thickness may be set such that 122 itself remains.

(Embodiment 3)
11 to 14 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention, and show a part of the semiconductor device in which a MOS transistor is formed on a semiconductor substrate. In this embodiment, first, the same steps as those in the first embodiment shown in FIGS. 1A to 1C and FIG. 2A are performed. Therefore, detailed description of these process parts is omitted. Also, in FIGS. 11 to 14, the same reference numerals are given to the same parts as those of the semiconductor device of the first embodiment, and description thereof is omitted. After performing the process of FIG. 2A, as shown in FIG. 11A, the SiC film or the SiCN film is formed on the lower buried wiring and the interlayer insulating film 106 made of the conductive film 109 by using, for example, a plasma CVD method. An etching stopper film 110 made of is deposited to a thickness of about 50 nm, and then an interlayer insulating film 120 made of SiOC is deposited to a thickness of about 400 nm on the surface of the etching stopper film 110 using, for example, a plasma CVD method. Further, a conductive film 130 made of TaN, for example, is deposited to a thickness of about 30 nm using the IMP method so as to cover the interlayer insulating film 120.

  Next, as shown in FIG. 11B, using the photolithography technique and the dry etching technique, only the conductive film 130 is first selectively etched, and then the interlayer insulating film 120 is formed using the conductive film 130 as a mask. By selectively performing dry etching, a wiring trench 131 having a depth of 300 nm is formed on the lower buried wiring. Although the film 130 is a conductive film, it may be an insulating film. In this case, it is necessary to use a material that can selectively etch the film 130 with respect to the interlayer insulating film 120, and the etching rate ratio of the film 130 to the interlayer insulating film 120 is desirably 2 or more. In FIG. 11B, the wiring groove 131 having a width larger than the width of the lower layer wiring is shown. However, a wiring groove having a width of 100 nm is formed in other regions not shown in the drawing as in the case of the lower layer wiring. Next, a conductive film 132 made of TaN, for example, is deposited to a thickness of about 10 nm so as to cover the inside of the wiring trench 131 and the conductive film 130 under the same conditions as in the first embodiment by using the IMP method. .

  Next, as shown in FIG. 12A, a photoresist film 133 is formed so as to cover the wiring trench 131. This photoresist film 133 has an opening pattern on the lower buried wiring. When patterning the photoresist film 133, if the photoresist film thickness becomes non-uniform due to the step (depth) of the wiring groove 131 and patterning failure occurs, the first photoresist film is formed as in the second embodiment. After coating, the excess photoresist film 133 formed outside the wiring trench 131 is removed by dry etching or CMP, and the entire surface is planarized so that the photoresist remains only in the wiring trench 131. A photoresist film is applied again to pattern the openings.

  Next, as shown in FIG. 12B, the conductive film 132 and the interlayer insulating film 120 are selectively dry-etched using the photoresist film 133 as a mask, and when the surface of the etching stopper film 110 is exposed, the etching almost proceeds. Etching is stopped because it disappears. In this embodiment, the film 132 is a conductive film, but an insulating film may be used. In this case, it is preferable that the etching in this step can be selectively performed with the underlying interlayer insulating film 120, so that the etching rate ratio of the film 132 to the interlayer insulating film 120 is desirably 2 or more. Next, the etching conditions are changed and the etching stopper film 110 is selectively etched using the interlayer insulating film 120 as a mask to form holes 134 to expose the surface of the conductive film 109 made of Cu of the lower buried wiring.

  Next, as shown in FIG. 13A, a laminated conductive film 135 in which, for example, a TaN film and a Ta film are sequentially laminated from the lower layer is formed on the interlayer insulating film 120 including the side wall and bottom surface of the wiring trench 131 and the hole 134. Using this method, the film is deposited to a thickness of about 15 nm under the same conditions as in the first embodiment. Next, as shown in FIG. 13B, the laminated conductive film 135 at the bottom of the hole 134 is removed by a sputter etching method, and one of the conductive films 109 constituting the lower buried wiring exposed below the hole 134 is obtained. The part is dug about 15 nm. At this time, the laminated conductive film 135 at the bottom of the wiring groove 131 is etched at a higher etching rate than the laminated conductive film 135 at the bottom of the hole 134 due to the difference in the aspect ratio between the cross sections of the wiring groove 131 and the hole 134. After the laminated conductive film 135 is completely removed, a part of the conductive film 132 thereunder is also sputter etched. However, everything is not etched, and the conductive film 132 at the bottom of the wiring trench 131 is only etched by about 7 nm at the end of the digging sputter etching. This sputter etching process can be performed in the chamber of the ion metal plasma sputtering apparatus, under the same conditions as in the first embodiment, following the deposition of the laminated conductive film 135.

  Subsequently, as shown in FIG. 14, Cu is formed on the entire surface including the conductive film 132 and the laminated conductive film 135 in the wiring trench 131, the laminated conductive film 135 in the hole 134, and the conductive film 109 on the bottom surface of the hole 135. Alternatively, a seed film made of a Cu alloy is deposited by using the IMP method, and then a Cu plating film is deposited by the electrolytic plating method. Thus, the conductive film 136 made of the seed film and the Cu plating film is embedded in the wiring groove 131 and the hole 134. Next, the conductive film 132, 136, and the laminated conductive film 135 deposited on portions other than the inside of the wiring trench 131, the hole 134 are polished and removed by CMP to remove the upper buried wiring composed of the conductive film 136. Form a structure. A portion embedded in the wiring groove 131 of the conductive film 136 forms an upper layer embedded wiring, and a portion embedded in the hole 134 forms a connection plug. In addition, the contact area between the lower layer wiring and the plug is increased by digging and etching the conductive film 109 in the step of FIG. 13B, and the reliability of connection characteristics such as electromigration and stress migration in this portion is increased. Can be improved.

  The depth of the wiring groove 131 is formed deeper than the depth of the hole 134 so that the height of the upper buried wiring is higher than the height of the plug. However, the height of both may be the same. Thus, by making the height of the plug equal to or less than the height of the wiring, the electrical resistance can be further reduced and the effect of the present invention is further exhibited.

  The manufacturing method according to the third embodiment of the present invention may be modified as follows. FIG. 15 is a cross-sectional view of a semiconductor device formed by the modified manufacturing method. This semiconductor device manufacturing method is different in that, after the steps up to FIG. 13B are completed according to the manufacturing method according to the present embodiment, a conductive film 137 made of, for example, a Ta film is deposited by about 8 nm using the IMP method. . After the deposition of the conductive film 137, a seed film or a Cu plating film made of Cu or Cu alloy is deposited inside the wiring trench 131 and the hole 134 in the same manner as in the step of FIG. The films 132 and 137, the conductive film 136 made of a seed film and a Cu plating film, and the laminated conductive film 135 are embedded to form an upper-layer embedded wiring.

  The structure manufactured by this method can further improve the reliability of connection characteristics related to copper wiring, such as electromigration and stress migration, especially at the connection between the plug portion of the upper embedded wiring and the lower embedded wiring. It becomes. In the method according to the third embodiment described at the beginning, the thickness of the conductive film 132 on the bottom surface of the wiring groove 131 is thinned by sputter etching (FIG. 13B). However, in the modified method, the conductive film 137 is used. Therefore, the barrier property against the thinned conductive film 132 can be more reliably ensured.

  In the manufacturing method according to the third embodiment of the present invention, the conductive film 132 is formed in advance in the step of FIG. 11B, and then the conductive film 109 of the lower buried wiring in the step of FIG. 13B. Etching to dig in. Therefore, similarly to the second embodiment, it is possible to prevent the underlying interlayer insulating film 120 from being etched by the conductive film 132 and to prevent the interlayer insulating film 120 from being damaged, and to stabilize the wiring structure by the dual damascene method. It can be manufactured with good yield. The thickness of the conductive film 132 is such that when the laminated conductive film 135 at the bottom of the hole 134 is removed and the etching of the conductive film 109 of the lower buried wiring is completed, the conductive film is formed on the bottom surface of the wiring groove 131. The film thickness may be set such that 132 itself remains.

  Further, in the manufacturing method according to the present embodiment, the conductive film 130 is made of a material that is difficult to be etched during etching of the interlayer insulating film 120 in the step of FIG. Acts as When the wiring trench 131 is formed (step of FIG. 11B), when only the photoresist film is used as a dry etching mask, the photoresist film is also etched and the width of the wiring trench 131 is widened so that the interval between the upper buried wirings is increased. There is a problem of narrowing. However, by using the conductive film 130 as a hard mask as in the present embodiment, the distance between the upper-layer embedded wirings can be ensured accurately, and the deterioration of the breakdown voltage between the wirings and the short circuit between the wirings can be prevented. .

In the above first to third embodiments, the TaN film is exemplified as the material of the conductive film pattern 112 and the conductive films 122, 130, and 132. However, the present invention is not limited to this. Refractory metals such as tantalum (Ta), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), ruthenium nitride (RuN), cobalt (Co), cobalt tungsten phosphorus (CoWP), or a compound of a refractory metal or An alloy or an aluminum (Al) metal may be used. Alternatively, an insulating film that has a selectivity ratio between the interlayer insulating films 111 and 120 and the sputter etching rate and is difficult to be sputter etched may be used as a material. Examples of this insulating film include SiN, SiCN, SiC, and a SiO ₂ film having a relative dielectric constant of 3.9 to 4.0.

  As the material of the interlayer insulating films 111 and 120, a material having a low relative dielectric constant is used as the element size of the semiconductor integrated circuit becomes minute and the operation speed of the circuit increases. The main material is SiOC shown in the above embodiments, but other than this, SiOCH or the like is possible. Such an interlayer insulating film can be manufactured by a low temperature plasma CVD method or a spin coating method using a silicon organic compound as a raw material. The relative dielectric constant of 3.5 to 2.0 can be used depending on the application, and preferably 3.0 to 2.0. However, the lower the relative dielectric constant, the lower the density and the higher the etching rate. Have. In particular, an insulating material such as porous SiOC having many fine voids inside has a low relative dielectric constant.

  INDUSTRIAL APPLICABILITY The present invention is useful for stably forming a multilayer wiring having high reliability with respect to electromigration, stress migration, etc. at a wiring interlayer connection portion by using a dual damascene method.

101 Semiconductor substrate 102 Gate 103 Source / drain regions 104, 106, 111, 113, 120 Interlayer insulating film 105 Plugs 107, 114, 121, 131 Wiring grooves 108, 109, 117, 118, 122, 126, 127, 130, 132 136, 137 Conductive film 110 Etching stopper film 112 Conductive film pattern 115, 124, 134 Hole 116, 125, 135 Laminated conductive film 123, 133 Photoresist film

Claims (24)

Forming a first interlayer insulating film on a lower layer wiring formed on a semiconductor substrate;
Forming a pattern comprising a film having an opening at a position where an upper wiring on the first interlayer insulating film is to be formed;
Forming a second interlayer insulating film on the pattern and on the first interlayer insulating film;
Selectively etching the second interlayer insulating film located on the pattern to expose the pattern and forming a groove;
Selectively etching the first interlayer insulating film using the pattern as a mask to form a hole reaching the lower layer wiring;
Forming a first conductive film on the inner surface of the groove and the hole;
Removing the first conductive film formed on the bottom surface of the hole to expose the surface of the lower layer wiring;
Etching the exposed surface of the lower layer wiring to form a recess;
Embedding a second conductive film in the groove, the hole and the recess, and forming the upper layer wiring in the groove.   A step of forming a third conductive film in the groove and the hole between the step of forming the recess and the step of embedding the second conductive film in the groove, the hole and the recess. The method of manufacturing a semiconductor device according to claim 1, wherein:   The method of manufacturing a semiconductor device according to claim 1, wherein the film constituting the pattern is made of a conductive film or an insulating film.   The semiconductor device according to claim 1, wherein a relative dielectric constant of the first interlayer insulating film is 3.5 or less.   4. The method of manufacturing a semiconductor device according to claim 3, wherein an etching rate ratio of the insulating film constituting the pattern with respect to the first interlayer insulating film is 2 or more. Forming an interlayer insulating film on a lower layer wiring formed on a semiconductor substrate;
Selectively etching the interlayer insulating film to form a groove;
Forming a coating film on the inner surface of the groove;
A step of sequentially and selectively etching a portion of the covering film and the interlayer insulating film located on the bottom surface of the groove to form a hole reaching the lower layer wiring;
Forming a first conductive film on the inner surface of the groove and the hole;
Removing the first conductive film formed on the bottom surface of the hole to expose the surface of the lower layer wiring;
Etching the exposed surface of the lower layer wiring to form a recess;
Embedding a second conductive film in the groove, the hole, and the recess, and forming an upper layer wiring in the groove.   A step of forming a third conductive film in the groove and the hole between the step of forming the recess and the step of embedding the second conductive film in the groove, the hole and the recess. The method of manufacturing a semiconductor device according to claim 6, wherein:   8. The method of manufacturing a semiconductor device according to claim 6, wherein the coating film is made of a conductive film or an insulating film. Forming an interlayer insulating film on a lower layer wiring formed on a semiconductor substrate;
Forming a first coating film on the interlayer insulating film;
Selectively etching the first coating film and the interlayer insulating film to form a groove;
Forming a second coating film on the inner surface of the groove;
A step of sequentially and selectively etching a portion of the second coating film and the interlayer insulating film located on the bottom surface of the groove to form a hole reaching the lower layer wiring;
Forming a first conductive film on the inner surface of the groove and the hole;
Removing the first conductive film formed on the bottom surface of the hole to expose the surface of the lower layer wiring;
Etching the exposed surface of the lower layer wiring to form a recess;
Embedding a second conductive film in the groove, the hole, and the recess, and forming an upper layer wiring in the groove.   A step of forming a third conductive film in the groove and the hole between the step of forming the recess and the step of embedding the second conductive film in the groove, the hole and the recess. The method of manufacturing a semiconductor device according to claim 9, wherein:   11. The method of manufacturing a semiconductor device according to claim 9, wherein the first covering film is made of a conductive film or an insulating film.   11. The method of manufacturing a semiconductor device according to claim 9, wherein the second coating film is made of a conductive film or an insulating film.   The method of manufacturing a semiconductor device according to claim 6, wherein a relative dielectric constant of the interlayer insulating film is 3.5 or less. Lower layer wiring formed on a semiconductor substrate;
An upper layer wiring formed in an upper layer of the lower layer wiring;
A plug for electrically connecting the lower layer wiring and the upper layer wiring;
A pattern formed of a film formed under the upper layer wiring in contact with the bottom surface of the upper layer wiring;
A conductive film formed on a side wall of the upper layer wiring and a side wall of the plug;
A semiconductor device, wherein a recess is formed on an upper surface of the lower layer wiring located immediately below the plug.   The semiconductor device according to claim 14, wherein the plug and the lower layer wiring are in direct contact with each other.   15. The semiconductor device according to claim 14, wherein the upper layer wiring is formed in a region inside the pattern.   15. The semiconductor device according to claim 14, wherein the upper layer wiring and the plug are formed by being embedded in an interlayer insulating film, and the relative dielectric constant of the interlayer interlayer insulating film is 3.5 or less.   The interlayer insulating film includes a first interlayer insulating film and a second interlayer insulating film, the plug is embedded in the first interlayer insulating film, and the upper layer wiring is embedded in the second interlayer insulating film, The semiconductor device according to claim 17, wherein a relative dielectric constant of the first interlayer insulating film is 3.5 or less.   The semiconductor device according to claim 14, wherein the film constituting the pattern is a conductive film or an insulating film. Lower layer wiring formed on a semiconductor substrate;
An upper layer wiring formed in an upper layer of the lower layer wiring;
A plug for electrically connecting the lower layer wiring and the upper layer wiring;
A coating film formed on the side wall and bottom surface of the upper layer wiring;
A second conductive film formed on the coating film formed on the side wall of the upper layer wiring and on the side wall of the plug;
A semiconductor device, wherein a recess is formed on an upper surface of the lower layer wiring located immediately below the plug.   21. The semiconductor device according to claim 20, wherein the plug and the lower layer wiring are in direct contact with each other.   21. The semiconductor device according to claim 20, wherein the upper layer wiring and the plug are formed by being embedded in an interlayer insulating film, and the relative dielectric constant of the interlayer insulating film is 3.5 or less.   21. The semiconductor device according to claim 20, wherein the coating film is a conductive film or an insulating film.   24. The semiconductor device according to claim 14, wherein a height of the upper layer wiring is equal to or higher than a height of the plug.

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