JP2011166054A - Semiconductor device, circuit substrate, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the fatigue life of solder by suppressing the fatigue of the solder by a resin core in the vicinity of an interface between the solder and an electrode. <P>SOLUTION: There are provided a connection pad 12 formed on a semiconductor substrate 11, a wire 21 electrically connected with the connection pad, a columnar electrode 22 electrically connected with the wire, a resin core 31 formed on the surface of the columnar electrode, solder 32 formed on the columnar electrode around the resin core and covering the resin core, and a sealing layer 26 formed on the semiconductor substrate around the electrode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a circuit board, and a method for manufacturing a semiconductor device.

  Conventionally, there is a semiconductor device in which a plurality of columnar electrodes are provided on a semiconductor substrate, a sealing layer is stacked on the semiconductor substrate around the columnar electrode, and a solder bump is formed on the top surface of the columnar electrode (for example, Patent Document 1). When mounting the semiconductor device on the circuit board, the semiconductor device is faced down to the circuit board, the solder bumps are placed on the electrodes of the circuit board, and the solder bumps are reflowed.

JP 2008-218731 A

However, when heat generation and cooling of the semiconductor device are repeated due to the use of the semiconductor device, the stress of the solder vibrates due to the difference between the coefficient of thermal expansion of the semiconductor substrate and the coefficient of thermal expansion of the circuit board. .
Therefore, the problem to be solved by the present invention is to suppress the fatigue of the solder and improve the fatigue life of the solder.

  In order to solve the above problems, a semiconductor device according to the present invention includes a semiconductor substrate, a connection pad formed on the semiconductor substrate, a wiring electrically connected to the connection pad, and the wiring and the electrical Connected electrodes, a core formed on the surface of the electrode, a solder covering the core and formed on the electrode around the core, and formed on the semiconductor substrate around the electrode The sealing layer made was provided.

Preferably, the core is made of a polyimide resin or an epoxy resin.
Preferably, the electrode is a land formed on one end of the wiring.
Preferably, the electrode is an external connection electrode.
Preferably, the core is provided on a surface of the external connection electrode.

  In the circuit board according to the present invention, the solder in the semiconductor device and the electrode of the circuit board are connected.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a core on the surface of an electrode of an electronic component, a step of covering the core with solder, and forming the solder on the surface of the electrode around the core; It was decided to include.

Preferably, the core is made of a polyimide resin or an epoxy resin.
Preferably, the electrode is a land formed on one end of the wiring.
Preferably, the electrode is an external connection electrode.
Preferably, the core is formed on a surface of the external connection electrode.

  According to the present invention, the core prevents the solder from fatigue near the interface between the solder and the electrode.

1 is a perspective view of a semiconductor device according to a first embodiment of the present invention. Sectional drawing of the semiconductor device in the embodiment. Sectional drawing of the mounting structure of the electronic component in the embodiment. Sectional drawing of the wafer before dividing into a semiconductor device in the same embodiment. FIG. 4 is a cross-sectional view in one step of a method for forming bumps on a wafer in the same embodiment. Sectional drawing in the process of following FIG. Sectional drawing in the process of following FIG. Sectional drawing in the process of following FIG. Sectional drawing of the semiconductor device in 2nd Embodiment of this invention. Sectional drawing of the mounting structure of the electronic component in the embodiment.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated using drawing. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

[First Embodiment]
FIG. 1 is a perspective view of the semiconductor device 1. FIG. 2 is a cross-sectional view of the semiconductor device 1.
As shown in FIGS. 1 and 2, the semiconductor device 1 includes an electronic component 10 and a bump 30 provided on the surface of a columnar electrode (electrode) 22 of the electronic component 10.

Hereinafter, the electronic component 10 will be described.
The electronic component 10 is a packaged semiconductor chip. That is, the electronic component 10 includes the semiconductor substrate 11, the wiring 21, the columnar electrode (external connection electrode) 22, the insulating film 25, the sealing layer 26, and the like.
The semiconductor substrate 11 is made of silicon or the like, and an integrated circuit is formed on the surface of the semiconductor substrate 11. A plurality of connection pads 12 are formed on the surface of the semiconductor substrate 11, and the connection pads 12 are connected to LSI wiring. The passivation film 13 is formed on the surface of the semiconductor substrate 11 and covers the integrated circuit. For example, the passivation film 13 is made of silicon oxide or silicon nitride. The passivation film 13 is provided with an opening 13a for exposing the connection pad 12.

  An insulating film 25 is formed on the passivation film 13. The insulating film 25 is made of epoxy resin, polyimide resin, or other resin. For example, the insulating film 25 can be made of a high-functional plastic material such as polyimide (PI) or polybenzoxazole (PBO), a plastic material such as epoxy, phenol, or silicon, or a composite material thereof. .

  The insulating film 25 is provided with an opening 25 a that exposes the connection pad 12. The opening 25a of the insulating film 25 is smaller than the opening 13a of the passivation film 13, and the connection pad 12 and the insulating film 25 are in close contact with each other at the outer periphery of the opening 25a.

  An electroplating seed layer 20 is formed on the surface of the insulating film 25. The electroplating seed layer 20 is a copper (Cu) thin film, a titanium (Ti) thin film, a thin film obtained by laminating copper on titanium, or other metal thin film. Patterned into a shape. A part of the electroplating seed layer 20 is laminated on the connection pad 12, and the electroplating seed layer 20 is connected to the connection pad 12 through the openings 13a and 25a. The insulating film 25 may not be formed, and the electroplating seed layer 20 may be formed on the passivation film 13.

A wiring 21 is laminated on the seed layer 20 for electrolytic plating. The wiring 21 is made of copper plating or other metal plating. In plan view, the wiring 21 is patterned into a predetermined shape, and the planar shape of the wiring 21 and the planar shape of the electroplating seed layer 20 are substantially the same. The wiring 21 is thicker than the electroplating seed layer 20.
Each of the electroplating seed layer 20 and wiring 21 is arranged so as to be electrically insulated from the other electroplating seed layer 20 and wiring 21 stacks.

A columnar columnar electrode 22 is formed on one end of the wiring 21. A portion 21 a serving as a base of the columnar electrode 22 in the wiring 21 is a land. The columnar electrode 22 is made of copper or other metal. The height (thickness) of the columnar electrode 22 is larger than the thickness of the wiring 21.
Each laminated body of the electroplating seed layer 20 and the wiring 21 electrically connects the corresponding connection pad 12 and the columnar electrode 22.

  A sealing layer 26 is formed on the insulating film 25. The wiring 21 is covered with a sealing layer 26 except for a portion overlapping the columnar electrode 22. The surface of the sealing layer 26 is provided flush with the top surface (surface) of the columnar electrode 22, and the top surface of the columnar electrode 22 is exposed without being covered by the sealing layer 26. The sealing layer 26 is made of an epoxy resin, a polyimide resin, or other insulating resin, and is preferably made of a thermosetting resin (eg, epoxy resin) containing a filler (eg, glass filler). The sealing layer 26 protects the columnar electrode 22 from its side surface. Further, the sealing layer 26 protects the electroplating seed layer 20 and the wiring 21 from above them. The sealing layer 26 has a light shielding property.

Hereinafter, the bump 30 will be described.
The bump 30 has a resin core 31 and solder 32. The resin core 31 is formed on the central portion of the top surface of the columnar electrode 22. The resin core 31 is provided in a columnar shape, and is provided in a state of being upright with respect to the top surface of the columnar electrode 22. The resin core 31 is in close contact with the top surface of the columnar electrode 22. The resin core 31 is made of a heat-resistant resin material that can withstand the reflow temperature of the solder 32. For example, the resin core 31 is made of a polyimide resin or an epoxy resin. The shape of the resin core 31 may be a frustum shape.

  The resin core 31 is embedded in the solder 32. The solder 32 covers the resin core 31 and is formed on the top surface of the columnar electrode 22 around the resin core 31. The solder 32 is coupled to the top surface of the columnar electrode 22 so that the solder 32 and the columnar electrode 22 are electrically connected to each other.

Hereinafter, the mounting structure of the electronic component 10 will be described with reference to FIG.
As shown in FIG. 3, in the mounting structure 2, the electronic component 10 is surface-mounted on the circuit board 80 with the surface of the sealing layer 26 facing the circuit board 80. A wiring is formed on the circuit board 80, and an end portion of the wiring is formed on the circuit board 80 as a terminal (electrode) 81. The terminal 81 and the columnar electrode 22 are joined by the solder 32, and the solder 32 is coupled to the terminal 81 and the columnar electrode 22. The terminal 81 and the columnar electrode 22 are joined by the solder 32 including the resin core 31. The joined body 40 is a solder joined body. The resin core 31 may be in contact with the terminal 81.

An underfill material 82 is filled in a gap between the electronic component 10 and the circuit board 80. A fillet 82 a of the underfill material 82 protrudes from the gap between the electronic component 10 and the circuit board 80, and the fillet 82 a covers a part of the side surface of the electronic component 10. The underfill material 82 is made of an epoxy resin, a polyimide resin, or other insulating resin. The underfill material 82 may contain a glass filler.
The underfill material 82 may not be provided.

A method for manufacturing the semiconductor device 1 will be described.
When the semiconductor device 1 is manufactured, a semiconductor wafer before being singulated is used. On the surface of the semiconductor wafer, an integrated circuit is formed for each chip region defined by a cutting line (dicing street) when the semiconductor wafer is separated.

First, an insulating film 25 is formed on the surface of the semiconductor wafer, and the insulating film 25 is patterned to form an opening 25 a in the insulating film 25.
Next, the electroplating seed layer 20 is grown on one surface of the insulating film 25 and the connection pads 12 by an electroless plating method, a vapor phase growth method (for example, sputtering method), or a combination thereof.
Next, a resist is applied onto the electroplating seed layer 20, and the resist is patterned by exposing and developing the resist.
Next, with the remaining resist as a mask, electrolytic plating is performed using the electrolytic plating seed layer 20 as an electrode in a state where a portion of the electrolytic plating seed layer 20 is covered with the resist. As a result, the wiring 21 is grown on the electroplating seed layer 20 and between the resists. Here, the wiring 21 is grown thicker than the electroplating seed layer 20.
After the wiring 21 is formed, the resist is removed.
Next, a dry film resist for forming the columnar electrode 22 thicker than the wiring 21 is attached to one surface of the electroplating seed layer 20 and the wiring 21, and the dry film resist is exposed and developed to thereby dry the resist. An opening is formed in One end of the wiring 21 is exposed in the opening of the dry film resist.
Next, using the remaining dry film resist as a mask, electrolytic plating is performed using the electroplating seed layer 20 and the wiring 21 as electrodes while the dry film resist covers a portion of the electroplating seed layer 20 and the wiring 21. . Thereby, the columnar electrode 22 is grown on the wiring 21 in the opening of the dry film resist. Here, the columnar electrode 22 is grown thicker than the wiring 21.
After forming the columnar electrode 22, the dry film resist is removed.
Next, the portion of the electrolytic plating seed layer 20 that does not overlap the wiring 21 is removed by etching. At this time, the surfaces of the wiring 21 and the columnar electrode 22 are partially etched, but the wiring 21 and the columnar electrode 22 remain because the wiring 21 and the columnar electrode 22 are sufficiently thicker than the seed layer 20 for electrolytic plating. .
Next, a sealing resin is applied to the surface of the wafer, and the sealing resin is cured to form the sealing layer 26. At this time, the entire columnar electrode 22 is embedded in the sealing layer 26, and the columnar electrode 22 is not exposed.
Next, the top surface of the columnar electrode 22 is exposed so that the surface of the sealing layer 26 is substantially flush with the top surface of the columnar electrode 22 by grinding the surface of the sealing layer 26 (see FIG. 4). . At this time, the top of the columnar electrode 22 is also ground. In FIG. 4, reference numeral 110 is a semiconductor wafer, reference numeral 111 is a chip region, and reference numeral 112 is a dicing street.

  Next, as shown in FIG. 5, a resist 130 is formed on the columnar electrode 22 and the sealing layer 26, and the resist 130 is exposed and developed to form an opening 131 in the resist 130. Here, the diameter of the opening 131 is made smaller than the diameter of the columnar electrode 22, and the opening 131 is formed on the central portion of the top surface of the columnar electrode 22. Thereby, a part of the top surface of the columnar electrode 22 is exposed in the opening 131. The resist 130 may be a dry film resist or a wet resist.

Next, as shown in FIG. 6, each opening 131 is filled with a liquid resin, and the resin is cured. Thereby, the resin core 31 is formed in the opening 131, the resin core 31 is erected on the top surface of the columnar electrode 22, and the resin core 31 is brought into close contact with the top surface of the columnar electrode 22.
Next, as shown in FIG. 7, after forming the resin core 31, the resist 130 is removed.
Next, as shown in FIG. 8, the resin core 31 is covered with solder 32, and the solder 32 is formed on the top surface of the columnar electrode 22. At this time, since the resin core 31 is in close contact with the top surface of the columnar electrode 22, the resin core 31 is not displaced when the solder 32 is formed, and the bump 30 can be easily manufactured.
As a method for forming the solder 32, there is a method in which a flux is applied to the top surface of the columnar electrode 22, an unmelted solder is mounted on the resin core 31 or the columnar electrode 22, and reflowed. The solder is melted by reflow, the solder covers the resin core 31, spreads on the top surface of the columnar electrode 22, and the solder is cured to become the solder 32.
As another method for forming the solder 32, a solder paste (preferably containing flux) is dropped onto the top surface of the columnar electrode 22 from the top of the resin core 31, and the resin core 31 is formed by the solder paste. There is a way to cover. The dropped solder paste is cured to become solder 32.

  Next, the semiconductor wafer 110 is diced along the dicing street 112 and divided into a plurality of semiconductor devices 1. The manufacture of the bumps 30 may be performed after the dicing process.

A method for mounting the electronic component 10 will be described.
A circuit board 80 having wiring and terminals 81 formed on the surface is prepared.
Next, the surface of the sealing layer 26 of the electronic component 10 is directed to the surface of the circuit board 80, the solder 32 is aligned with the terminal 81, and the electronic component 10 is faced down. As a result, the solder 32 is sandwiched between the columnar electrode 22 and the terminal 81.
Next, the circuit board 80 on which the electronic component 10 is mounted is placed in a reflow furnace, the solder 32 is reflowed, and the terminals 81 and the columnar electrodes 22 are soldered. Thereby, a solder joined body is manufactured. The solder 32 may be melted by reflow and the resin core 31 may be in contact with the terminal 81.
After cooling the solder 32 and the circuit board 80, an underfill material 82 is injected between the sealing layer 26 and the circuit board 80.

After the underfill material 82 is injected, the underfill material 82 is heated to cure the underfill material 82. The curing temperature of the underfill material 82 is lower than the reflow temperature of the solder 32. If the underfill material 82 is an ultraviolet curable resin, the underfill material 82 is cured by irradiating the underfill material 82 with ultraviolet rays.
Thus, the mounting structure 2 for the electronic component 10 is completed.

  As described above, according to the present embodiment, the stress caused by the difference between the thermal expansion coefficient of the sealing layer 26 and the thermal expansion coefficient of the circuit board 80 is relieved by the resin core 31 having elasticity. Therefore, even if heat generation / cooling of the electronic component 10 is repeated, the stress fluctuation generated in the solder 32 is reduced. Therefore, the fatigue life of the solder 32 is improved. In particular, since the resin core 31 is in close contact with the top surface of the columnar electrode 22, it is possible to prevent the solder 32 from being fatigued near the interface between the solder 32 and the columnar electrode 22.

  Further, since the resin core 31 is a heat-resistant resin such as a polyimide resin, the resin core 31 is not thermally damaged during reflow.

[Second Embodiment]
FIG. 9 is a perspective view of the semiconductor device 1A according to the second embodiment. In addition, the same code | symbol is attached | subjected to the part which mutually respond | corresponds in 2nd Embodiment and 1st Embodiment.

The sealing layer 26 in the second embodiment is thinner than the sealing layer 26 in the first embodiment.
In the semiconductor device 1A of the second embodiment, no columnar electrode is provided. An opening 26 a is formed on the land (electrode) 21 a of the wiring 21 in the sealing layer 26, and the land 21 a of the wiring 21 is an electrode of the electronic component 10.

  The bump 30 is provided on the land 21 a of the wiring 21. The resin core 31 of the bump 30 is formed on the land 21a in a state of being in close contact with the surface of the land 21a, and is provided in a state of being upright with respect to the land 21a. The solder 32 covers the resin core 31 and is formed on the surface of the land 21 a around the resin core 31.

  FIG. 10 shows the mounting structure 2A. As shown in FIG. 10, the terminal 81 and the land 21a of the circuit board 80 are joined by the solder 32, and the solder 32 is coupled to the terminal 81 and the land 21a.

Except for what has been described above, the corresponding portions of the second embodiment and the first embodiment are provided in the same manner.
Further, the method for manufacturing the bump 30 in the second embodiment is the same as the method for manufacturing the bump 30 in the first embodiment, except that the place where the bump 30 is installed is on the land 21a of the wiring 21.
The mounting method in the second embodiment is the same as the mounting method in the first embodiment except that the semiconductor device 1A is mounted.

  Also in this embodiment, since the resin core 31 is in close contact with the land 21a, the solder 32 can be easily formed. Further, the fatigue life of the solder 32 can be improved by the resin core 31.

DESCRIPTION OF SYMBOLS 1, 1A Semiconductor device 2, 2A Mounting structure 10 Electronic component 11 Semiconductor substrate 21a Land (electrode)
22 Columnar electrode (electrode, electrode for external connection)
26 Sealing layer 30 Bump 31 Resin core 32 Solder 40 Solder joint 80 Circuit board 81 Terminal (first electrode)

Claims (11)

A semiconductor substrate;
Connection pads formed on the semiconductor substrate;
A wiring electrically connected to the connection pad;
An electrode electrically connected to the wiring;
A core formed on the surface of the electrode;
Solder that covers the core and is formed on the electrode around the core;
A sealing layer formed on the semiconductor substrate around the electrode;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the core is made of a polyimide resin or an epoxy resin.   The semiconductor device according to claim 1, wherein the electrode is a land formed on one end of the wiring.   The semiconductor device according to claim 1, wherein the electrode is an external connection electrode.   The semiconductor device according to claim 4, wherein the core is provided on a surface of the external connection electrode.   6. A circuit board, wherein the solder in the semiconductor device according to claim 1 is connected to an electrode of the circuit board. Forming a core on the surface of the electrode of the electronic component;
Covering the core with solder and forming the solder on the surface of the electrode around the core;
A method for manufacturing a semiconductor device, comprising:   The method for manufacturing a semiconductor device according to claim 7, wherein the core is made of a polyimide resin or an epoxy resin.   The method of manufacturing a semiconductor device according to claim 7, wherein the electrode is a land formed on one end of the wiring.   The method of manufacturing a semiconductor device according to claim 7, wherein the electrode is an external connection electrode.   The method of manufacturing a semiconductor device according to claim 10, wherein the core is formed on a surface of the external connection electrode.

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