JP2011165740A - Semiconductor device, and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of measuring characteristics of a characteristic check element easily by an OBIRCH method, and a manufacturing method for the semiconductor device. <P>SOLUTION: The semiconductor device includes the characteristic check element whose characteristics are checked by exposing the element to laser light, and an upper wiring layer which is the characteristic check element and have dummy metals arranged on the wiring layer. The upper wiring layer has a first region overlapping the characteristic check element and a second region not overlapping the characteristic check element. The density of the dummy metals in the first region is smaller than the density of the dummy metals in the second region. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  In the semiconductor device, a characteristic check element is arranged in order to confirm the characteristic of the product. The characteristic check element is disposed in order to confirm, for example, Tr characteristics, wiring resistance, and via resistance. When the product yield deteriorates, there is a high possibility that changes will occur in the characteristics and yield of the characteristic check element, and failure analysis is performed using the characteristic check element. Based on the result of the failure analysis, measures are taken to improve the yield.

  When performing failure analysis, it is important to identify in which part of the semiconductor device the failure has occurred. An OBIRCH (Optical Beam Induced Resistance Change) method may be used to identify an unnecessary portion. In the OBIRCH method, laser light is irradiated to the characteristic check element in a state where a voltage is applied to the characteristic check element, and the resistance value of the characteristic check element is measured. Then, the irradiation position of the laser beam is scanned. In the characteristic check element, the normal portion and the abnormal portion have different rates of increase in resistance when irradiated with laser light. Therefore, the defective portion can be specified by obtaining the rate of increase in resistance value when the laser is irradiated.

  Incidentally, a dummy metal may be provided in the semiconductor device. For example, in a wiring layer formed by a damascene method, a dummy metal (dummy wiring) is provided in order to improve planarization by CMP (Chemical Mechanical Polishing). As a technique for providing a dummy metal, a semiconductor device described in Patent Document 1 (Japanese Patent Application Laid-Open No. 2004-235357) is given. This publication describes that a dummy pattern for CMP having high uniformity in a chip and high resistance to chipping in a scribe line is provided.

  Japanese Patent Application Laid-Open No. 5-95045 describes that a pseudo active pattern is arranged in the vicinity of a test element. As a result, since the pattern density of the circuit system portion of the semiconductor device and the pattern density of the test element region portion are equivalent, there is no difference in dimensional processing accuracy between the two, and it is described that a highly reliable semiconductor device is provided. Yes.

JP 2004-235357 A Japanese Utility Model Publication 5-95045

  In general, a semiconductor device is provided with a plurality of wiring layers. By arranging the above-described dummy metal in this wiring layer, the dummy metal may be provided also in the wiring layer on the characteristic check element provided in the semiconductor substrate of the semiconductor device. In this case, most of the characteristic check elements may be covered with the dummy metal (the layouts overlap). When the characteristic check element is covered with a dummy metal, the laser light is blocked by the dummy metal when the OBIRCH method is performed. Since the characteristic check element is not irradiated with laser light, there is a problem that it becomes difficult to perform characteristic check (measurement) of the characteristic check element by the OBIRCH method.

  A semiconductor device according to the present invention includes a characteristic check element whose characteristic is inspected by irradiating a laser beam, and an upper wiring layer which is located above the characteristic check element and in which a dummy metal is disposed. It has. The upper wiring layer includes a first region that overlaps the characteristic check element and a second region that does not overlap the characteristic check element. The density of the dummy metal in the first region is smaller than the density of the dummy metal in the second region.

  In the present invention, the density of the dummy metal is reduced in the first region located immediately above the characteristic check element. Therefore, when the laser beam is irradiated, the laser beam can be prevented from being blocked by the dummy metal. As a result, when the OBIRCH method is used, the characteristics of the characteristic check element can be easily measured.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a characteristic check element, a step of forming an upper wiring layer in which a dummy metal is disposed above the characteristic check element, and an upper side of the upper wiring layer. To irradiating the characteristic check element with laser light and inspecting the characteristic of the characteristic check element. The step of forming the upper wiring layer is such that the density of the dummy metal in the first region overlapping with the characteristic check element is smaller than the density of the dummy metal in the second region not overlapping with the characteristic check element. Forming a dummy metal.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device and the manufacturing method of a semiconductor device which maintained the measurement ease of the characteristic check element (circuit) comprised to the wiring layer which does not contain uppermost layer wiring are provided.

1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment. 1 is a plan view schematically showing a semiconductor device according to a first embodiment. 1 is a plan view schematically showing a semiconductor device according to a first embodiment. It is a top view which shows the semiconductor device which concerns on a comparative example. It is the schematic which shows the semiconductor device which concerns on the modification of 1st Embodiment. It is a figure which shows schematically the semiconductor device which concerns on the other modification of 1st Embodiment. It is a figure which shows schematically the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows schematically the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows schematically the semiconductor device which concerns on 4th Embodiment. FIG. 10 is a diagram showing a cross section taken along a plane BB ′ shown in FIG. 9.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to this embodiment.

  As illustrated in FIG. 1, the semiconductor device includes a silicon substrate 31 (semiconductor wafer) and a plurality of wiring layers (8-1 to 8-5). A contact interlayer film (SiO film) 33 is provided on the silicon substrate 31 via a diffusion layer 32. A plurality of wiring layers (8-1 to 8-5) are stacked on the contact interlayer film 33 via the via layer 6. In each wiring layer 8 and via layer 6, a portion where no via or wiring is formed is an insulating film (interlayer film 43 (Low-k film (low dielectric constant film), SiO film), etching stopper film 34). The uppermost layer 8-5 of the plurality of wiring layers 8 is covered with a cover film 52 (SiO or SiON film or the like).

  In this semiconductor device, a characteristic check element 4 is provided. In the present embodiment, the characteristic check element 4 is formed in the wiring layer 8-1. The characteristic check element 4 is an element whose characteristic can be checked by the OBIRCH method.

  FIG. 2 is a diagram when the semiconductor device is viewed from above, and shows the position of the characteristic check element 4. As shown in FIG. 2, in the semiconductor device, a user circuit region is provided in the semiconductor chip. The characteristic check element 4 is provided at a position surrounded by the user circuit area when viewed from above.

  Refer to FIG. 1 again. In the present specification, a wiring layer located above the characteristic check element 4 among the plurality of wiring layers 8 (8-1 to 8-5) is defined as an upper wiring layer. That is, in the present embodiment, each of the wiring layers 8-2 to 8-5 is defined as an upper wiring layer.

  As shown in FIG. 1, a dummy metal 7 is provided in each upper wiring layer (8-2 to 8-5). The dummy metal 7 is provided to improve the flatness when the upper wiring layer is formed using the CMP method. The dummy metal 7 is formed in the same wiring layer as the wiring layer in which the wiring pattern constituting the user logic circuit (not shown in FIG. 1) is formed, and electrically from the signal wiring included in the user logic circuit. It is an independent metal. The dummy metal 7 may be formed by a part of power supply wiring (including ground wiring) included in the user logic circuit. Note that a dummy metal is usually provided also for the wiring layer 8-1. However, the illustration of the dummy metal provided in the wiring layer 8-1 is omitted.

  A layout in each wiring layer 8 will be described with reference to FIG. In FIG. 3, the layout of the dummy metal 7 in each upper wiring layer (8-2 to 8-5) and the layout of the characteristic check element 4 in the wiring layer 8-1 are shown superimposed. Note that FIG. 1 described above shows a cross-section along AA ′ in FIG. 3.

  First, the characteristic check element 4 will be described. In the present embodiment, it is assumed that a comb-like element used for measuring the interwiring capacitance is used as the characteristic check element 4. As shown in FIG. 3, the characteristic check element 4 includes a pair of comb patterns (α, β) arranged to face each other. Each comb pattern (α, β) is connected to the electrode pad 5 via a lead wiring γ. The electrode pad 5 includes a metal provided in each wiring layer 8 and vias connecting the metals between the wiring layers, and is exposed in the uppermost layer 8-5. Therefore, the capacitance between the pair of comb patterns (α, β) can be measured by probing the electrode pad 5. At the same time, it is possible to examine whether or not a leak has occurred between the pair of comb patterns (α, β).

  Next, the layout of the dummy metal 7 disposed in each upper wiring layer (8-2 to 8-5) will be described.

  In each upper wiring layer (8-2 to 8-5), a region overlapping with the characteristic check element 4 is described as the first region 1, and a region not overlapping with the characteristic check element 4 is described as the second region 2. In the present embodiment, the density of the dummy metal 7 in the first region 1 is set smaller than the density of the dummy metal 7 in the second region 2.

  Specifically, when the pitch of the dummy metal 7 is the same between the first region 1 and the second region 2, the size of the dummy metal 7 in the first region 1 is provided in the second region 2. It is set smaller than the size of the dummy metal 7. Thereby, the density in the 1st field 1 can be made smaller than the density in the 2nd field. When the size of the dummy metal 7 is the same between the first region 1 and the second region 2, the pitch of the dummy metal 7 in the first region is set larger than the pitch in the second region 2. Is done. Even in this case, the density in the first region 1 can be made smaller than the density in the second region 2.

  By adopting the configuration as described above, it is possible to easily inspect characteristics by the OBIRCH method. This point will be described below using a comparative example.

  FIG. 4 is a plan view showing a semiconductor device according to a comparative example. In the semiconductor device according to the comparative example, the density of the dummy metal 7 is equal between the first region 1 and the second region 2. Generally, the layout of the dummy metal 7 is automatically determined based on the pitch and size designated by the user. Therefore, unless the layout of the dummy metal 7 is particularly devised, the density of the dummy metal 7 becomes uniform as in the comparative example. When the dummy metal 7 is arranged so as to have a uniform density in this way, the laser light is easily blocked by the dummy metal 7 when the characteristic check element 4 is irradiated with laser light from above. For example, when a defect occurs in a portion of the characteristic check element 4 that is located immediately below the dummy metal 7, a defective portion cannot be specified. That is, it becomes difficult for the characteristic check element 4 to hit the laser beam, and it becomes difficult to observe the characteristic check element 4 by the OBRICH method.

  On the other hand, in the present embodiment, since the density of the dummy metal 7 in the first region 1 is small, it is difficult to block the laser beam. Therefore, it becomes easy to irradiate the characteristic check element 4 with laser light, and the characteristic check element 4 can be easily observed by the OBRICH method.

  Next, a method for manufacturing the semiconductor device according to this embodiment will be described. First, a Si substrate 31 (see FIG. 1) is prepared, and a diffusion layer 32 is formed on the Si substrate 31. Further, a contact interlayer film 33 is formed on the diffusion layer 32. Thereafter, a plurality of wiring layers 8 (8-1 to 8-5) are stacked on the contact interlayer film 33 via the via layer 6. Further, after the uppermost wiring layer 8-5 is formed, the cover film 52 is formed. Note that the characteristic check element 4 is formed when the wiring layer 8-1 is formed. Further, when forming each upper wiring layer (8-2 to 8-5), the density of the dummy metal 7 in the first region 1 is made smaller than the density of the dummy metal 7 in the second region 2. A dummy metal 7 is formed. Further, when forming each upper wiring layer (8-2 to 8-5), a groove for embedding the wiring pattern and the dummy metal 7 is formed. Then, a metal layer is deposited so as to fill the groove, and polishing is performed by CMP. Thereby, the structure by which the wiring pattern and the dummy metal 7 were embedded in the groove | channel is obtained.

  Thereafter, when a defect occurs, the characteristic of the characteristic check element 4 is observed by the OBRICH method. That is, the characteristic check element 4 is irradiated with laser light from above. At this time, the electrical characteristics of the characteristic check element 4 are measured via the electrode pads 5. Then, based on the electrical characteristics when the laser beam is irradiated, a defective portion is identified. At this time, as described above, in the present embodiment, the laser light is not easily blocked by the dummy metal 7, and the characteristic check element 4 is easily hit by the laser light. Therefore, the characteristic check element 4 can be easily observed.

  Thereafter, a plurality of semiconductor chips are obtained by cutting along the scribe lines. Note that the observation of the characteristic check element 4 by the OBRICH method can be performed after being divided into a plurality of semiconductor chips.

  As described above, according to the present embodiment, since the density of the dummy metal 7 in the first region 1 is set to be small, the laser light can be easily applied to the characteristic check element 4. As a result, the characteristic check element 4 can be easily observed by the OBRICH method. For this reason, it is possible to identify the cause of the malfunction and plan a countermeasure at an early stage.

  The density of the dummy metal 7 in the first region 1 is preferably 95% or less of the density in the second region 2. In such a range, it becomes easy to reliably apply the laser beam by the characteristic check element 4.

  Further, when the density of the dummy metal 7 in the first region 1 is simply reduced, the characteristic check element 4 and the dummy metal 7 may partially overlap. Therefore, it is preferable that the dummy metal 7 is disposed in the first region 1 so as not to overlap with the characteristic check element 4.

  Further, in the present embodiment, the case where a comb-shaped element for inter-wiring capacitance measurement (and inter-wiring leakage measurement) is used as the characteristic check element 4 has been described. However, the characteristic check element 4 is not limited to a comb-shaped element for inter-wiring capacitance measurement. If it is possible to check the characteristics using the OBIRCH method, other elements may be used as the characteristic check element 4. For example, as the characteristic check element 4, a process development TEG (Test Element Group), a circuit evaluation TEG, a via chain for measuring a via resistance (chain), a wiring resistance inspection element for inspecting a wiring resistance, an integrated circuit A part of wiring included in the circuit, a contact resistance inspection element for inspecting contact resistance, an element for inspecting the characteristics of the SRAM (SRAM circuit itself, each memory cell included in the SRAM circuit, etc.), and transistor It is also possible to use a check transistor (transistor characteristic inspection element) or the like for checking the characteristics.

  Further, in the present embodiment, the case where the characteristic check element 4 is provided in the wiring layer 8-1 has been described. However, the characteristic check element 4 is not necessarily provided in the wiring layer 8-1. For example, when a transistor is used as the characteristic check element 4, the characteristic check element 4 exists below the wiring layer 8-1. In this case, each of the plurality of wiring layers 8 (8-1 to 8-5) is an upper wiring layer.

  Further, the characteristic check element 4 is not necessarily provided in a single wiring layer. For example, when a via chain is used as the characteristic check element 4, the characteristic check element 4 is formed across a plurality of wiring layers 8. In this case, the wiring layer located above the wiring layer in which the characteristic check element 4 is formed among the plurality of wiring layers 8 is the upper wiring layer.

  Further, in the present embodiment, as illustrated in FIG. 2, the case where the characteristic check element 4 is surrounded by the user circuit region when viewed from above has been described. However, the layout shown in FIG. 2 is merely an example, and the characteristic check element 4 is not necessarily surrounded by the user circuit area. For example, as shown in FIG. 5, the characteristic check element 4 may be provided at a corner of the semiconductor chip region, or may be independent from the user circuit region. Further, as shown in FIG. 6, the characteristic check element 4 may be disposed on a scribe line 13 that divides the semiconductor wafer into a plurality of chip regions 16.

(Second Embodiment)
Next, the second embodiment will be described. FIG. 7 is a diagram schematically showing a semiconductor device according to the second embodiment. FIG. 7 shows a layout of the dummy metal 7 in each upper wiring layer 8 (8-2 to 8-5). Similar to FIG. 3, the layout of the characteristic check element 4 is also shown in FIG.

  As shown in FIG. 7, in the present embodiment, no dummy metal 7 is disposed in the first region 1. That is, the density of the dummy metal 7 in the first region 1 is zero. The other points are the same as in the first embodiment.

  In the present embodiment, the dummy metal 7 is not disposed in the region immediately above the characteristic check element 4. Therefore, the laser beam by the OBIRCH method is not blocked by the dummy metal 7. Therefore, observation by the OBIRCH method can be performed more easily.

(Third embodiment)
Subsequently, a third embodiment will be described. FIG. 8 is a diagram schematically showing a semiconductor device according to the third embodiment. FIG. 8 shows a layout of the dummy metal 7 in each upper wiring layer 8 (8-2 to 8-5). Similar to FIG. 3, the layout of the characteristic check element 4 is also shown in FIG.

  In the present embodiment, the configuration of the second region 2 is changed with respect to the second embodiment. Since the other points can be the same as those in the second embodiment, detailed description thereof is omitted.

  As shown in FIG. 8, the second region 2 has an adjacent region 10 and a normal region 11. The adjacent area 10 is an area adjacent to the first area 1. The normal region 11 is a region provided separately from the first region 1 via the adjacent region 10. Here, the density of the dummy metal 7 in the adjacent region 10 is set to be larger than the density of the dummy metal 7 in the normal region 11.

  In the embodiment described above, the density of the dummy metal 7 in the first region 1 is set small. In this case, it is expected that the interlayer film and the wiring are hardly polished in the CMP process. That is, it is expected that the abrasiveness will deteriorate. On the other hand, according to the present embodiment, since the density of the dummy metal 7 in the adjacent region 10 is set high, it is possible to reduce the deterioration of the polishability in the CMP process.

  Note that the density of the dummy metal 7 in the adjacent region 10 is preferably 105% or more of the density of the dummy metal 7 in the normal region 11. By adopting such a configuration, it becomes possible to further reduce the deterioration of the polishing property.

  In the present embodiment, the dummy metal 7 is not disposed in the first region 1 as in the second embodiment. However, as in the first embodiment, the dummy metal 7 may also be disposed in the first region 1. In this case, the density of the dummy metal 7 in the first region 1 is set smaller than the density of the dummy metal 7 in the normal region 10.

(Fourth embodiment)
Subsequently, a fourth embodiment will be described. FIG. 9 is a diagram schematically showing the semiconductor device according to the present embodiment. Similarly to FIG. 3, FIG. 9 shows a layout of the dummy metal 7 in each upper wiring layer 8 (8-2 to 8-5). Similar to FIG. 3, the layout of the characteristic check element 4 is also shown in FIG.

  In the present embodiment, the configurations of the first region 1 and the characteristic check element 4 are changed with respect to the above-described embodiments. Since the other points can be the same as those of the above-described embodiment, detailed description thereof is omitted.

  First, the characteristic check element 4 will be described. In the present embodiment, a via chain is used as the characteristic check element 4. This via chain is used to confirm the resistance of vias provided in the via layer 6 and the via yield.

  As shown in FIG. 9, for convenience of explanation, a first direction and a second direction orthogonal to the first direction are defined. In addition, two electrode pads 5 (5-1, 5-2) are provided. When viewed from above, the via chain (characteristic check element 4) includes a first portion and a second portion. The first part is connected to the electrode pad 5-1 at one end and extends while being bent. The second portion is also connected to the electrode pad 5-2 at one end, and extends while being bent. The first part and the second part are connected at the other ends.

  FIG. 10 is a diagram showing a cross-section along the plane BB ′ shown in FIG. 9. As shown in FIG. 10, in this embodiment, a via chain (characteristic check element 4) is provided between the wiring layer 8-1 and the wiring layer 8-2. That is, in the present embodiment, the upper wiring layer is the wiring layer 8-3 to the wiring layer 8-5.

  Specifically, the characteristic check element 4 includes a pattern 26 provided in the wiring layer 8-1, a pattern 28 provided in the wiring layer 8-2, and a via 27 provided in the via layer 6. The pattern 26 and the pattern 28 are connected via the via 27 to form a via chain.

  Next, returning to FIG. 9, the configuration of each upper wiring layer 8 (8-3 to 8-5) will be described.

  As shown in FIG. 9, in the first region 1, the dummy metal 7 extends in the first direction and the second direction to form a dummy metal wiring 12. The dummy metal wiring 12 extends so as not to overlap the characteristic check element 4.

  Specifically, the dummy metal wiring 12 has a central wiring 12-1, a branch wiring 12-2, a branch wiring 12-3, and a pair of side wirings (12-4, 12-5). The central wiring 12-1 is provided at a position sandwiched between the first part and the second part of the characteristic check element 4 and extends along the first direction. The branch wiring 12-2 extends from the central wiring 12-1 along the second direction so as not to overlap the characteristic check element 4. The pair of side wirings (12-4, 12-5) is provided at a position so as to sandwich the characteristic check element 4 in the second direction, and extends along the first direction. The branch wiring 12-4 is connected to the side wiring (12-4 or 12-5) at one end, and extends along the second direction so as not to overlap the characteristic check element 4.

  Note that dummy metal wirings 12 are also arranged in the wiring layers (8-1, 8-2) provided with the characteristic check elements 4 in the same manner as the layout shown in FIG.

  Also in this embodiment, the dummy metal 7 (dummy metal wiring 12) does not overlap the characteristic check element 4. Therefore, the laser beam is not blocked by the dummy metal 7 when the OBIRCH method is executed. Therefore, the characteristic check element 4 can be easily observed by the OBIRCH method. In addition, the wiring density can be set to a desired value by adjusting the wiring width and pitch size of the dummy metal wiring 12. Therefore, it is possible to increase the density of the dummy metal wirings 12 in the first region 1, and it is possible to further improve the deterioration of polishing uniformity in the CMP process.

  Note that the shapes of the characteristic check element 4 and the dummy metal wiring 12 shown in FIG. 9 are merely examples. If the dummy metal wiring 12 extends so as not to overlap the characteristic check element 4, other shapes are used. May be. For example, the dummy metal wiring 12 may be disposed in a rectangular shape, and the characteristic check element 4 may be disposed so as to surround the dummy metal wiring 12.

  As above, the first to fourth embodiments of the present invention have been described. These embodiments are not independent of each other, and can be used in combination within a consistent range.

DESCRIPTION OF SYMBOLS 1 1st area | region 2 2nd area | region 4 Characteristic check element 5 Electrode pad 6 Via layer 7 Dummy metal 8 (8-1 to 8-5) Wiring layer 10 Adjacent area 11 Normal area 12 Dummy metal wiring 13 Scribe line 16 Chip area 26 Pattern 27 Via 28 Pattern 31 Si substrate 32 Diffusion layer on Si substrate 33 Contact interlayer film (SiO film)
34 Etching stopper film (SiCN, SiN)
43 Interlayer film (Low-k film (low dielectric constant film), SiO film)
52 Cover membrane

Claims (12)

A characteristic check element;
An upper wiring layer located above the characteristic check element and having a dummy metal disposed thereon,
Comprising
The upper wiring layer is
A first region overlapping the characteristic check element;
A second region that does not overlap the characteristic check element,
The semiconductor device according to claim 1, wherein the density of the dummy metal in the first region is smaller than the density of the dummy metal in the second region. A semiconductor device according to claim 1,
The upper wiring layer is a semiconductor device which is a layer flattened by CMP (Chemical Mechanical Polishing). A semiconductor device according to claim 1 or 2,
The semiconductor device in which the density of the dummy metal in the first region is zero. A semiconductor device according to any one of claims 1 to 3,
The second region is
An adjacent region disposed adjacent to the first region;
A normal region provided apart from the first region via the adjacent region,
A semiconductor device in which the density of the dummy metal in the adjacent region is higher than the density of the dummy metal in the normal region. A semiconductor device according to claim 1 or 2,
The density of the dummy metal in the first region is 95% or less of the density of the dummy metal in the second region. A semiconductor device according to any one of claims 1 to 5,
In the first region, the dummy metal extends so as not to overlap the characteristic check element to form a dummy metal wiring. A semiconductor device according to any one of claims 1 to 6,
The characteristic check element is a semiconductor device formed on a scribe line set on a semiconductor wafer. A semiconductor device according to any one of claims 1 to 6,
The characteristic check element is a semiconductor device provided in a corner portion of a chip region which is a region surrounded by a scribe line in a semiconductor wafer. A semiconductor device according to any one of claims 1 to 8,
The characteristic check element is a semiconductor device including a pattern that realizes at least one of a process development TEG (Test Element Group) and a circuit evaluation TEG. A semiconductor device according to any one of claims 1 to 8,
The characteristic check element includes a wiring resistance inspection element for inspecting a wiring resistance, a via chain for inspecting a via resistance, a contact resistance inspection element for inspecting a contact resistance, and a wiring for inspecting a wiring capacitance. A semiconductor device including at least one pattern selected from the group consisting of a capacitance inspection element, a transistor characteristic inspection element for inspecting transistor characteristics, and an SRAM characteristic inspection element for inspecting SRAM characteristics. A semiconductor device according to any one of claims 1 to 10,
The characteristic check element is a semiconductor device that is an element whose characteristic is inspected by being irradiated with laser light. Forming a characteristic check element;
Forming an upper wiring layer in which a dummy metal is disposed above the characteristic check element;
Irradiating the characteristic check element with laser light from above the upper wiring layer, and inspecting the characteristic of the characteristic check element;
Comprising
The step of forming the upper wiring layer includes:
A semiconductor including a step of forming the dummy metal such that a density of the dummy metal in the first region overlapping with the characteristic check element is smaller than a density of the dummy metal in the second region not overlapping with the characteristic check element; Device manufacturing method.

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