JP2011165312A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can reduce the number of data to be stored and generate a plurality of voltages easily. <P>SOLUTION: In a memory cell array 1, a plurality of memory cells connected to word lines and bit lines are disposed in a matrix form. A voltage generating circuit 7-2 generates a writing voltage of the word line in a writing operation. The voltage generating circuit further includes a variable circuit 72e that varies a reference voltage, and the variable circuit increases the reference voltage with an increase of the writing voltage. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a NAND flash memory using, for example, an EEPROM, and more particularly to a semiconductor memory device capable of storing multilevel data in one memory cell.

  In the NAND flash memory, a plurality of memory cells arranged in the column direction are connected in series to form a NAND cell, and each NAND cell is connected to a corresponding bit line via a selection gate. Each bit line is connected to a latch circuit that latches write data and read data. All or half of the plurality of cells arranged in the row direction are selected at the same time, and all the cells or half of the simultaneously selected cells are collectively written or read out ( For example, see Patent Document 1).

  By the way, recently, with an increase in capacity of a memory, a multi-value memory that stores 2 bits or more in one cell has been developed. For example, in order to store 2 bits in one cell, it is necessary to set four threshold distributions, and in order to store 3 bits, it is necessary to set eight threshold voltages. These threshold voltages must be set in a range that does not exceed the read voltage. Therefore, at the time of data writing, a write voltage is supplied to the control gate of the memory cell to change the threshold voltage, and it is verified whether or not this threshold voltage has reached the threshold voltage corresponding to predetermined data. If the threshold voltage has not reached the predetermined threshold voltage, the write voltage supplied to the word line is slightly increased and the write operation is repeated again. In this way, the threshold voltage of the memory cell is set. As described above, the multi-level memory needs to set a plurality of threshold voltages.

  The write voltage is generated using a pump circuit and a limiter circuit. This limiter circuit generates a predetermined voltage by changing a resistance ratio according to an input signal, and the pump circuit is controlled by this voltage to generate a predetermined voltage. In this pump circuit, a plurality of minimum generated voltages can be set according to input data.

  However, in the multi-level memory, it is necessary to change the initial value of the write voltage in accordance with the write page, or in accordance with the already written cell and the adjacent cell. Furthermore, it is necessary to change the increment (step width) of the write voltage at the time of rewriting according to the initial value of the write voltage. Therefore, it is necessary to generate many write voltages. This write voltage is set by data supplied to the limiter circuit, but it is necessary to store a large number of data corresponding to a large number of write voltages. These data are trimmed and set at the time of testing the semiconductor memory device. However, it takes a long time to trim a large amount of data.

JP 2004-192789 A

  An object of the present invention is to provide a semiconductor memory device that can easily generate a plurality of voltages by reducing the number of data to be stored.

  According to a first aspect of the semiconductor memory device of the present invention, a memory cell array in which a plurality of memory cells connected to a word line and a bit line are arranged in a matrix, and a voltage for generating a write voltage of the word line in a write operation The voltage generation circuit further includes a variable circuit that varies a reference voltage, and the variable circuit increases the reference voltage as the write voltage increases.

  According to a second aspect of the semiconductor memory device of the present invention, a memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix and the potentials of the word lines and bit lines are controlled. A control circuit; and a voltage generation circuit, the voltage generation circuit generates a write voltage, the control circuit performs a first write operation based on the write voltage from the voltage generation circuit, and the voltage The generation circuit generates a voltage that is higher by a first step voltage than the first write voltage, and performs a second write operation. The voltage generation circuit is (n-1) th from the (n-1) th write voltage. A voltage higher by the step voltage is generated and the nth write operation is performed. The voltage generation circuit generates a voltage higher by the nth step voltage than the nth write voltage, and the (n + 1) th write operation is generated. Was carried out, the n-th step voltage is characterized by an (n-1) th step voltage ≦ n-th step voltage.

1 is a configuration diagram showing a semiconductor memory device according to a first embodiment. FIG. FIG. 2 is a circuit diagram showing a configuration of a memory cell array 1 and a bit line control circuit 2 shown in FIG. 1. 3A is a cross-sectional view showing a memory cell, and FIG. 3B is a cross-sectional view showing a selection gate. FIG. 3 is a circuit diagram showing an example of a data storage circuit shown in FIG. 2. The block diagram which shows an example of the arithmetic circuit shown in FIG. FIG. 2 is a circuit diagram illustrating an example of a Vpgm generation unit included in the control signal and control voltage generation circuit of FIG. 1. FIGS. 7A and 7B are diagrams showing a relationship between data of a memory cell and a threshold voltage of the memory cell. FIG. 3 is a diagram schematically showing a writing order in the first embodiment. The flowchart which shows the program sequence of the 1st page. The flowchart which shows the program sequence of a 2nd page. FIGS. 11A, 11B, and 11C are diagrams showing different writing methods. 9 is a flowchart showing a method for calculating Vpgm of a write target word line. The figure which shows the example which converted Vpgm into data for every 20 mV. The figure which shows the example which converted Vpgm into data for every 25mV. The figure which shows the example which converted Vpgm into data every 30mV. The figure which shows the example which converted Vpgm into data for every 50 mV. The figure which shows the principle of 2nd Embodiment. A circuit diagram showing an example of a Vpgm generating part concerning a 2nd embodiment.

  Hereinafter, embodiments will be described with reference to the drawings.

  First, this embodiment will be schematically described.

  In order to speed up the write operation in a multi-level memory, it is necessary to pay attention to the following points.

(1) For the first page and the second page, and the first page and the second page of adjacent cells, the initial value of the write voltage Vpgm supplied to the word line at the time of writing and the increment of the write voltage (step voltage DVpgm) To optimize.

(2) The boost method is changed between the source side and the drain side of the word line.

(3) A correction value is set in Vpgm for each word line.

  However, if data in which the write voltage Vpgm and the step voltage DVpgm are optimized as in (1) is stored, the number of data increases. Further, when the step voltage is different as shown in (1), the minimum voltage of the write voltage Vpgm is different when the boost method of (2) is changed. For this reason, the correction value such as the differential voltage EASB-SB (Erase self boost-self boost) due to the difference in the boost method is different for each word line. For this reason, all data is required for each step voltage DVpgm.

  On the other hand, the write voltage Vpgm is generated by controlling the pump circuit to a limiter circuit. The minimum step voltage of the limiter circuit can be set to 0.3V, 0.250V, 0.200V, for example, corresponding to the first page and the second page, and the first page and the second page of the adjacent cells. Yes. However, when a large number of minimum step voltages are provided as described above, it is necessary to provide a correction value such as a potential difference due to a difference in boost method for each minimum step. Further, when the minimum step voltage of the limiter circuit is 50 mV, which is the least common multiple of 0.3V, 0.25V, and 0.2V, there arises a problem that the step width of the limiter circuit is not constant. For this reason, the minimum step of the limiter circuit needs to be set to 0.3 V, 0.25 V, and 0.2 V that are as large as possible.

  Therefore, in this embodiment, the write voltage Vpgm does not have an initial value for each minimum step voltage, and the initial value of the write voltage Vpgm is one set by trimming. At the beginning of writing, the trimmed initial Vpgm is temporarily set to 50 mV (0.4V = 0.05 × 8, 0), which is the greatest common divisor of the minimum step voltage of the odd and even bit lines of the first and second pages. .5V = 0.05 × 10, 0.9V = 0.05 × 18, 1.2V = 0.05 × 24), and the voltage to be written and the initial value of Vpgm Parameters such as other differential voltages, correction values for each word line, and EASB-SB difference values are added. After that, division is performed to return the limiter circuit to the minimum step voltage (0.3 V = 0.05 V × 6, 0.25 V = 0.05 V × 5, 0.2 V = 0.05 V × 4). In this way, it is not necessary to prepare data for each minimum step voltage of the limiter circuit, and a plurality of voltages can be easily generated.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 shows a configuration of a semiconductor memory device according to the present embodiment, specifically, a NAND flash memory that stores, for example, 4-level (2-bit) data.

  The memory cell array 1 includes a plurality of bit lines, a plurality of word lines, and a common source line, and memory cells that are electrically rewritable, such as EEPROM cells, are arranged in a matrix.

  The memory cell array 1 has a ROM section 1-1. The ROM unit 1-1 functions as a so-called fuse, and stores data of various voltages described later obtained by, for example, trimming during a test before shipment.

Further, a bit line control circuit 2 and a word line control circuit 6 for controlling the bit lines are connected to the memory cell array 1.
The bit line control circuit 2 reads the data of the memory cells in the memory cell array 1 via the bit lines, detects the state of the memory cells in the memory cell array 1 via the bit lines, and stores the memory via the bit lines. A write control voltage is applied to the memory cells in the cell array 1 to write to the memory cells. A column decoder 3 and a data input / output buffer 4 are connected to the bit line control circuit 2. The data storage circuit in the bit line control circuit 2 is selected by the column decoder 3. Data of the memory cell read to the data storage circuit is output to the outside from the data input / output terminal 5 via the data input / output buffer 4.

  Write data input from the outside to the data input / output terminal 5 is input to the data storage circuit selected by the column decoder 3 via the data input / output buffer 4.

The word line control circuit 6 selects a word line in the memory cell array 1 and applies a voltage necessary for reading, writing or erasing to the selected word line.
The memory cell array 1, the bit line control circuit 2, the column decoder 3, the data input / output buffer 4, and the word line control circuit 6 are connected to a control signal and control voltage generation circuit 7, and the control signal and control voltage generation circuit 7 Be controlled. The control signal and control voltage generation circuit 7 is connected to the control signal input terminal 8 and is controlled by a control signal input from the outside via the control signal input terminal 8. The control signal and control voltage generation circuit 7 includes an arithmetic circuit 7-1 and a Vpgm generation unit 7-2 which will be described later. The arithmetic circuit 7-1 calculates data necessary for generating a write voltage when writing data, and the Vpgm generator 7-2 generates the write voltage Vpgm according to the data supplied from the arithmetic circuit 7-1. To do.

  The bit line control circuit 2, column decoder 3, word line control circuit 6, control signal and control voltage generation circuit 7 constitute a write circuit and a read circuit.

  FIG. 2 shows the configuration of the memory cell array 1 and the bit line control circuit 2 shown in FIG. A plurality of NAND cells are arranged in the memory cell array 1. One NAND cell includes a memory cell MC made up of, for example, 32 EEPROMs connected in series, and select gates S1 and S2. The selection gate S2 is connected to the bit line BL0e, and the selection gate S1 is connected to the source line SRC. The control gates of the memory cells MC arranged in each row are commonly connected to the word lines WL0 to WL29, WL30, and WL31. The selection gate S2 is commonly connected to the select line SGD, and the selection gate S1 is commonly connected to the select line SGS.

  The bit line control circuit 2 has a plurality of data storage circuits 10. A pair of bit lines (BL0e, BL0o), (BL1e, BL1o)... (BLie, BLio), (BL8ke, BL8ko) are connected to each data storage circuit 10.

  The memory cell array 1 includes a plurality of blocks as indicated by broken lines. Each block includes a plurality of NAND cells, and data is erased in units of blocks, for example. The erase operation is simultaneously performed on two bit lines connected to the data storage circuit 10.

  In addition, a plurality of memory cells arranged every other bit line and connected to one word line (memory cells in a range surrounded by a broken line) constitute one sector. Data is written and read for each sector.

  During the read operation, the program verify operation, and the program operation, the address signals (YA0, YA1,... YAi,... YA8k) supplied from the outside of the two bit lines (BLie, BLio) connected to the data storage circuit 10 In response, one bit line is selected. Furthermore, one word line is selected according to the external address.

  3A and 3B are cross-sectional views of the memory cell and the select transistor. FIG. 3A shows a memory cell. An n-type diffusion layer 42 is formed in the substrate 51 (P well region 55 described later) as the source and drain of the memory cell. A floating gate (FG) 44 is formed on the P well region 55 via a gate insulating film 43, and a control gate (CG) 46 is formed on the floating gate 44 via an insulating film 45. . FIG. 3B shows a selection gate. In the P well region 55, an n-type diffusion layer 47 as a source and a drain is formed. A control gate 49 is formed on the P well region 55 through a gate insulating film 48.

  FIG. 4 is a circuit diagram showing an example of the data storage circuit 10 shown in FIG.

  The data storage circuit 10 includes a primary data cache (PDC), a secondary data cache (SDC), a dynamic data cache (DDC), and a temporary data cache (TDC). The SDC, PDC, and DDC hold input data at the time of writing, hold read data at the time of reading, temporarily hold data at the time of verification, and are used for internal data operations when storing multi-value data. The TDC amplifies and temporarily holds bit line data when reading data, and is used to manipulate internal data when storing multilevel data.

  The SDC includes clocked inverter circuits 61a and 61b and transistors 61c and 61d that constitute a latch circuit. The transistor 61c is connected between the input terminal of the clocked inverter circuit 61a and the input terminal of the clocked inverter circuit 61b. A signal EQ2 is supplied to the gate of the transistor 61c. The transistor 61d is connected between the output terminal of the clocked inverter circuit 61b and the ground. A signal PRST is supplied to the gate of the transistor 61d. The node N2a of the SDC is connected to the input / output data line IO via the column selection transistor 61e, and the node N2b is connected to the input / output data line IOn via the column selection transistor 61f. A column selection signal CSLi is supplied to the gates of the transistors 61e and 61f. The node N2a of the SDC is connected to the node N1a of the PDC via the transistors 61g and 61h. A signal BLC2 is supplied to the gate of the transistor 61g, and a signal BLC1 is supplied to the gate of the transistor 61h.

  The PDC includes clocked inverter circuits 61i and 61j and a transistor 61k. The transistor 61k is connected between the input terminal of the clocked inverter circuit 61i and the input terminal of the clocked inverter circuit 61j. A signal EQ1 is supplied to the gate of the transistor 61k. The node N1b of the PDC is connected to the gate of the transistor 61l. One end of the current path of the transistor 61l is grounded through the transistor 61m. A signal CHK1 is supplied to the gate of the transistor 61m. The other end of the current path of the transistor 61l is connected to one end of the current path of the transistors 61n and 61o constituting the transfer gate. A signal CHK2n is supplied to the gate of the transistor 61n. The gate of the transistor 61o is connected to the node N2a of the SDC. A signal COMi is supplied to the other end of the current path of the transistors 61n and 61o. This signal COMi is a signal common to all the data storage circuits 10 and indicates whether or not the verification of all the data storage circuits 10 has been completed. That is, as will be described later, when the verification is completed, the node N1b of the PDC becomes low level. In this state, if the signals CHK1 and CHK2n are set to the high level, the signal COMi is set to the high level when the verification is completed.

  Further, the TDC is constituted by, for example, a MOS capacitor 61p. The capacitor 61p is connected between the connection node N3 of the transistors 61g and 61h and the ground. A DDC is connected to the connection node N3 via a transistor 61q. A signal REG is supplied to the gate of the transistor 61q.

  The DDC is composed of transistors 61r and 61s. The signal VREG is supplied to one end of the current path of the transistor 61r, and the other end is connected to the current path of the transistor 61q. The gate of the transistor 61r is connected to the node N1a of the PDC through the transistor 61s. A signal DTG is supplied to the gate of the transistor 61s.

  Further, one end of a current path of the transistors 61t and 61u is connected to the connection node N3. A signal VPRE is supplied to the other end of the current path of the transistor 61u, and a signal BLPRE is supplied to the gate. A signal BLCLAMP is supplied to the gate of the transistor 61t. The other end of the current path of the transistor 61t is connected to one end of the bit line BLo through the transistor 61v, and is connected to one end of the bit line BLe through the transistor 61w. Signals BLSo and BLSe are supplied to the gates of the transistors 61v and 61w, respectively. The other end of the bit line BLo is connected to one end of the current path of the transistor 61x. A signal BIASo is supplied to the gate of the transistor 61x. The other end of the bit line BLe is connected to one end of the current path of the transistor 61y. A signal BIASe is supplied to the gate of the transistor 61y. A signal BLCRL is supplied to the other ends of the current paths of the transistors 61x and 61y. The transistors 61x and 61y are complementarily turned on in response to the signals BIASo and BIASe, and supply the potential of the signal BLCRL to the unselected bit lines.

  The above signals and voltages are generated by the control signal and control voltage generation circuit 7 shown in FIG. 1, and the following operations are controlled based on the control of the control signal and control voltage generation circuit 7.

  The NAND flash memory is, for example, a quaternary memory, and can store 2-bit data in one cell. Switching between 2 bits is performed by an address (first page, second page).

  FIG. 5 shows an example of the arithmetic circuit 7-1 shown in FIG.

  In FIG. 5, an arithmetic circuit 7-1 includes latch circuits 71a, 71b, 71c, selector circuits 71d, 71e, an adder circuit 71f, registers 71g, 71h, 71i, a comparator 71j, AND circuits 71k, 71l, and an OR circuit 71m. It is configured.

  Data read from the ROM section 1-1 is held in the latch circuits 71a, 71b, 71c. The output terminals of the latch circuits 71a, 71b, 71c and the output terminal of the register 71g are connected to the input terminal of the selector circuit 71d. The selector circuit 71d has a function of selecting an input signal in accordance with a control signal and shifting the input data in a LSB (Least Significant Bit) or MSB (Most Significant Bit) direction for output. Therefore, the input data is divided or multiplied depending on the data shift direction.

  The selector circuit 71e has the same function as the selector circuit 71d, and divides or multiplies the data supplied from the register 71g according to the control signal and outputs the result. The output data of these selector circuits 71d and 71e is supplied to the adding circuit 71f and added. The output data of the adder circuit 71f is held by the register 71g.

  The register 71h holds the maximum value Vpgmmax of the write voltage Vpgm calculated in advance by the selectors 71d and 71e and the addition circuit 71f. The comparator 71j compares Vpgm output from the adder circuit 71f with the maximum value Vpgmmax held in the register 71h. The AND circuits 71k and 71l and the OR circuit 71m constitute a selector 71n, and selects one of the output data of the adder circuit 71f and the output data of the register 71h according to the output signal of the comparator 71j. That is, when the output data of the adding circuit 71f is smaller than the maximum value Vpgmmax by the comparator 71j, the selector 71n outputs the output data of the adding circuit 71f, and when the output data of the adding circuit 71f is larger than the maximum value Vpgmmax, 71n outputs the maximum value Vpgmmax. The register 71i holds the output data of the selector 71n and outputs this data as control signals RV0 to RV5 for a limiter circuit described later. The registers 71g and 71i have their data output timing switched according to a control signal (not shown) in order to prevent output data from colliding.

  FIG. 6 shows a Vpgm generator 7-2 included in the control signal and control voltage generation circuit 7 of FIG. This Vpgm generation unit 7-2 shows a control unit 72a, an oscillator 72b, a pump circuit 72c, and a limiter circuit 72d. The control unit 72a controls the oscillator 72b according to the output voltage of the limiter circuit 72d. The pump circuit 72c generates a write voltage Vpgm according to the clock signal supplied from the oscillator 72b. The write voltage Vpgm is supplied to the word line control circuit 6 and to the limiter circuit 72d.

  The limiter circuit 72d includes resistors RL and RB, a plurality of N-channel transistors N01, N02, N11, N12, N21, N22, N31, N32, N41, N42, N51, and N52, a plurality of resistors R, and a resistor RD. Differential amplifiers DA1 and DA2 and a P-channel transistor P1.

  The resistors RL and RB connected in series divide the write voltage Vpgm. One ends of the current paths of the plurality of N-channel transistors N01, N11, N21, N31, N41, and N51 are connected to the connection node of the resistors RL and RB, and the plurality of N-channel transistors N02, N12, N22, N32, N42, and N52 are connected. One end of the current path is connected to one input end of the differential amplifier DA2. The plurality of resistors R are connected in a substantially ladder shape between the other ends of the current paths of the transistors N01 to N51 and N02 to 52 and one input end of the differential amplifier DA2. Further, the resistor RD is connected between the other end of the current path of the transistors N51 and N52 and the ground.

  The P-channel transistor P1 is connected between one input terminal of the differential amplifier DA2 and a terminal to which the power supply Vdd is supplied. The gate of the P-channel transistor P1 is connected to the output terminal of the differential amplifier DA2. A reference voltage Vref generated by a band gap reference circuit (not shown) is supplied to the other input terminal of the differential amplifier DA2.

  A reference voltage Vref is supplied to one input terminal of the differential amplifier DA1, and the other input terminal is connected to a connection node between the resistors RL and RB. The output terminal of the differential amplifier DA1 is connected to the control unit 72a.

  The limiter circuit 72d controls the write voltage Vpgm according to the signal supplied from the arithmetic circuit 7-1. That is, signals RV0 to RV5 supplied from the arithmetic circuit 7-1 are supplied to the gates of the transistors N01 to N51, and inverted signals RV0n to RV5n of the signals RV0 to RV5 are supplied to the gates of the transistors N02 to 52. The output voltage of the limiter circuit 72d is compared with the reference voltage Vref by the differential amplifier DA1. The output signal of the differential amplifier DA1 is supplied to the control unit 72a.

  The relationship among the write voltage Vpgm, the minimum value Vpgm_min of the write voltage Vpgm, and the step voltage DVpgm is expressed by the following equation.

Vpgm = Vpgm_min + DVpgm × (32RV5 + 16RV4 + 8RV3 +
4RV2 + 2RV1 + RV0)
Vpgm_min = Vref × (1 + RL / RB)
DVpgm = Vref × RL / (R + RD) / 64
Therefore, when 0.3 V, 0.25 V, and 0.2 V are required as the minimum Vpgm, the resistance value RD is prepared for each of the three, and these are switched and used.

  FIGS. 7A and 7B show the relationship between the memory cell data and the threshold voltage of the memory cell. As shown in FIG. 7A, when the erase operation is performed, the data in the memory cell becomes “0”. In writing the first page, the data in the memory cell becomes data “0” and data “2”. That is, when the write data is “1”, the data remains “0”, and when the write data is “0”, the data becomes “2”. After the second page is written, the data in the memory cell becomes data “0”, “1”, “2”, “3”. That is, when the first page write data is “1” and the second page write data is “1”, the memory cell data remains “0” and the first page write data is “1”. In the case where the write data of the second page is “0”, the data in the memory cell is “1”. When the first page write data is “0” and the second page write data is “0”, the memory cell data is “2”, the first page write data is “0”, and the second page write data is “2”. When the page write data is “1”, the data in the memory cell is “3”. In the present embodiment, the memory cell data is defined from the lowest threshold voltage to the higher threshold voltage.

FIG. 8 schematically shows the write order in this embodiment. FIG. 8 shows a case where one NAND cell is composed of four memory cells for the sake of simplicity. As shown in FIG. 8, in the block, a write operation is performed for each page from a memory cell close to the source line. That is,
(1) The first page of the memory cell 1 is written.

  (2) The first page of the memory cell 2 adjacent to the memory cell 1 in the word line direction is written.

  (3) The second page of the memory cell 1 is written.

  (4) The second page of the memory cell 2 is written.

  (5) The first page of the memory cell 3 adjacent to the memory cell 1 in the bit line direction is written.

  (6) The first page of the memory cell 4 adjacent to the memory cell 3 in the word line direction is written.

  (7) The second page of the memory cell 3 is written.

  (8) The second page of the memory cell 4 is written.

  Thereafter, data is sequentially written in the same manner.

  FIG. 9 shows the program sequence of the first page, and FIG. 10 shows the program sequence of the second page.

  In the program (write) operation, an address is first designated, and two pages shown in FIG. 2 are selected.

  This memory can perform a program operation only in the order of the first page and the second page of the two pages. Therefore, the first page is first selected by address.

  In the first page program shown in FIG. 9, first, data to be written is input from the outside and stored in SDCs in all data storage circuits (S11). When a write command is input, SDC data in all data storage circuits is transferred to the PDC (S12). When data “1” (not written) is input from the outside, the node N1a of the PDC of the data storage circuit shown in FIG. 4 becomes high level, and when data “0” (write is performed) is input. Become low level. Thereafter, the data of the PDC is the potential of the node N1a, and the data of the SDC is the potential of the node N2a.

  Thereafter, the initial Vpgm is calculated by the arithmetic circuit 7-1 while the write voltage Vpgm is boosted to a specific voltage by a pump circuit described later of the control signal and control voltage generation circuit 7 (S13). . This calculation will be described later.

(Program operation) (S14)
When the signal BLC1 and the signal BLCLAMP shown in FIG. 4 are Vdd + Vth (the threshold voltage of the N-channel transistor), the transistors 61h and 61t are turned on. Therefore, when data “1” (not written) is stored in the PDC, the bit line becomes Vdd. When data “0” (write is performed) is stored, the bit line becomes Vss. Become. In addition, a cell connected to the selected word line and not selected (the bit line is not selected) must not be written. For this reason, the voltage Vdd is also supplied to the bit lines connected to these cells.

  Next, by turning off the selection gate of the non-selected block, the word line of the non-selected block is in a floating state and the selection gate is set to Vss.

  By turning on a transfer gate of a row decoder (not shown) of the selected block, Vdd (or a potential slightly lower than Vdd) is selected on the select line SGD of the selected block, Vss is selected on the select line SGS of the selected block, and Vpgm ( 20 V), when Vpass (10 V) is applied to the unselected word line, if the bit line is at Vss, the cell channel is at Vss and the word line is at Vpgm, so that writing is performed. On the other hand, when the bit line is at Vdd, the channel of the cell is booted by coupling by raising Vpgm instead of Vss. Therefore, writing is not performed because the potential difference between the floating gate and the channel does not increase.

  When writing is performed in the order shown in FIG. 8, the number of written cells increases as the distance from the source line increases. For this reason, there is a problem that the channel is difficult to boot and erroneously written. In order to solve this problem, instead of the SB (Self Boost) writing method shown in FIG. 11A, an RLSB (Revised Local Self Boost) writing method shown in FIG. 11B or a REASB shown in FIG. (Revised Erased Area Self Boost) Switch to the writing method. In the RLSB writing method, the word line adjacent to the selected word line or two distances from the selected word line is set to Vss, the selected word line is set to Vpgm, and the other word lines are set to Vpass or an intermediate potential. In the REASB writing method, the word line adjacent to the selected word line on the source side or two words away from the selected word line is set to Vss, the selected word line is set to Vpgm, and the other word lines are set to Vpass or an intermediate potential. In this way, the word line adjacent to the selected word line or two lines away from the selected word line is turned off as the ground potential Vss, so that the potential of the channel immediately below the selected cell is easily boosted.

  By writing the first page, the data in the memory cell becomes data “0” or data “2”. After the second page is written, the data in the memory cell is one of data “0”, “1”, “2”, “3”.

(Program verify read) (S15)
The program verify read is the same as the read operation. However, reading is performed at potentials “a ′”, “b ′”, “c ′”, and “d ′” that are slightly higher than the original read potential. In the case of verify read for the first page, verify read is performed at the potential “a ′”. When the data in the memory cell reaches the verify read potential “a ′”, the PDC becomes data “1”, and writing is not performed.

  On the other hand, when the threshold voltage of the memory cell does not reach the verify read potential “a ′”, the PDC becomes data “0”, and writing is performed in the next program.

(Step up Vpgm) (S16, 17)
The program operation and the verify operation are repeated until the PDCs of all the data storage circuits become high level (S16). At this time, the program voltage Vpgm is gradually increased to perform writing (S17).

  Next, in the write operation of the second page shown in FIG. 10, first, write data is input from the outside and stored in the SDCs in all the data storage circuits 10 (S21). Thereafter, in the first page write, in order to confirm the written data, the read level “a” (for example, negative voltage) is set to the word line, and the data in the memory cell is read (S22). This read operation is as described above. When the threshold voltage of the cell is lower than the potential “a” of the word line, the PDC is at a low level, and when it is higher, the PDC is at a high level.

  Thereafter, the write voltage Vpgm is calculated by the arithmetic circuit 7-1 while the write voltage Vpgm is boosted to a specific voltage in the pump circuit 72c (S23).

  Next, a data cache is set (S24). That is, the second page is written as shown in FIG.

  In the case of data “1” in the first page write and in the case of data “1” in the second page write, the second page write is not performed.

  In the case of data “1” in the first page write and in the case of data “0” in the second page write, the data in the memory cell is set to “1” by the second page write.

  In the case of data “0” in the first page write and in the case of data “0” in the second page write, the data in the memory cell is set to “2” by the second page write.

  In the case of data “0” in the first page write and in the case of data “1” in the second page write, the cell data is set to “3” by the second page write.

  To perform this operation, a data cache is set.

  That is, when the data in the memory cell is set to “0” (data “1” on the first page, data “1” on the second page), the PDC is set to the high level, the DDC is set to the low level, and the SDC is set to the high level. The

  When the data in the memory cell is set to “1” (data “1” in the first page, data “0” in the second page), the PDC is set to the low level, the DDC is set to the high level, and the SDC is set to the high level.

  When the data in the memory cell is set to “2” (data “0” in the first page, data “0” in the second page), the PDC is set to low level, the DDC is set to high level, and the SDC is set to low level.

  When the data in the memory cell is set to “3” (data “0” on the first page and data “1” on the second page), the PDC is set to the low level, the DDC is set to the low level, and the SDC is set to the low level.

  Each data of PDC, DDC, SDC is set by supplying signals BLC1, BLC2, DTG, REG, VREG in a predetermined order and transferring data of PDC, DDC, SDC, TDC. The specific operation is omitted here.

(Program operation) (S25)
The program operation is exactly the same as the first page program operation. When data “1” is stored in the PDC, writing is not performed, and when data “0” is stored, writing is performed.

(Verify operation) (S26, S27, S28)
The program verify read is the same as the read operation. However, the verify levels “b ′”, “c ′”, and “d ′” are set slightly higher than the read level with a margin added to the read level. The verify read is performed using the verify levels “b ′”, “c ′”, and “d ′”.

  The verify operation is executed in the order of verify levels “b ′”, “c ′”, “d ′”, for example.

  That is, first, the verify level “b ′” is set to the word line, and it is verified whether the threshold voltage of the memory cell has reached the verify level “b ′” (S26). As a result, when the threshold voltage of the memory cell has reached the verify level, the PDC becomes high level and writing is not performed. On the other hand, when the verify read level has not been reached, the PDC goes low and writing is performed in the next program.

  Thereafter, the verify level “c ′” is set to the word line, and it is verified whether the threshold voltage of the memory cell has reached the verify level “c ′” (S27). As a result, when the threshold voltage of the memory cell has reached the verify level, the PDC becomes high level and writing is not performed. On the other hand, when the verify read level has not been reached, the PDC goes low and writing is performed in the next program.

  Next, the verify level “d ′” is set for the word line, and it is verified whether the threshold voltage of the memory cell has reached the verify level “d ′” (S28). As a result, when the threshold voltage of the memory cell has reached the verify level, the PDC becomes high level and writing is not performed. On the other hand, when the verify read level has not been reached, the PDC goes low and writing is performed in the next program.

  In this way, Vpgm is increased by the step voltage DVpgm until the PDCs of all the data storage circuits 10 become high level, and the program operation and the verify operation are repeated (S29, S30).

  The step voltage DVpgm is as follows.

(DVpgm voltage value)
As shown in FIG. 8, the odd-numbered bit line BLo cells are written after the even-numbered bit line BLe cells. For this reason, the threshold distribution width shown in FIGS. 7A and 7B becomes narrower when Vpgm is the same. However, since the distribution widths may be the same, high-speed writing is possible by making the odd-numbered DVpgm larger than the even-numbered DVpgm.

  Also, as shown in FIGS. 7A and 7B, the threshold distribution width after the first page write may be wider than the threshold distribution width after the second page write, so the DVpgm of the first page is the second It may be larger than the DVpgm of the page.

  The initial Vpgm at the start of writing is written to the potential “a ′” on the first page, but is first written to the potential “b ′” on the second page. Since the potential “b ′” is lower than the potential “a ′”, the initial Vpgm at the start of writing of the second page needs to be lower than that of the first page.

  In the SB shown in FIG. 11A, the potentials of the word lines (WL4, WL6) are set to Vpass in the cells adjacent to the write cell. On the other hand, in REASB shown in FIG. 11C, the potential of the word line (WL8 not shown) is Vpass only in the cell on one side of the write cell. For this reason, the voltage of the floating gate is relatively lowered. Therefore, when switching from SB to REASB, Vpgm is added to the voltage drop (about 1 V) of the floating gate.

  Furthermore, recently, cells adjacent to SGD and SGS (cells connected to word lines WL0 and WL31), or adjacent cells skipped by one from SGD and SGS (cells connected to word lines WL1 and WL30). Write characteristics differ from other cells due to processing reasons. Therefore, when writing data into these cells, the initial Vpgm at the start of writing is increased or decreased. Therefore, the step voltages DVpgme, DVpgmo, the relationship between the initial Vpgm, the differential voltage between SB and REASB (SB-REASB), WL0, WL1, WL30, The correction voltage of WL31 is as shown in Table 1 below, for example.

(Table 1)
DVpgme: DVpgmo: initial Vpgm
First page: 0.9V: 1.2V: 17V
Second page: 0.4V: 0.5V: 16V
SB-EASB differential voltage: 1V
Correction voltage of WL0: 0.8V
Correction voltage of WL1: 0.4V
WL30 correction voltage: -0.5V
Correction voltage of WL31: −0.3V
If the minimum step-up size of the limiter circuit is 0.3V, 0.25V, 0.2V, the step-up size is
DVpgme: DVpgmo
First page: 0.3V × 3: 0.2V × 4
Second page: 0.2V × 2: 0.25V × 2
Therefore, the initial Vpgm = 17V and 16V of the first page, even bit line, odd bit line, second page, even bit line, and odd bit line are as follows from FIG. 13, FIG. 14, and FIG.

Vpgme: Vpgmo
First page: 17.1V (FIG. 15, 18th stage): 17.0V (FIG. 13, 26th stage)
Second page: 16.0V (FIG. 13, 21st stage): 16.0V (FIG. 14, 17th stage)
Further, the differential voltage of SB-EASB and the correction values of the word lines WL0, WL1, WL30, WL31 must be integer multiples of the minimum step sizes. Therefore, the relationship between these correction values is as follows.

(Differential voltage of SB-EASB)
Odd Even number 1st page 0.9V (+3 stage) 1.0V (+5 stage)
2nd page 1.0V (+5 stage) 1.0V (+4 stage)
WL0 Odd Even number 1st page 0.9V (+3 stages) 0.8V (+4 stages)
2nd page 0.8V (+4 stage) 0.75V (+3 stage)
WL1 Odd Even number 1st page 0.3V (+1 stage) 0.4V (+2 stage)
2nd page 0.4V (+2 stages) 0.5V (+2 stages)
WL30 odd number even first page -0.6V (-2 stage) -0.4V (-2 stage)
2nd page -0.4V (-2 stage) -0.5V (-2 stage)
WL31 odd number even first page -0.3V (-1 stage) -0.4V (-2 stage)
2nd page -0.4V (-2 stage) -0.25V (-1 stage)
These voltages need to be stored in the ROM section 1-1 of the memory cell array 1 as 6-bit to 8-bit data, for example. However, the number of these data suppresses the problem that the threshold voltage written earlier changes due to the coupling between FG and FG (floating gate) due to the fluctuation of the threshold voltage of the adjacent cell written later, and a narrow threshold value. In order to obtain the distribution, when data is written into the memory cell by a plurality of write operations, the initial value data to be stored increases by the same number as the number of times of writing.

  For example, in the case of a memory storing 2 bits, the number of pages is 2, so that writing can be performed by two write operations. However, in the case of a memory storing 4 bits, the number of pages is 4, so that writing can be performed by writing operations twice, three times, and four times.

  Further, in order to obtain these data, it is necessary to perform a trimming operation during a die sort test before shipment. However, this work is complicated. That is, for example, in the die sort test, the initial Vpgm is first set to a low voltage value, and it is verified whether writing is completed in a prescribed write loop. If not completed, the initial Vpgm is increased little by little, and the Vpgm when writing is completed in the prescribed write loop is set as the initial Vpgm. When the initial Vpgm is as described above, it is necessary to perform such trimming work for each initial Vpgm, so that a long time is required for trimming.

  In the above example, it is necessary to trim the four initial Vpgm of the first page, even bit line, first page, odd bit line, second page, even bit line, second page, odd bit line.

  Therefore, in the present embodiment, one of Vpgm among the odd-numbered / even-numbered / first-page / second-page shown in Table 1 is trimmed as a representative, and the value of this one Vpgm is set to the ROM section 1-1. To remember. In this case, for example, the second page, odd-numbered Vpgm = 16 V is set as a representative value, and the representative value is trimmed and stored in the ROM section 1-1. In this case, since the step-up size is 0.5 V on the second page and odd-numbered pages, the minimum step size is 0.25 V (step size 0.5 V = 0.25 V × 2). Therefore, in the 25 mV table shown in FIG. 14, 16 V corresponds to the 17th stage data.

Furthermore, the differential voltage of SB-EASB = 1V (in this case, it corresponds to the difference between Vpgm = 16V and Vpgm = 17V),
Correction value of WL0 = 0.8V,
Correction value of WL1 = 0.4V,
Correction value of WL30 = −0.5V,
Correction value of WL31 = −0.3V
Are stored in the ROM section 1-1 as data for each 50 mV. The differential voltage of SB-EASB and the correction values of WL0, 1, 30, and 31 are calculated in advance from, for example, trimmed Vpgm. That is, the data of Vpgm is converted into data for every 50 mV, and based on this data, the differential voltage of SB-EASB and the correction values of WL0, 1, 30, 31 are calculated.

  Using the initial Vpgm stored in the ROM 1-1, the correction value, etc., the Vpgm of the write target word line is calculated.

  FIG. 12 shows a calculation method of Vpgm of the write target word line, and shows an example in which Vpgm of the odd page of the first page is generated from the second page, odd-numbered initial Vpgm.

  As described above, the minimum step voltage DVpgm of the write voltage is 0.4V, 0.5V, 0.9V, and 1.2V, and the greatest common divisor of these DVpgm is 0.05V (= 50 mV). Therefore, the initial Vpgm (= 16V) data of the second page even page stored in the ROM section 1-1 is converted into data for every 50 mV, and the Vpgm of the word line to be written is converted based on the converted data. Is calculated.

  First, the initial Vpgm (= 16V) data of the second page even-numbered page stored in the ROM section 1-1 is loaded into, for example, the latch circuit 71a shown in FIG. 5 (S31).

  Next, the initial Vpgm is converted into data every 50 mV. That is, the data of the latch circuit 71a is multiplied by 5 (S32).

In a binary number, when ²ⁿ is multiplied, the data is shifted n bits to the MSB side, and when ²ⁿ is divided, the data is shifted n bits to the LSB side. 5 times of the operation is, for example, ² 2 + 2 ^0. Therefore, first, the data of the latch circuit 71a is shifted by 2 bits to the MSB side by the selector circuit 71d and outputted, and this data is held in the register 71g via the adder circuit 71f. Next, the data held in the register 71g without being shifted by the selector 71e is supplied to the adding circuit 71f, and the data of the latch circuit 71a is supplied to the adding circuit 71f without being shifted by the selector circuit 71d. The data added by the adding circuit 71f is held in the register 71g. At this time, since the selector 71n selects the output data of the adding circuit 71f, the register 71i holds the same data as the register 71g.

  FIG. 16 shows an example in which Vpgm is converted into data every 50 mV. The data of initial Vpgm = 16V loaded from the ROM unit 1-1 to the latch circuit 71a is “010000” in the step of 0.25V shown in FIG. These are converted, and in the 25 mV table shown in FIG. 14, the data of 16.0 V is “001010000”.

  Thereafter, the initial voltage difference (= 1V) between the initial Vpgm (= 17V) of the first page odd page and the initial Vpgm (for example, 16V) of the second page even page is the initial Vpgm of the second page even page. (S33). That is, the SB-EASB difference voltage (= 1V) stored in the ROM section 1-1 is read and held in the latch circuit 71b. The data of the latch circuit 71b is selected by the selector 71d and supplied to the adding circuit 71f. At the same time, the data held in the register 71g is supplied to the adder circuit 71f via the selector 71e. The adder circuit 71f adds these data. This addition result is held in the registers 71g and 71i. As a result, the register has 17.0 V and “0011100100” in the 50 mV table shown in FIG.

  Next, when the selected word line is, for example, WL30 and the REASB writing method is used, the differential voltage (= 1V) of SB-EASB held in the latch circuit 71b and the word line WL30 stored in the fuse The correction voltage (= −0.3V) is further added to the data stored in the register 71g (S34). That is, the correction voltage of the word line WL30 is read from the ROM unit 1-1 and held in the latch circuit 71c. The data held in the latch circuits 71b and 71c are sequentially selected by the selector circuit 71d and supplied to the adder circuit 71f together with the data selected by the selector circuit 71e. The data added by the adding circuit 71f is held in the registers 71g and 71i. As a result, the register has 17.7 V and “001110010” in the 50 mV table shown in FIG.

Subsequently, since the odd page of the first page has a step voltage DVpgm of 0.9 V, the odd page is converted into data of voltage of every 0.3 V in accordance with the specification of the limiter circuit 72d (S35). That is, the data held in the register 71g is divided by 6. Specifically, for example, 1/6 = 1/2 ³ +1/2 ⁵ +1/2 ⁷ +1/2 ⁹ +1/2 ¹¹ using the register 71 g, the selector circuit 71 e, and the adder circuit 71 f.
Is calculated. As a result, the register has 17.7V and “010011” in the 0.3V table shown in FIG.

  Thereafter, the calculated data is supplied to the transistors N01 to N51 and N02 to N52 of the limiter circuit 7-5 (S36). The limiter circuit 72d controls Vpgm output from the pump circuit 72c according to this data.

  According to the first embodiment, only one set of data of one Vpgm as the initial Vpgm and the difference voltage of the write method (SB-EASB) and the correction value for each word line is stored in the ROM 1-1. A write voltage for each page is generated based on the stored data. For this reason, even when the step voltage DVpgm is different for each page, it is not necessary to store a plurality of initial Vpgm in the ROM 1-1. Therefore, since only one Vpgm needs to be trimmed at the time of testing before product shipment, the time required for trimming can be greatly reduced.

  Furthermore, since it is not necessary to store the difference voltage of the writing method and the data of the correction voltage for each word line for each of the first and second pages, every even number, and every odd number, the storage capacity of the ROM section 1-1 can be reduced. Has advantages.

  In the first embodiment, the control data of the limiter circuit is generated by the circuit shown in FIG. 6, but may be generated by software processing, for example.

(Second Embodiment)
The difference between the word line potentials “d” and “c” shown in FIG. 7B needs to be set larger than the difference between “c” and “b”. This is because the neutral threshold voltage (threshold voltage when no electrons are present in the floating gate) is between the potentials “b” and “c”, and the data retention becomes worse as the distance from the neutral threshold voltage increases. This is to ensure Therefore, as shown in the first embodiment, when the step voltage DVpgm is constant, there is a problem that the writing speed becomes slower as the threshold voltage becomes higher.

  Therefore, in the second embodiment, as shown in FIG. 17, the reference voltage Vref is gradually increased as the value of the write voltage Vpgm increases. In this way, the step voltage DVpgm can be increased as the write voltage Vpgm increases.

  FIG. 18 shows the second embodiment, and shows an example of a Vpgm generator including the reference voltage variable circuit 72e. In FIG. 18, the same parts as those in FIG.

  18 differs from FIG. 6 in that the reference voltage Vref supplied to the differential amplifier DA1 is variable. That is, in the reference voltage variable circuit 72e, the reference voltage Vref generated by a band gap reference circuit (not shown) is supplied to one input terminal of the differential amplifier DA3. The output terminal of the differential amplifier DA3 is connected to the gate of the P-channel transistor P2. One end of the current path of the transistor P2 is connected to a terminal to which the power supply Vdd is supplied, and the other end is connected to one input terminal of the differential amplifier DF2 and one end of the variable resistor R2. The other end of the variable resistor R2 is connected to the other input end of the differential amplifier DA3 and grounded via the resistor R1.

  In the above configuration, the reference voltage Vref can be increased by increasing the resistance value of the variable resistor R2 as the write voltage Vpgm increases. Therefore, the step voltage DVpgm can be increased as the reference voltage Vref increases.

  As described above, according to the second embodiment, the write voltage Vpgm is increased, and the step voltage at the time of writing a high threshold voltage can be increased, so that the write speed can be increased.

  In each of the above embodiments, the case where the present invention is applied to a semiconductor memory device that stores multilevel data has been described. However, the present invention is not limited to this, and the present invention can also be applied to a semiconductor memory device that stores binary data.

  In addition, it goes without saying that modifications can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 1-1 ... ROM part, 7 ... Control signal and control voltage generation circuit, 7-1 ... Operation circuit, 7-2 ... Vpgm generation part, 72c ... Pump circuit, 72d ... Limiter circuit, 72e ... Reference | standard Voltage variable circuit.

Claims (2)

A memory cell array in which a plurality of memory cells connected to a word line and a bit line are arranged in a matrix, and a voltage generation circuit for generating a write voltage of the word line in a write operation;
The semiconductor memory device, wherein the voltage generation circuit further includes a variable circuit that varies a reference voltage, and the variable circuit increases the reference voltage as the write voltage increases. A memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix;
A control circuit for controlling the potential of the word line and the bit line;
A voltage generation circuit,
The voltage generation circuit generates a write voltage, and the control circuit performs a first write operation based on the write voltage from the voltage generation circuit,
The voltage generation circuit generates a voltage higher than the first write voltage by a first step voltage, and performs a second write operation.
The voltage generation circuit generates a voltage that is (n-1) th step voltage higher than the (n-1) th write voltage, and performs an nth write operation.
The voltage generation circuit generates a voltage that is higher by the nth step voltage than the nth write voltage, and performs the (n + 1) th write operation, and the nth step voltage is (n−1) th step voltage ≦ the nth step voltage. A semiconductor memory device having an n-step voltage.

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