JP5296175B2 - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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JP5296175B2
JP5296175B2 JP2011233252A JP2011233252A JP5296175B2 JP 5296175 B2 JP5296175 B2 JP 5296175B2 JP 2011233252 A JP2011233252 A JP 2011233252A JP 2011233252 A JP2011233252 A JP 2011233252A JP 5296175 B2 JP5296175 B2 JP 5296175B2
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read
memory cell
write
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JP2012048813A (en
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昇 柴田
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株式会社東芝
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of reading stored data without fail even if a margin between threshold voltage distributions is narrow. <P>SOLUTION: In a semiconductor storage device, a control part sets a threshold voltage of a memory cell to a first level by an erase operation, sets the threshold voltage of the memory cell to a first level, a second level,..., the n-th level (n=2<SP POS="POST">k</SP>) in accordance with a write data inputted from outside by repeating write and verify operations to store k-bit data, counts a number of write operations of j times (j is a natural number) in a cell exceeding the (h-1)-th level among cells written to the h-th level (h&le;n) after exceeding the (h-1)-th level, and slows down a writing speed on and after the j-th write operations. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device that can store binary data or more in, for example, one memory cell.

    For example, in a NAND flash memory, a plurality of memory cells arranged in the row direction are each connected to a corresponding latch circuit via a bit line. Each latch circuit holds data when data is written and read. All the cells or half of the cells arranged in the row direction (for example, 2 to 4 kB cells) are collectively written or read. The threshold voltage is set to a positive voltage by injecting electrons into the memory cell by the erase operation and the memory cell by setting the threshold voltage to a negative voltage and by the write operation (see, for example, Patent Document 1).

  However, since the NAND flash memory has a plurality of memory cells connected in series, it is necessary to turn on non-selected cells during a read operation. Therefore, a voltage (Vread) higher than the threshold voltage is applied to the gate electrode during the read operation. For this reason, the threshold voltage in the write operation must not exceed Vread. In the write sequence, it is necessary to repeatedly perform program and program verify read for each memory cell and control the threshold voltage of the memory cell not to exceed Vread. For this reason, there is a problem that the writing speed is lowered.

  Further, in order to store a large amount of data, a multi-value memory that stores 2 bits or more in one cell has been developed. For example, in order to store 2 bits in one cell, it is necessary to set four threshold voltage distributions. For this reason, the threshold voltage distribution per cell must be set narrower than that of a memory storing 1 bit in one cell, and there is a problem that the writing speed is further slowed down.

  On the other hand, when the level of the read voltage Vread is increased, a high Vread is applied to the cell at the time of reading, which causes a problem that erroneous writing occurs. In addition, when writing to a high level among a plurality of threshold voltages, a high write voltage is required. In NAND flash memory, all cells or half of the cells arranged in the row direction are written at a time, so depending on the data, a high voltage is also applied to the gate electrode even in a non-written state, and erroneous writing occurs. There's a problem.

  Due to these problems, in a limited threshold voltage range, for example, between −2V to 5V, four threshold voltage distributions in the case of 4 values, eight threshold voltage distributions in the case of 8 values, and 16 values 16 threshold voltage distributions must be set. In recent years, the threshold voltage distribution width and the data holding margin can be set to be smaller than in the conventional case by improving the error correction capability by ECC (error correction code).

  However, conditions such as temperature differ between program verify and read. In addition, the write voltage, the verify voltage, and the read voltage that are set by trimming the resistance of the voltage generation circuit during the die sort test may deviate from the target voltage. For this reason, it is necessary to set a margin of, for example, about 80 mV between the threshold voltage distributions. Therefore, even if the ECC correction capability is increased and each threshold voltage distribution width is apparently narrowed, the setting margin remains large.

  As described above, in a multi-level memory in which a plurality of threshold voltages are set, it is preferable that the margin between the threshold voltages can be set narrow. However, conditions such as temperature are different between the verify time and the read time, the read voltage, It is necessary to set a certain margin due to the difference between the write voltage and the verify voltage.

JP 2004-192789 A

  An object of the present invention is to provide a semiconductor memory device capable of reliably reading stored data even when a margin between threshold voltage distributions is narrow.

According to a first aspect of the semiconductor memory device of the present invention, there are provided a memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix, and the potentials of the word lines and the bit lines. A voltage generation circuit that generates the data, a data storage circuit that is connected to the bit line and stores write data of the memory cell or data read from the memory cell, and controls the voltage generation circuit and the data storage circuit The control unit sets the threshold voltage of the memory cell to the first level by erasing operation, and repeats writing and verifying operations, according to write data input from the outside. the first level of the threshold voltage of the memory cell, second level, ... set to the n-level (n = 2 k), stores the data of k bits Of the cells written to the h-th level (h ≦ n), for cells that exceed the (h−1) level, j times (j is a natural number) after exceeding the (h−1) level. The writing operation is counted, and the writing speed is reduced in the j-th and subsequent writing operations.

5 is a flowchart showing a read operation according to the first embodiment. The block diagram which shows the semiconductor memory device applied to each embodiment. FIG. 3 is a circuit diagram showing an example of a memory cell array and a bit line control circuit shown in FIG. 2. FIG. 3 is a circuit diagram showing another example of the memory cell array and the bit line control circuit shown in FIG. 2. FIG. 5A is a cross-sectional view showing a memory cell, and FIG. 5B is a cross-sectional view showing a selection gate. 1 is a cross-sectional view showing a semiconductor memory device corresponding to a first embodiment. The figure which shows the example of the voltage supplied to each part shown in FIG. FIG. 5 is a circuit diagram showing an example of the data storage circuit shown in FIGS. 3 and 4. FIGS. 9A, 9B, and 9C are diagrams showing the relationship between data and threshold voltage when 2-bit data is stored in a memory cell. The figure which shows the order of writing of two NAND units. The flowchart which shows the program operation | movement of the 1st page. The flowchart which shows the program operation | movement of a 2nd page. The figure which shows the EASB write method. FIGS. 14A and 14B are diagrams showing a read sequence of the first page of the memory cell according to the first embodiment. 6 is a flowchart showing a specific operation of the data storage circuit in the read operation according to the first embodiment. FIGS. 16A and 16B are diagrams showing a read sequence of the first page of the memory cell according to the second embodiment. 9 is a flowchart illustrating a read sequence of a first page of memory cells according to the second embodiment. 18A, 18B, and 18C are diagrams showing a first page read sequence according to the third embodiment. 14 is a flowchart illustrating a read sequence of a first page of memory cells according to the third embodiment. 14 is a flowchart illustrating a read sequence of a first page of memory cells according to the fourth embodiment. The flowchart which shows the modification of 1st 4th Embodiment, and shows the read-out sequence of the 1st page of a memory cell. 9 is a flowchart showing a first modification example of the first embodiment and showing a read sequence of a first page of memory cells. The flowchart which shows the reading sequence of a 2nd page. Generally, a flowchart schematically showing a QPW (Quick Pass Write) method. The figure which shows the program pulse voltage applied to the cell in the case of writing by QPW system, and the change of a threshold voltage. The flowchart which shows a program sequence in connection with 7th Embodiment. The figure which concerns on 7th Embodiment and shows the change of the program pulse voltage applied to the cell in the case of writing, and a threshold voltage. 20 is a flowchart illustrating a program sequence according to the eighth embodiment. The figure which concerns on 8th Embodiment and shows the change of the program pulse voltage applied to the cell in the case of writing, and a threshold voltage. FIG. 30A shows a threshold voltage distribution with two values storing 1 bit in one cell, and FIG. 30B shows a threshold voltage distribution with 16 values storing 4 bits in one cell. . The figure which shows the relationship between the write / erase frequency of NAND type flash memory, and a data retention margin. FIG. 10 is a diagram schematically showing a NAND flash memory according to a ninth embodiment. FIG. 31 is a flowchart showing a write sequence when 16 values are stored in one cell shown in FIG. The flowchart which shows the write-in sequence at the time of a die sort test. The block diagram which shows the case where NAND type flash memory is used for storage / reproducing machines, such as music data and image data. The block diagram which shows the case where NAND type flash memory is used for storage / reproducing machines, such as music data and image data, concerning 10th Embodiment. 37 is a flowchart showing the operation of the storage / reproducing device shown in FIG. 36.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 2 shows a configuration of a semiconductor memory device applied to each embodiment of the present invention, for example, a NAND flash memory for storing four values (2 bits).

  The memory cell array 1 includes a plurality of bit lines, a plurality of word lines, and a common source line, and memory cells that are electrically rewritable, such as EEPROM cells, are arranged in a matrix. A bit control circuit 2 and a word line control circuit 6 for controlling bit lines are connected to the memory cell array 1.

  The bit line control circuit 2 reads the data of the memory cells in the memory cell array 1 via the bit lines, detects the state of the memory cells in the memory cell array 1 via the bit lines, and stores the memory via the bit lines. A write control voltage is applied to the memory cells in the cell array 1 to write to the memory cells. A column decoder 3 and a data input / output buffer 4 are connected to the bit line control circuit 2. The data storage circuit in the bit line control circuit 2 is selected by the column decoder 3. Data of the memory cell read to the data storage circuit is output to the outside from the data input / output terminal 5 via the data input / output buffer 4. The data input / output terminal 5 is connected to a host 11 outside the memory chip, for example. The host 11 is constituted by a microcomputer, for example, and receives data output from the data input / output terminal 5. Further, the host 11 outputs various commands CMD, an address ADD, and data DT for controlling the operation of the NAND flash memory. Write data input from the host 11 to the data input / output terminal 5 is supplied to the data storage circuit selected by the column decoder 3 via the data input / output buffer 4, and the command and address are supplied to the control signal and control voltage generation circuit. 7 is supplied.

  The word line control circuit 6 is connected to the memory cell array 1. The word line control circuit 6 selects a word line in the memory cell array 1 and applies a voltage necessary for reading, writing or erasing to the selected word line.

  The memory cell array 1, the bit line control circuit 2, the column decoder 3, the data input / output buffer 4, and the word line control circuit 6 are connected to a control signal and control voltage generation circuit 7, and the control signal and control voltage generation circuit 7 Be controlled. The control signal and control voltage generation circuit 7 is connected to the control signal input terminal 8, and receives control signals ALE (address latch enable) and CLE (command latch latch) input from the host 11 via the control signal input terminal 8. Enabled), WE (write enable), and RE (read enable).

  The bit line control circuit 2, column decoder 3, word line control circuit 6, control signal and control voltage generation circuit 7 constitute a write circuit and a read circuit.

  FIG. 3 shows the configuration of the memory cell array 1 and the bit line control circuit 2 shown in FIG. A plurality of NAND cells are arranged in the memory cell array 1. One NAND cell includes a memory cell MC made up of, for example, 32 EEPROMs connected in series, and select gates S1 and S2. The selection gate S2 is connected to the bit line BL0e, and the selection gate S1 is connected to the source line SRC. The control gates of the memory cells MC arranged in each row are commonly connected to the word lines WL0 to WL29, WL30, and WL31. The selection gate S2 is commonly connected to the select line SGD, and the selection gate S1 is commonly connected to the select line SGS.

  The bit line control circuit 2 has a plurality of data storage circuits 10. A pair of bit lines (BL0e, BL0o), (BL1e, BL1o)... (BLie, BLio), (BL8ke, BL8ko) are connected to each data storage circuit 10.

  The memory cell array 1 includes a plurality of blocks as indicated by broken lines. Each block includes a plurality of NAND cells, and data is erased in units of blocks, for example. The erase operation is simultaneously performed on two bit lines connected to the data storage circuit 10.

  In addition, a plurality of memory cells arranged every other bit line and connected to one word line (memory cells in a range surrounded by a broken line) constitute one sector. Data is written and read for each sector.

  During the read operation, the program verify operation, and the program operation, the address signals (YA0, YA1,... YAi,... YA8k) supplied from the outside of the two bit lines (BLie, BLio) connected to the data storage circuit 10 are used. In response, one bit line is selected. Furthermore, one word line is selected according to the external address.

  Further, one word line is selected by the external address, and two pages indicated by dotted lines in FIG. 3 are selected. Switching between the two pages is performed by an address. When 2 bits are stored in 1 cell, 2 pages are selected, but when 3 bits are stored in 1 cell, 3 pages are selected, and when 4 bits are stored in 1 cell, 4 pages are selected. The erase operation is performed in units of blocks indicated by dotted lines in FIG.

  FIG. 4 shows a configuration in which all cells arranged in the row direction are written together. In this example, each of the bit lines BL0, BL1,... BL8k-1, BL8k is connected to the data storage circuit 10, and the address signals YA0, YA1,... YA8k-1, YA8k are supplied to the data storage circuits 10, respectively. Has been.

  5A shows a memory cell, and FIG. 5B shows a cross-sectional view of the selection gate. In FIG. 5A, an n-type diffusion layer 42 as a source and drain of a memory cell is formed on a substrate 51 (P-type well region 55 described later). A floating gate (FG) 44 is formed on the P-type well region 55 via a gate insulating film 43, and a control gate (CG) 46 is formed on the floating gate 44 via an insulating film 45. Yes. In FIG. 5B, an n-type diffusion layer 47 as a source and a drain is formed in the P-type well region 55. A control gate 49 is formed on the P-type well region 55 via a gate insulating film 48.

  FIG. 6 is a cross-sectional view of the semiconductor memory device corresponding to the first embodiment. For example, N-type well regions 52, 53 and 54 and a P-type well region 56 are formed in the P-type semiconductor substrate 51. A P-type well region 55 is formed in the N-type well region 52, and a low-voltage N-channel transistor LVNTr constituting the memory cell array 1 is formed in the P-type well region 55. Further, a low-voltage P-channel transistor LVPTr and a low-voltage N-channel transistor LVNTr constituting the data storage circuit 10 are formed in the N-type well region 53 and the P-type well region 56. In the substrate 51, a high-voltage N-channel transistor HVNTr that connects the bit line and the data storage circuit 10 is formed. In the N-type well region 54, for example, a high voltage P-channel transistor HVPTr constituting a word line driving circuit or the like is formed. As shown in FIG. 6, the high voltage transistors HVNTr and HVPTr have, for example, a thicker gate insulating film than the low voltage transistors LVNTr and LVPTr.

  FIG. 7 shows an example of voltages supplied to the respective parts shown in FIG. 6 during erasing, programming, and reading of the memory cell.

  FIG. 8 is a circuit diagram showing an example of the data storage circuit 10 shown in FIG.

  The data storage circuit 10 includes a primary data cache (PDC), a secondary data cache (SDC), a dynamic data cache (DDC), a dynamic data cache Q (DDCQ), and a temporary data cache (TDC). The SDC, PDC, and DDC hold input data at the time of writing, hold read data at the time of reading, temporarily hold data at the time of verification, and are used for internal data operations when storing multi-value data. The TDC amplifies and temporarily holds bit line data when reading data, and is used to manipulate internal data when storing multilevel data. The DDCQ stores data indicating whether or not a verify level slightly lower than a specific verify level has been reached at the time of data writing to be described later.

  The SDC includes clocked inverter circuits 61a and 61b and transistors 61c and 61d that constitute a latch circuit. The transistor 61c is connected between the input terminal of the clocked inverter circuit 61a and the input terminal of the clocked inverter circuit 61b. A signal EQ2 is supplied to the gate of the transistor 61c. The transistor 61d is connected between the output terminal of the clocked inverter circuit 61b and the ground. A signal PRST is supplied to the gate of the transistor 61d. The node N2a of the SDC is connected to the input / output data line IO via the column selection transistor 61e, and the node N2b is connected to the input / output data line IOn via the column selection transistor 61f. A column selection signal CSLi is supplied to the gates of the transistors 61e and 61f. The node N2a of the SDC is connected to the node N1a of the PDC via the transistors 61g and 61h. A signal BLC2 is supplied to the gate of the transistor 61g, and a signal BLC1 is supplied to the gate of the transistor 61h.

  The PDC includes clocked inverter circuits 61i and 61j and a transistor 61k. The transistor 61k is connected between the input terminal of the clocked inverter circuit 61i and the input terminal of the clocked inverter circuit 61j. A signal EQ1 is supplied to the gate of the transistor 61k. The node N1b of the PDC is connected to the gate of the transistor 61l. One end of the current path of the transistor 61l is grounded through the transistor 61m. A signal CHK1 is supplied to the gate of the transistor 61m. The other end of the current path of the transistor 61l is connected to one end of the current path of the transistors 61n and 61o constituting the transfer gate. A signal CHK2n is supplied to the gate of the transistor 61n. The gate of the transistor 61o is connected to the output terminal of the clocked inverter circuit 61a. A wiring COMi is connected to the other end of the current path of the transistors 61n and 61o. This wiring COMi is a wiring common to all the data storage circuits 10, and when the verification of all the data storage circuits 10 is completed, the potential of the wiring COMi becomes high level. That is, as will be described later, when the verification is completed, the node N1b of the PDC goes to a low level. In this state, when the signals CHK1 and CHK2n are set to the high level, the potential of the wiring COMi is set to the high level when the verification is completed.

  Further, the TDC is constituted by, for example, a MOS capacitor 61p. The capacitor 61p is connected between the connection node N3 of the transistors 61g and 61h and the ground. A DDC is connected to the connection node N3 via a transistor 61q. A signal REG is supplied to the gate of the transistor 61q. Further, one end of the capacitor C1 at the node N3 is connected, and the signal BOOST is supplied to the other end of the capacitor C2.

  The DDC is composed of transistors 61r and 61s. The signal VPRE is supplied to one end of the current path of the transistor 61r, and the other end is connected to the current path of the transistor 61q. The gate of the transistor 61r is connected to the node N1a of the PDC through the transistor 61s. A signal DTG is supplied to the gate of the transistor 61s.

  The DDCQ includes transistors 61Qr and 61Qs. The signal VPRE is supplied to one end of the current path of the transistor 61Qr, and the other end is connected to the connection node N3 via the transistor 61Qq. A signal REGQ is supplied to the gate of the transistor 61Qq. The gate of the transistor 61Qr is connected to the node N1a of the PDC through the transistor 61Qs. A signal DTGQ is supplied to the gate of the transistor 61Qs.

  Further, one end of a current path of the transistors 61t and 61u is connected to the connection node N3. The signal VPRE is supplied to the other end of the current path of the transistor 61u, and BLPRE is supplied to the gate. A signal BLCLAMP is supplied to the gate of the transistor 61t. The other end of the current path of the transistor 61t is connected to one end of the bit line BLo through the transistor 61v, and is connected to one end of the bit line BLe through the transistor 61w. The other end of the bit line BLo is connected to one end of the current path of the transistor 61x. A signal BIASo is supplied to the gate of the transistor 61x. The other end of the bit line BLe is connected to one end of the current path of the transistor 61y. A signal BIASe is supplied to the gate of the transistor 61y. A signal BLCRL is supplied to the other ends of the current paths of the transistors 61x and 61y. The transistors 61x and 61y are turned on complementarily to the transistors 61v and 61w in response to the signals BIASo and BIASe, and supply the potential of the signal BLCRL to the unselected bit lines.

  The above signals and voltages are generated by the control signal and control voltage generation circuit 7 shown in FIG. 3, and the following operations are controlled based on the control of the control signal and control voltage generation circuit 7.

  The data storage circuit 10 shown in FIG. 4 is the same as that shown in FIG. 8, and only the connection with the bit line is different. That is, as shown in FIG. 8, only the transistor 61v, for example, is connected to the other end of the transistor 61t, and the bit line BLe or BLo is connected via the transistor 61v.

  This memory is a multi-level memory and can store 2-bit data in one cell. Switching between 2 bits is performed by an address (first page, second page). When 2 bits are stored in one cell, there are two pages. However, when 3 bits are stored in one cell, switching is performed according to addresses (first page, second page, third page). Further, when storing 4 bits in one cell, switching is performed according to addresses (first page, second page, third page, fourth page).

  FIGS. 9A, 9B, and 9C show the relationship between the data and the threshold voltage when 2-bit data is stored in the memory cell. When the erase operation is performed, the data in the memory cell becomes “0” as shown in FIG. After erasing, in order to narrow the spread of the threshold distribution, for example, writing is performed using a verify level “z”. This data “0” is set to a negative threshold voltage distribution, for example.

  As shown in FIG. 9A, in the first page write, when the write data is “1”, the memory cell data remains “0”, and when the write data is “0”, the memory cell The data of “1” is “1”.

  As shown in FIG. 9B, after the second page is written, the data in the memory cell is “0”, “2”, “3”, or “4” depending on the write data. That is, when the data of the memory cell after the first page write is “0” and the write data of the second page is “1”, the data of the memory cell remains “0” and the write data is “0”. In the case of “,” the data in the memory cell is “2”. In addition, when the data of the memory cell after the first page write is “1” and the write data is “0”, the data of the memory cell is “3”, and when the write data is “1”, the memory The cell data is “4”. In the present embodiment, the memory cell data is defined from the lower threshold voltage to the higher threshold voltage. The data “1”, “2”, “3”, “4” are, for example, positive threshold voltages.

  FIG. 10 shows the write order of the two NAND units. In the block, data is written for each page from a memory cell close to the source line. For example, first page data is written to memory cells 1 and 2, and then first page data is written to memory cells 3 and 4. Next, the second page data is written into the memory cells 1 and 2, and the first page data is written into the memory cells 5 and 6. Thereafter, writing is performed sequentially as shown in FIG.

(Read operation)
As shown in FIG. 9B, after the second page write, the memory cell data is set to one of threshold voltage distributions of “0”, “2”, “3”, and “4”. For this reason, the reading of the second page is executed by setting the reading levels “BR”, “CR”, and “DR” between them.

  The read operation will be specifically described.

  First, a voltage Vfix (for example, 1.6 V) is generated from the control signal and control voltage generation circuit 7 and applied to the well of the selected cell, the source line, the unselected bit line, and the selected gate of the unselected block. When the threshold voltage distribution of data “0” is not set on the negative voltage side and the threshold voltage of data “0” is set on the positive voltage side, Vfix is set to 0V.

  The read potential Vfix + AR or BR, CR, DR is applied to the selected word line. For example, when AR = −0.5V, Vfix + AR is 1.1V. At the same time, Vread + Vfix is applied to the non-selected word line of the selected block, Vsg (Vdd + Vth) + Vfix (Vth: threshold voltage of n-channel MOS transistor) is applied to the selection gate SGD of the selected block, and Vfix is applied to SGS. Vfix is also applied to the source line (SRC) and the cell well.

  Next, the signal VPRE of the data storage circuit 10 shown in FIG. 8 is set to Vdd (for example, 2.5 V), the signal BLPRE is set to Vsg (Vdd + Vth), and the signal BLCLAMP is set to, for example, (0.6 V + Vth) + Vfix, and then applied. Thereafter, the bit line is precharged to 0.6V + Vfix = 2.2V, for example. Next, the select line SGS on the source side of the cell is set to Vsg (Vdd + Vth) + Vfix. Since the well and source are at Vfix, the cell is turned off when the threshold voltage of the cell is higher than AR or BR, CR, DR (eg, AR = −0.5 V). For this reason, the bit line remains at a high level (eg, 2.2 V). When the threshold voltage of the cell is lower than AR or BR, CR, DR, the cell is turned on. For this reason, the bit line is discharged to the same potential as the source, that is, Vfix (for example, 1.6 V).

  After that, the signal BLPRE of the data storage circuit 10 shown in FIG. 8 is once set to Vsg (Vdd + Vth), the TDC node is precharged to Vdd, the signal BOOST is changed from low level to high level, and TDC = αVdd (for example, α = 1.7, αVdd = 4.25V). Here, for example, a voltage of (0.45 V + Vth) + Vfix is applied to the signal BLCLAMP. When the bit line is lower than 0.45V + Vfix, the TDC node is at a low level (Vfix (eg, 1.6V)), and when the bit line is higher than 0.45V, it remains at a high level (αVdd (eg, 4.25V)). It becomes. After setting the signal BLCLAMP = Vtr (for example, 0.1 V + Vth), the signal BOOST is changed from the high level to the low level. Here, when the TDC is at a low level, it falls from Vfix (for example, 1.6 V), but since the signal BLCLAMP = Vtr (for example, 0.1 V + Vth), it does not drop from 0.1 V. When TDC is at a high level, αVdd (for example, 4.25 V) is changed to Vdd. Here, as the signal BLC1 = Vsg (Vdd + Vth), the potential of the TDC is read into the PDC. When the threshold voltage of the cell is lower than the level of AR or BR, CR, DR, the PDC is at a low level, and when it is higher, the PDC is at a high level and reading is performed.

(program)
FIG. 11 shows a flowchart of the first page program operation, and FIG. 12 shows a flowchart of the second page program operation.

  In the program operation, first, an address is designated, and two pages shown in FIGS. 3 and 4 are selected. This memory can be programmed only in the order of the first page and the second page of the two pages. Therefore, the first page is first selected by address.

  In the first page program operation shown in FIG. 11, when write data is input from the host 11, these data are stored in the SDCs (shown in FIG. 8) in all the data storage circuits 10 (S11). When a write command is input from the host 11, the data of the SDC in all the data storage circuits 10 is transferred to the PDC (S12). When data “1” (not written) is input from the host 11, the node N1a of the PDC becomes high level in the data storage circuit 10, and when data “0” (written) is input, Become a level. Thereafter, the data of the PDC is the potential of the node N1a, and the data of the SDC is the potential of the node N2a.

(Program operation) (S13)
When the signal BLC1 in FIG. 8 is set to Vdd + Vth, when data “1” (not written) is stored in the PDC, the bit line becomes Vdd and data “0” (written) is stored. The bit line is at Vss. In the case of the configuration shown in FIG. 3, the cell connected to the selected word line and not selected (bit line is not selected) must not be written. For this reason, the bit lines connected to these cells are also set to Vdd as in the cells to which data “1” is input.

  Here, when Vdd is applied to the select line SG1 of the selected block, Vpgm (20V) is applied to the selected word line, and Vpass (10V) is applied to the non-selected word line, if the bit line is Vss, the cell channel Since Vss and the word line become Vpgm, writing is performed. On the other hand, when the bit line is at Vdd, the channel of the cell is not Vss, and the voltage is about Vpgm / 2 due to coupling, so that programming is not performed.

  By writing the first page, the data in the memory cell becomes data “0” and data “1”.

(Program verify read) (S14)
In the program operation, the memory cell is written from a low threshold voltage level. Therefore, program verification is performed at the AV level on the first page. The program verify operation is almost the same as the read operation.

  First, a voltage Vfix (for example, 1.6 V) is generated and applied from the control signal and control voltage generation circuit 7 to the well of the selected cell, the source line, the unselected bit line, and the selection gate of the unselected block. In this state, a potential Vfix + AV slightly higher than the potential Vfix + AR at the time of reading (for example, when AR = −0.4 V, Vfix + AV is 1.2 V) is applied to the selected word line. By applying a potential Vfix + AV at the time of verify read, for example, 1.2 V, to the selected word line, a negative potential can be apparently applied to the gate of the cell. At the same time, Vread + Vfix is applied to the unselected word lines of the selected block, Vsg (Vdd + Vth) + Vfix is applied to the selected gate SGD of the selected block, and Vfix is applied to SGS. Vfix is applied to the source line SRC, and Vfix is also applied to the well of the cell.

  Next, the signal VPRE of the data storage circuit 10 shown in FIG. 8 is set to Vdd (for example, 2.5 V), the signal BLPRE is set to Vsg (Vdd + Vth), the signal BLCLAMP is set to, for example, (0.6 V + Vth) + Vfix, and the bit The line is precharged to eg 0.6V + Vfix = 2.2V.

  Next, the select line SGS on the source side of the cell is set to Vsg (Vdd + Vth) + Vfix. Since the well and the source are at Vfix, the cell whose threshold voltage is higher than AV (for example, AV = −0.4 V) is turned off. For this reason, the bit line remains at a high level (eg, 2.2 V). A cell having a threshold voltage lower than AV is turned on. For this reason, the bit line is discharged and has the same potential as the source, that is, Vfix (for example, 1.6 V). During the discharge time of the bit line, the signal DTG = Vsg (Vdd + Vth) is temporarily copied to the DDC.

  Next, the signal BLPRE of the data storage circuit 10 is once set to Vsg (Vdd + Vth), and the node of the TDC is precharged to Vdd. Thereafter, the signal BOOST is changed from the low level to the high level, and TDC = αVdd (for example, α = 1.7, αVdd = 4.25V) is set. Here, the potential of the signal BLCLAMP is set to, for example, (0.45V + Vth) + Vfix. The TDC node is at a low level (Vfix (eg, 1.6 V)) when the bit line is lower than 0.45 V + Vfix, and remains at a high level (αVdd (eg, 4.25 V)) when the bit line is higher than 0.45 V. . After setting the signal BLCLAMP = Vtr (for example, 0.1 V + Vth), the signal BOOST is set from the high level to the low level. Here, when the signal BOOST is at a low level, the TDC falls from Vfix (for example, 1.6 V). However, since the signal BLCLAMP = Vtr (for example, 0.1V + Vth) is set, the TDC does not fall below 0.1V. When the signal BOOST is at a high level, the node of the TDC changes from (αVdd (for example, 4.25 V)) to Vdd. Here, as the signal BLC1 = Vsg (Vdd + Vth), the potential of the TDC is read into the PDC.

  Next, when the signal VPRE = Vdd and the signal REG = Vsg (Vdd + Vth) and the DDC is at a high level (non-write), the TDC is forcibly set to a high level. However, when DDC is at a low level (non-write), the value of TDC does not change. Here, as the signal BLC1 = Vsg (Vdd + Vth), the potential of the TDC is read into the PDC. Therefore, when the PDC is originally low level (write) and the threshold voltage of the cell is lower than the level AV, the PDC becomes low level (write) again, and when it is higher, the PDC becomes high level and the next program loop Not written.

  When PDC = high level (non-write) originally, PDC = high level, and the next program loop is also non-write. This operation is repeated until the PDC of all the data storage circuits 10 becomes high level (S15-S13).

(2nd page program)
(Second page write operation)
In the write operation of the second page shown in FIG. 12, first, write data is input from the outside and stored in the SDCs in all the data storage circuits 10 (S21). Thereafter, in the first page write, in order to check the written data, the read level AR (for example, negative voltage) is set to the word line, and the data in the memory cell is read (S22). This read operation is as described above. When the threshold voltage of the cell is lower than the word line potential AR, the PDC is at a low level, and when it is higher, the PDC is at a high level.

  Thereafter, the data cache is set (S23). That is, the second page is written as shown in FIG.

  In the case of data “1” in the first page write and in the case of data “1” in the second page write, the second page write is not performed.

  In the case of data “1” in the first page write and in the case of data “0” in the second page write, the data in the memory cell is set to “2” by the second page write.

  In the case of data “0” in the first page write and in the case of data “0” in the second page write, the data in the memory cell is set to “3” by the second page write.

  In the case of data “0” in the first page write and in the case of data “1” in the second page write, the cell data is set to “4” by the second page write.

  To perform this operation, a data cache is set.

  That is, when the data in the memory cell is set to “0” (data “1” on the first page, data “1” on the second page), the PDC is set to the high level, the DDC is set to the low level, and the SDC is set to the high level. The

  When the data in the memory cell is set to “2” (data “1” in the first page, data “0” in the second page), the PDC is set to the low level, the DDC is set to the high level, and the SDC is set to the high level.

  When the data in the memory cell is set to “3” (data “0” in the first page, data “0” in the second page), the PDC is set to the low level, the DDC is set to the high level, and the SDC is set to the low level.

  When the memory cell data is set to “4” (data “0” on the first page, data “1” on the second page), the PDC is set to low level, the DDC is set to low level, and the SDC is set to low level.

  Each data of PDC, DDC, SDC is set by supplying signals BLC1, BLC2, DTG, REG, VPRE in a predetermined order and transferring data of PDC, DDC, SDC, TDC. The specific operation is omitted here.

(Program operation) (S24)
The program operation is exactly the same as the first page program operation. When data “1” is stored in the PDC, writing is not performed, and when data “0” is stored, writing is performed.

(Verify operation) (S25, S26, S27)
The program verify read is the same as the read operation. However, the verify levels BV, CV, DV are set slightly higher than the read level with a margin added to the read level. Verify read is performed using the verify levels BV, CV, and DV.

  The verify operation is executed in the order of verify levels BV, CV, DV, for example.

  That is, first, the verify level BV is set for the word line, and it is verified whether the threshold voltage of the memory cell has reached the verify level BV (S25). As a result, when the threshold voltage of the memory cell has reached the verify level, the PDC becomes high level and writing is not performed. On the other hand, when the verify read level has not been reached, the PDC goes low and writing is performed in the next program.

  Thereafter, a verify level CV is set for the word line, and it is verified whether the threshold voltage of the memory cell has reached the verify level CV (S26). As a result, when the threshold voltage of the memory cell has reached the verify level, the PDC becomes high level and writing is not performed. On the other hand, when the verify read level has not been reached, the PDC goes low and writing is performed in the next program.

  Next, the verify level DV is set to the word line, and it is verified whether the threshold voltage of the memory cell has reached the verify level DV (S27). As a result, when the threshold voltage of the memory cell has reached the verify level, the PDC becomes high level and writing is not performed. On the other hand, when the verify read level has not been reached, the PDC goes low and writing is performed in the next program.

  When the second page is written, if the above operation is performed in the level BV program verify, the cells written in the levels CV and DV are not written in the level BV program verify. Therefore, for example, in the case of level CV and DV writing, the node N2a shown in FIG. 8 is set to a low level, and in the case of level BV writing, the node N2a is set to a high level. In this state, the signal REG = Vsg is set, and in the case of non-writing, before the operation for forcibly setting the TDC to the high level, the signal BLC2 = Vtr (0.1 V + Vth) and the level CV and DV are written. TDC is forced to be at a low level. Thus, the writing is not completed in the program verify at the level BV.

  Further, in the level CV program verify in the second page write, if the above operation is performed, the write cell to the level DV is not written in the level CV program verify. Therefore, for example, in the case of level CV writing, the node N1a shown in FIG. 8 is set to the low level, and in other cases, the node N1a is set to the low level. In this state, the signal REG = Vsg. Further, in the case of non-writing, the signal BLC1 = Vtr (0.1 V + Vth) is set before the operation for forcibly setting the TDC to the high level. In the case of level DV writing, the TDC is forcibly set to a high level so that writing is not completed by program verification at level DV. When the PDC is at the low level, the write operation is performed again, and this program operation and the verify operation are repeated until the PDCs of all the data storage circuits 10 become the high level (S28-S24).

(Erase operation)
As described above, the erase operation is performed in units of blocks indicated by broken lines in FIGS. After erasing, the threshold voltage of the cell becomes data “0” of the memory cell as shown in FIG. After erasing, the threshold voltage distribution of the cell is widened. For this reason, in the case of an EASB (Erased Area Self Boost) writing method, the threshold voltage of the cell is decreased after erasing. First, the EASB writing method will be described. This writing method always writes from the source side.

  FIG. 13 is a diagram showing an EASB writing method. As shown in FIG. 13, first, the bit line is set to Vss when writing and Vdd when not writing. Next, for example, when writing a cell of the word line WL7, the word lines WL0 to WL4 are set to Vpass, the word line WL5 is set to Vss, the word line WL6 is set to Vdd, the word line WL7 is set to Vpgm, and the word lines WL8 to 31 are set to Vpass. At this time, writing is performed because the gate of the word line WL7 is Vpgm and the channel is Vss. In the case of non-writing, the channel is, for example, Vpass / 2. However, if the number of written cells is large, the channel is not easily boothed. However, the EASB writing method is always written from the source side. Accordingly, when the word line WL5 is set to Vss and the booth is set, the cells of the word lines WL8 to 31 are erased, so that the channel is boosted and cannot be written. As described above, it is necessary to prevent the booth charges from moving to the already written cells, and when the cells connected to the word line WL5 are in the erased state, the cells are not turned off when the threshold voltage is deep. . Therefore, it is necessary to make the erase cell shallow.

Therefore, after the erase operation, all word lines in the block are selected, program and program verify read are performed, and the write operation is performed up to level “z” as shown in FIG. 9C. In this program and program verify read operation, all word lines are selected, the potential of the selected word line at verify is z + Vfix (for example, 0 V), and other potentials are exactly the same as those of normal program and program verify read. Set to.
(First embodiment)
FIG. 1, FIG. 14A and FIG. 14B relate to the first embodiment, and show, for example, a read sequence of the first page after writing the second page. In reading the first page after writing the second page, the potential CR is supplied to the selected word line as a read level as shown in FIG. 9B. The read operation of the first page will be described with reference to FIGS. 1, 14A and 14B.

  In the first embodiment, as shown in FIG. 14A, the read level (CR) is located within the threshold voltage distribution to be read. In this case, first, as shown in FIG. 14A, a read level (CR) is set, and data is read from one page of memory cells (2 to 4 kB) according to the read level (CR) (S31). Thereafter, one page of data is read at a read level (CR-x) obtained by subtracting a certain level (x) from the read level (CR) (S32). For example, the host 11 counts the number of cells existing between both levels (CR) and (CR-x) (S33). For example, the data storage circuit 10 takes an exclusive OR (XOR) of data read at both levels (CR) and (CR-x) and supplies the result to the host 11. The host 11 obtains the number of cells existing between both levels by counting the number of data “1” in the supplied data. Next, the host 11 determines whether or not the count value is equal to or less than a specified value (S34). As a result, when the number of cells is within the specified number, the data read at the level (CR) is set as the read result (S35).

  On the other hand, when the count value is not less than the specified value, the read level is lowered and the read operation is performed again (S36, S31, S32). For example, when the read level CR is lowered by x, the number of cells existing between the read levels (CR-x) and (CR-2x) is counted as shown in FIG. Is determined to be less than or equal to the specified value (S33, S34). As a result, when the number of cells is within the specified number, the data read at this level is set as the read result (S35).

  At this time, if the value to decrease the read level is the same value as (x) used in the previous read, the read level CR in step S31 is the data read at the read level (CR-x) in step S32. It has already been read. For this reason, there is no need to read by the read level (CR-x). Therefore, step S31 can be omitted and the number of readings can be reduced.

  FIG. 15 is a slow chart showing a specific operation of the data storage circuit 10 in the read operation. In FIG. 15, the same parts as those in FIG.

  First, a read level (CR) is applied to the selected word line to read data in the memory cell. The read data is latched in the PDC and then copied to the DDC0 (S31). Thereafter, the PDC data is copied to the SDC. Next, a read level (CR-x) is applied to the selected word line to read data in the memory cell. The read data is latched in the PDC and then copied to the DDC 1 (S32).

  Next, an exclusive OR (XOR) of the data of DDC0 and the data of DDC1 is taken (S33-1). That is, the signal VPRE is set to Vss, the signal BLPRE is set to Vdd, and the TDC is set to Vss. Thereafter, the signal VPRE is set to Vdd, the signal REG0 is set to the high level, and the data of DDC0 is copied to the TDC. Next, when the signal VPRE is set to Vss and the signal REG1 is set to high level and the data of the DDC1 is “1”, the TDC is forcibly set to Vss. Thereafter, the TDC data is transferred to the PDC. As a result, the data of DDC0, DDC1, and PDC are as follows.

DDC0: 1 1 0 0
DDC1: 1 0 1 0
PDC: 0 1 0 0
Next, the signal VPRE is set to Vss, the signal BLPRE is set to Vdd, and the TDC is set to Vss. Thereafter, the signal VPRE is set to Vdd and the signal REG1 is set to the high level to copy the data of the DDC1 to the TDC. Further, when the signal VPRE is set to Vss, the signal REG0 is set to high level, and the data of the DDC1 is “1”, the TDC is forcibly set to Vss. As a result, DDC0, DDC1, PDC, and TDC data are as follows.

DDC0: 1 1 0 0
DDC1: 1 0 1 0
PDC: 0 1 0 0
TDC: 0 0 1 0
Next, the signal DTG0 is once set to the high level, the PDC data is transferred to the DDC0, the signal VPRE is set to Vdd, the signal REG0 is set to the high level, and when the DDC0 is “1”, the TDC is forcibly set to Vdd. Thereafter, the TDC data is transferred to the PDC. As a result, data obtained by XORing the data of DDC0 and DDC1 is latched in the PDC as follows.

DDC0: 0 1 0 0
DDC1: 1 0 1 0
PDC: 0 1 1 0
Thereafter, the host 11 counts the number of data “1” from the XOR result (S33-2). That is, the signal DTG0 is set to the high level, the PDC data is copied to the DDC0, the SDC data is copied to the PDC, and the DDC0 data is copied to the SDC. The SDC data is output to the host 11. The host 11 counts the number of data “1” supplied from each data storage circuit.

  Next, in the host, it is determined whether or not the count value is equal to or less than a specified value (S34). As a result, if it is equal to or less than the specified value, the data read at the read level (CR) is latched in the PDC, so the data in the PDC is copied to the SDC and output from the SDC to the host 11 (S35).

  In step S34, if the count value is equal to or greater than the specified value, the read level is lowered (S36), and the read operation is performed again. Here, when using data read at the read level (CR-x) before, since the data read at the read level (CR-x) is in the DDC1, the data of the DDC1 is copied to the PDC and (CR-x ) Is the data read in (CR). In this case, step S31 can be omitted as indicated by a broken line in FIG.

  According to the first embodiment, data is read out in place of the read levels (CR) and (CR-x), the number of cells existing between the two read levels is counted, and this count value is less than a specified value. In some cases, data read at the read level (CR) is output as regular read data. For this reason, even when the margin between adjacent threshold voltage distributions is narrowed due to, for example, a change with time, data of each threshold distribution can be accurately read.

  In the first embodiment, reading is performed at a reading level (CR-x) obtained by subtracting a certain level (x) from the reading level (CR). However, the present invention is not limited to this. For example, reading is performed at a read level (CR + x) obtained by adding (x) to the read level (CR), and the number of cells existing between the read levels (CR) and (CR + x) is counted. It is also possible to compare this count value with a reference value.

  In the first embodiment, the number of cells and the comparison between the count value and the reference value are performed by the host 11, but the present invention is not limited to this. For example, the control signal and the control voltage generation circuit 7 It is also possible to do this.

(Second Embodiment)
FIGS. 16A, 16B, and 17 show a read sequence of the first page of the memory cell according to the second embodiment. In FIG. 17, the same parts as those in FIG.

  As shown in FIG. 16A, when the read level (CR) is located in a threshold voltage distribution lower than the read target threshold voltage distribution, if the read level (CR) is further lowered by a certain level (x). The specified number will increase. Therefore, in the second embodiment, in such a case, the read level is increased and reread is performed.

  That is, as shown in FIGS. 16B and 17, first, similarly to the first embodiment, one page of memory cells (2 to 4 kB) according to read levels (CR) and (CR-x). Data is read from (S31, S32). The number of cells existing between the read levels (CR) and (CR-x) is counted (S33). It is determined whether or not the count value is equal to or less than a specified value (S34). As a result, when it is below the specified value, the data read at the read level (CR) is output as normal data.

  On the other hand, if the determination result is equal to or greater than the specified value, the read operation is performed at the read level (CR + y) obtained by adding the constant level (y) to the read level (CR) (S41), and the read level that has already been read ( The number of memory cells existing between CR) and the read level (CR + y) is counted (S42). Thereafter, it is determined whether (number of cells not less than (CR-x) and not more than (CR)) <(number of cells not less than (CR) and not more than (CR + y)) (S43). As a result, when this condition is satisfied, the read level is lowered (S45), and the read operation is performed again (S31).

  At this time, assuming that the constant levels (x) and (y) are levels having the same potential difference, the data read at the read level (CR-x) first is set as the data read at (CR). Thus, as indicated by a broken line in FIG. 17, the read operation (step S31) at the read level (CR) can be omitted. Further, by using the data read at the read level (CR) as the data read at (CR + y), the read operation (step S41) at the read level (CR + y) can be omitted as shown by the broken line.

  In step S43, when the condition is not satisfied, that is, (the number of cells not less than CR−x and not more than CR)> (number of cells not less than CR and not more than CR + y), the read level is set to a certain level (y ) And the read operation is performed again (S44 to S31).

  At this time, by setting the data read at the read level (CR + y) to the data read at (CR), the read operation at the read level (CR) (step S31) can be omitted. Since the data read at the read level (CR) is changed to the data read at (CR-x), the read operation (step S32) at the read level (CR-x) can be omitted. Therefore, in this case, as shown by a broken line in FIG. 17, the control is shifted from step S44 to S33. Furthermore, in this case, since the read level (CR) is (+ y) in step S44, step S41 can also be omitted as indicated by a broken line.

  When the above operation is repeated and the condition of step S34 is satisfied, regular data is read out.

  In addition, when the above operation is repeated, convergence may not occur. In this case, a maximum value is set for the number of repetitions, and the process ends when the number of repetitions reaches the maximum value.

  Alternatively, each time the above operation is repeated, the values of the constant levels (x) and (y) can be reduced.

  According to the second embodiment, an optimum value between adjacent threshold voltage distributions can be set by raising or lowering the read level. For this reason, even when the margin between adjacent threshold voltage distributions is small, it is possible to read data reliably.

(Third embodiment)
FIGS. 18A, 18B, 18C, and 19 show a first page read sequence according to the third embodiment. The third embodiment is a modification of the first embodiment.

  NAND flash memory writes 2-4 kB cells at the same time, but the data written to each level is not at the same rate. For example, in the case where 4 bits of data are stored at 16 levels in one cell and the writing unit is 4 kB = 32 kbits, and there is data evenly at each level (threshold voltage distribution), 32 kbits / 16 = 2k bits. However, depending on the write data, there may be 10 bits or less or 0 bits.

  In this case, as shown in FIG. 18A, when reading is performed at the read levels (CR) and (CR-x) using the first embodiment, and the number of cells existing between these read levels is counted. The count value is below a specified value. For this reason, repeated reading is not performed.

  In the third embodiment, in order to make a more accurate determination, as shown in FIGS. 18B and 18C, the read levels (CR) and (CR-x) and the read level (CR) are set to a constant level (z ) Is added to (CR + z) to read data from the cell, and the ratio of the number of cells existing between these read levels (CR-x) and (CR + z) is compared with the specified value. The constant level (z) is larger than, for example, (x) and (y), and the number of cells existing between the read levels (CR) and (CR + z) includes the majority of cells existing in the threshold voltage distribution. Set to.

  In the sequence shown in FIG. 19, the same parts as those in the first embodiment are denoted by the same reference numerals. In steps S31 and S32, after reading data from the cell at the read levels (CR) and (CR-x), the read level (CR + z) obtained by adding a constant value (z)> (x) to the read level (CR). Thus, data is read from the cell (S32-1). Thereafter, for example, in the host 11, the number of cells existing between the read levels (CR) and (CR-x) is counted, and the number of cells existing between the read levels (CR) and (CR + z) is counted. (S33-3). Next, it is determined whether (number of cells not less than CR-x and not more than CR) / (number of cells not less than CR and not more than CR + z) is not more than a specified value (S34-1). As a result, when the value is less than the specified value, the data read at the read level (CR) is output as normal data. On the other hand, if it is determined that the value is equal to or greater than the specified value, the read operation is repeated with the read level (CR) lowered by a certain value (x) (S36).

  According to the third embodiment, the number of cells existing between the read levels (CR) and (CR−x) is counted, and the number of cells existing between the read levels (CR) and (CR + z) is calculated. The read level is determined by counting and determining whether (number of cells not less than CR−x and not more than CR) / (number of cells not less than CR and not more than CR + z) is not more than a specified value. For this reason, even when data does not exist evenly at each level (threshold voltage distribution) of the cell, the data of the memory cell can be read accurately.

(Fourth embodiment)
FIG. 20 shows a first page read sequence according to the fourth embodiment. The fourth embodiment is a modification of the second and third embodiments, and the same reference numerals are given to the same parts as those in FIGS. 17 and 19.

  As shown in FIG. 20, the fourth embodiment counts the number of cells existing between read levels (CR) and (CR-x) and reads the read level ( The number of cells existing between (CR) and (CR + z) is counted, and it is determined whether (number of cells not less than CR-x and not more than CR) / (number of cells not less than CR and not more than CR + z) is not more than a specified value. (Steps S31 to S34-1).

  As a result, if it is not less than the specified value, data is read at the read level (CR + y) as in the second embodiment, and (cells of CR−x or more and CR or less) <(cells of CR or more and CR + y or less) ) Is satisfied (steps S42 and S43). If the condition is satisfied as a result of this determination, the read level is lowered and read (step S31 or S32). Further, if the determination result condition is not satisfied, the read level is increased and read (step S44 to S31 or S32-1).

  According to the fourth embodiment, even when the read level is on the lower side of the two adjacent threshold voltage distributions and the ratio of the threshold voltage distributions is different, the data in the memory cell is reliably read out. Can do.

  In the first to fourth embodiments, after comparing the count value or the ratio of the count value with the specified value, the read level is changed by the same level as (x) or (y) used in the determination. And read again. However, it is not limited to this.

  FIG. 21 shows a modification of the first to fourth embodiments, and shows the fourth embodiment as an example. In the case of this modification, as shown in steps S44-1 and S44-2 in FIG. 21, the read level CR is set and read again. That is, in step S44-1, the read level CR is set to CR + α, and in step S44-2, the read level CR is set to CR−α. The value of α is, for example, a value equal to or smaller than x, and is set to be small every time rereading is performed.

  As described above, it is possible to set an optimum read level by repeating the re-read operation by gradually decreasing the value to be added to or subtracted from the read level CR, that is, the value of α. However, even in this example, there are cases where convergence does not occur when re-reading is performed repeatedly. In such a case, a maximum value may be set for the number of repetitions, and the process may be terminated when the number of rereads reaches the maximum value.

  Also in the second to fourth embodiments, as in the first embodiment, the number of cells and the comparison between the count value and the reference value are not limited to the host 11. For example, the control signal The control voltage generation circuit 7 can also be used.

(Fifth embodiment)
FIG. 22 shows a first modification of the first embodiment, and the same components as those in FIG. 15 are denoted by the same reference numerals.

  In the first embodiment, the XOR between the data read at the read level (CR) and the data read at the read level (CR-x) is output from the SDC to the host 11 and the number of data “1” is counted. did. However, there is a problem that it takes time to output and count one bit to several bits at a time. When the PDC of the data storage circuit 10 illustrated in FIG. 8 latches data “0”, the node N1b is at a high level. Therefore, when the signal CHK2n and the signal CHK1 are at a high level, the potential of the wiring COMi is Go down. The wiring COMi is connected to all the data storage circuits 10. Therefore, a current flows according to the number of data storage circuits 10 in which the node N1b is at a high level. Therefore, by monitoring the current connected to the wiring COMi, the data “1” obtained by XORing the read result at the read level (CR) and the read result at the read level (CR−x). Can be detected.

  That is, as shown in FIG. 22, in step S33-1, after the result of XOR is transferred to the PDC, the data in the PDC is inverted (S33-3). Thereafter, the current of the wiring COMi is monitored (S33-4). As a result, when the current value of the wiring COMi is equal to or less than the specified value, the data read at the read level (CR) is latched by the SDC, and therefore the SDC data is output (S35-1). On the other hand, when the current of the wiring COMi is not less than the specified value, the read level CR is lowered by (x) (S36), and the read operation is executed again.

  The same effect as that of the first embodiment can also be obtained by the above configuration. In addition, the host 11 merely compares the current value of the wiring COMi with the specified value, and does not need to count the number of XORed data “1” supplied from the data storage circuit 10, thereby speeding up the determination operation. Is possible.

  In the above description, the first embodiment is modified. However, the second to fourth embodiments can be similarly modified.

(Sixth embodiment)
FIG. 23 shows a second page read sequence. In reading the second page, as shown in FIG. 9B, a potential (BR) or (DR) is supplied to the selected word line as a read level. At the time of reading at these read levels (BR) (DR), the read level (BR) (DR) is corrected according to the correction value of the read level CR detected in the first page read operation.

  That is, the data “2”, “3”, and “4” of the second page are written simultaneously. For this reason, the intervals of the threshold voltage distribution of these data are almost equal. Therefore, in the reading of the first page, the read level (BR) (DR) is optimally set by adding the correction value of the detected read level (CR) to the read level (BR) (DR). Can do.

  The correction value is set as follows. For example, in the case of reading the first page, when the data read at the read level CR is output, the correction value is “0”, and the data read at the read level CR-x is output The correction value is “−x”.

  In the reading of the second page shown in FIG. 23, first, data is read from a plurality of memory cells connected to the selected word line by the read level (DR) + correction value, and these data correspond to each other. It is latched by PDC and DDC0 of the data storage circuit (S51). Thereafter, data is read from a plurality of memory cells connected to the selected word line by the read level (BR) + correction value, and these data are latched by the PDC and DDC0 of the corresponding data storage circuit. (S52). Next, the PDC data is copied to the SDC and output to the outside (S53).

  According to the sixth embodiment, the correction value obtained in the first page read operation is added to the read level (BR) (DR) used in the second page read operation. For this reason, the data of the second page can be read at the optimum read level. In addition, it is not necessary to detect the optimum read level as in the first page read operation. Therefore, the delay of the read operation for the second page can be prevented.

  Of course, the read sequence of the second page is the same as the read sequence of the first page, and the optimum read level is detected by obtaining the correction value at each of the read levels (BR) and (DR). It is also possible to read data.

  In addition, if the same block is controlled to be written at the same time, the correction value may be close. In such a case, the correction value obtained by reading the word line WL0 can be used for reading the other word lines WL1 to WL31 in the same block. By doing in this way, it can prevent that reading speed falls.

(Seventh embodiment)
In the first to sixth embodiments, the read operation has been described. In contrast, the seventh embodiment describes an improvement in program operation.

  A QPW (Quick Pass Write) method has been devised as a method of narrowing the threshold voltage distribution width after writing while suppressing an increase in writing time. In the QPW method, an intermediate potential is applied to the bit line at the time of writing after the next time for a cell exceeding a level lower than the original verify level, and the fluctuation of the threshold voltage is reduced by reducing the writing strength. The threshold voltage distribution can be narrowed.

  24 and 25 generally show a QPW scheme schematically. In this QPW method, similarly to the above-described program operation, after the data is loaded into each data storage circuit 10, the program operation is performed (S51, S52). In verifying each level, the first verify operation is performed by setting the word line potential to a level (AVL, BVL, CVL) lower than the original verify level (S53, S54, S55). As a result of the verification, if the level (AVL, BVL, CVL) has not been reached, the program voltage Vpgm is increased by a certain voltage, and the program and verify are performed again (S56, S57, S52).

  On the other hand, if the threshold voltage of the memory cell has reached a level (AVL, BVL, CVL) lower than the original verify level, the cell channel and control are performed by supplying an intermediate potential to the bit line in the next write. The potential difference with the gate is reduced to weaken the writing, the change in the threshold voltage of the cell is reduced, and the writing and verifying operations are repeated until the original verify level (AV, BV, CV) is reached.

  As described above, the QPW method generally requires two verifications, ie, verification using a level lower than the original write verification level and verification using the original write verification level, so the verification time is doubled. Or there is a problem of increasing nearly twice.

  FIG. 25 shows the program pulse voltage applied to the cell and the change in the threshold voltage after the program pulse voltage is applied when level “C” is written by the QPW method. As apparent from FIG. 25, after the threshold voltage of the cell exceeds the lower verify level CVL, the increment of the program pulse voltage is reduced and the writing is weakened. For this reason, it turns out that the change of the threshold voltage of a cell has decreased.

  FIG. 26 shows a program sequence of the seventh embodiment, and FIG. 27 shows a change in threshold voltage after application of each program pulse in a cell written at level “C”. In FIG. 26, the same parts as those in FIG. 24 are denoted by the same reference numerals, and only different parts will be described. In the seventh embodiment, three threshold voltages are simultaneously written using verify levels (AV, BV, CV).

  As shown in FIG. 26, in the seventh embodiment, only the verifications (S58, S59, S60) using the original verification levels (AV, BV, CV) are executed. In this verification, writing is performed while stepping up the program voltage Vpgm after exceeding the verify level (BV) that is one level lower than the verify level corresponding to the threshold voltage to be written, and this writing has exceeded the third time, for example. In this case, after the next program, writing is weakened by supplying an intermediate potential to the bit line (S71). In this state, verification is performed using the level CV (S59). As a result, when the threshold voltage of the cell does not reach the level CV, the PDC is at the low level (S56). Therefore, the program voltage is stepped up (S57), and weak writing is performed again (71). This operation is repeated until all PDCs become high level.

  In this operation, when the level CV is verified, if the writing to the next lower verify level (AV) has been completed, this verify operation can be skipped. In the case of verify at the lowest verify level (AV), there is no level below this. Therefore, in step S58 of FIG. 26, for example, verification at level AV is performed twice, as shown in FIG. 24, verification at a lower verification level (AVL) and verification at the original verification level (AV). You may go.

  As shown in FIG. 27, in the seventh embodiment, a cell written to the level “C” exceeds the verify level BV of the level “B” (the verify level one level lower than the level “C”). The writing is weakened by applying an intermediate potential to the bit line after the nth writing, for example, after the third writing (after the 9th writing in the figure). Therefore, the change in threshold voltage is reduced.

As shown in FIG. 27, in the seventh embodiment, a cell written to the level “C” exceeds the verify level BV of the level “B” (the verify level one level lower than the level “C”). The writing is weakened by applying an intermediate potential to the bit line after the nth writing, for example, after the third writing (after the 9th writing in the figure). Therefore, the change in threshold voltage is reduced.

  In the seventh embodiment, n = after the third writing, but the present invention is not limited to this, and the value of n may be determined as an optimum number by evaluation.

(Eighth embodiment)
FIG. 28 shows a program sequence according to the eighth embodiment, and FIG. 29 shows a change in threshold voltage after application of each program pulse in a cell written at level “C”. The eighth embodiment is a modification of the seventh embodiment. In FIG. 28, the same parts as those in FIG.

In the seventh embodiment, after the verify level that is one level lower than the verify level to be written is exceeded, the writing is weakened after the n-th writing. On the other hand, in the eighth embodiment, as shown in Step 81 of FIG. 28, after the verify level that is two levels below the verify level to be written is exceeded, the verify level that is one level lower than the verify level to be written is set. The number of times of writing until reaching the level is counted k times (here, 3 times), and the bit line is read from the hth time (h = k ± α, α: correction value) after exceeding the next verify level. By applying an intermediate potential, etc., writing is weakened and fluctuations in threshold voltage are reduced. The number of times “h” is, for example, α = 0, and h is also 3 times. That is, as shown in FIG. 29, when writing to level “C”, the number of times of writing from exceeding the verify level AV to reaching the verify level BV Count. When counting is performed for each cell in which writing is performed, a circuit for counting the number is provided in the data storage circuit connected to each bit line, and this circuit is used. In addition, when obtaining the average value of simultaneously written cells, for example, a counter is provided in the control signal and control voltage generation circuit 7, and for example, the number of step-ups of the program voltage Vpgm may be counted by this counter. When the count value of this counter is “k” = 3 and “α” is set to “0”, for example, an intermediate potential is supplied to the bit line from the verify level BV by “h” = third write. To weaken the writing.

  The number of times “h” is a value obtained by adding the correction value “α” to the count value “k”. However, normally, the higher the level of the margin between the threshold voltages stored in the memory cell, the more margin is required to improve data retention. That is, (BV-AV) ≦ (CV-BV). For this reason, the number of times “h” may be substantially the same as the count value “k”.

  According to the eighth embodiment, the same effect as that of the seventh embodiment can be obtained. Moreover, according to the eighth embodiment, each threshold distribution can be written accurately even when there are fast writing cells and slow writing cells.

(Ninth embodiment)
FIG. 30A shows a binary threshold voltage distribution storing 1 bit in one cell, and FIG. 30B shows a 16 threshold voltage distribution storing 4 bits in one cell. The 16-value has an advantage that 4 bits can be stored in one cell. However, each threshold voltage distribution must be written narrowly. For this reason, it is necessary to repeat writing and verifying operations little by little, and the writing speed becomes very slow. In FIGS. 30A and 30B, a threshold voltage distribution indicated by a solid line indicates a state immediately after writing, and a threshold voltage distribution indicated by a broken line indicates a state when left for a long period of time. As described above, when left unattended for a long time, the threshold voltage distribution is widened, so that the data retention margin (margin between threshold voltage distributions) is small.

  FIG. 31 shows the relationship between the number of times of writing / erasing of the NAND flash memory and the necessary data retention margin. As is apparent from FIG. 31, in the NAND flash memory, a necessary data retention margin increases with an increase in writing / erasing. Therefore, if the binary value is 100,000 times of write / erase and the 16 value is 1,000 times of write / erase, the required data retention margin can be reduced. Has been.

  FIG. 32 schematically shows a NAND flash memory according to the ninth embodiment. The memory cell array 1 of the NAND flash memory (corresponding to the memory cell array 1 in FIG. 2) includes a plurality of blocks BLK0 to BLK4095 which are erase units. In the ninth embodiment, among these blocks, a block included in the first area 91 surrounded by a broken line is used for storing binary data and included in a second area 92 surrounded by a broken line. This block is used for storing 16-value data. For example, when it is necessary to write data at high speed, or data that is frequently written / erased is written in a binary data block included in the first area 91. Further, for example, control is performed so that data that does not require high-speed writing and has a small number of times of writing / erasing is written in the second area 92. This write area selection control is performed by, for example, the host 11. That is, the host 11 writes frequently rewritten data in the first area 91 and writes other data in the second area 92, such as system information updated every time data is rewritten.

  According to the ninth embodiment, the memory cell array 1 is divided into a first area 91 and a second area 92, and a plurality of blocks included in the first area 91 are used as binary data storage blocks. A plurality of blocks included in the second area 92 are used as 16-value data storage blocks. For this reason, it is possible to prevent the deterioration of the data retention margin and the decrease of the writing speed.

  FIG. 33 shows a write sequence when 16 values are stored in one cell shown in FIG. In this case, after one write operation, 16 verify operations are performed (S81). This write and verify operation is repeated until all the cells that are simultaneously written pass the verify. If there is no cell to be written at the level to be written, this verification can be skipped.

  On the other hand, the die sort test may be sufficient to evaluate only the data with the lowest threshold voltage and the highest threshold voltage. FIG. 34 shows a write operation during the die sort test. In this case, first, a test command is input from the outside (S91). In response to this test command, for example, verify is executed only for level “0”, level “1”, level “F”, or only level “1” and level “F” (S92). By doing so, it is possible to shorten the test time.

  In the test, it is shown that the verification is performed only for level “0”, level “1”, level “F”, or only level “1” and level “F”. It is also possible to perform only any specific level or any specific number of levels of verification.

(Tenth embodiment)
FIG. 35 shows a case where the NAND flash memory is used as a storage / reproduction device for multimedia data such as music data and image data. The storage / reproduction device 100 is, for example, a personal computer or a mobile phone, and includes a communication unit 101 such as an Internet connection unit or a radio, a NAND flash memory 102, a reproduction circuit 103, and a control unit 104. Recently, it is possible to purchase music data or image data from the data server 110 using such a storage / reproduction device 100. That is, when purchasing music data or image data, the user accesses the data server 110 via the Internet or wireless communication means of the storage / reproduction device 100 and makes a purchase request for music data or image data. In response to this request, the data stored in the data server 110 is downloaded to the storage / reproduction device 100 via communication means such as the Internet. The data downloaded to the storage / reproduction device 100 is stored in the NAND flash memory 102.

  By the way, music data or image data may have a very large data amount. For this reason, it may take time to write to the NAND flash memory 102. Moreover, when the NAND flash memory 102 stores, for example, 16-value data in one cell, there is a problem that it takes a long time to write a large amount of data because the writing speed is slow.

  FIG. 36 and FIG. 37 relate to the tenth embodiment and show a method for downloading music data and image data while reproducing them.

  When reproducing music data or image data stored in the NAND flash memory 102 using the recording / reproducing device 100, the control unit 104 of the recording / reproducing device 100 displays the music data to be reproduced in the NAND flash memory 102 or Whether there is image data is searched (S100). If there is data, the data is reproduced by the reproduction circuit 103 (S101).

  On the other hand, when there is no music data or image data to be reproduced in the NAND flash memory 102, the control unit 104 searches whether there is purchase right data in the NAND flash memory 102 (S102). As a result, if there is no purchase right data, the user is prompted to input whether or not to purchase the data (S103). If purchase is desired, the data server 110 is accessed via the communication means 101 such as the Internet or wireless. Then, a purchase request for music data or image data desired to be purchased is transmitted (S104). When the purchase request is approved by the data server 110, the control unit 104 downloads the purchase right data from the data server 110 (S105), and stores the downloaded purchase right data in the NAND flash memory 102 (S106). That is, at this time, music data and image data having a large amount of data are not downloaded, but only purchase right data consisting of a small amount of data is downloaded. For this reason, the time required for downloading the purchase right data and storing it in the NAND flash memory 102 can be shortened.

  Thereafter, when the user reproduces music data or image data, it is determined whether or not there is purchase right data in step S102 via step S100. In this case, since the purchase right data is stored in the NAND flash memory 102, the control unit 104 accesses the data server 110 via the communication unit 101, and music data or image data corresponding to the purchase right data. Is downloaded (S107). The downloaded data is stored in the NAND flash memory 102 and reproduced (S108). Since the data reproduction time is much longer than the speed at which data is written to the NAND flash memory 102, there is no problem in reproducing data even if the downloaded data is written to the NAND flash memory 102 while being reproduced.

  The downloaded data is stored in, for example, a buffer circuit (not shown), and the data stored in the buffer circuit is reproduced and written into the NAND flash memory 102.

  Further, as indicated by a broken line, steps 107 and 108 can be executed immediately after step S106.

  According to the tenth embodiment, when purchasing music data or image data, first, only purchase right data with a small amount of data is downloaded, and when music data or image data is played back, The corresponding music data or image data is being written to the NAND flash memory 102 while being reproduced. Therefore, music data and image data having a large amount of data can be downloaded without being aware of the time required for writing.

  In the ninth and tenth embodiments, the first to sixth embodiments can be used for reading data, and the seventh and eighth embodiments can be applied to writing data. is there.

  In each of the above embodiments, data to be written in the memory cell is not limited to 2 bits and 4 bits, but can be 3 bits or n bits of 5 bits or more.

  Of course, various modifications can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 7 ... Control signal and control voltage generation circuit, 10 ... Data storage circuit, 11 ... Host, 91, 92 ... 1st, 2nd area | region, 100 ... Memory | storage player, 101 ... Communication means, 102 ... NAND flash memory, 103... Reproduction circuit, 104.

Claims (4)

  1. A memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix;
    A voltage generation circuit for generating the potential of the word line and the bit line;
    A data storage circuit which is connected to the bit line and stores write data of the memory cell or data read from the memory cell;
    A controller for controlling the voltage generation circuit and the data storage circuit,
    The control unit sets the threshold voltage of the memory cell to the first level by an erasing operation, and repeats the writing and verifying operation to set the threshold voltage of the memory cell to the first level according to write data input from the outside. Level, second level,..., Nth level (n = 2 k ), k-bit data is stored, and (h−1) th of the cells written to the hth level (h ≦ n) Counting j times (j is a natural number) of write operations after exceeding the (h-1) th level for cells exceeding the level, and slowing down the write speed in the jth and subsequent write operations. A semiconductor memory device.
  2. A memory cell array in which a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix;
    A voltage generation circuit for generating the potential of the word line and the bit line;
    A data storage circuit which is connected to the bit line and stores write data of the memory cell or data read from the memory cell;
    A controller for controlling the voltage generation circuit and the data storage circuit,
    The control unit sets the threshold voltage of the memory cell to the first level by an erasing operation, and repeats the writing and verifying operation to set the threshold voltage of the memory cell to the first level according to write data input from the outside. Level, second level,..., Nth level (n = 2 k ), k-bit data is stored, and (h−2) th of the cells written to the hth level (h ≦ n) The number of times of writing i (i is a natural number) from when the level is exceeded until when the level exceeds the (h-1) th level is counted, and in the writing to the hth level, the (h-1) th level is exceeded. A semiconductor memory device, wherein a writing speed is slowed down in a writing operation after j (j = i + α) (α is a natural number including “0”) times for a cell.
  3. In the write operation, the control unit performs the first level, the second level,... The nth level (n = 2). k ) Of n levels, and in the write operation after the input of the first command, only the verify operation for h (h <n) levels among the n levels is performed. The semiconductor memory device according to claim 1.
  4. 4. The semiconductor memory device according to claim 3, wherein the control unit performs only a first level or nth level verify operation in the write operation after the first command is input.
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