JP2011164903A - Data communication controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data communication controller allowing proper adjustment of operation timing of a bus. <P>SOLUTION: The data communication controller includes a bus bridge 20 between a CPU core 10 and a peripheral apparatus 60, the CPU core and the bus bridge are connected by a high-speed bus 70, and the peripheral apparatus and the bus bridge are connected by a low-speed bus 72. The data communication controller includes changeover control parts 30. 62A dynamically or statically changing over a transmission method of data by the low-speed bus to the bus bridge from the peripheral apparatus between serial communication and parallel communication when transmitting the data to the CPU core from the peripheral apparatus through the bus bridge. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data communication control device that controls data communication between a CPU core and peripheral devices.

  Conventionally, a serial-parallel conversion reception block that converts a serial reception input signal into a parallel reception signal, a parallel-serial conversion transmission block that converts a parallel transmission signal into a serial transmission output signal, and a plurality of input / output ports A communication data bus connecting the reception block or transmission block and the input / output port selected by the selector, a CPU data bus for MPU connection connectable to the input / output port selected by the selector, a communication data bus, There is known a fixed channel type gate array having a data register connected to a CPU data bus and storing transmission data transmitted to the transmission block or reception data from the reception block by the data register (for example, Patent Document 1). reference).

Japanese Unexamined Patent Publication No. 08-147140

  By the way, when realizing a function that was previously realized by multiple microcomputers with a single microcomputer, or when realizing a function that was conventionally realized by multiple microcomputers with a multi-core type microcomputer, between these functions Difference, required bandwidth, required response, etc. need to be considered. For this reason, it is necessary to mount a plurality of buses that guarantee a plurality of bands in accordance with these differences and the like, but mounting such a plurality of buses is disadvantageous in terms of cost.

  SUMMARY An advantage of some aspects of the invention is that it provides a data communication control device that can appropriately adjust the operation timing of a bus.

In order to achieve the above object, according to one aspect of the present invention, there is provided a data communication control device for controlling data communication between a CPU core and peripheral devices,
A bus bridge is provided between the CPU core and peripheral devices.
The CPU core and the bus bridge are connected by a high-speed bus,
The peripheral device and the bus bridge are connected by a low-speed bus,
When transmitting data from the peripheral device to the CPU core via the bus bridge, the data transmitted from the peripheral device to the bus bridge via the low-speed bus is stored in the buffer of the bus bridge in a predetermined number of bits. Is configured to transmit the predetermined number of bits of data to the CPU core on the high-speed bus
A data communication control device comprising: a switching control unit that dynamically or statically switches a data transmission method from the peripheral device to the bus bridge via the low-speed bus between serial communication and parallel communication. Provided.

  ADVANTAGE OF THE INVENTION According to this invention, the data communication control apparatus which can adjust the operation timing of a bus | bath appropriately is obtained.

It is a figure which shows the principal part structure of the microcomputer 1 which actualizes one Example of the data communication control apparatus by this invention. FIG. 2 is a functional conceptual diagram of a bus bridge 20 and peripheral functions 60 in FIG. 1. 3 is a flowchart showing a flow of data exchange between the bus bridge 20 and a peripheral function 60. 4A shows a parallel communication waveform when data is output in parallel, and FIG. 4B shows a parallel communication waveform when data is output serially. 3 is a table showing an example of serial / parallel selection viewpoints that may be employed in the serial / parallel control unit 30. FIG. It is a figure which shows an example of the detail of the serial / parallel control part 30 when implement | achieving static switching. It is a flowchart which shows operation | movement of the serial / parallel control part 30 shown in FIG. It is a figure which shows an example of the detail of the serial / parallel control part 30 when implement | achieving semi-dynamic switching. It is a flowchart which shows operation | movement of the serial / parallel control part 30 shown in FIG. It is a figure which shows an example of the detail of the serial / parallel control part 30 when implement | achieving perfect dynamic switching. 11 is a flowchart showing an operation of the serial / parallel control unit 30 shown in FIG. 10. It is a figure which shows an example of the detail of the serial / parallel control part 30 at the time of mounting using software. 13 shows an operation flowchart of the software unit 30B of FIG. It is a functional conceptual diagram of the bus bridge 20 and the peripheral function 60 by the other Example. It is a functional conceptual diagram of the bus bridge 20 and the peripheral function 60 by the other Example. 16 is a flowchart showing a flow of data exchange between the bus bridge 20 and a peripheral function 60 according to another embodiment shown in FIG. FIG. 17 is a diagram showing an example of an order of access to peripheral functions 60A, 60B, and 60C by the CPU core 10 in relation to the flowchart shown in FIG. It is a figure which shows the operation | movement waveform of the serial communication performed according to the flowchart shown in FIG. It is a figure which shows the principal part structure of the microcomputer 2 which embodies another one Example (Example 2) of the data communication control apparatus by this invention. It is a figure which shows the principal part structure of the microcomputer 3 which embodies another one Example (Example 3) of the data communication control apparatus by this invention. It is a conceptual diagram which shows the case where the function of three microcomputer 100,102,104 before integration is integrated with the microcomputer 1. FIG. It is a figure which shows the difference in the operation waveform of the microcomputer 100 before integration, and the microcomputer 102 (or 104) before integration. FIG. 23A shows a parallel communication waveform of 48 MHz band assignment in the microcomputer 1, and FIG. 23B shows a serial communication waveform of 48 MHz band assignment in the microcomputer 1. It is a conceptual diagram which shows the case where the function of microcomputer 200,202,204 before integration is integrated into the microcomputer 2 by the above-mentioned Example 2. FIG. It is a conceptual diagram which shows the case where the function of microcomputer 300,302,304 before integration is integrated into the microcomputer 3 by the above-mentioned Example 3. FIG.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a main configuration of a microcomputer 1 that embodies an embodiment (embodiment 1) of a data communication control device according to the present invention.

  The microcomputer 1 includes a CPU core 10. The CPU core 10 is connected to a high-speed bus 70 with low latency. A local memory 50 and a bus bridge 20 are connected to the high-speed bus 70. A low-speed bus 72 having a large latency is connected to the bus bridge 20. The bus bridge 20 performs frequency conversion between the high-speed bus 70 and the low-speed bus 72 (PB). Peripheral functions 60 such as a serial interface, an A / D converter, a CAN, and a timer function are connected to the low-speed bus 72. Here, as an example, the high-speed bus 70 has a bus width of 64 bits and an operating frequency of 192 MHz. The low-speed bus 72 has a bus width of 8 bits and an operating frequency of 9.6 MHz.

  FIG. 2 is a functional conceptual diagram of the bus bridge 20 and the peripheral function 60 of FIG. In FIG. 2, one specific peripheral function 60A (CAN in this example) is shown as a representative. Other peripheral functions may be the same as the peripheral function 60A.

  As shown in FIG. 2, the bus bridge 20 includes a buffer 22 for storing data, an address / request management unit (ARC) 24, an end control unit (FC) 26, a data distribution unit (DD) 28, a serial A parallel control unit 30 is provided.

  The address request management unit 24 interprets the address request from the CPU core 10 and issues an address request to the peripheral function 60A. The end control unit 26 interprets the end flag sent from the peripheral function 60A. Further, the end control unit 26 manages the necessary data amount and sends an end flag to the CPU core 10.

  The data distribution unit 28 distributes and stores the data transmitted serially or in parallel (bus) from the peripheral function 60A in the buffer 22.

  The serial / parallel control unit 30 refers to a serial / parallel setting register 32 (described later) of the low-speed bus 72, and outputs a signal indicating whether data is output serially or data is output in parallel (serial / parallel switching signal) as a peripheral function. 60A and the data distribution unit 28. The configuration and functions of the serial / parallel control unit 30 will be described in detail later.

  As shown in FIG. 2, the peripheral function 60A includes a serial / parallel control unit 62A and an output stage 64A.

  The serial / parallel control unit 62A switches between serial data output and parallel data output from the output stage 64A of the peripheral function 60A according to the serial / parallel switching signal from the serial / parallel control unit 30.

  FIG. 3 is a flowchart showing the flow of data exchange between the bus bridge 20 and the peripheral function 60A.

  In step 300, the serial / parallel control unit 30 determines whether to output data serially or in parallel. Details of this determination method will be described later. In the case of outputting data serially, the process proceeds to step 302, where the data distribution unit (DD) 28 is designated for serial conversion, and the peripheral function 60A is notified of data output by serial communication. On the other hand, when data is output in parallel, the process proceeds to step 304, where the data distribution unit (DD) 28 is designated for parallel conversion, and the peripheral function 60A is notified of data output by parallel communication.

  In Step 306, when an address request from the CPU core 10 to the peripheral function 60A (CAN) is issued, the address request management unit 24 of the bus bridge 20 interprets the address request and selects the corresponding peripheral function 60A. And send an address request. When this address request is transmitted, data is output from the peripheral function 60A through the low-speed bus 72 by the parallel communication method after a certain latency elapses. At this time, the low-speed bus 72 uses the eight lines PB (7: 0) of the low-speed bus 72, and the data is stored in the buffer 22 (step 308).

  In Step 310, when an address request from the CPU core 10 to the peripheral function 60A (CAN) is issued, the address request management unit 24 of the bus bridge 20 interprets the address request and selects the corresponding peripheral function 60A. And send an address request. When this address request is transmitted, data is output from the peripheral function 60A through the low-speed bus 72 by the serial communication method after a certain latency has elapsed. At this time, the specific one line PB (0) is used for the low-speed bus 72. In this way, data is sent from the low-speed bus 72 to the data distribution unit (DD) 28. In the subsequent step 312, the data distribution unit (DD) 28 arranges the data from the peripheral function 60A according to the serial method and stores the data in the buffer 22.

  In step 314, when data required by the CPU core 10 (for example, 64-bit data) is stored in the buffer 22, an end flag is transmitted from the peripheral function 60A, and the end flag notified from the peripheral function 60A is ended. The control unit 26 interprets and notifies the CPU core 10.

  In step 316, the data stored in the buffer 22 (for example, 64-bit data) is transferred to the CPU core 10 via the high-speed bus 70.

  FIG. 4A shows a parallel communication waveform when data is output in parallel, and corresponds to the processing of step 306.308 in FIG. FIG. 4B shows a parallel communication waveform when data is output serially, and corresponds to the processing of step 310.312 in FIG.

  When data is output in parallel, as shown in FIG. 4A, when an address request is issued, data is transferred from the peripheral function 60A to the low-speed bus 72 after a certain latency (2 cycles in this example) has elapsed. Are output 8 bits at a time. In FIG. 4 (A), data 0, 1,. . . , 7 represents a set of 8-bit data. When 64-bit data is accumulated in the buffer 22 of the bus bridge 20 from the low-speed bus 72, 64-bit data (data # 0 indicated by a pentagonal symbol in the figure) is sent to the CPU core 10 via the high-speed bus 70. . That is, data is returned to the high-speed bus 70 180 cycles after the address issuance with the number of operation clocks.

  On the other hand, when data is output serially, as shown in FIG. 4B, when an address request is issued, after a certain latency (two cycles in this example) has elapsed, the peripheral function 60A sends a low-speed bus 72. The data is output bit by bit. When 64-bit data is accumulated in the buffer 22 of the bus bridge 20 from the low-speed bus 72, 64-bit data (data # 0 indicated by a pentagonal symbol in the figure) is sent to the CPU core 10 via the high-speed bus 70. . In other words, data is returned to the high-speed bus 70 after 1300 cycles from the issuance of addresses by the number of operating clocks.

  As described above, in this embodiment, when data is returned from the peripheral function 60 to the CPU core 10 according to an address request from the CPU core 10, switching between serial data output and parallel data output is performed. Thus, the timing for returning data can be adjusted (hereinafter, this function is also referred to as “data transfer timing adjustment function”).

  FIG. 5 is a table showing an example of a serial / parallel selection viewpoint that may be employed in the serial / parallel control unit 30.

  As shown in FIG. 5, serial / parallel selection (switching) is performed by at least one of an allocated bandwidth (processing load of the CPU core 10), the responsiveness of the peripheral function 60, the frequency of use of the peripheral function 60, and the amount of transmission data. It may be realized based on one of them.

  Based on the allocated bandwidth (processing load of the CPU core 10), parallel is selected when the allocated bandwidth is high, and serial is selected when the allocated bandwidth is low. This is because when the allocated bandwidth is high, the request for transmitting data quickly is high, whereas when the allocated bandwidth is low, it is not necessary to transmit data quickly. The threshold for determining whether the allocated bandwidth is high or low is the time required for transmitting 64-bit data to the CPU core 10 in the serial mode as described above (in the above example, 1300 cycles), or in the parallel mode. The time required for the data transmission (180 cycles in the above example), and the relationship between the time difference between them and the allocated bandwidth may be set arbitrarily.

  Based on the responsiveness of the peripheral function 60, parallel is selected when the responsiveness of the peripheral function 60 is fast, and serial is selected when the responsiveness of the peripheral function 60 is slow. This is because the peripheral function 60 with fast responsiveness has a high request for transmitting data quickly, whereas the peripheral function 60 with low responsiveness does not need to transmit data quickly. The threshold for determining whether the responsiveness of the peripheral function 60 is fast or slow is the time required for transmitting 64-bit data to the CPU core 10 at the time of serial as described above or the same data transmission at the time of parallel. It may be arbitrarily set in consideration of the time and the relationship between the time difference between them and the responsiveness of the peripheral function 60.

  Based on the frequency of use of the peripheral function 60, parallel is selected when the frequency of use of the peripheral function 60 is high, and serial is selected when the frequency of use of the peripheral function 60 is low. This is because when the peripheral function 60 is frequently used, the peripheral function 60 is often used in a plurality of processes, and there is a high demand for transmitting data quickly in order to prevent the peripheral function 60 from being occupied. This is because when the frequency of use of the function 60 is low, there is often no problem even if the peripheral function 60 is occupied for a long time, and it is not necessary to transmit data quickly. Similarly, the threshold value for determining whether the peripheral function 60 is frequently used or not is the same as the time required for transmitting 64-bit data to the CPU core 10 in the serial mode as described above or the same data in the parallel mode. The time required for transmission, and the relationship between the time difference between them and the frequency of use of the peripheral function 60 may be set arbitrarily.

  Based on the transmission data amount, parallel is selected when the transmission data amount is large, and serial is selected when the transmission data amount is small. This is because when the amount of transmission data is large, the request for transmitting data quickly is high, whereas when the amount of transmission data is small, it is not necessary to transmit data quickly. Similarly, the threshold value for determining whether the amount of transmission data is large or small is the time required for transmitting the transmission data amount to the CPU core 10 at the time of serial as described above or the same data transmission at the time of parallel. It may be arbitrarily set in consideration of the time required for the above and the time difference between them.

  The serial / parallel control unit 30 performs serial / parallel selection (switching) statically or dynamically in accordance with a selection viewpoint as shown in FIG. Here, static means that serial / parallel settings are made at startup, and that serial / parallel cannot be changed during operation. Dynamic refers to a semi-dynamic mode in which serial / parallel settings are set at startup and serial / parallel settings are changed only for some operations, and serial / parallel settings are changed for each operation, function, process, etc. It is possible to include a completely dynamic mode in which the serial / parallel setting is changed.

  FIG. 6 is a diagram illustrating an example of details of the serial / parallel control unit 30 when static switching is realized.

  As shown in FIG. 6, the serial / parallel control unit 30 includes a serial / parallel setting register 32 and a serial / parallel switching circuit 34.

  The serial / parallel setting register 32 is a register that holds a serial / parallel setting value (serial / parallel switching setting information of the low-speed bus 72) sent from the CPU core 10.

  The serial / parallel switching circuit 34 generates a serial / parallel switching signal based on the setting information (serial / parallel setting value) in the serial / parallel setting register 32. This serial / parallel switching signal is used in steps 302 to 304 in FIG.

  FIG. 7 is a flowchart showing the operation of the serial / parallel control unit 30 shown in FIG.

  As shown in FIG. 7, in the start-up process of the microcomputer 1, the serial / parallel setting register 32 is set based on the serial / parallel setting value sent from the CPU core 10. This process corresponds to an example of the determination process in step 300 of FIG.

  FIG. 8 is a diagram showing an example of details of the serial / parallel control unit 30 when realizing semi-dynamic switching.

  As illustrated in FIG. 8, the serial / parallel control unit 30 includes a serial / parallel setting register 32, a serial / parallel switching circuit 34, a necessary bit number determination unit 36, and a processing determination unit 38.

  Based on the bit number information sent from the CPU core 10, the necessary bit number determination unit 36 determines whether or not it is data transmission / reception of only a single bit (for example, data transmission / reception only of flag information). The process determination unit 38 determines whether or not the process to be executed by the peripheral function 60 is a predetermined process based on the process information sent from the CPU core 10. The predetermined processing is assumed not to require a high communication speed from the viewpoint shown in FIG. 5, for example, a hardware for a polling operation or a peripheral function 60 that operates at high speed is provided, but a function that is actually a low speed is provided. This is the case when it may be.

  FIG. 9 is a flowchart showing the operation of the serial / parallel control unit 30 shown in FIG. The process shown in FIG. 9 corresponds to an example of the determination process in step 300 of FIG.

  In step 900, the serial / parallel setting register 32 is set based on the serial / parallel setting value sent from the CPU core 10 in the startup process of the microcomputer 1. At this time, the serial / parallel setting value sent from the CPU core 10 is a default value.

  In step 902, the necessary bit number determiner 36 determines whether or not the data transmission / reception is only a single bit based on the bit number information sent from the CPU core 10. If it is a single bit data transfer, the process proceeds to step 906; otherwise, the process proceeds to step 904.

  In step 904, the process determination unit 38 determines whether the process to be executed by the peripheral function 60 is a predetermined process based on the process information sent from the CPU core 10. If the process is a predetermined process, the process proceeds to step 906; otherwise, the process proceeds to step 908.

  In step 906, the serial / parallel switching signal is set to "serial" and transmitted (see step 302 in FIG. 3).

  In step 908, a serial / parallel switching signal is generated based on the default setting of the serial / parallel setting register 32. For example, when the default setting of the serial / parallel setting register 32 is “parallel”, the serial / parallel switching signal is set to “parallel” and transmitted (see step 304 in FIG. 3).

  FIG. 10 is a diagram showing an example of details of the serial / parallel control unit 30 when realizing complete dynamic switching.

  As shown in FIG. 10, the serial / parallel control unit 30 includes a serial / parallel setting register 32, a serial / parallel switching circuit 34, a necessary bit number determination unit 36, a processing determination unit 38, and a schedule determination unit 39. Is provided.

  The configuration shown in FIG. 10 is different from the configuration shown in FIG. 8 in that a schedule determiner 39 is added. However, the difference in operation from the semi-dynamic mode is the serial / parallel default setting. First, the serial / parallel switching is dynamically performed using the viewpoint shown in FIG.

  FIG. 11 is a flowchart showing the operation of the serial / parallel control unit 30 shown in FIG. The process shown in FIG. 11 corresponds to an example of the determination process in step 300 of FIG.

  In step 1100, the schedule determiner 39 determines whether or not the schedule allocation is small (that is, whether or not the allocated bandwidth is small) based on the schedule information sent from the CPU core 10. If the schedule assignment is small, the process proceeds to step 1106; otherwise, the process proceeds to step 1102.

  In step 1102, the necessary bit number determiner 36 determines whether or not the data transmission / reception is a single bit based on the bit number information sent from the CPU core 10. If it is a single bit data transfer, the process proceeds to step 1106; otherwise, the process proceeds to step 1104.

  In step 1104, the process determiner 38 determines whether the process to be executed by the peripheral function 60 is a predetermined process based on the process information sent from the CPU core 10. The predetermined process may be the same as the predetermined process described with reference to FIGS. If the process is a predetermined process, the process proceeds to step 1106; otherwise, the process proceeds to step 1108.

  In step 1106, the serial / parallel switching signal is set to "serial" and transmitted (see step 302 in FIG. 3).

  In step 1108, the serial / parallel switching signal is set to “parallel” and transmitted (see step 304 in FIG. 3).

  FIG. 12 is a diagram showing an example of details of the serial / parallel control unit 30 when implemented using software. The serial / parallel control unit 30 shown in FIG. 12 is different from the configuration shown in FIG. 10 in that a required bit number determination unit 36, a processing determination unit 38, and a schedule determination unit 39 are configured by a software unit 30B. There are mainly differences. The hardware unit 30A may have the same configuration as that shown in FIG. The software unit 30B makes a determination from the viewpoint shown in FIG. 5, and outputs a serial / parallel setting value corresponding to the determination result. Serial / parallel setting values are input from the software unit 30B to the hardware unit 30A. The software unit 30B may be realized by the CPU core 10.

  FIG. 13 shows an operation flowchart of the software unit 30B of FIG.

  In step 1300, the serial / parallel setting register 32 is set in the startup process of the microcomputer 1. At this time, the serial / parallel setting value may be a predetermined initial value.

  In step 1302, the schedule determiner 39 of the software unit 30B determines whether the schedule allocation is small (that is, whether the allocated bandwidth is small) based on the schedule information. If the schedule assignment is small, the process proceeds to step 1308. Otherwise, the process proceeds to step 1304.

  In step 1304, the necessary bit number determination unit 36 of the software unit 30B determines whether or not the data transmission / reception is a single bit based on the bit number information. If it is a single bit data transfer, the process proceeds to step 1308. Otherwise, the process proceeds to step 1306.

  In step 1306, the process determination unit 38 of the software unit 30B determines whether the process to be executed by the peripheral function 60 is a predetermined process based on the process information. The predetermined process may be the same as the predetermined process described with reference to FIGS. If the process is a predetermined process, the process proceeds to step 1308; otherwise, the process proceeds to step 1310.

  In step 1308, the serial / parallel setting value “serial” is generated, and the serial / parallel setting register 32 is set to “serial”. Accordingly, a serial / parallel switching signal “serial” is transmitted (see step 302 in FIG. 3).

  In step 1310, the serial / parallel setting value “parallel” is generated, and the serial / parallel setting register 32 is set to “parallel”. Accordingly, a serial / parallel switching signal “parallel” is transmitted (see step 304 in FIG. 3).

  FIG. 14 is a functional conceptual diagram of the bus bridge 20 and peripheral function 60 according to another embodiment. In FIG. 14, similar to FIG. 2 described above, one specific peripheral function 60A (CAN in this example) is shown as a representative. Other peripheral functions may be the same as the peripheral function 60A.

  The embodiment shown in FIG. 14 realizes the same function as that of the embodiment shown in FIG. 2 without changing the circuit of the peripheral function 60A. Specifically, instead of the function (serial / parallel control unit 62A) for switching between serial output and parallel output in the peripheral function 60A (CAN) shown in FIG. 2, a serial / parallel converter (CV) 80 is provided. The components that may be the same as those in the embodiment shown in FIG. 2 are denoted by the same reference numerals shown in FIG.

  As shown in FIG. 14, the serial / parallel converter 80 is provided between the bus bridge 20 and the peripheral function 60A, and is connected to a low-speed bus (PB (7: 0)) 72 that is an output from the peripheral function 60A. To do. The serial / parallel converter 80 receives a serial / parallel switching signal similar to that described above from the serial / parallel control unit 30 of the bus bridge 20. The serial / parallel converter 80 converts and transmits data of the low-speed bus (PB (7: 0)) 72 in accordance with the serial / parallel switching signal. The data converted by the serial / parallel converter 80 is sent to the bus bridge 20 and sent to the CPU core 10 by the same processing as the data processing shown in FIG.

  FIG. 15 is a functional conceptual diagram of the bus bridge 20 and the peripheral function 60 according to another embodiment. FIG. 15 shows a configuration in which a plurality of peripheral functions 60A, 60B, and 60C can be accessed simultaneously. In the illustrated example, as the peripheral function 60, in addition to the peripheral function 60A that is a CAN, a total of peripheral functions 60B and 60C that are two A / D converters (hereinafter also referred to as A / D and A / D2, respectively). It is assumed that there are three.

  As shown in FIG. 15, the bus bridge 20 includes a buffer 22 for accumulating data, an address / request management unit (ARC) 24, an address / request order storage unit (ARM) 25, and an end control unit (FC) 26. A data distribution unit (DD) 28 and a serial / parallel control unit 30.

  A plurality of buffers 22 are provided so that simultaneous access to the plurality of peripheral functions 60A, 60B, and 60C is possible. In the illustrated example, the buffer 22 has a total of eight buffers 220, 221,. . . , 227. Each buffer 220, 221,. . . , 227 are selectively connected to the high-speed bus 70. Each buffer 220, 221,. . . , 227 stores the PB (0) data of the low-speed bus 72 in the buffer (BF0) 220 and sends the data of the PB (1) of the low-speed bus 72 when serially sending data from the peripheral functions 60A, 60B, 60C. Is stored in the buffer (BF1) 221, so that data can be transmitted simultaneously from a plurality of peripheral functions 60A, 60B, 60C.

  The address / request order storage unit 25 stores the order of address requests issued from the CPU core 10 and is used to hold the order when data is sent from the peripheral functions 60A, 60B, 60C to the high-speed bus 70. Is done.

  The peripheral functions 60A, 60B, and 60C include serial / parallel control units 62A, 62B, and 62C and output stages 64A, 64B, and 64C, respectively. In the illustrated example, since the address request to all the peripheral functions 60A, 60B, and 60C and the low-speed bus 72 are shared, the input buffers (not shown) of the peripheral functions 60A, 60B, and 60C, respectively. And output stages 64A, 64B, 64C. As described above, the serial / parallel control units 62A, 62B, and 62C output the output stages 64A, 64B, and 64C of the peripheral functions 60A, 60B, and 60C in accordance with the serial / parallel switching signal from the serial / parallel control unit 30 of the bus bridge 20. Switch between serial data output and parallel data output. In the configuration shown in FIG. 15, a serial / parallel converter (CV) as shown in FIG. 14 may be set instead of the serial / parallel control units 62A, 62B, and 62C.

  FIG. 16 is a flowchart showing the flow of data exchange between the bus bridge 20 and the peripheral function 60 according to another embodiment shown in FIG. The flowchart shown in FIG. 16 relates to a case where the CPU core 10 accesses the peripheral functions 60A, 60B, and 60C in the order shown in FIG. 17 as an example. Here, as shown in FIG. 17, first, an address request for obtaining 64-bit data is issued from the peripheral function (A / D) 60B from the CPU core 10, and secondly, from the CPU core 10, An address request for obtaining 16-bit data is issued from the peripheral function (CAN) 60A. Third, an address request for obtaining 32-bit data from the peripheral function (A / D2) 60C is issued from the CPU core 10. It is assumed that it will be issued.

  Referring to FIG. 16, in step 1600, the serial / parallel control unit 30 determines whether to output data serially or in parallel. This determination method may be any of the methods described above (see FIG. 5 and the like). In the case of outputting data serially, the process proceeds to step 1601, and the data distribution unit (DD) 28 is designated for serial conversion, and serial communication is performed to the serial / parallel control units 62A, 62B, and 62C of the peripheral functions 60A, 60B, and 60C. Notify that data is to be output. On the other hand, if the data is output in parallel, the process proceeds to step 1631 and the data distribution unit (DD) 28 is designated for parallel conversion, and the serial / parallel control units 62A, 62B, and 62C are notified of the data output by parallel communication. To do.

  In step 1602, an address request from the CPU core 10 to the peripheral function 60B (A / D) is issued.

  In step 1603, the address / request management unit 24 of the bus bridge 20 interprets the address request, selects the corresponding peripheral function 60B (A / D), and transmits the address request. At the same time, the address / request management unit 24 records in the address / request order storage unit 25 that the access to the peripheral function 60B (A / D) is the first request. When the process of step 1603 ends, the process after step 1604 and the process after step 1611 are executed in parallel.

  In step 1611, an address request from the CPU core 10 to the peripheral function 60A (CAN) is issued.

  In step 1612, the address / request management unit 24 of the bus bridge 20 interprets the address request, selects the corresponding peripheral function 60A (CAN), and transmits the address request. At the same time, the address / request management unit 24 records in the address / request order storage unit 25 that the access to the peripheral function 60A (CAN) is the second request. When the process of step 1612 is completed, the process after step 1604, the process after step 1613, and the process after step 1621 are executed in parallel.

  In step 1621, the CPU core 10 issues an address request to the peripheral function 60C (A / D2).

  In step 1622, the address request management unit 24 of the bus bridge 20 interprets the address request, selects the corresponding peripheral function 60C (A / D2), and transmits the address request. At the same time, the address / request management unit 24 records in the address / request order storage unit 25 that the access to the peripheral function 60C (A / D2) is the third request. When the process of step 1622 is completed, the process after step 1604, the process after step 1613, and the process after step 1623 are executed in parallel.

  In steps 1604, 1613, and 1623, after processing of the above steps 1603, 1612, and 1622, and after a certain latency, in response to the address request, peripheral function 60B (A / D), peripheral function 60A (CAN), and Serial data communication is started from the peripheral function 60C (A / D2) via the lines PB (0), PB (1), and PB (2) of the low-speed bus 72, respectively. Each data from the peripheral function 60B (A / D), the peripheral function 60A (CAN), and the peripheral function 60C (A / D2) is sent to the data distribution unit (DD) 28 of the bus bridge 20.

  In steps 1605, 1614, and 1624, each data from the peripheral function 60B (A / D), the peripheral function 60A (CAN), and the peripheral function 60C (A / D2) is serialized in the data distribution unit (DD) 28. In accordance with the above, the data are stored in the buffers 220, 221, 222, respectively.

  In step 1606, when data required by the CPU core 10 (64-bit data in this example) is stored in the buffer 220, an end flag is transmitted from the peripheral function 60B (A / D), and the peripheral function 60B. The end control unit 26 interprets the end flag notified from (A / D), notifies the CPU core 10, and proceeds to step 1607.

  In step 1607, the data stored in the buffer 220 (64-bit data in this example) is sent to the CPU core 10 via the high-speed bus 70. When the process (data transfer) in step 1607 is completed, a determination condition in step 1616 described later is satisfied.

  In step 1615, when data required by the CPU core 10 (16-bit data in this example) is stored in the buffer 221, an end flag is transmitted from the peripheral function 60A (CAN), and the peripheral function 60A (CAN The end control unit 26 interprets the end flag notified from).

  In step 1616, it is determined whether or not the transfer of data (A / D data) from the peripheral function 60B (A / D) in step 1607 to the CPU core 10 has been completed. When the transfer of the A / D data to the CPU core 10 is completed, the CPU core 10 is notified of the end flag related to the peripheral function 60A (CAN), and the process proceeds to step 1617. On the other hand, when the transfer of the A / D data to the CPU core 10 is not completed, the process waits until the transfer of the A / D data to the CPU core 10 is completed.

  In step 1617, the data stored in the buffer 221 (16-bit data in this example) is sent to the CPU core 10 via the high-speed bus 70. When the process (data transfer) in step 1617 is completed, a determination condition in step 1626 described later is satisfied.

  In step 1625, when data required by the CPU core 10 (32-bit data in this example) is stored in the buffer 222, an end flag is transmitted from the peripheral function 60C (A / D2), and the peripheral function 60C. The termination control unit 26 interprets the termination flag notified from (A / D2).

  In step 1626, it is determined whether or not the transfer of data (CAN data) from the peripheral function 60A (CAN) in step 1617 to the CPU core 10 has been completed. If the transfer of the CAN data has been completed, the CPU core 10 is notified of an end flag relating to the peripheral function 60C (A / D2), and the process proceeds to step 1627. On the other hand, if the transfer of the CAN data is not completed, the process waits until the transfer of the CAN data to the CPU core 10 is completed.

  In step 1627, the data stored in the buffer 222 (32-bit data in this example) is sent to the CPU core 10 via the high-speed bus 70. Thereby, serial communication is completed. FIG. 8 shows operation waveforms of serial communication executed in this way.

  In the case of parallel communication, data is transmitted in parallel in the order of the peripheral function 60B (A / D), the peripheral function 60A (CAN), and the peripheral function 60C (A / D2) in accordance with the order of the address request.

  Specifically, in step 1632, data is transmitted from the peripheral function 60 </ b> B (A / D) to the bus bridge 20 in parallel. That is, data is transmitted in parallel from the peripheral function 60B (A / D) using the eight lines PB (7: 0) of the low-speed bus 72.

  In step 1633, data from the peripheral function 60 </ b> B (A / D) is stored in the buffer 220 by the eight lines PB (7: 0) of the low-speed bus 72.

  In step 1634, when data required by the CPU core 10 (64-bit data in this example) is stored in the buffer 220, an end flag is transmitted from the peripheral function 60B (A / D), and the peripheral function 60B. The end control unit 26 interprets the end flag notified from (A / D) and notifies the CPU core 10 of it. Then, the data stored in the buffer 220 (64-bit data in this example) is sent to the CPU core 10 via the high-speed bus 70. When this transfer ends, the process proceeds to step 1635.

  In step 1635, data is transmitted from the peripheral function 60A (CAN) to the bus bridge 20 in parallel. That is, data is transmitted in parallel from the peripheral function 60A (CAN) using the eight lines PB (7: 0) of the low-speed bus 72.

  In step 1636, data from the peripheral function 60A (CAN) is stored in the buffer 220 by the eight lines PB (7: 0) of the low-speed bus 72.

  In step 1637, when data required by the CPU core 10 (16-bit data in this example) is stored in the buffer 220, an end flag is transmitted from the peripheral function 60A (CAN), and the peripheral function 60A (CAN The end control unit 26 interprets the end flag notified from () and notifies the CPU core 10 of it. Then, the data stored in the buffer 220 (16-bit data in this example) is sent to the CPU core 10 via the high-speed bus 70. When this transfer ends, the process proceeds to step 1638.

  In step 1638, data is transmitted from the peripheral function 60C (A / D2) to the bus bridge 20 in parallel. That is, data is transmitted in parallel from the peripheral function 60C (A / D2) using the eight lines PB (7: 0) of the low-speed bus 72.

  In step 1639, the data from the peripheral function 60C (A / D2) is stored in the buffer 220 by the eight lines PB (7: 0) of the low-speed bus 72.

  In step 1640, when data required by the CPU core 10 (32-bit data in this example) is stored in the buffer 220, an end flag is transmitted from the peripheral function 60C (A / D2), and the peripheral function 60C. The end control unit 26 interprets the end flag notified from (A / D2), and notifies the CPU core 10 of it. Then, the data stored in the buffer 220 (32-bit data in this example) is sent to the CPU core 10 via the high-speed bus 70. When this transfer ends, parallel communication is completed.

  FIG. 18 is a diagram showing operation waveforms of serial communication executed according to the flowchart shown in FIG.

  According to another embodiment shown in FIG. 15, the low-speed bus 72 has a free line PB (1) of the low-speed bus 72 even if one peripheral function 60 (for example, the peripheral function 60B) is accessed. , PB (2), etc., can exchange data with other peripheral functions 60 (for example, peripheral functions 60A and 60C). Thereby, the latency concealment effect after the address request is issued can be expected. Further, since the access order from the CPU core 10 to the peripheral functions 60A, 60B, and 60C is stored, data from the peripheral functions 60A, 60B, and 60C can be passed to the CPU core 10 in that order.

  FIG. 19 is a diagram showing a main configuration of a microcomputer 2 that embodies another embodiment (embodiment 2) of the data communication control apparatus according to the present invention.

  The second embodiment is mainly different from the first embodiment described above (see FIG. 1 and the like) in that the microcomputer 2 is a multi-core microcomputer including a plurality of CPU cores 10A and 10B. As shown in FIG. 19, the CPU cores 10 </ b> A and 10 </ b> B are connected to the common bus bridge 20 to the high-speed buses 70 </ b> A and 70 </ b> B, and are connected to the peripheral function 60 through the bus bridge 20 and the common low-speed bus 72. Here, as an example, the high-speed buses 70A and 70B have a bus width of 64 bits and an operating frequency of 96 MHz. The low-speed bus 72 has a bus width of 8 bits and an operating frequency of 9.6 MHz.

  The microcomputer 2 may have a data transfer timing adjustment function (FIGS. 2, 14, 15, etc.) similar to that described in the first embodiment. In this case, the serial / parallel switching determination in the serial / parallel control unit 30 is an address request from the CPU core 10A or an address request from the CPU core 10B in consideration of the viewpoint shown in FIG. Depending on whether it is present, it may be realized in a dynamic manner.

  In the second embodiment shown in FIG. 19, the number of cores of the multi-core microcomputer is 2, but three or more CPU cores may exist. In the illustrated example, one specific peripheral function (CAN in this example) is shown. However, the same applies to other peripheral functions (A / D converter), and a plurality of peripheral functions are also provided. May be present.

  FIG. 20 is a diagram showing a main configuration of a microcomputer 3 that embodies another embodiment (embodiment 3) of the data communication control apparatus according to the present invention.

  The third embodiment is similar to the second embodiment (FIG. 19) in that the microcomputer 2 is a multi-core microcomputer including a plurality of CPU cores 10A and 10B. The main difference is that the bus bridges 20A and 20B are independently provided. CPU cores 10A and 10B are connected to peripheral functions 60A1 and 60A2 by low-speed buses 72A and 72B via bus bridges 20A and 20B, respectively. Here, as an example, the high-speed buses 70A and 70B have a bus width of 64 bits and an operating frequency of 96 MHz. The low speed buses 72A and 72B have a bus width of 8 bits and an operating frequency of 9.6 MHz.

  The microcomputer 2 may have a data transfer timing adjustment function (FIGS. 2, 14, 15, etc.) similar to that described in the first embodiment. In this case, serial / parallel switching in each of the serial / parallel control units (not shown) in the bus bridges 20A and 20B may be realized in a static manner in consideration of the viewpoint shown in FIG.

  In the third embodiment shown in FIG. 20, the number of cores of the multi-core microcomputer is 2, but three or more CPU cores may exist. In the illustrated example, one specific peripheral function (CAN in this example) is shown. However, the same applies to other peripheral functions (A / D converter), and a plurality of peripheral functions are also provided. May be present.

  Next, as a preferred application example of the present invention, an example in which a plurality of microcomputers are integrated into the above-described microcomputers 1, 2, 3 will be described.

  FIG. 21 shows the functions of three microcomputers 100, 102, and 104 (hereinafter referred to as pre-integration microcomputers 100, 102, and 104 for distinction from the above-described microcomputer 1) integrated with the microcomputer 1 according to the first embodiment. It is a conceptual diagram which shows a case. During integration, some functions of the pre-integration microcomputers 100, 102, and 104 may be omitted or improved, or new functions that do not exist in the pre-integration microcomputers 100, 102, and 104 may be added. Also good.

  The pre-integration microcomputer 100 has an operation frequency of 96 MHz, and the high-speed bus used by the pre-integration microcomputer 100 has a bus width of 64 bits, an operation frequency of 96 MHz, and the pre-integration microcomputer 100 used. The low speed bus is assumed to have a bus width of 8 bits and an operating frequency of 9.6 MHz.

  The pre-integration microcomputers 102 and 104 have an operation frequency of 48 MHz, and the high-speed bus used by the pre-integration microcomputer 100 has a bus width of 64 bits and an operation frequency of 48 MHz. The low-speed bus that was used is assumed to have a bus width of 8 bits and an operating frequency of 1.2 MHz.

  In the microcomputer 1, the operating frequency of the high-speed bus 70 is 192 MHz, which is set in accordance with the total operating frequency of the high-speed buses of the microcomputers 100, 102, and 104 before integration. In the microcomputer 1, the low-speed bus 72 has an operating frequency of 9.6 MHz, which is set in accordance with the operating frequency (highest operating frequency) of the low-speed bus of the microcomputer 100 before integration. In the microcomputer 1, the bus widths of the high-speed bus 70 and the low-speed bus 72 are set according to the bus widths in the microcomputers 100, 102, and 104 before integration.

  FIG. 22 is a diagram illustrating a difference in operation waveforms between the pre-integration microcomputer 100 and the pre-integration microcomputer 102 (or 104). FIG. 22A illustrates the operation waveforms of the pre-integration microcomputer 100, and FIG. Indicates an operation waveform of the pre-integration microcomputer 102 (or 104). As shown in FIG. 22, in the pre-integration microcomputer 100, data is returned to the high-speed bus 90 cycles after address issuance, whereas in the pre-integration microcomputer 102 (or 104), data is returned to the high-speed bus 360 cycles after address issuance. Data is returned. As described above, in the pre-integration microcomputer 100 and the pre-integration microcomputer 102 (or 104), there is a difference in performance between the microcomputers regarding the data output timing due to the difference in the bus operation speed between the microcomputers.

  In addition, regarding the pre-integration microcomputer 100, there is no difference in the operating frequency of the low-speed bus 72 with respect to the microcomputer 1 (after integration). 104), since there is a difference in the operating frequency of the low-speed bus 72 with respect to the microcomputer 1 (after integration), there is a difference in data output timing before and after the integration.

  FIG. 23A shows a parallel communication waveform of 48 MHz band assignment in the microcomputer 1, and FIG. 23B shows a serial communication waveform of 48 MHz band assignment in the microcomputer 1.

  As shown in FIG. 23A, in the parallel communication with the 48 MHz band allocation in the microcomputer 1, data is returned to the high-speed bus 45 cycles after address issuance. On the other hand, as shown in FIG. 23B, in the serial communication with the 48 MHz band assignment in the microcomputer 1, data is returned to the high-speed bus after 325 cycles from the address issuance. Here, as shown in FIG. 22B, the pre-integration microcomputer 102 (or 104) returns data to the high-speed bus 360 cycles after address issuance. Therefore, in the microcomputer 1, it is understood that the difference in the data output timing before and after the integration can be reduced if the data of the microcomputer 102 (or 104) before the integration is exchanged by serial communication.

  In this case, from the viewpoint shown in FIG. 5, in the case of processing related to the function of the pre-integration microcomputer 100, since the allocated bandwidth is high, parallel communication is selected, and processing related to the function of the pre-integration microcomputer 102 (or 104). In this case, since the allocated bandwidth is low, serial communication may be selected. Thereby, the software change man-hours before and after the integration can be unnecessary or minimized.

  FIG. 24 is a conceptual diagram illustrating a case where the functions of the pre-integration microcomputers 200, 202, and 204 are integrated into the microcomputer 2 according to the second embodiment. During integration, some functions of the pre-integration microcomputers 200, 202, and 204 may be omitted or improved, or new functions that do not exist in the pre-integration microcomputers 200, 202, and 204 are added. Also good.

  The pre-integration microcomputer 200 has an operating frequency of 96 MHz, and the high-speed bus used by the pre-integration microcomputer 200 has a bus width of 64 bits, an operating frequency of 96 MHz, and was used by the pre-integration microcomputer 200. The low speed bus is assumed to have a bus width of 8 bits and an operating frequency of 9.6 MHz. The function of the microcomputer 200 before integration is transferred to the CPU core 10A of the microcomputer 2.

  The pre-integration microcomputers 202 and 204 have an operation frequency of 48 MHz, and the high-speed bus used by the pre-integration microcomputers 202 and 204 has a bus width of 64 bits and an operation frequency of 48 MHz. It is assumed that the low-speed bus used by 204 has a bus width of 8 bits and an operating frequency of 2.4 MHz. The functions of the pre-integration microcomputers 202 and 204 are transferred to the CPU core 10B of the microcomputer 2.

  In the microcomputer 2, the operating frequency of the high-speed bus 70A is 96 MHz, which is set in accordance with the high-speed bus of the microcomputer 200 before integration. The high-speed bus 70B has an operating frequency of 96 MHz, which is set according to the total operating frequency of the high-speed buses of the pre-integration microcomputers 202 and 204. In the microcomputer 2, the operating frequency of the low-speed bus 72 is 9.6 MHz. This is set in accordance with the operating frequency (highest operating frequency) of the low-speed bus of the microcomputer 200 before integration. In the microcomputer 2, the bus widths of the high-speed buses 70 </ b> A and 70 </ b> B and the low-speed bus 72 are set in accordance with the same bus widths in the pre-integration microcomputers 200, 202 and 204.

  In such an integrated mode, the bus operation speed (both high-speed bus and low-speed bus) is different before and after the integration as in the integrated mode shown in FIG. Become. In this case, since the allocated bandwidth is high in the case of an address request from the CPU core 10A, parallel communication is selected. In the case of an address request from the CPU core 10B, the allocated bandwidth is low, so that serial communication is performed. May be selected. Thereby, the software change man-hours before and after the integration can be unnecessary or minimized.

  FIG. 25 is a conceptual diagram showing a case where the functions of the pre-integration microcomputers 300, 302, and 304 are integrated into the microcomputer 3 according to the third embodiment. During integration, some functions of the pre-integration microcomputers 300, 302, and 304 may be omitted or improved, or new functions that do not exist in the pre-integration microcomputers 300, 302, and 304 are added. Also good.

  The pre-integration microcomputer 300 has an operating frequency of 96 MHz, and the high-speed bus 70 used by the pre-integration microcomputer 100 has a bus width of 64 bits and an operating frequency of 96 MHz. The low-speed bus 72 is assumed to have a bus width of 8 bits and an operating frequency of 9.6 MHz. The function of the pre-integration microcomputer 300 is transferred to the CPU core 10 </ b> A of the microcomputer 3.

  The pre-integration microcomputers 302 and 304 have an operation frequency of 48 MHz, and the high-speed bus used by the pre-integration microcomputers 302 and 304 has a bus width of 64 bits and an operation frequency of 48 MHz. It is assumed that the low speed bus used by 304 has a bus width of 8 bits and an operating frequency of 2.4 MHz. The functions of the pre-integration microcomputers 302 and 304 are transferred to the CPU core 10B of the microcomputer 3.

  In the microcomputer 3, the high-speed bus 70A has an operating frequency of 96 MHz, which is set according to the high-speed bus of the microcomputer 300 before integration. The high-speed bus 70B has an operating frequency of 96 MHz, which is set in accordance with the total operating frequency of the high-speed buses of the pre-integration microcomputers 302 and 304. In the microcomputer 3, the low-speed buses 72A and 72B have an operating frequency of 9.6 MHz, and this is set in accordance with the operating frequency (highest operating frequency) of the low-speed bus of the microcomputer 300 before integration. . In the microcomputer 3, the bus widths of the high-speed buses 70 </ b> A and 70 </ b> B and the low-speed bus 72 are set according to the bus widths of the microcomputers 300, 302 and 304 before integration.

  Also in such an integration mode, as in the integration mode shown in FIG. 21, when there is a performance difference between the high-speed bus and the low-speed bus before and after the integration (in this example, the pre-integration microcomputers 302 and 304 integrated into the CPU core 10B). ), The CPU core 10A side uses the low-speed bus 72A as usual, and the CPU core 10B side reduces the difference in bus transfer speed before and after integration by serial communication by the above switching (in this example, static switching). can do.

  According to the preferred application example of the present invention described above, the following excellent effects can be obtained.

  By guaranteeing the operation timing of the microcomputer bus before and after the integration, it is possible to eliminate the need for software modification before and after the integration. In addition, it is possible to maintain the programming structure when integrating the functions of a plurality of ECUs, thereby reducing costs. In addition, since it is not necessary to separate the bus lines and have two or more systems, it is possible to perform functional integration without cost disadvantages. Further, since integration is possible regardless of the bus topology (APB, NPB, etc.), there is no need to worry about the bus configuration of the microcomputer before integration, and the degree of freedom of the integrated microcomputer increases. Furthermore, since there is a reduction in the number of output stages activated by this function for those that have a margin in speed (data may be transmitted later), an effect of reducing power consumption can be obtained.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

1, 2, 3 Microcomputer 10, 10A, 10B CPU core 20, 20A, 20B Bus bridge 22, 220, 221, 222 Buffer 24 Address / request management unit 25 Address / request order storage unit 26 Termination control unit 28 Data distribution unit 30 Serial / Parallel Control Unit 30A Hardware Unit 30B Software Unit 32 Serial / Parallel Setting Register 34 Serial / Parallel Switching Circuit 36 Required Bit Number Determinator 38 Processing Determinator 39 Schedule Determinator 50 Local Memory 60, 60A, 60B, 60C, 60A1 , 60A2 Peripheral function 62A, 62B, 62C Serial / parallel controller 64A, 64B, 64C Output stage 70, 70A, 70B High-speed bus 72, 72A, 72B Low-speed bus 80 Serial / parallel converter

Claims (2)

A data communication control device that controls data communication between a CPU core and peripheral devices,
A bus bridge is provided between the CPU core and peripheral devices.
The CPU core and the bus bridge are connected by a high-speed bus,
The peripheral device and the bus bridge are connected by a low-speed bus,
When transmitting data from the peripheral device to the CPU core via the bus bridge, the data transmitted from the peripheral device to the bus bridge via the low-speed bus is stored in the buffer of the bus bridge in a predetermined number of bits. Is configured to transmit the predetermined number of bits of data to the CPU core on the high-speed bus
A data communication control device, comprising: a switching control unit that dynamically or statically switches a data transmission method from the peripheral device to the bus bridge via the low-speed bus between serial communication and parallel communication.   The switching control unit, based on at least one of the processing load of the CPU core, the responsiveness of the peripheral device, the usage frequency of the peripheral device, and the amount of data to be sent to the CPU core, The data communication control device according to claim 1, wherein: