CN118175111A - Data transmission method, DMA controller, equipment and storage medium - Google Patents

Abstract

The present application relates to the field of data communications technologies, and in particular, to a data transmission method for a DMA controller, a device, and a storage medium. The DMA controller can determine the actual throughput of the corresponding source node and the target node based on the received DMA request; furthermore, the data bandwidth of the data transmission is determined based on the smaller actual throughput, so that the rate of the data transmission is controlled to be not more than the receiving and transmitting rate between the source node and the target node, the conditions of data congestion, blindness of the target node and the like are avoided, and the data transmission quality is effectively ensured; and the hardware function of the DMA controller is adopted, so that the virtual channel and the physical channel which are matched for the data transmission and correspond to the data bandwidth do not need to be additionally increased, and the equipment resource is saved.

Description

Data transmission method, DMA controller, equipment and storage medium

Technical Field

The present application relates to the field of data communications technologies, and in particular, to a data transmission method, a DMA controller, a device, and a storage medium.

Background

In a network-on-chip (Networkon Chip, noC) communication scenario of a direct memory access (Direct Memory Access, DMA) mechanism, data transfer or request to a common bus at maximum speed is allowed in an independent manner between nodes of the network-on-chip without quality of service (Quality of Service, qoS) guarantees.

In this case, if the bus bandwidth is insufficient, data blocking is easily generated, and for a target node that cannot receive data in time, the source node applies for retransmitting the data, which further aggravates the data blocking. If the bus bandwidth is designed to be large enough, network layout and wiring overhead are increased, and for a communication scene with asynchronous transceiving speed, backlog of data at one end of a sender or a receiver is possibly caused, so that additional buffer space is required to be increased; for the communication scene with slower data transmission speed, the bus bandwidth can not be well utilized, so that the communication resource is wasted greatly.

Therefore, a new technical solution is needed to overcome the above technical problems.

Disclosure of Invention

The application provides a data transmission method for a DMA controller, the DMA controller, equipment and a storage medium, which are used for adjusting the data transmission speed according to the actual throughput capacity of a start-stop node of transmission data under the condition of not increasing hardware cost and ensuring the data transmission quality.

In a first aspect, the present application provides a data transmission method, which is applicable to a DMA controller, including: receiving a DMA request, wherein the DMA request comprises a source address, a target address and data volume of data to be transmitted; determining the actual throughput corresponding to the source node and the target node respectively according to the source address and the target address; determining the data bandwidth of the current transmission data according to the actual throughput corresponding to the source node and the target node respectively; and determining a matched transmission channel according to the data bandwidth so as to transmit the data to be transmitted corresponding to the data quantity from the source node to the target node through the transmission channel.

In an alternative embodiment, determining the data bandwidth of the current transmission data according to the actual throughput corresponding to the source node and the target node respectively includes: according to the actual throughput corresponding to the source node and the target node respectively, determining a node with small throughput as a reference node; and determining the data bandwidth of the current transmission data according to the actual throughput of the reference node.

In an alternative embodiment, determining a matched transmission channel according to the data bandwidth includes: determining a matched target virtual channel according to the data bandwidth; determining a target physical channel corresponding to the target virtual channel; and distributing the access right of the target physical channel for the target virtual channel, and taking the target physical channel as a transmission channel.

In an alternative embodiment, determining a matched target virtual channel according to the data bandwidth includes: acquiring first configuration information, wherein the first configuration information comprises transmission bandwidth of each virtual channel; and determining a target virtual channel adapted to the data bandwidth according to the transmission bandwidth of each virtual channel.

In an alternative embodiment, determining a target physical channel corresponding to the target virtual channel includes: acquiring second configuration information, wherein the second configuration information comprises a mapping relation between each physical channel and each virtual channel; and determining a target physical channel matched with the target virtual channel according to the mapping relation.

In an alternative embodiment, allocating the access right of the target physical channel to the target virtual channel includes: acquiring a first access frequency preset for the transmission data at this time; and distributing the access right of the target physical channel for the target virtual channel according to the first access frequency.

In an alternative embodiment, allocating the access right of the target physical channel to the target virtual channel includes: determining a second access frequency according to the data volume and the transmission bandwidth; and distributing the access right of the target physical channel for the target virtual channel according to the second access frequency.

In a second aspect, an embodiment of the present application provides a DMA controller configured to implement the data transmission method described in the first aspect.

In a third aspect, an embodiment of the present application provides an electronic device, including a DMA controller, where the DMA controller is configured to implement the data transmission method described in the first aspect.

In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, where computer program instructions are stored, where the computer program instructions, when executed, implement the data transmission method according to the first aspect.

In the embodiment of the application, the DMA controller can determine the actual throughput of the corresponding source node and target node based on the received DMA request; furthermore, the data bandwidth of the data transmission is determined based on the smaller actual throughput, so that the rate of the data transmission is controlled to be not more than the receiving and transmitting rate between the source node and the target node, the conditions of data congestion, blindness of the target node and the like are avoided, and the data transmission quality is effectively ensured; and the hardware function of the DMA controller is adopted, so that the virtual channel and the physical channel which are matched for the data transmission and correspond to the data bandwidth do not need to be additionally increased, and the equipment resource is saved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1a is a flow chart of a data transfer method for a DMA controller according to an embodiment of the present application;

FIG. 1b is a schematic diagram of a data transfer process for a DMA controller according to an embodiment of the present application;

FIG. 2 is a block diagram of a DMA controller according to an embodiment of the present application;

Fig. 3 is a block diagram of an electronic device according to an embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

Compared with the traditional bus type communication network, the network on chip (Networkon Chip, noC) can support parallel communication, is easy to expand and reconstruct, and is more flexible in design. In a network-on-chip system for multi-core communication, a plurality of cores are connected together through a network-on-chip, and data communication between different cores is completed by the network-on-chip. In a network-on-chip system for multi-core communication, a traditional data communication mode is completed by a central processing unit (Central Processing Unit, CPU) with data transmission requirement, and for a communication scene with frequent data transmission, the repeated work of occupying a large amount of computing resources of the CPU to transmit and receive data is caused, so that the efficiency and performance of the CPU for processing other important tasks are reduced.

To address this issue, direct memory access (Direct Memory Access, DMA) mechanisms have emerged whereby a DMA controller can effect data transfer between a peripheral and memory or between memory and memory, copying data from one address space to another. In the whole communication engineering, the CPU only needs to send a communication instruction to the DMA controller, and the CPU which is idle can finish other more important tasks without participating in the data carrying process. By the data transmission mode, the CPU computing resource can be saved, and the overall processing performance and efficiency of the system can be improved.

In order to guarantee the communication quality, a certain quality of service (Quality of Service, qoS) guarantee mechanism is usually set to control the stability of data transmission, for example, common QoS guarantee modes include a best effort (besteffort) mode and a differentiated services (diffserv) mode. The best effort service is also called as transmission of the maximum throughput capacity of the network, and the mode is to perform dynamic negative feedback adjustment based on the transmission condition of the network, and after a certain node in the network is congested, a feedback signal is transmitted from the congested node to a source node for data transmission so as to inform the source node to reduce or even suspend transmitting data. The differentiated service refers to distinguishing according to the type of the data packet sent by the source node, and during data transmission, a hardware device responsible for data forwarding, for example, a router on a transmission path, can perform differentiated transmission according to different types of data packets. For example, by marking the type of data packets with priority, data packets that are more delay sensitive may be marked with higher priority, and such data packets may be preferentially distributed during data transmission.

Although the above-mentioned quality of service guarantee method can alleviate the problem that the data congestion and the transmission efficiency are low because of the bandwidth is insufficient to a certain extent, for best effort service method, it is difficult to guarantee the reflection speed and avoid the situation of the data congestion by performing negative feedback adjustment after the data congestion occurs. For the differentiated service mode, when the differentiated processing is performed on the data packets of different types, arbitration needs to be performed once or even multiple times, so that more computing resources are consumed, and processing logic is more complex. Therefore, it is necessary to provide a qos guarantee mode with simple processing logic and low resource consumption, so as to improve the efficiency and performance of network-on-chip data transmission.

Therefore, the embodiment of the application provides a data transmission method for a DMA controller, the DMA controller, equipment and a storage medium, which can adjust the speed of data transmission according to the throughput capacity of a source node or a target node for transmitting data and reduce the load pressure of network transmission; and the arbitration and judgment of different data are realized by utilizing the arbiter of the DMA controller, no additional hardware resource is needed, and the physical realization is simpler.

The data transmission method, the DMA controller, the device and the storage medium according to the embodiments of the present application are described below with reference to the accompanying drawings.

Fig. 1a is a data transmission method for a DMA controller according to an embodiment of the present application, where, as shown in fig. 1a, the method includes:

S1, receiving a DMA request, wherein the DMA request comprises a source address, a target address and data volume of data to be transmitted;

s2, determining the actual throughput corresponding to the corresponding source node and the corresponding target node respectively according to the source address and the target address;

S3, determining the data bandwidth of the current transmission data according to the actual throughput corresponding to the source node and the target node respectively;

And S4, determining a matched transmission channel according to the data bandwidth so as to transmit the data to be transmitted of the corresponding data quantity from the source node to the target node through the transmission channel.

Before the steps in the method are specifically described, first, in the embodiment of the application, the mode of transmitting data by the DMA controller is not limited, and the transmission mode can be different according to different application scenes of the DMA controller, and the specific transmission mode can be determined according to actual requirements. For example, in an alternative manner, the DMA control may be implemented in a separate electronic device, in which case the DMA controller may transfer data from one memory address space to another memory address space in the memory of the electronic device, or may transfer data from the memory of the electronic device to an external device. For another example, in another alternative, for a network system composed of a plurality of independent electronic devices together, the DMA controller may be applied to a control device in the system, in which case the DMA controller may transfer data from one electronic device to another.

In the above description, two alternative cases have been mentioned, respectively, in which the DMA controller is applied to a separate electronic device and to a control device in a network system constituted by a plurality of separate electronic devices. The manner in which the DMA controller transfers data in both cases will be illustrated separately.

Taking the example of the DMA controller being applied to a separate electronic device, it is assumed that there is a separate embedded system comprising a DMA controller and a memory for storing data. In this case, the DMA controller may transfer data by: first, a transfer is made from one memory address space to another memory address space. For example, assuming an application program that needs to process large amounts of data, the data may be stored in the memory of the system. The DMA controller may be configured to read data from one memory address and then transfer it to another memory address so that other processing units may directly access the data without intermediation by the CPU. Further, the data is transmitted to an external device. Alternatively, the DMA controller may be used to transfer data from the system memory to an external device, such as a memory, network interface, display device, etc. For example, when audio data needs to be sent to the sound card for playback, the DMA controller may be configured to transfer the audio data from memory into the buffer of the sound card so that the sound card can play.

In another example, the DMA controller is applied to a control device in a network system constituted by a plurality of independent electronic devices. It is assumed that a network system is formed of a plurality of individual electronic devices, each of which has its own DMA controller. In this case, the DMA controller may be used to transfer data between different devices, e.g., transfer data from one electronic device to another electronic device: for example, in a local area network, if one device needs to transfer data to another device, the DMA controller may be configured to transfer data directly between the two devices without intermediation by the CPU. Thus, the efficiency of data transmission can be improved and the load of the CPU can be reduced. The DMA controller is illustratively applied in a network switch or router. In a network device, a DMA controller may be used to manage the transfer of data packets. For example, in a router, when a packet arrives, a DMA controller may be used to transfer the packet from an input port to an appropriate output port without the intervention of a CPU, thereby enabling fast forwarding of the data. In summary, the DMA controller can adopt different transmission modes under different application scenarios, so as to meet the actual requirements and improve the performance and efficiency of the system.

In the embodiment of the present application, the implementation process of the above method is exemplarily described by taking an example that the DMA controller is applied to a network-on-chip system formed by a plurality of independent electronic devices, and it is understood that the DMA controller may implement transmission of data to be transmitted from one electronic device to another electronic device. For convenience of explanation, for data to be transmitted, an electronic device that transmits the data is referred to as a source node, and an electronic device that receives the data is referred to as a target node in the embodiments of the present application.

Based on the above, in the case that any one of the electronic devices has a data transmission requirement, a DMA request may be sent to the DMA controller to perform an initialization operation on the DMA controller. In the embodiment of the application, the specific mode of sending the DMA request to the DMA controller by the electronic device is not limited, for example, the electronic device can send the DMA request to the DMA controller by adopting any one of a single byte transmission mode, a group transmission mode or a query transmission mode, and the mode of sending the DMA request can be different according to different actual requirements. Further, the embodiment of the present application is not limited to specific contents of initializing the DMA controller by the electronic device, including but not limited to executing necessary Input/Output (I/O) instructions, setting a start address and a data amount of data to be transferred, setting initial values of related registers of the DMA controller, testing a use state of the external device, starting the external device, and the like, which may be specifically determined according to actual requirements, and will not be described in detail herein.

In the embodiment of the application, the DMA request comprises the source address, the target address and the data volume of the data to be transmitted, and based on the source address, the target address and the data volume of the data to be transmitted can be determined by the DMA controller after the DMA request is received. Further, according to the source address and the target address, the DMA controller can determine the actual throughput corresponding to the source node and the target node respectively, so as to determine the data bandwidth of the data transmitted according to the actual throughput corresponding to the source node and the target node respectively. In this way, in the process of subsequent data transmission, the speed of the data transmission can be controlled according to the actual throughput of the source node for transmitting the data or the target node for receiving the data, hardware equipment is not needed, and the implementation mode is simpler.

It should be noted that, the embodiment of the present application is not limited to a specific manner in which the DMA controller determines the actual throughput corresponding to each of the source node and the target node, and the determination manner may also be different according to different specific situations of the DMA controller application. For example, the DMA controller may determine the data transfer rate, data bandwidth, transfer protocol, etc. through hardware interfaces and specifications that match the source node and the target node to determine the actual throughput to which the source node and the target node correspond, respectively. For another example, the DMA controller may determine the actual throughput corresponding to the source node and the target node, respectively, by a device driver in the source node and the target node communicatively coupled to the DMA controller. For another example, in the case that the DMA controller has a bandwidth monitoring and feedback function, the data transmission rate between the source node and the target node may also be monitored and measured in real time by the function, and further, according to the monitored and measured data transmission rate, the DMA controller may determine the actual throughput corresponding to the source node and the target node, respectively. Of course, the above manner is merely exemplary, and is not limited thereto in practical application.

Further, after determining the data bandwidth of the data to be transferred, the DMA controller may further determine a transfer channel matching the data bandwidth, so as to transfer the data to be transferred of the corresponding data amount from the source node to the destination node through the matched transfer channel. The embodiment of the present application is not limited to a specific manner of determining a transmission channel, for example, a transmission channel that can be used for transmitting data from a source node to a target node may be determined according to a preset correspondence between the transmission channel and an external device in the DMA controller; for another example, a transmission channel matched with the type of the data to be transmitted at this time can be determined according to the type of the data which can be transmitted by the transmission channel in the DMA controller; for another example, the transmission channel used by the transmission data at this time can be determined according to the priorities set by the DMA controller for different transmission channels; for another example, the matched transmission channel may be dynamically determined for the current transmission data according to the current load and performance of the system determined by the operating system or the device driver, and so on. The specific manner of determining the transmission channel can be flexibly determined according to the actual requirements, and in practical application, the method is not limited to the above-mentioned several examples.

In the following, specific implementation forms of each step in the above method are exemplarily described.

In an alternative embodiment, when determining the data bandwidth of the current transmission data according to the actual throughputs corresponding to the source node and the target node respectively, the DMA controller may determine the node with the small throughput as the reference node according to the actual throughputs corresponding to the source node and the target node respectively, and further determine the data bandwidth of the current transmission data according to the actual throughputs of the reference node. The purpose of using the node with small throughput as the reference node is to ensure that the data bandwidth of the current transmission data does not exceed the actual throughput of the reference node. In this way, during the data transmission process, the situation that data are accumulated in the target node because the sending speed of the source node is greater than the receiving speed of the target node is avoided, and the situation that the target node is blind and the like because the sending speed of the source node is less than the receiving speed of the target node is avoided. Alternatively, when determining the data bandwidth of the current transmission data according to the actual throughput of the reference node, the transmission rate corresponding to the actual throughput of the reference node may be directly used as the maximum value of the data bandwidth of the current transmission data. Of course, in order to ensure a certain fault-tolerant rate, the transmission rate may be appropriately adjusted based on the transmission rate corresponding to the actual throughput of the reference node, for example, the transmission rate may be reduced according to a preset adjustment ratio, and the adjusted transmission rate may be used as the maximum value of the data bandwidth of the current transmission data. The specific determination mode can be determined according to actual requirements, and is not limited herein.

As an alternative embodiment, in the following, in connection with a specific example, how to determine the data bandwidth of the current transmission data according to the actual throughput of the source node and the target node is described.

First, according to the actual throughput corresponding to each of the source node and the target node, a node with a small throughput is first determined as a reference node. The purpose of this is to ensure that the data bandwidth of the current transmission does not exceed the actual throughput of the reference node. For example, if the actual throughput of the source node is 100Mbps and the actual throughput of the target node is 80Mbps, the target node is selected as the reference node. Further, the transmission rate corresponding to the actual throughput of the reference node may be directly set as the maximum value of the data bandwidth of the current transmission data. Continuing with the example above, if the actual throughput of the target node is 80Mbps, then 80Mbps is taken as the maximum value of the data bandwidth of the current transmission data. Or the transmission rate corresponding to the actual throughput of the reference node is properly adjusted to ensure a certain fault tolerance. For example, the transmission rate of the reference node may be adjusted according to a preset adjustment ratio (for example, reduced by 10%), and then the adjusted transmission rate is taken as the maximum value of the data bandwidth of the current transmission data.

In this way, problems due to throughput mismatch between the source node and the target node can be avoided. If the sending speed of the source node is greater than the receiving speed of the target node, data may be accumulated in the target node. Otherwise, if the sending speed of the source node is smaller than the receiving speed of the target node, the target node may be blind, and the overall transmission efficiency is affected.

It should be noted that, the specific adjustment mode and fault tolerance rate may be determined according to the actual requirement and the system characteristic, and may be flexibly adjusted according to the actual situation. The method can effectively manage the bandwidth of data transmission and improve the stability and efficiency of the system.

In an alternative embodiment, when determining the matched transmission channel according to the data bandwidth of the current transmission data, the DMA controller may determine the matched target virtual channel according to the data bandwidth of the current transmission data; and determining a target physical channel matched with the target virtual channel, and taking the target physical channel as a transmission channel. The embodiment of the present application is not limited to a specific manner of determining the target virtual channel, and optionally, the DMA controller may configure a different transmission bandwidth for each virtual channel through the first configuration information. Based on this, by acquiring the first configuration information, the DMA controller may determine a transmission bandwidth of each virtual channel, and further determine, according to the transmission bandwidth of each virtual channel, a target virtual channel adapted to the data bandwidth of the present transmission data. Accordingly, the method for determining the target physical channel is not limited, alternatively, the DMA controller may configure a mapping relationship between each physical channel and each virtual channel through the second configuration information, and based on this, the DMA controller may determine the target physical channel matching the target virtual channel by acquiring the second configuration information.

In addition, the DMA controller may also employ other policies to match the target physical channel to the target virtual channel. For example, for a single-threaded communication scenario, the DMA controller may detect the usage status of each physical channel in a polling manner, and if it determines that there is an idle physical channel, then determine the idle physical channel as the target physical channel to which the target virtual channel matches. For another example, for a multi-threaded communication scenario, if multiple virtual channels request access to a physical channel, the DMA controller may determine a target physical channel to which the target virtual channel matches based on the priority of each virtual channel; accordingly, the priority of each virtual channel may be preconfigured, or may be determined according to the order in which each virtual channel requests access based on the First Come, first common FIRST SERVICE, FCFS principle, and the specific manner is not limited. Further alternatively, if there are multiple idle physical channels, the priority of each physical channel may be further combined to match the target virtual channel with the target physical channel, and so on. It should be noted that the above determination method is only an exemplary illustration, and is not limited to this in practical application, and any feasible determination method is applicable to the embodiments of the present application, and is not described herein.

Based on this, after the access right of the target physical channel is allocated to the target virtual channel, the data to be transmitted can be transmitted from the source node to the target node through the target physical channel. The embodiment of the application is not limited to a specific manner of allocating the access right of the target physical channel to the target virtual channel, and different manners may be selected according to the actual communication scenario and the communication requirement.

For example, when the DMA controller determines a matching transfer channel, it needs to consider the data transfer requirements between the source node and the target node as well as the channel resources available in the system. The following is a specific example of how a DMA controller determines a matching transfer channel. In this example, it is assumed that there is an embedded system that includes a DMA controller and a plurality of virtual channels, each virtual channel corresponding to a particular data transfer requirement. In addition, there are multiple physical channels in the system available to the DMA controller. Firstly, the DMA controller acquires the transmission bandwidth of each virtual channel according to the first configuration information. For example, assume that there are three virtual channels in the system: A. b, C, their transmission bandwidths are 100Mbps, 80Mbps and 120Mbps, respectively. It is assumed that the data bandwidth currently required to be transmitted is 90Mbps. The DMA controller will select the target virtual channel that matches this data bandwidth. In this case, the transmission bandwidth of the virtual channel B is closest to the demand, and thus the DMA controller selects the virtual channel B as the target virtual channel. And further, the DMA controller acquires the mapping relation between each virtual channel and the physical channel according to the second configuration information. The mapping relationship is assumed as follows: virtual channel A corresponds to physical channel 1, virtual channel B corresponds to physical channel 2, and virtual channel C corresponds to physical channel 3. In addition, the DMA controller will also check the usage status of each physical channel. Suppose that physical channels 1 and 3 are currently in use, while physical channel 2 is idle. In this case, the DMA controller selects physical channel 2 corresponding to virtual channel B as the target physical channel. Thus, the matching transfer channels determined by the DMA controller are virtual channel B and physical channel 2. In this way, the DMA controller can use the physical channel 2 to transfer data to be transferred, thereby meeting the transfer requirements and ensuring efficient utilization of channel resources in the system.

In an alternative manner, before the data is transferred, a first access frequency for accessing the physical channel may be set in advance for the data transferred, based on which, by obtaining the first access rate, the DMA controller may allocate an access right of the target physical channel to the target virtual channel. As for the specific form of the first access frequency, the present embodiment is not limited, and alternatively, the first access frequency may be a preset access period including n clock periods; the value of n is not limited, and can be flexibly determined according to actual situations such as network load, data volume transmitted at this time, throughput of the source node and the target node, and the like. Further alternatively, a preset access period may be stored in the control and status register (Control and Status Registers, CSR), based on which the DMA controller, after retrieving the preset access period from the control and status register, may allocate the access right of the target physical channel to the target virtual channel according to the access period.

In another alternative, the DMA controller may dynamically determine the second access frequency according to a transmission bandwidth of the target virtual channel for transmitting data. For example, according to the data amount of the present transmission data and the transmission bandwidth of the target virtual channel, the DMA controller may determine the total duration of the present transmission data, and further, may determine an appropriate second access frequency in combination with actual situations such as the network load, the data amount of the present transmission, throughput of the source node and the target node, and the like. Based on this, the DMA controller may allocate the access right of the target physical channel to the target virtual channel according to the second access frequency.

Of course, the foregoing manner is merely illustrative, and in practical applications, the access right of the target physical channel may be alternatively allocated to the target virtual channel, which is not described in detail herein.

Based on the above, after the target virtual channel obtains the access right of the target physical channel, the target virtual channel can enter the network on chip through the matched physical channel, and the corresponding data is transmitted from the source node to the target node, so as to complete the data transmission process.

The application of the above method is described in overview from the point of view of the data transmission process with reference to the accompanying drawings.

FIG. 1b is a schematic diagram of a data transmission process according to an embodiment of the present application, where, as shown in FIG. 1b, in a case where a plurality of electronic devices have data transmission requirements, DMA requests may be sent to a DMA controller respectively; based on the above, after receiving DAM requests sent by a plurality of electronic devices, the DMA controller can determine the process of each electronic device requesting data transmission as a processing task, and according to the DMA request corresponding to each processing task, can determine the actual throughput corresponding to the source node and the target node of the corresponding request, and determine the data bandwidth corresponding to each processing task; further, according to the data bandwidth corresponding to each processing task, a matched virtual channel is determined, and an access right of a physical channel is allocated to each virtual channel, so that the corresponding processing task is completed through the corresponding physical channel via the network on chip. As shown in fig. 1b, when the DMA controller allocates the access right of the physical channel to each virtual channel, the DMA controller can be realized through an arbitration module inside the DMA controller, without adding additional hardware overhead, and can save equipment resources while ensuring the data transmission quality.

It should be noted that the number of virtual channels and physical channels in the DMA controller shown in fig. 1b is only shown as an example, and is not limited to this in practical application. In this example, the data transmission method provided by the embodiment of the application is used for implementing reasonable scheduling of a plurality of data processing tasks with different data bandwidths, but is not limited to this in practical application. For example, in the case that the communication system includes a plurality of DMA controllers, the plurality of electronic devices may also respectively send DAM requests to different DMA controllers, where the processing procedure of each DMA controller for data transmission is the same as the procedure principle shown in fig. 1b, and will not be described herein.

It should be further noted that the example shown in fig. 1b only outlines the application procedure of the above method from the point of view of the data transmission procedure, and for other specific processing procedures, reference may be made to the description of the corresponding parts in the foregoing method embodiment, which is not described in detail herein.

In the embodiment of the application, the DMA controller can determine the actual throughput of the corresponding source node and target node based on the received DMA request; furthermore, the data bandwidth of the data transmission is determined based on the smaller actual throughput, so that the rate of the data transmission is controlled to be not more than the receiving and transmitting rate between the source node and the target node, the conditions of data congestion, blindness of the target node and the like are avoided, and the data transmission quality is effectively ensured; and the hardware function of the DMA controller is adopted, so that the virtual channel and the physical channel which are matched for the data transmission and correspond to the data bandwidth do not need to be additionally increased, and the equipment resource is saved.

Based on the same implementation principle, the embodiment of the application also provides a DMA controller, which is used for realizing the data transmission method in the embodiment.

Fig. 2 is a block diagram of a DMA controller 200 according to an embodiment of the present application, and as shown in fig. 2, the DMA controller 200 includes: a receiving module 201, a determining module 202 and an arbitration module 203; wherein,

The receiving module 201 is configured to receive a DMA request, where the DMA request includes a source address, a destination address, and a data amount of data to be transferred;

the determining module 202 is configured to determine actual throughput corresponding to the source node and the target node according to the source address and the target address; determining the data bandwidth of the current transmission data according to the actual throughput corresponding to the source node and the target node respectively;

The arbitration module 203 is configured to determine a matched transmission channel according to the data bandwidth, so as to transmit data to be transmitted of a corresponding data amount from the source node to the target node through the transmission channel.

In an alternative embodiment, the determining module 202 is configured to, when determining the data bandwidth of the current transmission data according to the actual throughputs corresponding to the source node and the target node respectively: according to the actual throughput corresponding to the source node and the target node respectively, determining a node with small throughput as a reference node; and determining the data bandwidth of the current transmission data according to the actual throughput of the reference node.

In an alternative embodiment, the arbitration module 203 is configured to, when determining a matching transmission channel according to the data bandwidth: and determining a matched target virtual channel according to the data bandwidth, determining a target physical channel corresponding to the target virtual channel, distributing the access right of the target physical channel for the target virtual channel, and taking the target physical channel as a transmission channel.

In an alternative embodiment, the arbitration module 203 is configured to, when determining a matching target virtual channel according to the data bandwidth: acquiring first configuration information, wherein the first configuration information comprises the transmission bandwidth of each virtual channel; and determining a target virtual channel adapted to the data bandwidth according to the transmission bandwidth of each virtual channel.

In an alternative embodiment, the arbitration module 203, when determining the target physical channel corresponding to the target virtual channel, is configured to: acquiring second configuration information, wherein the second configuration information comprises a mapping relation between each physical channel and each virtual channel; and determining a target physical channel matched with the target virtual channel according to the mapping relation.

In an alternative embodiment, the arbitration module 203 is configured to, when allocating the access right of the target physical channel to the target virtual channel: acquiring a first access frequency preset for the transmission data at this time; and according to the first access frequency, allocating the access right of the target physical channel for the target virtual channel.

In an alternative embodiment, the arbitration module 203 is configured to, when allocating the access right of the target physical channel to the target virtual channel: determining a second access frequency according to the data volume and the transmission bandwidth; and according to the second access frequency, allocating the access right of the target physical channel for the target virtual channel.

It should be noted that, regarding the DMA controller provided by the implementation of the present application, specific functions and implementation details of each module have the same implementation principle as those of the implementation process of the corresponding steps in the foregoing method embodiment, and specific reference may be made to the description of the corresponding parts in the foregoing method embodiment, which is not repeated herein.

Based on the same implementation principle, the embodiment of the present application further provides an electronic device, fig. 3 is a block diagram of a structure of the electronic device 300, and as shown in fig. 3, the electronic device 300 includes: a processor 301, a memory 302, a communication interface 303, a communication bus 304 and a DMA controller 305; wherein, the processor 301, the memory 302, and the communication interface 303 complete the communication with each other through the communication bus 304; the memory 302 is used for storing a computer program; the processor 301 is configured to execute a program stored in the memory 302 to implement a corresponding processing function; the communication interface 304 is used for communication between the electronic device 300 and other devices; the DMA controller 305 is configured to implement the data transmission method described in the above method embodiment.

In the embodiment of the present application, the communication bus 304 may be a peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, etc., and the communication bus 304 may be divided into an address bus, a data bus, a control bus, etc., which are not limited in specific form. For ease of illustration, only one thick line is shown in fig. 3, but not only one bus or one type of bus.

The memory 302 may include random access memory (Random Access Memory, RAM) or may include non-volatile memory (non-volatil ememory), such as at least one disk memory. Alternatively, the memory may be at least one memory device located remotely from the processor 301.

Processor 301 may be a general-purpose processor including a Central Processor (CPU), a network processor (Network Processor, NP), etc.; but also digital signal processors (DIGITAL SIGNAL Processing, DSP), application specific integrated circuits (Application SpecificIntegrated Circuit, ASIC), field-Programmable gate arrays (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, the specific form of which may be determined according to the actual requirements.

Accordingly, the present application also provides a computer readable storage medium storing a computer program, where the computer program is executed to implement the steps executable by the electronic device in the above method embodiments.

It should be noted that while one or more embodiments of the present application provide method operational steps as described in the embodiments or flowcharts, more or fewer operational steps may be included based on conventional or non-inventive labor. The order of steps recited in the embodiments is merely one way of performing the order of steps and does not represent a unique order of execution. When implemented by an actual device or client product, the instructions may be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment) as shown in the embodiments or figures.

It will be appreciated by those skilled in the art that embodiments of the application may be provided as a method, apparatus (system) or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of the application may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

One or more embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to one or more embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

The embodiments of the present application are described in a progressive manner, and the same and similar parts of the embodiments are all referred to each other, and each embodiment is mainly described in the differences from the other embodiments. In particular, for apparatus and system embodiments, the description is relatively simple, as it is substantially similar to method embodiments, with reference to the description of method embodiments in part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The specific meaning of the terms in one or more embodiments of the application will be understood by those of ordinary skill in the art as appropriate.

It should be noted that, without conflict, one or more embodiments of the present application and features of the embodiments may be combined with each other. The one or more embodiments of the application are not limited to any single aspect, nor to any single embodiment, nor to any combination and/or permutation of these aspects and/or embodiments. Moreover, each aspect and/or embodiment of one or more embodiments of the application can be used alone or in combination with one or more other aspects and/or embodiments.

Finally, it should be noted that: the above embodiments are merely for illustrating the technical solution of one or more embodiments of the present application, and are not limiting thereof; while one or more embodiments of the present application have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application and are intended to be within the scope of the appended claims and description of one or more embodiments of the application.

The foregoing description of one or more embodiments of the application has been presented in conjunction with alternative embodiments, but these embodiments are merely exemplary and serve only as illustrations. On this basis, various substitutions and modifications may be made to one or more embodiments of the present application, which fall within the scope of one or more embodiments of the present application.

Claims (10)

1. A data transfer method, suitable for use in a DMA controller, comprising:

receiving a DMA request, wherein the DMA request comprises a source address, a target address and data volume of data to be transmitted;

Determining the actual throughput corresponding to the source node and the target node respectively according to the source address and the target address;

Determining the data bandwidth of the current transmission data according to the actual throughput corresponding to the source node and the target node respectively;

And determining a matched transmission channel according to the data bandwidth so as to transmit the data to be transmitted corresponding to the data quantity from the source node to the target node through the transmission channel.

2. The method of claim 1, wherein determining the data bandwidth of the current transmission of data according to the actual throughputs respectively corresponding to the source node and the target node comprises:

According to the actual throughput corresponding to the source node and the target node respectively, determining a node with small throughput as a reference node;

And determining the data bandwidth of the current transmission data according to the actual throughput of the reference node.

3. The method of claim 2, wherein determining a matched transmission channel based on the data bandwidth comprises:

determining a matched target virtual channel according to the data bandwidth;

Determining a target physical channel corresponding to the target virtual channel;

And distributing the access right of the target physical channel for the target virtual channel, and taking the target physical channel as a transmission channel.

4. A method according to claim 3, wherein determining a matching target virtual channel based on the data bandwidth comprises:

Acquiring first configuration information, wherein the first configuration information comprises transmission bandwidth of each virtual channel;

And determining a target virtual channel adapted to the data bandwidth according to the transmission bandwidth of each virtual channel.

5. The method of claim 3, wherein determining a target physical channel corresponding to the target virtual channel comprises:

Acquiring second configuration information, wherein the second configuration information comprises a mapping relation between each physical channel and each virtual channel;

And determining a target physical channel matched with the target virtual channel according to the mapping relation.

6. A method according to claim 3, wherein assigning the access rights of the target physical channel to the target virtual channel comprises:

acquiring a first access frequency preset for the transmission data at this time;

And distributing the access right of the target physical channel for the target virtual channel according to the first access frequency.

7. A method according to claim 3, wherein assigning the access rights of the target physical channel to the target virtual channel comprises:

Determining a second access frequency according to the data volume and the transmission bandwidth;

and distributing the access right of the target physical channel for the target virtual channel according to the second access frequency.

8. A DMA controller adapted to implement the data transfer method of any of the preceding claims 1-7.

9. An electronic device comprising a DMA controller for implementing the data transfer method according to any of the preceding claims 1-7.

10. A computer readable storage medium, characterized in that the computer readable storage medium has stored thereon computer program instructions, which when executed, implement the data transmission method according to any of the preceding claims 1-7.