JP2011160084A - Clock output method, clock output circuit, and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce jitter of a clock pulse in one clock pulse unit, in real time. <P>SOLUTION: A clock output circuit for reducing jitter included in a clock pulse includes: a delaying part for generating a plurality of delay clock pulses having different phases from an input clock pulse (input clock pulse); a period measuring part for measuring the period of each pulse of the input clock pulse; an accumulation operating part for accumulatingly operating each period measured by the period measuring part to obtain an accumulated operation value; a target accumulation operating part for accumulatingly operating the period (target period) of a targeted clock pulse to obtain a target accumulation operation value; a difference operating part for comparing the accumulation operation value with the target accumulation operation value to obtain a difference value in each period of the clock pulse; and a selecting part for selecting a delay clock pulse wherein the influence of the difference value is offset by referring to the difference value from the delaying part, and outputting the delay clock pulse as an output clock pulse. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a clock output method, a clock output circuit, and an image forming apparatus for reducing jitter included in a clock pulse, and to a technique for reducing jitter included in a clock pulse used for image formation.

  An image forming apparatus that forms an image of one line in the main scanning direction according to image data, and forms an image for one page by repeating image formation for each line in the main scanning direction in the sub-scanning direction. Are known.

  The image formation in the main scanning direction according to the image data is positioned with reference to a clock pulse which is a reference of a pixel to be formed, a clock pulse called “pixel clock” or “dot clock”.

  As an example, in an electrophotographic image forming apparatus, a laser beam modulated in accordance with image data is scanned in the main scanning direction, and in parallel with this, the laser is placed on an image carrier that rotates in the sub-scanning direction. An image is formed by the beam. In this case, the laser beam is modulated with the image data on the basis of the clock pulse described above.

  In this case, even if the frequency of the clock pulse does not change due to the influence of each part of the circuit that generates the clock pulse, fluctuations in the power supply voltage, etc., a slight time or phase shift (jitter) occurs at the rising or falling timing of the clock pulse. ) May occur.

  The jitter may slightly shift the position where the pixel is formed in the main scanning direction. Further, when the pixel position deviation in the main scanning direction is periodic, that is, aligned in the sub-scanning direction, moire may occur in the image. In the case of a color image forming apparatus, if there is a difference in the degree of occurrence of jitter in each color, color misregistration will occur in the contour portion of the image.

  In such a case, it is conceivable to use a high-accuracy clock pulse generation circuit that is extremely less influenced by jitter, but this is not preferable from the viewpoint of cost. Further, the fluctuation of the power supply voltage is not only a problem of the power supply circuit, but may be affected by the fluctuation of the power supply voltage in a circuit such as an ASIC, and it may be extremely difficult to take a countermeasure.

  In addition, as a technique regarding the clock pulse related to the image data, for example, it is described in Patent Document 1 and Patent Document 2 below.

JP 2007-110184 A JP 2000-198235 A

  In the above-mentioned Patent Document 1, although the clock pulse jitter countermeasure is taken, the clock pulse is selected according to the remaining capacity of the image data transmitted from the memory. For this reason, the above-mentioned problem cannot be solved.

In Patent Document 2, although it is possible to change the position of a clock pulse, jitter cannot be removed in real time in units of one clock pulse.
In Patent Document 2, a reference clock is separately provided, and the position of the clock pulse is changed with reference to the reference clock. However, when such a reference clock does not exist, There are also problems that cannot be addressed.

  Although a PLL exists as a well-known technique, the clock pulse used for image formation is reset with an index signal every time an image is formed in one line in the main scanning direction, so that the PLL cannot be applied. was there.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a clock output method capable of reducing the jitter of a clock pulse caused by various factors in real time in units of one clock pulse, It is to realize a clock output circuit and an image forming apparatus.

That is, the present invention as means for solving the problems is as described below.
(1) The invention of the clock output method is a clock output method for reducing jitter included in a clock pulse, and a delay step of generating a plurality of delayed clock pulses having different phases from an input clock pulse (input clock pulse). A period measuring step for measuring the period of each pulse of the input clock pulse, a cumulative calculating step for accumulating each period measured by the period measuring unit to obtain a cumulative calculation value, and a target clock pulse A target accumulation calculation step of accumulating the period of time (target period) to obtain a target accumulation calculation value, and a difference for obtaining a difference value for each period of the clock pulse by comparing the accumulation calculation value and the target accumulation calculation value The delayed clock pulse in a state where the influence of the difference value is canceled by referring to the calculation step and the difference value is selected and output as an output clock pulse. A selecting step of, characterized by comprising a.

  In the period measurement step, a synchronous delay clock pulse synchronized with the input clock pulse is obtained, and in the selection step, the influence of the difference value is canceled by referring to the synchronous delay clock pulse and the difference value. It is desirable to select the delayed clock pulse in the selected state and output it as an output clock pulse.

  The target accumulation calculation step is characterized in that the target period is obtained by averaging the input clock pulse or the delayed clock pulse over a predetermined period of a plurality of pulses.

  Further, the selecting step refers to the delay clock pulse so that an output clock pulse having a frequency different from that of the input clock pulse is obtained by referring to the difference value so that the influence of the difference value is offset. Is selected and output as an output clock pulse.

  (2) The invention of the clock output circuit is a clock output circuit for reducing jitter included in a clock pulse, and generates a plurality of delayed clock pulses having different phases from an input clock pulse (input clock pulse). A period measurement unit that measures the period of each pulse of the input clock pulse, a cumulative calculation unit that cumulatively calculates each period measured by the period measurement unit to obtain a cumulative calculation value, and a target clock pulse A target accumulating unit for accumulating the period (target period) to obtain a target accumulated calculated value, and a difference for obtaining a difference value for each period of the clock pulse by comparing the accumulated calculated value with the target accumulated calculated value A delay clock pulse in which the influence of the difference value is canceled by referring to the arithmetic unit and the difference value is selected from the delay unit and output as an output clock pulse. A selection unit for, characterized by comprising a.

  The period measurement unit obtains a synchronous delay clock pulse synchronized with the input clock pulse, and the selection unit cancels the influence of the difference value by referring to the synchronous delay clock pulse and the difference value. It is desirable to select the delayed clock pulse in the selected state and output it as an output clock pulse.

  The target accumulating unit obtains the target period by averaging the input clock pulse or the delayed clock pulse over a predetermined period of a plurality of pulses.

  Further, the selection unit refers to the difference value, the delay clock pulse so that an output clock pulse having a frequency different from that of the input clock pulse is obtained in a state where the influence of the difference value is offset. Is selected and output as an output clock pulse.

  (3) The invention of the image forming apparatus includes a clock generation unit that generates a clock pulse, a delay unit that generates a plurality of delayed clock pulses having different phases from an input clock pulse (input clock pulse), and the input clock pulse. A period measurement unit that measures the period of each pulse of the pulse, a cumulative calculation unit that cumulatively calculates each period measured by the period measurement unit to obtain a cumulative calculation value, and a target clock pulse period (target period) A target accumulation calculation unit that obtains a target accumulation calculation value by performing a cumulative calculation, a difference calculation unit that compares the accumulation calculation value and the target accumulation calculation value to obtain a difference value for each cycle of the clock pulse, and the difference A selection unit that selects a delayed clock pulse in a state in which the influence of the difference value is canceled by referring to a value from the delay unit and outputs the delayed clock pulse as an output clock pulse; and Using the output clock pulse as a reference, image formation for one line in the first direction according to the image data is performed, and image formation for each page in the first direction is repeated in the second direction for an image for one page. An image forming unit that forms an image, and the image forming unit includes an index signal generating unit that generates an index signal at a predetermined end position of image formation of one line in the first direction, and the cumulative calculation unit And the target cumulative calculation unit resets the cumulative calculation based on the index signal.

  The period measurement unit obtains a synchronous delay clock pulse synchronized with the input clock pulse, and the selection unit cancels the influence of the difference value by referring to the synchronous delay clock pulse and the difference value. It is desirable to select the delayed clock pulse in the selected state and output it as an output clock pulse.

  The target accumulating unit obtains the target period by averaging the input clock pulse or the delayed clock pulse over a predetermined period of a plurality of pulses.

  Further, the selection unit refers to the difference value, the delay clock pulse so that an output clock pulse having a frequency different from that of the input clock pulse is obtained in a state where the influence of the difference value is offset. Is selected and output as an output clock pulse.

  In the present invention, a plurality of delayed clock pulses having different phases are generated from the input clock pulse, the period of each pulse of the input clock pulse or the delayed clock pulse is measured, and the measured period is cumulatively calculated to be a cumulative calculation value. The target clock pulse period (target period) is cumulatively calculated to obtain a target cumulative calculation value, and these cumulative calculation values are compared with the target cumulative calculation value to obtain a difference value for each clock pulse period. By referring to the difference value, a delayed clock pulse in a state where the influence of the difference value is canceled is selected and output as an output clock pulse.

  As a result, the difference value between the cumulative calculation value and the target cumulative calculation value corresponds to jitter. By selecting and outputting the delayed clock pulse in a state where the influence of the difference value is canceled, the reference clock is output. Without requiring a pulse, it is possible to reduce the jitter of a clock pulse caused by various factors in real time in units of one clock pulse.

1 is a configuration diagram illustrating an overall configuration of an image forming apparatus to which an embodiment of the present invention is applied. It is a block diagram which shows the structure of the principal part of embodiment of this invention. It is a flowchart explaining operation | movement of embodiment of this invention. 6 is a time chart for explaining an operation state of the image forming apparatus according to the embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments (embodiments) for carrying out a clock output method, a clock output circuit, and an image forming apparatus of the present invention will be described in detail below with reference to the drawings.
In this embodiment, an image forming apparatus that implements a clock output method and an image forming apparatus that includes a clock output circuit (clock output unit) are taken as specific examples to reduce jitter included in clock pulses used for image formation. Give an explanation.

[Overall configuration of image forming apparatus]
Here, the configuration of the electrophotographic image forming apparatus 100 according to the first embodiment will be described in detail with reference to FIG. Note that descriptions of general parts that are known as the image forming apparatus 100 and are not directly related to the characteristic operations and controls of the present embodiment are omitted.

  An image forming apparatus 100 illustrated in FIG. 1 includes an overall control unit 101 that controls each unit, a clock generation unit 103 that generates a clock pulse necessary as a pixel clock, a dot clock, and the like during image processing and image formation. An operation display unit 105 that performs various operation inputs and various displays, a printer controller 110 that receives supply of image data from the outside, a scanner 120 that reads a document and generates image data, an input system (reading) for input image data System) input system image processing unit 130 for performing image processing, storage unit 140 for storing image data and various data over a necessary period, and output system (writing system) image processing for the image data stored in the storage unit 140. Output system image processing unit 150 to be applied, print engine 1 that forms an image on paper based on image data 0, and is configured with a.

  Here, the overall control unit 101 includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like (not shown). Here, the CPU uses a predetermined area of the RAM as a work area, executes various programs stored in the ROM, and comprehensively controls each unit of the image forming apparatus 100.

  Here, the operation display unit 105 includes input devices such as a keyboard, a mouse, and a touch panel, and transmits various input instruction signals to the overall control unit 101. The operation display unit 105 includes display means such as an LCD (Liquid Crystal Display) and a CRT (Cathode Ray Tube), and displays various image data input from the overall control unit 101. The operation display unit may be a separate operation unit and display unit, but may be a touch panel that presses a displayed icon or key (hereinafter referred to as “key”).

  The input system image processing unit 130 reads image data such as shading correction, scaling processing, tilt correction processing, and color conversion (RGB → YMCK) for color image formation on the input image data obtained by the scanner 120. Apply processing.

The storage unit 140 stores various data and image data using a flash memory or a hard disk device.
The output system image processing unit 150 performs output system image processing such as printer gamma conversion, error diffusion processing, and micro scaling processing necessary for image formation on the image data stored in the storage unit 140.

  The print engine 160 is an image forming unit or a printing apparatus of an electrophotographic system or various systems, and forms and outputs an image on a predetermined sheet in a copying machine, a printer, a facsimile machine, or the like.

  The print engine 160 includes a frequency adjustment unit 161, a synchronous clock generation unit 162, a clock output unit 163, a PWM unit 164, a light emitting unit 165, and a process unit 166.

  Here, the frequency adjusting unit 161 adjusts the frequency of the clock pulse in order to eliminate a magnification error of an optical system used for exposure for image formation of an electrophotographic method, and a predetermined range is used for exposure on the photoconductor. A predetermined number of dots are formed on the screen.

  The synchronization clock generation unit 162 receives an index signal indicating a position of a predetermined end during the exposure of electrophotographic image formation, and generates a clock pulse (synchronization clock pulse) in a state synchronized with the index signal.

  The clock output unit 163 is a characteristic part of the present embodiment, and outputs a clock pulse in a state where the influence of jitter is reduced. Details of the clock output unit 163 will be described with reference to FIG.

The PWM unit 164 receives the clock pulse and the image data, and generates light emission driving data for driving the light emitting unit.
The light emitting unit 165 is composed of a laser diode or the like, and receives light emission driving data to expose the photoconductor.

  The process unit 166 receives exposure from the light emitting unit 165 on the charged photoreceptor surface, and forms a toner image corresponding to the image data on the recording paper through various processes such as development and transfer.

When the image forming apparatus 100 is a color image forming apparatus, the print engine 160 may be provided for each color of YMCK.
[Configuration and operation of clock output circuit (clock output unit)]
FIG. 2 is a block diagram showing the configuration of the clock output unit 163 (clock output circuit in the claims) included in the image forming apparatus 100 of FIG. FIG. 3 is a flowchart showing the operation of the clock output unit 163, that is, the procedure of the clock output method. FIG. 4 is a time chart showing the operation of the clock output unit 163, that is, the state of the clock output method.

  The clock output unit 163 includes a delay element array unit 1631, a period measurement unit 1632, an accumulation operation unit 1633, an average operation unit 1634, a target accumulation operation unit 1635, a difference operation unit 1636, and a selection unit 1637.

  The operation of the clock output circuit (clock output unit 163) will be described below. Although the flowchart is shown to clearly show the operation, the operation shown in the flowchart is executed for each clock pulse. Here, the input clock pulse may be the basic clock pulse itself, or may be a clock pulse generated by dividing the basic clock pulse. In any case, the clock pulse input to the clock output unit 163 will be described.

  Here, the delay element array unit 1631 is a means for executing a delay process, and a plurality of delayed clock pulses (delayed clock pulse group (FIG. 2 (i))) having different phases from the input clock pulse (input clock pulse). Is generated (step S101 in FIG. 3). Note that in the delay element array unit 1631, delay elements are cascaded in a chain so that the number of stages that can be generated over two cycles of the basic clock is obtained for delayed clock pulses that are slightly different in phase so as to be useful for eliminating jitter. It is preferable. That is, it is only necessary to determine the number of cascade connection stages of delay elements constituting the delay element array unit 1631 according to the resolution required for eliminating jitter.

  FIG. 4A shows an input clock pulse or a delayed clock pulse in the group of delayed clock pulses, which includes the influence of jitter. The rise or fall timing of the pulse is subtle due to this jitter. It is in a state shifted to

  The period measurement unit 1632 is a means for executing a period measurement process, and is performed for each pulse of the input clock pulse (for each pulse) or for each pulse of the delay clock pulse generated by the delay element array unit 1631 (for each pulse). The period is measured, and the period measurement result (FIG. 2 (ii), FIG. 4 (b)) is supplied to an accumulation calculation unit 1633 described later.

  In this case, the period measurement unit 1632 is a system in which the frequency of each pulse of the input clock pulse (every pulse) or each pulse of the delay clock pulse (every pulse) is sufficiently higher than that of the delay clock pulse. Count with a clock to measure the period.

  Further, the period measurement unit 1632 obtains a delay clock pulse (hereinafter referred to as “synchronization delay clock pulse”) synchronized with the input clock pulse, and information on the number of delay element rows of the synchronization delay clock pulse (synchronization point information (FIG. 2 (iii)). )) Or the synchronous delay clock pulse itself is supplied to the selection unit 1637 described later (step S102 in FIG. 3).

  Note that the period measurement by the period measurement unit 1632 may be performed using the input clock pulse itself, but the period measurement is performed using the delay clock pulse to deal with the influence of the delay element array unit 1631. It becomes possible.

  In this embodiment, the delay element column stage number information of the synchronous delay clock pulse or the synchronous delay clock pulse itself, which is the output of the period measurement unit 1632, is collectively referred to as delay element column stage number information.

  The cumulative calculation unit 1633 is a means for executing a cumulative calculation step, and cumulatively calculates the cycle for each pulse measured by the cycle measurement unit 1632 to obtain a cumulative calculation value (FIG. 2 (iv), FIG. 4 ( c)) is obtained (step S103 in FIG. 3). The cumulative calculation of the cumulative calculation unit 1633 may be executed using an input clock pulse preceding the cycle measurement unit 1632. However, the cumulative calculation is performed using the output of the cycle measurement unit 1632, and the influence of each unit is also affected. It becomes possible to deal with it.

  The average calculation unit 1634 is a means for executing an average calculation process, performs an average calculation from the cumulative calculation value at the time when the predetermined number of pulses are reached, and sets the target clock pulse period (target period) as each pulse period. An average value (FIG. 2 (v)) is obtained. Note that the average calculation period measurement of the average calculation unit 1634 may be performed using a clock pulse preceding the accumulation calculation unit 1633, but the influence of each unit is obtained by performing the average calculation using the output of the accumulation calculation unit 1633. It is possible to deal with it.

  As the target period, it is possible to use a value obtained by performing an average calculation in advance, and it is also possible to directly input a fixed value or the like from the outside without performing the average calculation.

  The target accumulation calculation unit 1635 is a means for executing the target accumulation calculation step, and by accumulating the above target period, the target period is accumulated with the same number of pulses as the accumulation calculation value (FIG. 2 (iv)). The target cumulative calculation value (FIG. 2 (vi)) in the state is obtained (step S104 in FIG. 3). FIG. 4D shows an example of the target cumulative calculation value when the target period is 40.

  For the above cumulative calculation value and target cumulative calculation value, image formation is a method in which exposure for each line in the first direction (for example, main scanning direction) is repeated in the second direction (for example, sub-scanning direction). Is reset by an index signal obtained at the end in the first direction.

  The difference calculation unit 1636 is a means for executing the difference calculation step, and for each period of the input clock pulse, the accumulated calculation value (FIG. 2 (iv), FIG. 4 (c)) and the target accumulated calculation value (FIG. 2 (vi)). 4 (d)) and a difference value (FIG. 2 (vii), FIG. 4 (e)) is obtained (step S105 in FIG. 3). The difference value obtained for each cycle of the input clock pulse corresponds to the jitter of the input clock pulse. Here, if the period measurement result is 41, the difference value corresponding to the jitter is +1 as a difference from the target period of 40.

  The selection unit 1637 is a means for executing a selection step. The delay element array stage number information (FIG. 2 (iii)) obtained by the period measurement unit 1632 and the difference value obtained by the difference calculation unit 1636 (FIG. 2 (vii )), And by subtracting the difference value (FIG. 2 (vii)) from the delay element array stage number information (FIG. 2 (iii)), the delay clock pulse group (FIG. 2 (i)) Then, a delayed clock pulse in a state where the influence of the difference value corresponding to the jitter is canceled is selected and output as an output clock pulse (step S106 in FIG. 3). The above selection is repeated at the timing of each clock pulse.

  As a result, the difference value between the cumulative calculation value and the target cumulative calculation value corresponds to jitter. By selecting and outputting the delayed clock pulse in a state where the influence of the difference value is canceled, the reference clock is output. Without requiring a pulse, it is possible to reduce the jitter of a clock pulse caused by various factors in real time in units of one clock pulse.

  In this case, the selection unit 1637 obtains a correction cycle (FIG. 4F) obtained by subtracting the difference value from the target cycle. Then, the selection unit 1637 starts counting the correction period from the rising edge of the clock pulse including the jitter in FIG. 4A and selects and outputs the delayed clock pulse so that the counting end timing becomes the rising timing. It outputs as a clock pulse (FIG. 4 (f), (g)).

  In this way, by obtaining the difference between the cumulative calculation value and the target cumulative calculation value at the timing of each pulse, it becomes possible to remove the accumulated jitter at that time, and the absolute reference and Without using such an accurate clock, it is possible to select a delayed clock pulse in a state where the influence of the difference value corresponding to the jitter is canceled and output it as an output clock pulse.

  In the specific example of FIG. 4, the case where the influence of jitter is eliminated at the rising timing is shown, but the present invention is not limited to this, and the influence of jitter can be eliminated at the falling timing. is there.

  Further, the above description is the jitter removal for one color in the monochrome image forming apparatus, but in the case of a color image forming apparatus, by performing the process of removing the jitter from the clock pulse in the same manner for each color, Color misregistration between colors is also eliminated.

  In addition, although it demonstrated using the flowchart in the above description, a process can be performed by software and a process can also be implement | achieved by hardware (circuit). Further, since the operation of the flowchart is executed for each clock pulse, it is preferable to realize the processing by hardware (circuit).

<Other embodiments>
In the first and second embodiments described above, the electrophotographic image forming apparatus using a laser beam has been described. However, the present invention is not limited to this. For example, each embodiment of the present invention can be applied to various image forming apparatuses such as a laser imager that exposes photographic paper using a laser beam and an ink jet printer that ejects ink from a head. It is possible to obtain

100 Image forming apparatus (image forming system)
101 Overall Control Unit 103 Clock Generation Unit 105 Operation Display Unit 110 Printer Controller 120 Scanner 130 Input System Image Processing Unit 140 Storage Unit 150 Output System Image Processing Unit 160 Print Engine 161 Frequency Adjustment Unit 162 Synchronization Clock Generation Unit 163 Clock Output Unit (Clock Output circuit)
164 PWM unit 165 Light emitting unit 166 Process unit 1631 Delay element array unit 1632 Period measurement unit 1633 Accumulation calculation unit 1634 Average calculation unit 1635 Target accumulation calculation value 1636 Difference calculation unit 1637 Selection unit

Claims (9)

A clock output method for reducing jitter included in a clock pulse,
A delay process for generating a plurality of delayed clock pulses having different phases from an input clock pulse (input clock pulse);
A period measuring step of measuring a period of each pulse of the input clock pulse;
A cumulative calculation step of cumulatively calculating each period measured by the period measurement unit to obtain a cumulative calculation value;
A target cumulative calculation step of cumulatively calculating a target clock pulse period (target period) to obtain a target cumulative calculation value;
A difference calculation step of comparing the cumulative calculation value and the target cumulative calculation value to obtain a difference value for each cycle of the clock pulse;
A selection step of selecting the delayed clock pulse in a state where the influence of the difference value is canceled by referring to the difference value and outputting as an output clock pulse;
A clock output method comprising: The target cumulative calculation step obtains the target period by averaging the input clock pulse or the delayed clock pulse for a predetermined period of a plurality of pulses.
The clock output method according to claim 1, wherein: In the selection step, the delayed clock pulse is selected so that an output clock pulse having a frequency different from that of the input clock pulse is obtained by referring to the difference value, in which the influence of the difference value is offset. Output as an output clock pulse,
The clock output method according to claim 1, wherein: A clock output circuit for reducing jitter contained in a clock pulse,
A delay unit that generates a plurality of delayed clock pulses having different phases from an input clock pulse (input clock pulse);
A period measuring unit for measuring the period of each pulse of the input clock pulse;
A cumulative calculation unit that cumulatively calculates each cycle measured by the cycle measurement unit to obtain a cumulative calculation value;
A target cumulative calculation unit that cumulatively calculates a target clock pulse period (target period) to obtain a target cumulative calculation value;
A difference calculation unit that compares the cumulative calculation value with the target cumulative calculation value to obtain a difference value for each cycle of the clock pulse;
A selection unit that selects a delayed clock pulse in a state in which the influence of the difference value is canceled by referring to the difference value, and outputs it as an output clock pulse;
A clock output circuit comprising: The target cumulative calculation unit obtains the target period by averaging the input clock pulse or the delayed clock pulse over a period of a predetermined plurality of pulses.
5. The clock output circuit according to claim 4, wherein: The selection unit selects the delayed clock pulse so that an output clock pulse having a frequency different from that of the input clock pulse is obtained by referring to the difference value and in which the influence of the difference value is offset. Output as an output clock pulse,
6. The clock output circuit according to claim 4-5. A clock generator for generating clock pulses;
A delay unit that generates a plurality of delayed clock pulses having different phases from an input clock pulse (input clock pulse);
A period measuring unit for measuring the period of each pulse of the input clock pulse;
A cumulative calculation unit that cumulatively calculates each cycle measured by the cycle measurement unit to obtain a cumulative calculation value;
A target cumulative calculation unit that cumulatively calculates a target clock pulse period (target period) to obtain a target cumulative calculation value;
A difference calculation unit that compares the cumulative calculation value with the target cumulative calculation value to obtain a difference value for each cycle of the clock pulse;
A selection unit that selects a delayed clock pulse in a state in which the influence of the difference value is canceled by referring to the difference value, and outputs it as an output clock pulse;
Using the clock pulse output from the selection unit as a reference, image formation of one line in the first direction according to image data is performed, and image formation for each line in the first direction is repeated in the second direction to 1 An image forming unit for forming an image for a page;
With
The image forming unit includes an index signal generating unit that generates an index signal at a predetermined end position of image formation of one line in the first direction,
The cumulative calculation unit and the target cumulative calculation unit reset the cumulative calculation based on the index signal.
An image forming apparatus. The target cumulative calculation unit obtains the target period by averaging the input clock pulse or the delayed clock pulse over a period of a predetermined plurality of pulses.
The image forming apparatus according to claim 7. The selection unit selects the delayed clock pulse so that an output clock pulse having a frequency different from that of the input clock pulse is obtained by referring to the difference value and in which the influence of the difference value is offset. Output as an output clock pulse,
The image forming apparatus according to claim 7-8.

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