JP6455317B2 - Clock output method, clock output circuit, and image forming apparatus - Google Patents

Description

  The present invention relates to a clock output method, a clock output circuit, and an image forming apparatus that reduce jitter included in a clock pulse.

An image forming apparatus that forms an image of one line in the main scanning direction according to image data, and forms an image for one page by repeating image formation for each line in the main scanning direction in the sub-scanning direction. Are known.
In the image formation in the main scanning direction according to the image data, each pixel is positioned on the basis of a clock pulse which is a reference of a pixel to be formed, a clock pulse called “pixel clock” or “dot clock”.

  As an example, in an electrophotographic image forming apparatus, a laser beam modulated in accordance with image data is scanned in the main scanning direction, and in parallel with this, the laser is placed on an image carrier that rotates in the sub-scanning direction. An image is formed by the beam. In this case, the laser beam is modulated with the image data on the basis of the clock pulse described above.

In this case, even if the frequency of the clock pulse does not change due to the influence of each part of the circuit that generates the clock pulse, fluctuations in the power supply voltage, etc., a slight time or phase shift (jitter) occurs at the rising or falling timing of the clock pulse ) May occur.
In the image forming apparatus, the processing in each unit (image processing unit, image forming unit) of the image forming apparatus is periodically repeated, so that the power consumption changes every moment. The change may be a factor for changing the power supply voltage on the substrate.

  The jitter may slightly shift the position where the pixel is formed in the main scanning direction. Further, when the pixel position deviation in the main scanning direction is periodic, that is, aligned in the sub-scanning direction, moire may occur in the image. In the case of a color image forming apparatus, if there is a difference in the degree of occurrence of jitter in each color, color misregistration will occur in the contour portion of the image.

  In such a case, it is conceivable to use a highly accurate clock pulse generation circuit in which the influence of jitter is extremely smaller than before. However, it is not preferable from the viewpoint of cost effectiveness. Further, the fluctuation of the power supply voltage is not only a problem of the power supply circuit, but as described above, it may be affected by the fluctuation of the power supply voltage inside the circuit of each part, and it may be extremely difficult to take a countermeasure.

  In addition, as a technique regarding the clock pulse related to the image data, for example, it is described in Patent Document 1 and Patent Document 2 below.

JP 2011-160084 JP-A-2014-216706

  In the above Patent Document 1, in an image forming apparatus that repeats image formation in the main scanning direction in the sub-scanning direction, an error of jitter generated in one line in the main scanning direction is cumulatively calculated and the error is to be removed. . Therefore, the variation in length of one line is eliminated near the end of one line. However, it is impossible to cope with a case where the pulse period is slightly different for each clock pulse.

The above-mentioned Patent Document 2 also describes that the phase of a media clock for reproducing media is displaced by a phase displacement amount distributed at equal intervals over one period. That is, it is presumed that the processing is the same as that of the above Patent Document 1.
FIG. 9 shows an ideal clock pulse and how an image is formed by the clock pulse. Clock pulses with ideal cycles (FIG. 9A) are all measured as “8” by the cycle measurement (FIG. 9B). When the density is formed by the area gradation method in the image forming apparatus, the maximum density is all uniform (FIG. 9C).

On the other hand, FIG. 9 shows a clock pulse in which the period of each pulse may fluctuate and a state of image formation by the clock pulse.
The fluctuation of the period of each pulse is referred to as “period jitter”. The clock pulse having the period jitter (FIG. 10E) is measured as “8”, “7”, “8”, “9”, “8” by the period measurement (FIG. 10F). ing. In this case, the length variation is finally canceled out to “0”.

However, in the pixel corresponding to the second clock pulse (FIG. 10 (g)), although it depends on the method of generating the density, the maximum density is not completely obtained and the density is lowered (FIG. 10 (h)). ).
On the other hand, in the pixel corresponding to the fourth clock pulse (FIG. 10G), although the maximum density can be obtained depending on the method of generating the density, a blank portion (FIG. 10I) is generated. ing. In the color image forming apparatus, each color is formed at a predetermined different timing, and the respective color images are superimposed on the transfer body. In this case, in the part of FIG. 10 (i), since the timing is different for other colors, there is a high possibility that no blank part has occurred, and color misregistration occurs.

  As described above, it has been found that the period jitter of the clock pulse generated under the influence of each part of the image forming apparatus has an adverse effect on the image quality (density and color shift). In recent years, the resolution of image forming apparatuses has been increased, and the influence of pixel misalignment due to period jitter is relatively increasing.

In addition, with regard to period jitter generated in units of one clock pulse, even if various conventionally proposed techniques are used, jitter cannot be detected and removed in real time in units of one clock pulse. There was a problem.
The present invention has been made to solve the above-described problem, and an object of the present invention is to provide a clock output method, a clock output circuit, and an image forming apparatus capable of reducing jitter related to the period of a clock pulse in real time. Is to realize.

That is, the present invention as means for solving the problems is as described below.
(1) The present invention provides a clock output method, a clock output circuit, and an image forming apparatus for outputting an output clock pulse in a state in which jitter included in the clock pulse is reduced, and a plurality of phases different from the input clock pulse to be input A delay step for generating a delayed clock pulse, a period measuring step for measuring a period for each pulse of the input clock pulse, and a difference between a measurement period and a target period for each pulse measured in the period measuring step. A period fluctuation component that is a time change is extracted, and a period prediction step that predicts a scheduled period of an input clock pulse that is scheduled to be input with reference to the period fluctuation component, and a difference between the scheduled period and the target period is reduced. As described above, one of the plurality of delayed clock pulses is selected and output as an output clock pulse having a target period. A scan selection step, characterized by comprising a.
Clock output method.

(2) In the above (1), in the pulse selection step, the delayed clock pulse is selected and the output clock pulse is output so that the influence of the difference of the scheduled period with respect to the target period is offset. It is characterized by that.
(3) In the above (1) to (2), the period measurement step is characterized in that one pulse of the input clock pulse is measured by the number of delay stages whose phases are synchronized with a plurality of the delay clock pulses. .

(4) In the above (1) to (3), the period prediction step applies the extracted period variation component to the period variation component basic pattern obtained by measuring the period variation component. Predicting a scheduled period of an input clock pulse scheduled to be input.
(5) In (1) to (4) above, the output clock pulse is supplied to an image forming apparatus that forms a two-dimensional image by repeating line-shaped image formation in the main scanning direction in the sub-scanning direction. In the clock output method, an index signal indicating a start timing or an end timing of line image formation in the main scanning direction of the image forming apparatus is supplied, and in the period prediction step, a period divided by the index signal Is a main scanning period, the scheduled period is predicted using the period variation component obtained by measurement one main scanning period before.

  (6) In the above (1) to (4), the output clock pulse is supplied to an image forming apparatus that forms a two-dimensional image by repeating line-shaped image formation in the main scanning direction in the sub-scanning direction. The clock output method is supplied with a sub-scanning direction effective area signal indicating an effective area of image formation in the sub-scanning direction of the image forming apparatus, and is divided by the sub-scanning direction effective area signal in the period prediction step. When the period is set as a sub-scanning period, the scheduled period is predicted using the period fluctuation component obtained by measurement before one sub-scanning period.

  (7) In the above (1) to (6), an output cycle accumulation calculation step for calculating the output cycle accumulation calculation result by calculating the output clock pulse cycle, and the target cycle accumulation by calculating the target cycle. A target cycle cumulative calculation step for calculating a calculation result, a cumulative difference calculation step for calculating a cumulative difference that is a difference between the output cycle cumulative calculation result and the target cycle cumulative calculation result, and the cumulative difference exceeds a predetermined value. And a target period correcting step of correcting the target period so as to reduce the cumulative difference.

  (8) In the above (1) to (7), when outputting a test chart in the image forming apparatus, at least one image area is prepared in the test chart, and for the specific image area, At the Nth timing with respect to the clock cycle M, specific image data and image positions are output at a constant value, and at different timings, different specific image data and image positions are output at a constant value. Output clock pulses for output.

In the present invention, the following effects can be obtained.
(1) The present invention generates a plurality of delayed clock pulses having different phases from an input clock pulse that is input, measures the period of each pulse of the input clock pulse, and measures the measured period and target for each pulse. Extract the period fluctuation component, which is the time change of the difference from the period, and refer to this period fluctuation component to predict the expected period of the input clock pulse scheduled to be input, so that the difference between the expected period and the target period becomes smaller One of the plurality of delayed clock pulses is selected and output as an output clock pulse having a target period.

In this way, by predicting the expected period of the input clock pulse that is scheduled to be input and outputting the output clock pulse so that the difference between the scheduled period and the target period is reduced, jitter related to the period of the clock pulse is reduced in real time. It becomes possible to do.
(2) In the above (1), the delay clock pulse is selected and the output clock pulse is output so that the influence of the difference of the scheduled period with respect to the target period is offset, so that the state close to the target period Output clock pulses can be generated in real time.

  (3) In (1) to (2) above, one pulse of the input clock pulse is measured by the number of delay stages whose phases are synchronized with a plurality of delay clock pulses, so that the period fluctuation component of the input clock pulse can be accurately detected in real time. Thus, jitter related to the period of the clock pulse can be reduced in real time.

  (4) In (1) to (3) above, by applying the extracted periodic variation component to the periodic variation component basic pattern obtained by measuring the periodic variation component, The scheduled period can be accurately predicted, and the jitter related to the period of the clock pulse can be reduced in real time.

  (5) In the above (1) to (4), the expected period of the input clock pulse is predicted by using the period fluctuation component obtained by measurement before one main scanning period, so that The scheduled period can be accurately predicted, and the jitter related to the period of the clock pulse can be reduced in real time.

  (6) In the above (1) to (4), the expected cycle of the input clock pulse is predicted by using the cycle variation component obtained by measurement before one sub-scanning period. The scheduled period can be accurately predicted, and the jitter related to the period of the clock pulse can be reduced in real time.

  (7) In the above (1) to (6), a cumulative difference that is a difference between the output cycle cumulative calculation result and the target cycle cumulative calculation result is calculated, and the cumulative difference is referred to in addition to the predicted cycle prediction result, When the accumulated difference exceeds a predetermined value, select one of a plurality of delayed clock pulses so that the accumulated difference is reduced and output it as an output clock pulse of the target period. Thus, it is possible to reduce both the period jitter for each of the periods and the long term jitter for the result of accumulating the clock pulses.

  (8) In the above (1) to (7), when outputting a test chart in the image forming apparatus, at least one image area is prepared in the test chart, and a clock is generated for the specific image area. By setting the specific image data and image position to be output at a constant value at the Nth timing with respect to the cycle M, and to output different specific image data and image positions at a constant value at other timings. It becomes possible to output a test chart that can recognize the difference in the period of the clock pulse.

1 is a configuration diagram illustrating a configuration of an image forming apparatus including a clock output circuit according to a first embodiment of the present invention. It is a flowchart explaining operation | movement of 1st Embodiment of this invention. It is a time chart explaining the operation state of 1st Embodiment of this invention. It is a time chart explaining the operation state of 1st Embodiment of this invention. It is a block diagram which shows the structure of the image forming apparatus provided with the clock output circuit of 2nd Embodiment of this invention. It is a flowchart explaining operation | movement of 2nd Embodiment of this invention. It is a time chart explaining the operation state of 2nd Embodiment of this invention. It is explanatory drawing which shows an example of the pattern in 3rd Embodiment of this invention. 3 is a time chart for explaining an operation state of the image forming apparatus. 3 is a time chart for explaining an operation state of the image forming apparatus.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments (embodiments) for carrying out a clock output method, a clock output circuit, and an image forming apparatus of the present invention will be described in detail below with reference to the drawings.
In this embodiment, an image forming apparatus that implements a clock output method and an image forming apparatus that includes a clock output circuit (clock output unit) are taken as specific examples to reduce jitter included in clock pulses used for image formation. Give an explanation.

[Configuration of Image Forming Apparatus (1)]
Here, the configuration of the electrophotographic image forming apparatus 100 according to the first embodiment will be described in detail with reference to FIG. Note that descriptions of general parts that are known as the image forming apparatus 100 and are not directly related to the characteristic operations and controls of the present embodiment are omitted.

  An image forming apparatus 100 illustrated in FIG. 1 includes an overall control unit 101 that controls each unit, a storage unit 103 that stores various types of data, an operation display unit 105 that performs various types of display while an operator inputs various types of operations, and image processing and image processing. A clock generator 110 that generates a clock pulse required as a pixel clock or a dot clock at the time of formation, a clock output circuit 120 that reduces jitter included in the clock pulse, and an image processor that performs image processing on image data 140, and a print engine 160 that forms an image on a sheet based on the image data.

  Here, the overall control unit 101 includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), and the like (not shown). Here, the CPU uses a predetermined area of the RAM as a work area, executes various programs stored in the ROM, and comprehensively controls each unit of the image forming apparatus 100.

  The operation display unit 105 includes input devices such as a keyboard, a mouse, and a touch panel, and transmits various input instruction signals to the overall control unit 101. The operation display unit 105 includes display means such as an LCD (Liquid Crystal Display) and a CRT (Cathode Ray Tube), and displays various image data input from the overall control unit 101. The operation display unit may be a separate operation unit and display unit, but may be a touch panel that presses a displayed icon or key (hereinafter referred to as “key”).

The clock output circuit 120 includes a delay element array unit 121, a cycle measurement unit 122, a target cycle setting unit 123, a fluctuation extraction unit 124, a cycle prediction unit 125, a target cycle correction unit 126, a selection stage number calculation unit 127, a pulse selection unit 128, It is configured with.
The image processing unit 140 performs output system image processing such as printer gamma conversion, error diffusion processing, and micro scaling processing necessary for image formation on the image data.

  The print engine 160 is an image forming unit or a printing apparatus of an electrophotographic system or various systems, and forms and outputs an image on a predetermined sheet in a copying machine, a printer, a facsimile machine, or the like. Here, the PWM processing unit built in the print engine 160 receives the clock pulse with reduced jitter from the clock output circuit 120 and the image data from the image processing unit 140 to generate light emission drive data, and emits light. Driving part. The light emitting unit built in the print engine 160 is composed of a laser diode or the like, and receives light emission drive data to expose the photoconductor. Then, the process unit built in the print engine 160 receives the exposure from the light emitting unit on the surface of the charged photoreceptor, and through various processes such as development and transfer, forms a toner image corresponding to the image data on the recording paper. Form.

When the image forming apparatus 100 is a color image forming apparatus, the print engine 160 executes image formation for each color of YMCK.
[Operation (1)]
FIG. 2 is a flowchart showing the operation of the clock output circuit of the first embodiment, that is, the procedure of the clock output method. FIG. 3 is a time chart showing the operation of the clock output circuit, that is, the state during operation of the clock output method.

Although the flowchart is shown to clearly show the operation, the operation shown in the flowchart is executed for each clock pulse.
Here, the description will be given focusing on the clock output circuit 120. Therefore, a clock pulse input from the clock generation unit 110 to the clock output circuit 120 is expressed as an input clock pulse, and a clock pulse output from the clock output circuit 120 to the print engine 160 is expressed as an output clock pulse.

In the following description, first, generation of an output clock pulse that does not consider a periodic variation component will be described first, and then generation of an output clock pulse that considers a periodic variation component will be described.
[Basic operation of operation (1)]
Here, generation of an output clock pulse in a state in which the period variation component is not considered will be described.

During the image forming operation of the image forming apparatus 100, the delay element array unit 121 includes a plurality of delayed clock pulses (delayed clock pulse group (FIG. 1 (i))) having different phases from the input clock pulse (input clock pulse). (Step S101 in FIG. 2).
Note that in the delay element array unit 121, delay elements are cascaded in a chain form so that the number of stages that can be generated over two cycles of the basic clock is obtained with respect to delayed clock pulses that are slightly different in phase so as to be useful for eliminating jitter. It is preferable. That is, the number of cascade connection stages of the delay elements constituting the delay element array unit 121 may be determined according to the resolution required for eliminating jitter. For example, the delay element array unit 121 is configured by delay elements having a total of about 200 stages, in which one clock pulse is delayed with a resolution of about 1/100 and is divided into two periods.

  The period measuring unit 122 is means for executing a period measuring step. Here, the period measuring unit 122 obtains a delayed clock pulse (hereinafter referred to as “synchronized delay clock pulse”) synchronized with the input clock pulse, and information on the number of delay stages of the synchronized delayed clock pulse (synchronization point information (FIG. 1 (iii))). ) Or the synchronous delay clock pulse itself is supplied to the pulse selection unit 128 described later (step S102 in FIG. 2). In this embodiment, the delay stage number information of the synchronization delay clock pulse or the synchronization delay clock pulse itself, which is the output of the period measurement unit 122, is collectively referred to as delay stage number information.

  The period measuring unit 122 measures the period of each input clock pulse (one pulse), and the period measurement result (FIG. 1 (ii)) is used as a target period setting unit 123 and a fluctuation extracting unit 124 described later. To supply. Also in this case, the period measurement unit 122 calculates the period of each input clock pulse (each pulse) as a synchronous delay clock pulse and calculates it as the delay stage number information of the synchronous delay clock pulse (step in FIG. 1). S103). The period may be measured by counting with a system clock having a frequency sufficiently higher than the input clock pulse. Here, in FIG. 3 to be described later, the measurement period of the input clock pulse by the period measurement unit 122 is expressed as PRD value = 8 if it is equivalent to eight system clocks serving as a period reference.

  Further, the target cycle setting unit 123 refers to the cycle measurement result (FIG. 1 (ii)) in the cycle measurement unit 122, the instruction value from the overall control unit 101, and the index signal from the print engine 160 to obtain a desired value. A target period (FIG. 1 (vi), for example, PRD value = 8 in the case of FIG. 3) for obtaining an output clock pulse is set (step S104 in FIG. 2).

  In the target cycle correction unit 126, a correction instruction value (FIG. 1 (v)) created according to the scheduled cycle predicted by the cycle prediction unit 125 from the cycle variation component (FIG. 1 (iv)) stored in the variation extraction unit 124. In response, the target period is corrected (steps S105 to S107 in FIG. 2). This part will be described later in detail.

  In the selected stage number calculation unit 127, in order to output an output clock pulse having a period corresponding to the target period based on the target period (FIG. 1 (vii)) and the delay stage number information (FIG. 1 (iii)), a delay element Information on the number of selected stages (FIG. 1 (viii)) regarding which stage of the delayed clock pulse group (FIG. 1 (i)) output from the column unit 121 should be selected is generated and sent to the pulse selecting unit 128. Supply.

  The pulse selection unit 128 selects the delay clock pulse having the number of stages based on the selected stage number information (FIG. 1 (viii)) from the delay clock pulse group (FIG. 1 (i)), and the desired rise and desired A falling output clock pulse (FIG. 1 (ix)) is generated and supplied to the print engine 160 (step S108 in FIG. 2).

  Note that the clock output circuit 120 updates the storage of the period fluctuation component by either the index signal or the stop of the sub-scanning direction effective area signal (YES in step S109 in FIG. 2, S110), and image formation is performed. The above processing is repeated until the end to generate a desired rising / falling output clock pulse (steps S111, S101 or end in FIG. 2). The update of the periodic fluctuation component will be described in detail later.

In the above processing, the delay clock pulse having the number of stages based on the selected stage number information (FIG. 1 (viii)) is selected from the delay clock pulse group (FIG. 1 (i)), and the desired rise and the desired rise. Since a falling output clock pulse (FIG. 1 (ix)) is generated, it is possible to adjust a minute pixel size and pixel position of less than one pixel, such as a minute scaling process and a pixel position adjustment.
[Operation corresponding to periodic fluctuation component of operation (1)]
Here, generation of an output clock pulse in a state in which a period variation component is considered will be described.

  The fluctuation extractor 124 is a period fluctuation component that is a time change of a difference between the measurement period (PRD value in FIG. 3) for each pulse measured by the period measurement unit 122 and the target period instructed from the overall control unit 101. Is extracted, and this periodic variation component is stored and output to the subsequent cycle prediction unit (step S105 in FIG. 2).

3A is an input clock pulse that is in an ideal state and does not include a jitter component, FIG. 3B is a period reference in the period measurement unit 122, and FIG. 3C is a measurement that is measured by the period measurement unit 122. An example of the period is shown.
Here, from the first pulse p1 to the ninth pulse p9 of the input clock pulse, the measurement cycle is “8” (upper stage in FIG. 3C). In this case, the period fluctuation component which is the time change of the difference between the measurement period and the target period is p2-p1 = 0, p3-p2 = 0, p4-p3 = 0, p5-p4 = 0, p6-p5 = 0. , P7-p6 = 0, p8-p7 = 0, p9-p8 = 0 (lower part of FIG. 3C).

On the other hand, FIG. 3D shows an input clock pulse including a jitter component in an actual state, FIG. 3E shows a period reference in the period measurement unit 122, and FIG. An example of the measured measurement period is shown.
Here, from the first pulse p1 to the ninth pulse p9 of the input clock pulse, the measurement period is “8”, “7”, “8”, “9”, “8”, “7”, “8”, It has changed to “9”. In this measurement cycle, “8”, “7”, “8”, and “9” are periodically repeated.

  In this case, the period fluctuation component which is the time change of the difference between the measurement period and the target period is p2-p1 = -1, p3-p2 = + 1, p4-p3 = + 1, p5-p4 = -1, p6-p5. = -1, p7-p6 = + 1, p8-p7 = + 1, p9-p8 = -1. The periodic variation component is in a state where “−1”, “+1”, “+1”, and “−1” are periodically repeated.

  By the way, in the image forming apparatus 100, various processes are periodically (periodically) repeated in each unit (the image processing unit 140 and the print engine 160) of the image forming apparatus 100. Also in the image processing unit 140, reading of image data from the storage unit, image processing on the image data, writing of the image data to the storage unit, and the like are repeated periodically in accordance with the timing of image formation. It has become.

  For this reason, the power consumption of each part also changes every moment, and such a change in power consumption may be a factor that periodically changes the power supply voltage on the substrate. When such a periodic fluctuation of the power supply voltage occurs, even if the frequency of the clock pulse generated by the clock generation unit 110 has a crystal oscillation accuracy and does not change, the period is subtle if attention is paid to each one pulse. It is thought that there is a decrease that increases or decreases.

Here, the fluctuation extracting unit 124 obtains a difference (three consecutive differences) between the measurement periods of the adjacent clock pulses for each of the three adjacent clock pulses for the period variation component of the above measurement period, and the three consecutive differences. Find the histogram of.
In the example of FIG. 3, (−1, +1, +1), (+1, +1, −1), (+1, −1, −1), (−1, −1, +1) are obtained by histogram as three consecutive differences. It can be seen that only four types of) are repeatedly generated (FIG. 3 (g1) to (g4), (1) to. Then, the fluctuation extracting unit 124 generates the four types of three consecutive differences in the generation order ((−1, + 1, + 1), (+ 1, + 1, −1), (+ 1, −1, −1), ( -1, -1, + 1)) is also stored. In other words, the fluctuation extraction unit 124 stores the three consecutive differences repeatedly generated as described above and the generation order thereof as basic patterns.

However, as shown in FIG. 3 (h), from the state where all the cyclic fluctuation components are stored in series as -1, +1, +1, -1, +1, +1, -1,. The basic pattern may be calculated.
Or you may memorize | store the part of -1, + 1, + 1, -1 which becomes the origin of repetition as a periodic fluctuation component basic pattern.

As described above, the fluctuation extracting unit 124 extracts the period fluctuation component of the input clock pulse and outputs it to the period prediction unit 125 and stores the period fluctuation component basic pattern of the input clock pulse.
It is expected that this periodic variation component basic pattern changes depending on the operation pattern of the image forming apparatus. For this reason, it is desirable that the fluctuation extracting unit 124 updates the above-described calculation of the histogram and storage of the order during the image forming operation to those based on the latest operation state for a certain period.

  For example, when a period divided by the index signal is a main scanning period, a predicted period is predicted for the next main scanning period using a period fluctuation component obtained by measuring one main scanning period. (Step S108 in FIG. 2). It should be noted that it is not strictly limited to just one main scanning period, and it is also possible to use a periodic fluctuation component measured in several main scanning periods before prediction.

  Alternatively, when the period divided by the sub-scanning direction effective area signal is set as the sub-scanning period, the period of the next one sub-scanning period is determined using the period fluctuation component obtained by measuring one sub-scanning period. Is predicted (step S108 in FIG. 2). It should be noted that it is not strictly limited to just one sub-scanning period, and it is also possible to use a periodic fluctuation component measured in several sub-scanning periods before prediction. As another example, it is also possible to acquire a periodic fluctuation component during a paper interval in which the sub-scanning direction effective area signal is off.

  Then, the period prediction unit 125 predicts the scheduled period of the input clock pulse scheduled to be input using the period variation component extracted by the variation extraction unit 124 as described above (step S106 in FIG. 2). That is, the period predicting unit 125 extracts the period variation component of the input clock pulse input from the clock generation unit 110 and extracted by the variation extraction unit 124, and the period variation component basics extracted and stored by the variation extraction unit 124. By applying to the pattern, the expected period of the input clock pulse scheduled to be input can be predicted. The “scheduled cycle” means a cycle of a clock pulse that has not been input yet.

  For example, assuming that a clock pulse of p5 = 8 in FIG. 3D is input at the present time, the period variation component extracted from the input clock pulse matches the basic patterns (g1) and (g2). Then, when the p5 clock pulse is input, the period predicting unit 125 can predict that the PRD value = 7 for the scheduled period of the next-p6 clock pulse to be input.

  Therefore, the period predicting unit 125 finally outputs an PRD value = 8 in the pulse selecting unit 128 in response to an input clock pulse of PRD value = 7 that is narrower than the target period and includes jitter of −1. A correction instruction value (FIG. 1 (v)) for incrementing the target period (FIG. 1 (vi)) is given to the target period correction unit 126 so that a clock pulse can be output.

The target cycle correcting unit 126 receives the correction instruction value (FIG. 1 (v)) from the cycle predicting unit 125, adds +1 to the target cycle (FIG. 1 (vi)), and corrects the corrected target cycle (FIG. vii)) is generated (step S107 in FIG. 2).
The selected stage number calculator 127 outputs an output clock pulse having a period corresponding to the target period based on the corrected target period (FIG. 1 (vii)) and delay stage number information (FIG. 1 (iii)). The selected stage number information (FIG. 1 (viii)) about which stage of the delayed clock pulse group (FIG. 1 (i)) output from the delay element array unit 121 should be selected is used to select a pulse. To the unit 128.

  The pulse selection unit 128 selects the delay clock pulse having the number of stages based on the selected stage number information (FIG. 1 (viii)) from the delay clock pulse group (FIG. 1 (i)), and the desired rise and desired A falling output clock pulse (FIG. 1 (ix)) is generated and supplied to the print engine 160 (step S108 in FIG. 2).

Note that, as predicted by the period predicting unit 125, since the PRD value = 7 is expected by including jitter of −1 in the clock pulse p6, the corrected target period (FIG. 1 (vii)) is a normal PRD value. PRD value added by +1 to 8 = 9.
That is, since a wide (+1) target period is set for a narrow (−1) input clock pulse, the pulse selection unit 128 outputs an output clock pulse with a PRD value = 8 from which the jitter component has been canceled. Can be output (step S108 in FIG. 2).

  4 shows an input clock pulse having a period jitter component (FIG. 4A), a measurement period in the period measurement unit 122 (FIG. 4B), and a correction instruction given by the period prediction unit 125 to the target period correction unit 126. FIG. 4C is a time chart showing values (FIG. 4C) and output clock pulses (FIG. 4D) from which the period jitter component output from the pulse selection unit 128 is removed, in a state in which each timing is associated. is there.

In this way, by predicting the expected period of the input clock pulse that is scheduled to be input and outputting the output clock pulse so that the difference between the scheduled period and the target period is reduced, jitter related to the period of the clock pulse is reduced in real time. It becomes possible to do.
Here, by selecting the delayed clock pulse and outputting the output clock pulse so that the influence of the difference between the scheduled period and the target period is canceled out, the output clock pulse in the state close to the target period can be obtained in real time. Can be generated.

  In addition, by measuring one pulse of the input clock pulse by the number of delay stages whose phases are synchronized with a plurality of delayed clock pulses, it becomes possible to accurately detect the period fluctuation component of the input clock pulse in real time. It becomes possible to reduce the jitter related to the period of the pulse in real time.

  In addition, by applying the extracted periodic variation component to the periodic variation component basic pattern obtained by measuring the periodic variation component, it is possible to accurately predict the expected cycle of the input clock pulse scheduled to be input. Thus, it is possible to reduce the jitter related to the period of the clock pulse in real time.

  In addition, it is possible to accurately predict the expected period of the input clock pulse to be input by predicting the expected period of the input clock pulse by using the period fluctuation component obtained by measurement before one main scanning period. Thus, it is possible to reduce the jitter related to the period of the clock pulse in real time.

  In addition, it is possible to accurately predict the expected period of the input clock pulse to be input by predicting the expected period of the input clock pulse by using the period fluctuation component obtained by measurement before one sub-scanning period. Thus, it is possible to reduce the jitter related to the period of the clock pulse in real time.

[Configuration and Operation of Image Forming Apparatus (2)]
Here, the configuration of the electrophotographic image forming apparatus 100 of the second embodiment will be described in detail based on the configuration diagram of FIG. 5, the flowchart of FIG. 6, and the time chart of FIG. In addition, the overlapping description about the part which is common in 1st Embodiment is abbreviate | omitted.

According to the first embodiment described above, the jitter component of the input clock pulse is predicted and removed.
However, since the first embodiment is a feed-forward control, a jitter component remains in the output clock pulse (uncorrected) in order not to remove the necessary jitter when the prediction is wrong, and it actually occurs. There may be a slight phenomenon in which a jitter component is generated in the output clock pulse (overcorrection) because an unnecessary jitter component is removed.

In the first embodiment described above, correction for each clock pulse is performed as period jitter. Therefore, the uncorrected and overcorrected components as described above accumulate and remain as long term jitter. The image quality will be adversely affected.
Hereinafter, as a second embodiment, an embodiment of a clock output method, a clock output circuit, and an image forming apparatus capable of reducing both period jitter and long term jitter will be described.

The image forming apparatus 100 shown in FIG. 5 has the same basic configuration and basic operation as those of the first embodiment for calculating the period variation component, predicting the expected period of the input clock pulse, and removing the period jitter component (FIG. 6). Middle steps S101 to S111).
The newly provided parts in FIG. 5 are an accumulation calculation unit 129-1, an accumulation calculation unit 129-2, and an accumulation difference calculation unit 129-3.

  Here, the accumulative calculation unit 129-1 has a target cycle (FIG. 1 (vi) for obtaining a desired output clock pulse set by the target cycle setting unit 123, for example, in the case of FIG. 3, PRD value = 8) is cumulatively calculated until the end position of image formation in the main scanning direction, and a target period cumulative calculation result is calculated (step S112 in FIG. 6).

Further, the cumulative calculation unit 129-2 cumulatively calculates the period of the output clock pulse (FIG. 1 (ix)) from which period jitter has been reduced until reaching the end position of image formation in the main scanning direction, and outputs the output period. The cumulative calculation result is calculated (step S113 in FIG. 6).
Then, the cumulative difference calculation unit 129-3 calculates a cumulative difference that is a difference between the output cycle cumulative calculation result and the target cycle cumulative calculation result (step S114 in FIG. 6).
The cumulative difference calculation unit 129-3 calculates whether or not the cumulative difference has reached a predetermined value while calculating the cumulative difference in this way (step S115 in FIG. 6). This cumulative difference is a cumulative result of uncorrected and overcorrected components when the period jitter of the first embodiment is not corrected accurately.

  7A is a target cycle (PRD value = 8) and is constant, and FIG. 7B is a state in which a period jitter is corrected, but some uncorrected and overcorrected are included. This is the output cycle. FIG. 7C shows a cumulative calculation result, where the target cycle cumulative calculation result is x, the output cycle cumulative calculation result is y, and the cumulative difference is z as [x, y, z]. ing.

Therefore, the cumulative difference calculation unit 129-3 continues monitoring until the predetermined value of the cumulative difference exceeds, for example, about 0.5 pixels (in FIG. 3, PRD value = 3) (step S115 in FIG. 6). .
Here, when the accumulated difference does not exceed the predetermined value (NO in step S115 in FIG. 6), nothing is dealt with with respect to the long term jitter, and output is performed so as to remove the period jitter as in the first embodiment. A clock pulse is output (step S108 in FIG. 6).

  On the other hand, when the accumulated difference exceeds a predetermined value (YES in step S115 in FIG. 6), if the accumulated difference is left as it is, there is a possibility that the pixel position shift becomes a problem. In FIG. 7C, in the clock pulse of p6, the cumulative calculation result is [48, 51, +3], and the cumulative difference reaches the predetermined value +3.

  Therefore, the cumulative difference calculation unit 129-3 gives a correction instruction (FIG. 5 (x), FIG. 7 (d)) for correcting the target value so as to reduce the cumulative difference described above to the target period correction unit 126 (FIG. 6 in step S116). In this case, if the cumulative calculation result is +3, about 1/2 to 1/4, for example, -1 is set as the correction instruction value. That is, in order to prevent a large period jitter from occurring at the time of the correction instruction, a part of the cumulative calculation result is eliminated.

  Here, since the accumulated difference does not exceed the predetermined value (YES in step S115 in FIG. 6), in addition to period jitter removal, part of long term jitter is removed and output clock pulses are output. (Step S108 in FIG. 6). Based on the correction instruction (FIG. 7D), the cumulative calculation result is [56, 58, +2] at the position of the clock pulse p7, and the cumulative difference is decreased by 1 from the position of the immediately preceding clock pulse p6. ing.

  Thereafter, as described in the first embodiment, the clock output circuit 120 updates the storage of the period variation component by either the index signal or the stop of the sub-scanning direction effective area signal (step in FIG. 6). In S109, YES, S110), the above processing is repeated until the end of image formation to generate a desired rising / falling output clock pulse (step S111, S101 or end in FIG. 6).

  According to the second embodiment, a cumulative difference that is a difference between the output cycle cumulative calculation result and the target cycle cumulative calculation result is calculated, and the cumulative difference is determined by referring to the cumulative difference in addition to the predicted cycle prediction result. If the value exceeds the value, select one of the multiple delayed clock pulses to reduce the cumulative difference and output it as the output clock pulse of the target period. It is possible to reduce both the period jitter and the long term jitter for the result of accumulating clock pulses. That is, period jitter is reduced by feedforward control, and long term jitter is reduced by feedback control.

[Configuration and Operation of Image Forming Apparatus (3)]
With the first and second embodiments described above, it is possible to reduce period jitter and long term jitter. In the image forming apparatus 100 with reduced jitter in this way, it is desirable that whether or not the jitter is actually reduced can be confirmed by the control of the overall control unit 101.

  Hereinafter, patches included in a test chart generated by an instruction from the overall control unit 101 will be described with specific examples. In the case shown in FIGS. 3D to 3F, the fluctuation extracting unit 124 extracts the measurement cycle that “8”, “7”, “8”, “9” is periodically repeated.

That is, here, the number M of the periodic variation component basic patterns is M = 4 (the variation in the cycle of the clock pulse is a repetition for every M (= 4) clock pulses), so that four clock pulses are considered as one cycle. The following patches are formed side by side.
One patch is about 128 pixels × 128 pixels.

Here, as shown in FIG. 8, as patches from D1_41 to D15_44,
D1_41 (only the first pixel in one cycle is ON (pixel value = 1/15), the other is OFF),
D1_42 (only the second pixel in one cycle is ON (pixel value = 1/15), the other is OFF),
D1_43 (only the third pixel in one cycle is ON (pixel value = 1/15), the other is OFF),
D1_44 (only the fourth pixel in one cycle is ON (pixel value = 1/15), the other is OFF),
Are arranged in the main scanning direction.

Also, the same position in the main scanning direction as above, the sub-scanning direction position is changed,
D2_41 (only the first pixel in one cycle is ON (pixel value = 2/15), the other is OFF),
D2_42 (only the second pixel in one cycle is ON (pixel value = 2/15), the other is OFF),
D2_43 (only the third pixel in one cycle is ON (pixel value = 2/15), the other is OFF),
D2_44 (only the fourth pixel in one cycle is ON (pixel value = 2/15), the other is OFF),
Are arranged in the main scanning direction.

Repeat the same in the following, and the same main scanning direction position as above, changing the sub scanning direction position,
D15_41 (only the first pixel in one cycle is ON (pixel value = 15/15), the other is OFF),
D15_42 (only the second pixel in one cycle is ON (pixel value = 15/15), the other is OFF),
D15_43 (only the third pixel in one cycle is ON (pixel value = 15/15), the other is OFF),
D15_44 (only the fourth pixel in one cycle is ON (pixel value = 15/15), the other is OFF),
Are arranged in the main scanning direction.

  In the Nth patch (1 ≦ N ≦ M) of the M patches, the Nth M clock pulse has a predetermined density d, and other clock pulses have a different constant density other than the predetermined density. Since the test chart is formed so as to include the patch, the above patch can be expressed as Dd_MN.

In addition, although M patches are arranged in the main scanning direction, it is also possible to prepare a plurality of L sets of these and arrange L × M patches in the main scanning direction.
A test chart composed of a set of patches (a group of patches) is formed as described above. Here, one patch group is 4 × 15 = 60 in this specific example. However, the number of patches included in the patch group also changes if the periodic variation component basic pattern described above or the gradation of density differs.

When the light emitting unit of the image forming apparatus is in a multi-beam format and uses a plurality of laser beams in one main scan, similar patch groups are arranged in the sub-operation direction like LD1, LD2, LD3. (See LD_1, LD_2, LD_3 in FIG. 8).
In the above test chart, since the number M of the periodic variation component basic patterns is 4, the following patches are arranged side by side with four clock pulses as one period. One patch is about 128 pixels × 128 pixels. Further, if there are at least M patches in the horizontal direction, it is possible to confirm the removal of jitter.

  The above specific example can be expressed in general as follows. When the periodic variation component basic pattern of the clock pulse is repeated every M clock pulses of the number of patterns, at least M or more patches are prepared in the test chart, and the Nth (1 ≦ N ≦ N) in the M patches. In the patch M), the overall control unit is configured to form the test chart including the patch with the Nth M clock pulse having a predetermined density and the clock pulses other than the Nth with another constant density other than the predetermined density. 101 controls test chart formation.

  In this way, in the test chart having a plurality of areas in which the clock pulses to be emitted are changed according to the periodic variation component basic pattern and the density of each patch is gradually changed in each patch, the period of the clock pulse is caused by period jitter. In a patch including a state shorter than the target cycle, it can be confirmed that the image density is lower than in other patches adjacent in the main scanning direction.

Similarly, a patch including a state in which the period of the clock pulse is longer than the target period due to period jitter can be confirmed by an increase in image density or occurrence of color misregistration compared to other patches adjacent in the main scanning direction. .
For this test chart, the density of the toner image on the photoconductor may be read by a line sensor, or the operator may visually recognize the toner image transferred to the transfer paper. Alternatively, the toner image transferred to the transfer paper may be read by a scanner.

If the jitter reduction function of the present embodiment can be turned on / off according to an instruction from the overall control unit 101, the above test chart is formed before and after the jitter reduction function of the present embodiment is executed. The effect of reduction can be confirmed from the test chart.
Even if the jitter reduction function of this embodiment cannot be turned off, the effect of reducing jitter can be confirmed by forming the above test chart while the jitter reduction function of this embodiment is operating. Can do.

  If the density reduction is generated in each patch arranged in the main scanning direction as a result of executing the jitter reduction of the present embodiment and forming an image of the above test chart, the overall control unit 101 It is also possible to determine that an operation abnormality has occurred in any part, and control to stop the image forming operation.

Also, when forming this test chart, by placing some low density data on the data = 0 portion, it becomes easy to observe the density without isolating dots in the patch.
<Other embodiment (1)>
The clock output circuit 120 in the above embodiment may be a clock generation circuit (clock generation device) integrated with the clock generation unit 110. Further, the clock output circuit 120 in the above embodiment may be a clock correction circuit (clock correction device) that can be connected to the clock generation unit 110 and corrects a clock pulse.

<Other embodiment (2)>
In the first and second embodiments described above, the electrophotographic image forming apparatus using a laser beam has been described. However, the present invention is not limited to this. For example, each embodiment of the present invention can be applied to various image forming apparatuses such as a laser imager that exposes photographic paper using a laser beam and an ink jet printer that ejects ink from a head. It is possible to obtain

DESCRIPTION OF SYMBOLS 100 Image forming apparatus 101 Overall control part 103 Memory | storage part 105 Operation display part 110 Clock generation part 120 Clock output circuit 121 Delay element row | line | column part 122 Period measurement part 123 Target period setting part 124 Fluctuation extraction part 125 Period prediction part 126 Target period correction part 127 selection stage number calculation unit 128 pulse selection unit 140 image processing unit 160 print engine

Claims (16)

A clock output method for reducing jitter included in a clock pulse,
A delay step for generating a plurality of delayed clock pulses having different phases from an input clock pulse to be input;
A period measuring step for measuring the period of each pulse of the input clock pulse;
A periodic fluctuation component, which is a time change of the difference between the measurement period for each pulse measured in the period measurement step and the target period, is extracted, and the expected period of the input clock pulse scheduled to be input is referred to the periodic fluctuation component. A period prediction step for predicting
A pulse selection step of selecting any one of the plurality of delayed clock pulses so as to reduce a difference between the scheduled period and the target period, and outputting as an output clock pulse of the target period;
A clock output method comprising: The pulse selection step selects the delayed clock pulse and outputs the output clock pulse so that the influence of the difference of the scheduled period with respect to the target period is offset.
The clock output method according to claim 1, wherein: In the period measuring step, one pulse of the input clock pulse is measured by the number of delay stages whose phases are synchronized with a plurality of the delayed clock pulses.
The clock output method according to claim 1, wherein the clock output method is a clock output method. The cycle prediction step predicts a scheduled cycle of an input clock pulse to be input by fitting the extracted cycle variation component to a cycle variation component basic pattern obtained by measuring the cycle variation component. ,
The clock output method according to claim 1, wherein the clock output method is a clock output method. A clock output method for supplying the output clock pulse to an image forming apparatus that forms a two-dimensional image by repeating line-shaped image formation in the main scanning direction in the sub-scanning direction,
Receiving from the image forming apparatus an index signal indicating a line-shaped image forming reference in the main scanning direction of the image forming apparatus;
In the period predicting step, when the period divided by the index signal is a main scanning period, the scheduled period is predicted using the period variation component obtained by measuring one main scanning period before,
The clock output method according to claim 1, wherein the clock output method is a clock output method. A clock output method for supplying the output clock pulse to an image forming apparatus that forms a two-dimensional image by repeating line-shaped image formation in the main scanning direction in the sub-scanning direction,
Receiving a sub-scanning direction effective area signal indicating an effective area of image formation in the sub-scanning direction of the image forming apparatus;
In the cycle prediction step, when the period divided by the sub-scanning direction effective area signal is a sub-scan period, the scheduled cycle is calculated using the cycle variation component obtained by measuring one sub-scan period. Predict,
The clock output method according to claim 1, wherein the clock output method is a clock output method. An output cycle accumulation calculation step of accumulating the cycle of the output clock pulse and calculating an output cycle accumulation calculation result;
A target cycle cumulative calculation step of calculating the target cycle and calculating a target cycle cumulative calculation result;
A cumulative difference calculation step of calculating a cumulative difference that is a difference between the output cycle cumulative calculation result and the target cycle cumulative calculation result;
A target period correction step of correcting the target period so as to decrease the cumulative difference when the cumulative difference exceeds a predetermined value;
Further comprising
The clock output method according to claim 1, wherein the clock output method is a clock output method. A clock output circuit for reducing jitter contained in a clock pulse,
A delay unit that generates a plurality of delayed clock pulses having different phases from an input clock pulse that is input;
A period measuring unit for measuring the period of each pulse of the input clock pulse;
Extract a period fluctuation component that is a time change of the difference between the measurement period for each pulse measured by the period measurement unit and the target period, and refer to the period fluctuation component to determine the expected period of the input clock pulse to be input. A period prediction unit that predicts
A pulse selector that selects any one of the plurality of delayed clock pulses and outputs it as an output clock pulse of the target period, so that the difference between the scheduled period and the target period becomes small;
A clock output circuit comprising: The pulse selection unit selects the delayed clock pulse and outputs the output clock pulse so that the influence of the difference of the scheduled period with respect to the target period is offset.
9. The clock output circuit according to claim 8, wherein: The period measurement unit measures one pulse of the input clock pulse based on the number of delay stages whose phases are synchronized with a plurality of the delayed clock pulses.
The clock output circuit according to claim 8, wherein the clock output circuit is provided. The period predicting unit predicts a scheduled period of an input clock pulse to be input by fitting the extracted period variation component to a period variation component basic pattern obtained by measuring the period variation component. ,
The clock output circuit according to claim 8, wherein the clock output circuit is provided. A clock output circuit that supplies the output clock pulse to an image forming apparatus that forms a two-dimensional image by repeating line-shaped image formation in the main scanning direction in the sub-scanning direction;
Receiving an index signal indicating the timing of the start or end of line-shaped image formation in the main scanning direction of the image forming apparatus;
In the period prediction unit, when the period divided by the index signal is a main scanning period, the scheduled period is predicted using the period variation component obtained by measuring one main scanning period before,
The clock output circuit according to any one of claims 8 to 11, wherein the clock output circuit is configured as described above. A clock output circuit that supplies the output clock pulse to an image forming apparatus that forms a two-dimensional image by repeating line-shaped image formation in the main scanning direction in the sub-scanning direction;
Receiving a sub-scanning direction effective area signal indicating an effective area of image formation in the sub-scanning direction of the image forming apparatus;
In the period prediction unit, when the period divided by the sub-scanning direction effective area signal is set as a sub-scan period, the scheduled period is calculated using the period variation component obtained by measuring one sub-scan period. Predict,
The clock output circuit according to any one of claims 8 to 12, wherein the clock output circuit is configured as described above. An output period accumulation calculation unit that calculates the output period accumulation calculation result by accumulating the period of the output clock pulse;
A target period accumulation calculation unit for calculating the target period and calculating a target period accumulation calculation result;
A cumulative difference calculation unit that calculates a cumulative difference that is a difference between the output cycle cumulative calculation result and the target cycle cumulative calculation result;
A target period correcting unit that corrects the target period so as to decrease the accumulated difference when the accumulated difference exceeds a predetermined value;
Further comprising
The clock output circuit according to any one of claims 8 to 13, wherein the clock output circuit is configured as described above. A clock output circuit according to any one of claims 8 to 14,
An image forming unit that receives an output clock pulse from the clock output circuit and forms an image according to image data using the output clock pulse as a pixel clock pulse;
An image forming apparatus comprising: A control unit for controlling each unit is provided,
The controller is
When outputting a test chart in the image forming unit,
When the variation of the clock pulse cycle is repeated every M clock pulses, at least M patches are prepared in the test chart, and the Nth (1 ≦ N ≦ M) patches in the M patches The test chart is formed so as to include the patch with the Nth M clock pulse as a predetermined density and with a clock pulse other than the Nth as another constant density other than the predetermined density,
The image forming apparatus according to claim 15.