JP2011154154A - Display device and photodetection method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device and a photodetection method of the display device capable of stabilizing output voltage with a small number of elements in photodetection of a display part. <P>SOLUTION: Pixel circuits that emit light by means of a light emission element therein in accordance with an image signal and light reception circuits 61 that detect light are arranged in a matrix shape on a display part of the display device. In the light reception circuits 61, a sensor transistor T<SB>SE</SB>functions as a switching element and, at the same time, functions as a photosensor that flows an electric current in accordance with a detection amount of light in the off-state. A retention capacitance Cse is connected with the sensor transistor T<SB>SE</SB>and retains a prescribed potential. By a leak current flowing when the sensor transistor T<SB>SE</SB>is off, the potential retained beforehand on the retention capacitance Cse is changed in such a direction that the potential decreases and an output transistor T<SB>OUT</SB>outputs a photodetection signal in accordance with the potential after the change retained by the retention capacitance Cse. The display device and the photodetection method of the display device can be applied to, for example, a display device which displays an image and, at the same time, performs photodetection. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display device and a light detection method thereof, and more particularly, to a display device and a light detection method thereof that can stabilize an output voltage with a small number of elements in light detection of a display unit.

  In an active matrix type display device using an organic EL (ELectro Luminescent) element as a light emitting element, an active element (generally a thin film transistor: TFT) provided in the pixel circuit is a current flowing through the light emitting element in each pixel circuit. Controlled by. Since the organic EL element is a current light-emitting element, color gradation can be obtained by controlling the amount of current flowing through the organic EL element. That is, in a pixel circuit having an organic EL element, light of a gradation corresponding to the signal potential is emitted by causing a current corresponding to the given signal potential to flow through the organic EL element.

  FIG. 1 is a block diagram illustrating a general configuration example of an active matrix display device 1 using an organic EL element as a light emitting element.

  The display device 1 includes a video processing unit 11, a video signal output circuit 12, a display unit 13, and a writing scanning circuit 14. The video processing unit 11 performs predetermined signal conversion processing such as correction processing on the input video signal, and outputs the processed video signal to the video signal output circuit 12. The video signal output circuit 12 outputs the video signal of the signal potential Vsig input from the video processing unit 11 to each pixel circuit (the pixel circuit 21 in FIG. 2) of the display unit 13 in synchronization with the scanning of the writing scanning circuit 14. . The display unit 13 includes pixel circuits for video display (light emission) arranged in a matrix. Each pixel circuit emits light according to the supplied signal potential Vsig by the organic EL element inside. The writing scanning circuit 14 performs line-sequential writing control of the video signal of the signal potential Vsig output from the video signal output circuit 12 to the pixel circuits arranged in a matrix.

  FIG. 2 is a diagram illustrating a detailed configuration example of the display unit 13 of FIG.

The display unit 13 includes N × M pixel circuits 21 _{1,1 to} 21 _{N, M} arranged in a matrix (N and M are integer values of 2 or more independent from each other). In FIG. 2, only a part of the pixel circuits 21 _{1,1 to} 21 _{N, M} is shown due to space limitations. In the following description, the pixel circuits 21 _{1,1 to} 21 _{N, M} are simply referred to as pixel circuits 21 when it is not necessary to distinguish them.

Among the pixel circuits 21 arranged in a matrix, the pixel circuits 21 arranged in the vertical direction are connected to the video signal output circuit 12 by one video signal line DTL. For example, the pixel circuits 21 _{1,1 to} 21 _{1, M} in the first column are connected to the video signal output circuit 12 by the video signal line DTL ₁ . Therefore, the entire display unit 13 and the video signal output circuit 12 are connected by _N video signal lines DTL _{1 to} DTL _N.

Further, among the pixel circuits 21 arranged in a matrix, the pixel circuits 21 arranged in the horizontal direction are connected to the writing scanning circuit 14 by one writing scanning line WSL. For example, the pixel circuits 21 _{1,1 to} 21 _{N, 1} in the first row are connected to the writing scanning circuit 14 by the writing scanning line WSL ₁ . Accordingly, the entire display unit 13 and the writing scanning circuit 14 are connected by _M writing scanning lines WSL _{1 to} WSL _M.

  FIG. 3 is a diagram illustrating a detailed configuration example of the pixel circuit 21.

The pixel circuit 21 includes a sampling transistor T _WS using an n-channel TFT, a storage capacitor C1, a driving transistor T _DRV using a p-channel TFT, and an organic EL element ELP.

Video signal line DTL is connected to the drain of the sampling transistor T _WS, the write scanning line WSL is connected to the gate of the sampling transistor T _WS.

The drive transistor T _DRV and the organic EL element ELP are connected between the power supply Vcc and the cathode potential Vcat which is the ground potential. The sampling transistor _TWS and the storage capacitor C1 are connected to the gate of the drive transistor _TDRV .

  Next, the operation of the pixel circuit 21 will be briefly described with reference to the driving timing chart of FIG.

In the pixel circuit 21, in the 1H period in which the signal potential Vsig to itself is supplied to the video signal line DTL in one field period (1F), the potential of the writing scanning line WSL is set to a high potential by the writing scanning circuit 14. V _{WS_H} . For example, in the example illustrated in FIG. 4, the potential of the write scanning line WSL is set to the high potential V _{WS_H} from the time t ₂ to the time t _{3 in} the 1H period from the time t ₁ to the time t ₄ . As a result, the sampling transistor _TWS is turned on, and the signal potential Vsig is written into the storage capacitor C1. Further, the signal potential Vsig written in the storage capacitor C1 becomes the gate potential Vg of the drive transistor _TDRV .

At time t ₃ , when the writing scanning circuit 14 _sets the potential of the writing scanning line WSL to the low potential V _{WS_L} , the video signal line DTL and the driving transistor T _DRV are electrically disconnected, but the gate potential Vg of the driving transistor T _DRV. Is stably held by the holding capacitor C1. At this time, the drive current Ids flows through the drive transistor _TDRV and the organic EL element ELP. The current Ids has a value corresponding to the gate-source voltage Vgs of the drive transistor _TDRV , and the organic EL element ELP emits light with luminance corresponding to the current value Ids. That is, the pixel circuit 21 changes the voltage applied to the gate of the driving transistor T _DRV by writing the signal potential Vsig of the video signal line DTL to the holding capacitor C1, thereby controlling the current value Ids flowing through the organic EL element ELP To obtain color gradation.

式（１）において、Ｉｄｓは飽和領域で動作する駆動トランジスタＴ_DRVのドレイン・ソース間に流れる電流、μは駆動トランジスタＴ_DRVの移動度を表す。また、Ｗは駆動トランジスタＴ_DRVのチャネル幅、Ｌは駆動トランジスタＴ_DRVのチャネル長、Ｃｏｘは駆動トランジスタＴ_DRVのゲート容量、Ｖｔｈは駆動トランジスタＴ_DRVの閾値電圧を表している。また、Ｖｇｓは、駆動トランジスタＴ_DRVのゲートとソース間の電圧（ゲートソース間電圧）であり、Ｖｔｈは、駆動トランジスタＴ_DRVの閾値電圧である。なお、飽和領域とは、（Ｖｇｓ−Ｖｔｈ＜Ｖｄｓ）の条件を満たした状態をいう（Ｖｄｓは、駆動トランジスタＴ_DRVのソースとドレイン間の電圧）。 Since the source of the driving transistor T _DRV by the p-channel TFT is connected to the power source Vcc and is always designed to operate in the saturation region, the driving transistor T _DRV is a constant having the value shown in the following equation (1). It becomes a current source.

In Expression (1), Ids represents a current flowing between the drain and source of the driving transistor T _DRV operating in the saturation region, and μ represents the mobility of the driving transistor T _DRV . Further, W is the channel width of the driving transistor T _DRV, L is the channel length of the driving transistor T _DRV, Cox is the gate capacitance of the driving transistor T _DRV, Vth represents the threshold voltage of the driving transistor T _DRV. Vgs is a voltage between the gate and source of the drive transistor T _DRV (gate-source voltage), and Vth is a threshold voltage of the drive transistor T _DRV . Note that the saturation region means a state where the condition of (Vgs−Vth <Vds) is satisfied (Vds is a voltage between the source and the drain of the driving transistor T _DRV ).

The equation (1) As is clear from, in the saturation region, the drain current Ids of the driving transistor T _DRV is controlled by the gate-source voltage Vgs. Since the gate-source voltage Vgs is kept constant, the driving transistor T _DRV operates as a constant current source, and can emit the organic EL element ELP with constant luminance.

However, when the transistor characteristics of the drive transistor T _DRV are varied, that is, when the mobility μ and the threshold voltage Vth of the drive transistor T _DRV are varied, the current flowing through the organic EL element ELP also varies, resulting in uniform display. Sexuality will deteriorate. In addition, when the light emission time becomes long, the drive transistor _TDRV and the organic EL element ELP deteriorate with time, and image sticking that causes a difference in light emission luminance from a pixel having a short light emission time occurs.

  Accordingly, there have been proposed techniques for correcting the light emission luminance to be uniform over the entire screen and correcting the luminance change due to deterioration over time. For example, in the techniques disclosed in Patent Documents 1 to 3, as shown in FIG. 5, a photosensor is incorporated in a display device using a characteristic that a leakage current increases when a transistor receives light, and the pixel A technique for directly measuring and correcting the emission luminance has been proposed.

Special table 2008-505366 JP 2007-11233 A JP 2006-30317 A

  However, the technique proposed in Patent Document 1 has a problem in that since the detection voltage of the sensor is directly connected to the output line, it is vulnerable to external factors such as noise and coupling, and the output voltage tends to fluctuate. In addition, the techniques proposed in Patent Documents 2 and 3 have a problem that the yield is likely to deteriorate because the number of transistors in the sensor section is large.

  The present invention has been made in view of such a situation, and enables the output voltage to be stabilized with a small number of elements in the light detection of the display unit.

  A display device according to one aspect of the present invention includes a pixel circuit that emits light by an internal light emitting element according to a video signal, and a display unit in which a plurality of light receiving circuits that detect light are arranged in a matrix, and the light receiving circuit includes a switch A sensor transistor that functions as an element and functions as an optical sensor that passes a current corresponding to the detected amount of light in an off state, a storage capacitor that is connected to the sensor transistor and holds a predetermined potential, and the sensor transistor An output transistor that outputs a photodetection signal corresponding to the changed potential held by the holding capacitor, which changes in a direction in which the potential held in the holding capacitor in advance decreases due to a current that flows when the capacitor is off. .

  A display device photodetection method according to an aspect of the present invention includes a display device including a plurality of pixel circuits that emit light by an internal light emitting element according to a video signal and a plurality of light receiving circuits that detect light arranged in a matrix. The light receiving circuit of the sensor functions as a switch element and functions as a light sensor that flows a current corresponding to the detected amount of light in an off state, a holding capacitor connected to the sensor transistor, and the holding An output transistor connected to a capacitor, wherein the holding capacitor holds a predetermined potential by a current that flows when the sensor transistor is on, and the output transistor has a current that flows when the sensor transistor is off, The potential held in the storage capacitor changes in a decreasing direction, and the potential after the change held by the storage capacitor is changed. And it outputs a light detection signal.

  In one aspect of the present invention, in the storage capacitor, a predetermined potential is held by the current that flows when the sensor transistor is on, and in the output transistor, the potential that is held in the storage capacitor by the current that flows when the sensor transistor is off is In the decreasing direction, a light detection signal corresponding to the changed potential held by the storage capacitor is output.

  According to one aspect of the present invention, the output voltage can be stabilized with a small number of elements in the light detection of the display unit.

It is a block diagram which shows the general structural example of the conventional display apparatus. It is a figure which shows the detailed structural example of the display part of FIG. FIG. 3 is a diagram illustrating a detailed configuration example of a pixel circuit in FIG. 2. 3 is a drive timing chart illustrating the operation of a pixel circuit. It is a figure which shows the light reception characteristic of a transistor. It is a block diagram which shows the structural example of the display apparatus used as the foundation of this invention. It is a figure which shows the detailed structural example of the display part of the display apparatus of FIG. It is a figure which shows the detailed structural example of the light-receiving circuit of FIG. 7, and a sensor output detection circuit. It is a drive timing chart which shows operation | movement of a light-receiving circuit and a sensor output detection circuit. It is a figure which shows the state of the light receiving circuit and sensor output detection circuit during b point initialization process. It is a figure which shows the state of the light-receiving circuit and sensor output detection circuit during a photon detection process. It is a figure which shows the state of the light receiving circuit and sensor output detection circuit in ab point initialization process. It is a block diagram which shows 1st Embodiment of the display apparatus to which this invention is applied. It is a figure which shows the detailed structural example of the display part of the display apparatus of FIG. It is a drive timing chart which shows operation | movement of a light-receiving circuit and a sensor output detection circuit. It is a figure which shows the state of the light receiving circuit and sensor output detection circuit during b point initialization process. It is a figure which shows the state of the light-receiving circuit and sensor output detection circuit during a photon detection process. It is a figure which shows the state of the light receiving circuit and sensor output detection circuit in ab point initialization process. It is a block diagram which shows 2nd Embodiment of the display apparatus to which this invention is applied. It is a flowchart explaining a mode switching process. It is a block diagram which shows 3rd Embodiment of the display apparatus to which this invention is applied. It is a figure explaining the structure of the pixel circuit of FIG. FIG. 22 is a timing chart for explaining the operation of the pixel circuit of FIG. 21. FIG. 22 is a diagram describing in detail the operation of the pixel circuit of FIG. 21. FIG. 22 is a diagram describing in detail the operation of the pixel circuit of FIG. 21. FIG. 22 is a diagram describing in detail the operation of the pixel circuit of FIG. 21. FIG. 22 is a diagram describing in detail the operation of the pixel circuit of FIG. 21. FIG. 22 is a diagram describing in detail the operation of the pixel circuit of FIG. 21. FIG. 22 is a diagram describing in detail the operation of the pixel circuit of FIG. 21. FIG. 22 is a diagram describing in detail the operation of the pixel circuit of FIG. 21. FIG. 22 is a diagram describing in detail the operation of the pixel circuit of FIG. 21. FIG. 22 is a diagram describing in detail the operation of the pixel circuit of FIG. 21. It is a drive timing chart which shows operation | movement of a light-receiving circuit and a sensor output detection circuit. It is a block diagram which shows the other example of 3rd Embodiment of the display apparatus to which this invention is applied. It is a drive timing chart which shows operation | movement of a light-receiving circuit and a sensor output detection circuit.

Hereinafter, modes for carrying out the present invention (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. Embodiment 2 of a display device which is the basis of an embodiment of the present invention First embodiment of the present invention (embodiment using minus leak)
3. Second embodiment of the present invention (embodiment for switching between minus leak and plus leak)
4). Third Embodiment of the Invention (Embodiment in which the power supply scanning line DSS is shared with the power supply scanning line for controlling the light emission period of the pixel circuit)
5. Other examples of the third embodiment of the present invention (other embodiments in which the power supply scanning line DSS is shared with a control line for controlling the light emission period of the pixel circuit)

<1. Embodiments Basic to the Present Invention>
[Configuration of Display Device as a Basis of the Present Invention]
First, in order to facilitate understanding of the present invention and to clarify the background, the configuration and operation of a display device that is the basis of the present invention will be described with reference to FIGS.

  FIG. 6 is a block diagram illustrating a configuration example of a display device that is a basis of the present invention.

  The display device 50 in FIG. 6 is an active matrix type display device that has an organic EL element as a light emitting element inside each pixel circuit, generally called an organic EL display. However, the display device 50 is different from the display device 1 of FIG. 1 in that it can detect not only video but also light.

  The display device 50 includes a video processing unit 51, a video signal output circuit 52, a display unit 53, a writing scanning circuit 54, a sensor scanning circuit 55, a sensor output detection circuit 56, and a comparison unit 57.

  The video processing unit 51 performs predetermined signal conversion processing such as correction processing on the input video signal, and outputs the processed video signal to the video signal output circuit 52. For example, the video processing unit 51 performs a correction conversion process for correcting the uniformity of the light emission luminance of each pixel and the deterioration over time based on the correction amount of each pixel supplied from the comparison unit 57.

  The video signal output circuit 52 outputs the video signal of the signal potential Vsig input from the video processing unit 51 to each pixel circuit of the display unit 53 in synchronization with the scanning of the writing scanning circuit 54. The display unit 53 includes a pixel circuit (pixel circuit 21 in FIG. 7) for video display (light emission) and a light receiving circuit (light receiving circuit 61 in FIG. 7) for light detection, which are arranged in a matrix. The write scanning circuit 54 performs line-sequential writing control of the video signal of the signal potential Vsig output from the video signal output circuit 52 to the pixel circuits arranged in a matrix.

  The sensor scanning circuit 55 controls each light receiving circuit in the display unit 53 to receive light and outputs a light detection signal corresponding to the amount of received light to the sensor output detection circuit 56 in a line-sequential manner.

  The sensor output detection circuit 56 measures the luminance value of each pixel based on the light detection signal supplied from each light receiving circuit in the display unit 53 and outputs it to the comparison unit 57. The comparison unit 57 compares the luminance value of each pixel supplied from the sensor output detection circuit 56 with the luminance value of each pixel acquired in the initial state, calculates the correction value of the luminance value, and performs video processing. Supplied to the unit 51. Further, the comparison unit 57 calculates the correction amount of each pixel from the luminance value of each pixel supplied from the sensor output detection circuit 56 so that the light emission luminance of each pixel is uniform over the entire screen, and the video processing unit 51. To supply.

[Detailed Configuration Example of Display Unit 53]
FIG. 7 shows a detailed configuration example of the display unit 53 of the display device 50 of FIG. In FIG. 7, portions corresponding to the display unit 13 of the display device 1 described with reference to FIG. 2 are denoted by the same reference numerals, and description thereof is omitted as appropriate.

In the display unit 53, similarly to the display unit 13 of FIG. 2, pixel circuits 21 _{1,1 to} 21 _{N, M} are arranged in a matrix. In the display unit 53, light receiving circuits 61 _{1,1 to} 61 _{N, M} are arranged in a matrix so as to correspond to the pixel circuit 21 on a one-to-one basis. In the following description, the light receiving circuits 61 _{1,1 to} 61 _{N, M} are simply referred to as the light receiving circuit 61 when it is not necessary to distinguish them.

Among the light receiving circuits 61 arranged in a matrix, the light receiving circuits 61 arranged in the horizontal direction are connected to the sensor scanning circuit 55 by one power supply scanning line DSS, initialization scanning line AZ, and readout scanning line RSL. ing. For example, the light receiving circuits 61 _{1,1 to} 61 _{N, 1} in the first row are connected to the sensor scanning circuit 55 through the power supply scanning line DSS ₁ , the initialization scanning line AZ ₁ , and the readout scanning line RSL ₁ . Therefore, the entire display unit 53 and the sensor scanning circuit 55 are connected by M power source scanning lines DSS _{1 to} DSS _M , initialization scanning lines AZ _{1 to} AZ _M , and readout scanning lines RSL _{1 to} RSL _M. .

Further, among the light receiving circuits 61 arranged in a matrix, the light receiving circuits 61 arranged in the vertical direction are connected to the sensor output detection circuit 56 by one sensor output line SOL. For example, the light receiving circuits 61 _{1,1 to} 61 _{1, M} in the first column are connected to the sensor output detection circuit 56 through the sensor output line SOL ₁ . Therefore, the entire display unit 53 and the sensor output detection circuit 56 are connected by _N sensor output lines SOL _{1 to} SOL _N. The light receiving circuit 61 outputs a light detection signal corresponding to the amount of received light via the sensor output line SOL.

[Detailed Configuration Example of Light Receiving Circuit 61 and Sensor Output Detection Circuit 56]
FIG. 8 shows a detailed configuration example of the light receiving circuit 61 and the sensor output detection circuit 56. For the sensor output detection circuit 56, only the portion corresponding to one sensor output line SOL is shown.

The light receiving circuit 61 includes a sensor transistor T _SE , a holding capacitor Cse, an output transistor T _OUT using an n-channel TFT, and a read transistor T _RS .

Sensor transistor T _SE is connected between the gate of the output transistor T _OUT and power scanning line DSS. The gate of the sensor transistor T _SE is connected to the initialization scan line AZ.

Sensor transistor T _SE functions as a switch element to be turned on or off depending on the potential V _{AZ_H} or V _{AZ_L} supplied from the sensor scanning circuit 55 via the initialization scan line AZ. The sensor transistor T _SE is when on, the output transistor T potential V _{DSS_H} or V _{DSS_L} the power scanning line DSS to the gate of _OUT is inputted.

The sensor transistor _TSE functions as an optical sensor when turned off. That is, when the sensor transistor _TSE is off, a leak current corresponding to the amount of received light flows to the gate of the output transistor _TOUT . As shown in FIG. 5, the sensor transistor _TSE has a characteristic that when it is off, the leakage current increases or decreases according to the amount of received light. That is, if the amount of received light is large, the increase amount of the leakage current is large, and if it is small, the increase amount of the leakage current is small.

The storage capacitor Cse is connected between the ground potential (cathode potential V _CAT ) and the gate of the output transistor T _OUT . The holding capacitor Cse is provided to hold the gate voltage of the output transistor T _OUT .

Hereinafter, the source of the sensor transistor T _SE, the holding capacitor Cse, and the connection point of the gate of the output transistor T _OUT, suitably as a point.

The drain of the output transistor T _OUT is connected to the power supply scanning line DSS. The source of the output transistor T _OUT is connected to the read transistor T _RS .

The read transistor T _RS is connected between the source of the output transistor T _OUT and the sensor output line SOL. The gate of the read transistor T _RS is connected to the readout scanning line RSL. The read transistor T _RS functions as a switch element that is turned on or off according to the potential V _{RSL_H} or V _{RSL_L} supplied from the sensor scan circuit 55 via the read scan line RSL. When reading transistor T _RS is on, the current flowing through the output transistor T _OUT is output to the sensor output line SOL.

  On the other hand, the sensor output detection circuit 56 includes a reset transistor Trst, a fixed power source VRST having a reset potential Vrst, a holding capacitor Cout, and a voltage detection unit 56a.

  The reset transistor Trst is connected between the fixed power source VRST and the sensor output line SOL. The source of the reset transistor Trst connected to the sensor output line SOL is also connected to the storage capacitor Cout and the voltage detection unit 56a. The gate of the reset transistor Trst is connected to the reset scanning line RST.

The reset transistor Trst functions as a switch element that is turned on or off in accordance with the potential V _{RST_H} or V _{RST_L} supplied via the reset scanning line RST. The potential V _{RST_H} or V _{RST_L} of the reset scanning line RST is controlled by the sensor scanning circuit 55.

  The voltage detection unit 56a detects, as an output voltage Vout, a potential Vb at a point b that is a connection point of the source of the reset transistor Trst, the sensor output line SOL, and the storage capacitor Cout. Then, the voltage detection unit 56a outputs the detected output voltage Vout to the comparison unit 57 as a signal representing a luminance value.

The holding capacitor Cout is connected between the ground potential (cathode potential V _CAT ) and the sensor output line SOL. The holding capacitor Cout is provided to hold the output voltage Vout.

[Explanation of light detection operation]
Next, the light detection operation by the light receiving circuit 61 and the sensor output detection circuit 56 will be described with reference to FIGS.

  FIG. 9 is a drive timing chart showing the operation of the light receiving circuit 61 and the sensor output detection circuit 56.

  FIG. 9 shows changes in the potentials of the power supply scanning line DSS, the initialization scanning line AZ, the readout scanning line RSL, and the reset scanning line RST, and changes in the potential Va at the point a and the potential Vb (output voltage Vout) at the point b. Is shown.

In FIG. 9, one cycle time from time t ₁₁ to time t ₂₁ corresponds to a time (1F time) for scanning the M light receiving circuits 61 of the display unit 53 once for each row. In the light detection operation, the amount of light received by the light receiving circuits 61 in a predetermined row is acquired during the 1 Cycle time. Then, the light reception amount of the entire display unit 53 is acquired by changing the row of the light reception circuit 61 that acquires the light reception amount, for example, line-sequentially every 1 cycle time.

State at time t ₁₁ in FIG. 9 is an initial state in which the power scanning line DSS, initializing the scan line AZ, the read scanning lines RSL, and all of the potential of the reset scan line RST is at a low potential.

In the light detection operation, first, a b point initialization process for initializing the potential Vb at the b point is executed. Specifically, at time t ₁₂ , the potentials of the initialization scanning line AZ, the readout scanning line RSL, and the reset scanning line RST are set to a high potential by the sensor scanning circuit 55. As a result, the sensor transistor T _SE , the read transistor T _RS , and the reset transistor Trst are all turned on, and as a result, the potential at the point b (output voltage Vout) is initialized to the reset potential Vrst.

  FIG. 10 shows the state of the light receiving circuit 61 and the sensor output detection circuit 56 during the b-point initialization process.

Since the potential of the power scanning line DSS is a low potential V _{DSS_L,} sensor transistor T _SE is by turning on, the potential Va at point a becomes the V _{DSS_L.} In addition, by reading transistor T _RS and the reset transistor Trst is turned on, the potential Vb at point b becomes the reset potential Vrst. By this b point initialization process, the potential Vb at the point b is initialized to a constant potential (reset potential Vrst) regardless of the previous state.

After completion of the point b initialization, at time _13, the potential of the initialization scan line AZ and the reset scan line RST is returned to a low potential, the sensor transistor T _SE, and the reset transistor Trst is turned off.

Next, from time ₁₄ to time _15, the potential of the power supply scanning line DSS is set to the high potential V _{DSS_H,} and light detection processing for detecting light is performed.

  FIG. 11 shows the states of the light receiving circuit 61 and the sensor output detection circuit 56 during the light detection process.

The sensor transistor _TSE is turned off, and a leak current corresponding to the amount of received light flows to point a. Here, the amount of change in potential when a leak current flows through the sensor transistor T _SE △ V is the leakage current i, 2 one capacity C of the gate capacitance of the storage capacitor Cse and the output transistor T _OUT, and the time t, the following It can be represented by Formula (2).

The potential Va at the point a can be expressed as (V _{DSS_L} + ΔV) using a potential change ΔV corresponding to the amount of received light. Since the reset transistor Trst is off, when the current flows from the output transistor T _OUT to the point b as the potential Va at the point a increases, the potential Vb at the point b increases. When the threshold voltage of the output transistor T _OUT is expressed as Vth _OUT , the potential Vb at the point b is (V _{DSS_L} + ΔV) −Vth _OUT . As described above, the amount of change ΔV in potential according to the amount of received light increases as the amount of received light increases.

The voltage detection unit 56a detects the potential Vb at the point b as the output voltage Vout at a predetermined timing from time ₁₄ to time ₁₅ when the potential of the power supply scanning line DSS is set to the high potential V _{DSS_H} .

The detection period of the received light amount _ends at time _{15 when} the potential of the power supply scanning line DSS is set to the low potential V _{DSS_L} and the potential of the readout scanning line RSL is set to the low potential V _{RSL_L} .

In the period from time ₁₆ to time ₁₇ after time ₁₅ , the ab point initialization process for initializing the potential Va at the point a and the potential Vb at the point b is performed so as not to affect other operations until the next detection. Executed. Specifically, between time ₁₆ and time ₁₇ , the potentials of the initialization scanning line AZ and the reset scanning line RST are set to a high potential.

  FIG. 12 shows the states of the light receiving circuit 61 and the sensor output detection circuit 56 during the ab point initialization process.

Initialization scan line AZ is changed to the high potential V _{AZ_H,} by sensor transistor T _SE is turned on, the potential Va of the node a, the power scanning line DSS a potential the same potential V _{DSS_L.} Further, the potential of the reset scanning line RST changes to the high potential V _{RST_H} and the reset transistor Trst is turned on, whereby the potential Vb at the point b becomes the reset potential Vrst. By this ab point initialization processing, initialization of the sensor output detection circuit 56 in the light receiving circuit 61 in the next row is completed.

  The light detection operation by the light receiving circuit 61 and the sensor output detection circuit 56 is performed as described above. The comparison unit 57 compares the luminance values of the pixels supplied as the output voltage Vout from the sensor output detection circuit 56 with each other. Thereby, the uniformity of light emission luminance can be improved. The comparison unit 57 compares the luminance value of each pixel supplied as the output voltage Vout with the luminance value acquired in the initial state. Thereby, deterioration with time can be corrected.

  The correction process can be executed at a predetermined timing after the normal video display is finished, during normal video display execution, or before the normal video display start. Here, “normal video display” refers to a state in which a video potential as a normal moving image or still image is displayed by applying a signal potential Vsig based on the video signal supplied to the display device 50 to each pixel circuit 21. To tell.

Further, in the display device 50, the light receiving circuit 61 is constituted by three transistors and the storage capacitor Cse by providing the sensor transistor _TSE and disposing the sensor output detection circuit 56 outside the display unit 53. Can do. Therefore, the display device 50 can perform light detection with the output voltage stabilized with a small number of elements.

  Note that the light detection function of the display device 50 can also detect light from the outside of the display device 50, and thus can be used for functions other than the function for correcting the light emission luminance of each pixel as described above. For example, it can be used for a part of functions such as a function of capturing an image like a scanner and a touch panel or a pointer sensor.

  In the display device 50 described with reference to FIGS. 6 to 12, the power supply scanning line DSS connected to the light receiving circuit 61 is shared with the power supply scanning line for controlling the light emission period in the pixel circuit 21 in order to reduce the number of wirings. It is possible to make it.

When the power supply scanning line DSS is shared with the power supply scanning line for controlling the light emission period of the pixel circuit, a detection period for detecting the amount of received light when the light emission period of the pixel is shortened in order to improve moving image characteristics (FIG. 9). Will also be shorter. That is, if the light emission period of the pixel is shortened, the period for setting the potential of the power supply scanning line to a high potential is also shortened. Therefore, the period for setting the potential of the power supply scanning line DSS shared with the potential to the high potential V _{DSS_H} is also increased. It will be shorter.

  Since the detection of the amount of received light detects the amount of change in potential due to the leak current, the detection period needs to be sufficiently long to some extent. Therefore, when the power supply scanning line DSS is shared with the power supply scanning line for controlling the light emission period of the pixel circuit, there is a problem that the detection period of the received light amount is shortened.

<2. First embodiment of the present invention>
[Configuration Example of First Embodiment of Display Device to which Present Invention is Applied]
Therefore, even when the power source scanning line DSS is shared with the power source scanning line for controlling the light emission period of the pixel circuit, and the light emission period of the pixel is shortened, a sufficient detection period of the amount of received light can be secured. The example of a structure of the target display apparatus 100 is shown. That is, FIG. 13 shows a first embodiment of a display device to which the present invention is applied.

  In FIG. 13, portions corresponding to those of the display device 50 illustrated in FIG. 6 are denoted by the same reference numerals, and description thereof is omitted as appropriate. The same applies to the drawings after FIG.

  The display device 100 in FIG. 13 is configured in the same manner as the display device 50 in FIG. 6 except that the sensor scanning circuit 101 is different.

[Detailed Configuration Example of Display Unit 53]
FIG. 14 shows a detailed configuration example of the display unit 53 of FIG.

The sensor scanning circuit 101 includes M power scanning lines DSS _{1 to} DSS _M , initialization scanning lines AZ _{1 to} AZ _M , and readout scanning lines RSL _{1 to} RSL _M in the same manner as the sensor scanning circuit 55 of FIG. The entire display unit 53 is connected.

  Similar to the sensor scanning circuit 55, the sensor scanning circuit 101 controls each light receiving circuit 111 in the display unit 53 to receive light and outputs a light detection signal corresponding to the amount of received light to the sensor output detection circuit 56 in a line-sequential manner.

As described above, the sensor scanning circuit 55 of the basic display device 50 initializes the power supply scanning line DSS so that the period in which the potential of the power supply scanning line DSS is set to the high potential V _{DSS_H} becomes the detection period. The potentials of the scanning line AZ and the readout scanning line RSL were controlled. On the other hand, the sensor scanning circuit 101 of the display device 100 has the power scanning line DSS and the initialization scanning line AZ so that the period during which the potential of the power scanning line DSS is set to the low potential V _{DSS_L} is the detection period. , And the potential of the readout scanning line RSL.

  In other words, in the display device 100, the connection method between the display unit 53 and the sensor scanning circuit 101, and the internal configuration of the pixel circuit 21 and the light receiving circuit 61 in the display unit 53 are the same as those of the display device 50 shown in FIG. Is the same. The display device 100 and the display device 50 differ only in the method for controlling the potential of the power supply scanning line DSS.

[Explanation of light detection operation]
The light detection operation by the display device 100 will be described with reference to FIGS.

  FIG. 15 is a drive timing chart showing operations of the light receiving circuit 61 and the sensor output detection circuit 56 of the display device 100.

  FIG. 15 shows changes in the potentials of the power supply scanning line DSS, the initialization scanning line AZ, the readout scanning line RSL, and the reset scanning line RST, and the potential Va at the point a and the potential Vb at the point b, as in FIG. A change in (output voltage Vout) is shown.

Note that one cycle time from time t ₃₁ to time t ₄₁ in FIG. 15 corresponds to one cycle time from time t ₁₁ to time t _{21 in} FIG.

From time t ₃₁ to time t ₃₂ , the initialization scanning line AZ, the readout scanning line RSL, and the reset scanning line RST are each set at a low potential, and the power supply scanning line DSS is initially set at a high potential. State.

At time t ₃₃ from the time t _32, point b initialization processing for initializing the electric potential Vb of the point b is executed. Specifically, at time t ₃₂ , the potentials of the initialization scanning line AZ, the readout scanning line RSL, and the reset scanning line RST are set to a high potential by the sensor scanning circuit 101. As a result, the sensor transistor T _SE , the read transistor T _RS , and the reset transistor Trst are all turned on, and as a result, the potential at the point b (output voltage Vout) is initialized to the reset potential Vrst.

  FIG. 16 shows the state of the light receiving circuit 61 and the sensor output detection circuit 56 during the b-point initialization process.

Since the potential of the power scanning line DSS is the high potential V _{DSS_H,} sensor transistor T _SE is by turning on, the potential Va at point a becomes the V _{DSS_H.} In addition, by reading transistor T _RS and the reset transistor Trst is turned on, the potential Vb at point b becomes the reset potential Vrst. By this b point initialization process, the potential Vb at the point b is initialized to a constant potential (reset potential Vrst) regardless of the previous state.

After completion of the point b initialization, at time _33, the potential of the initialization scan line AZ and the reset scan line RST is returned to a low potential, the sensor transistor T _SE, and the reset transistor Trst is turned off.

Next, between time ₃₄ and time _35, the potential of the power supply scanning line DSS is set to the low potential V _{DSS_L} and light detection processing for detecting light is performed.

  FIG. 17 shows a state of the light receiving circuit 61 and the sensor output detecting circuit 56 during the light detection process.

The sensor transistor _TSE is turned off, and a leak current corresponding to the amount of received light flows to the power supply scanning line DSS. Then, when a leak current corresponding to the amount of received light flows, the potential Va at the point a is _decreased from the potential V _{DSS_H} by the amount of change ΔV in Expression (2). That is, the potential Va at the point a becomes (V _{DSS_H −ΔV} ) due to the leakage current flowing.

When the leak current does not flow, a current flows from the output transistor T _OUT to the point b in accordance with the potential Va = V _{DSS_H} at the point a, and the potential Vb at the point b also rises as shown by a solid line in FIG.

However, as indicated by the dotted line in FIG. 15, the potential Va at the point a decreases by a change ΔV due to the flow of the leakage current. Therefore, the increase in the potential Vb at the point b also depends on the magnitude of the leakage current. And become gradual. Here, when the threshold voltage of the output transistor T _OUT is expressed as Vth _OUT , the potential Vb at the point b is expressed as (V _DSS — _{H −ΔV} ) −Vth _OUT .

The voltage detection unit 56a detects the potential Vb at the point b as the output voltage Vout at a predetermined timing from time ₃₄ to time ₃₅ when the potential of the power supply scanning line DSS is set to the low potential V _{DSS_L} .

The detection period _ends when the potential of the power supply scanning line DSS is set to the high potential V _{DSS_H} and the potential of the readout scanning line RSL is set to the low potential V _{RSL_L} at time ₃₅ .

In the period from time ₃₆ to time ₃₇ after time ₃₅ , an ab point initialization process for initializing the potential Va at the point a and the potential Vb at the point b is performed so as not to affect other operations until the next detection. Executed. Specifically, between time ₃₆ and time ₃₇ , the potentials of the initialization scanning line AZ and the reset scanning line RST are set to a high potential.

  FIG. 18 shows a state of the light receiving circuit 61 and the sensor output detection circuit 56 during the ab point initialization process.

Initialization scan line AZ is changed to the high potential V _{AZ_H,} by sensor transistor T _SE is turned on, the potential Va at point a returns to the power scanning line DSS potential and the same potential V _{DSS_H.} Further, the potential of the reset scanning line RST changes to the high potential V _{RST_H} and the reset transistor Trst is turned on, whereby the potential Vb at the point b becomes the reset potential Vrst. By this ab point initialization processing, initialization of the sensor output detection circuit 56 in the light receiving circuit 61 in the next row is completed.

  The light detection operation of the display device 100 is performed as described above. The comparison unit 57 compares the luminance values of the pixels supplied as the output voltage Vout from the sensor output detection circuit 56 with each other. Thereby, the uniformity of light emission luminance can be improved. The comparison unit 57 compares the luminance value of each pixel supplied as the output voltage Vout with the luminance value acquired in the initial state. Thereby, deterioration with time can be corrected.

In the display device 100, the amount of change in potential due to leakage current is detected during the period when the potential of the power supply scanning line DSS is set to the low potential V _{DSS_L} . Therefore, even when the period for setting the potential of the power supply scanning line to a high potential is shortened, a sufficient period for detecting the amount of received light can be secured.

  Therefore, even when the power source scanning line DSS is shared with the power source scanning line for controlling the light emission period of the pixel circuit and the light emission period of the pixel is shortened, a sufficient detection period of the received light amount can be ensured.

  The light detection process performed by the display device 50, which is the basis of the present invention, is referred to as a plus leak mode because the potential change ΔV due to the leak current is added to the potential before detection. On the other hand, the light detection processing by the display device 100 according to the first embodiment of the present invention subtracts the potential change ΔV due to the leakage current from the potential before detection. This can be called a leak mode.

On the plus leakage mode, the sensor transistor T _SE is the potential of the power scanning line DSS when on is set to the low potential V _{DSS_L,} sensor transistor T _SE is the potential of the power scanning line DSS in the off and the high potential V _{DSS_H} Is done. Conversely, the negative leak mode, the sensor transistor T _SE is the potential of the power scanning line DSS in the off set to the low potential V _{DSS_L,} sensor transistor T _SE is the potential of the power scanning line DSS is a high potential when the ON V _{DSS_H} .

<3. Second embodiment of the present invention>
Next, a second embodiment of a display device to which the present invention is applied will be described.

  In the light detection process in the plus leak mode of the basic display device 50 described above, there is a problem that the detection period of the received light amount is shortened when the light emission period of the pixel is shortened. On the contrary, in the light detection process in the minus leak mode of the display device 100, there is a problem that the detection period of the received light amount is shortened when the light emission period of the pixel is long.

  Therefore, in the second embodiment of the display device to which the present invention is applied, a configuration is adopted in which the light detection processing in the plus leak mode and the minus leak mode is switched according to the light emission period of the pixel.

[Configuration Example of Second Embodiment of Display Device to which Present Invention is Applied]
FIG. 19 shows a configuration example of the second embodiment of the display device to which the present invention is applied.

  19 includes a video processing unit 51, a video signal output circuit 52, a writing scanning circuit 54, a sensor output detection circuit 56, a display unit 53, a sensor operation setting unit 201, a sensor scanning circuit 202, and a comparison unit 203. Composed.

  That is, the display device 200 of FIG. 19 is provided with a sensor scanning circuit 202 and a comparison unit 203 instead of the sensor scanning circuit 101 and the comparison unit 57 as compared with the display device 100 shown in FIG. A part 201 is added.

  The sensor operation setting unit 201 is supplied with light emission period information indicating the light emission period of the pixel from a control unit or an operation setting unit (not shown) of the display device 200. For example, a Duty ratio, which is a ratio of light emission periods in one field period (1F), is supplied to the sensor operation setting unit 201 as light emission period information. The sensor operation setting unit 201 acquires the supplied light emission period information, and controls the sensor scanning circuit 202 to operate in the plus leak mode as mode 1 when the duty ratio is 50% or more. On the other hand, when the duty ratio is less than 50%, the sensor operation setting unit 201 controls the sensor scanning circuit 202 to operate in the minus leak mode as the mode 2. Specifically, the sensor operation setting unit 201 supplies a mode switching signal indicating mode 1 or mode 2 to the sensor scanning circuit 202 and the comparison unit 203 depending on whether the duty ratio is 50% or more.

  Further, since the magnitude of the output voltage Vout supplied from the sensor output detection circuit 56 changes depending on whether it is the plus leak mode or the minus leak mode, the current mode is also applied to the comparison unit 203 that performs correction processing and the like. A mode switching signal is supplied as a signal representing.

  The sensor scanning circuit 202 switches the control of the potential of the power supply scanning line DSS according to the mode switching signal from the sensor operation setting unit 201. Specifically, when a mode switching signal representing mode 1 (plus leak mode) is supplied, the sensor scanning circuit 202 controls the potential of the power supply scanning line DSS so that the light detection process is in the plus leak mode. That is, the sensor scanning circuit 202 executes the control described with reference to FIGS.

  On the other hand, when a mode switching signal representing mode 2 (minus leak mode) is supplied, the sensor scanning circuit 202 controls the potential of the power supply scanning line DSS so that the light detection process is in the minus leak mode. That is, the sensor scanning circuit 202 executes the control described with reference to FIGS.

  The comparison unit 203 recognizes the current mode based on the mode switching signal, and performs a temporal deterioration correction process for calculating a correction amount compared with the luminance value of each pixel in the initial state, and makes the light emission luminance of each pixel uniform over the entire screen. A uniform correction process for calculating the correction amount is executed. Note that the temporal deterioration correction process may be performed only in one of the mode 1 and the mode 2.

[Light detection mode switching process]
FIG. 20 shows a flowchart of the mode switching process by the display device 200. This process is started when light emission period information is supplied from, for example, a control unit (not shown) of the display device 200.

  In step S1, the sensor operation setting unit 201 acquires light emission period information supplied from a control unit or the like.

  In step S2, the sensor operation setting unit 201 determines whether the duty ratio is 50% or more based on the supplied light emission period information. If it is determined in step S2 that the duty ratio is 50% or more, the process proceeds to step S3, and the sensor operation setting unit 201 transmits a mode switching signal indicating mode 1 (plus leak mode) to the sensor scanning circuit 202. And supplied to the comparison unit 203.

  The sensor scanning circuit 202 to which the mode switching signal representing the mode 1 is supplied controls the potential of the power supply scanning line DSS so that the light detection process is in the plus leak mode. That is, the sensor scanning circuit 202 executes the control described with reference to FIGS. The comparison unit 203 calculates a correction amount for correcting the uniformity of light emission luminance and / or deterioration with time in the plus leak mode, and supplies the correction amount to the video processing unit 51.

  On the other hand, if it is determined in step S2 that the duty ratio is less than 50%, the process proceeds to step S4, and the sensor operation setting unit 201 transmits a mode switching signal indicating mode 2 (minus leak mode) to the sensor scanning. This is supplied to the circuit 202 and the comparison unit 203.

  The sensor scanning circuit 202 supplied with the mode switching signal representing the mode 2 controls the potential of the power supply scanning line DSS so that the light detection process is in the minus leak mode. That is, the sensor scanning circuit 202 executes the control described with reference to FIGS. The comparison unit 203 calculates a correction amount for correcting the uniformity of light emission luminance and / or deterioration with time in the minus leak mode, and supplies the correction amount to the video processing unit 51.

  After the process of step S3 or step S4, the mode switching process ends.

  By executing the above mode switching process, the display device 200 can switch between the plus leak mode and the minus leak mode according to the length of the light emission period of the pixel. Accordingly, it is possible to always ensure a sufficient detection period of the received light amount without depending on the light emission period of the pixel.

<4. Third Embodiment of the Present Invention>
Next, a third embodiment of a display device to which the present invention is applied, which is an embodiment in which the power supply scanning line DSS is shared with the power supply scanning line for controlling the light emission period of the pixel circuit, will be described.

[Detailed Configuration of Pixel Circuit 303]
FIG. 21 is a block diagram illustrating a configuration example of the third embodiment of the display device.

  A display device 300 in FIG. 21 includes a video signal output circuit 52, a display unit 53, a writing scanning circuit 54, a sensor output detection circuit 56, a power supply scanning circuit 301, and a sensor scanning circuit 302.

  In FIG. 21, the image processing unit 51 and the comparison unit 57 similar to those in the first embodiment, or the image processing unit 51, the sensor operation setting unit 201, and the comparison unit 203 similar to those in the second embodiment are described. The illustration is omitted.

  FIG. 21 shows the configuration of one pixel circuit 303 and the light receiving circuit 61 among the N × M pixel circuits 303 and the light receiving circuits 61 arranged in a matrix of the display unit 53.

Power scanning circuit 301, the power scanning line DSL, by supplying switching the potential V _{DSL_L} potential V _{DSL_H} and a low potential of high potential, for controlling the emission period of the pixel circuit 303.

Here, power scanning line DSL is also connected to the drain of the sensor transistor T _SE and the output transistor T _OUT of the light receiving circuit 61. Therefore, the power supply scanning line DSL is shared with the power supply scanning line DSS of the first and second embodiments. On the other hand, the power supply scanning line DSL corresponding to the power supply scanning line DSS of the first and second embodiments is not connected to the sensor scanning circuit 302. Therefore, in the sensor scanning circuit 302, the function of controlling the potential V _{DSS_H} or V _{DSS_L} is omitted, and the rest is the same as the sensor scanning circuit 101 or 202.

The pixel circuit 303 includes a sampling transistor T _WS , a drive transistor T _DRV , a storage capacitor C 1, and an organic EL element ELP. A detailed configuration of the pixel circuit 303 will be described later with reference to FIG.

  As described above, in the third embodiment, the power supply scanning line DSS of the first and second embodiments is shared with the power supply scanning line DSL that controls the light emission period of the pixel circuit 303.

[Detailed Configuration Example of Pixel Circuit 303]

  Next, a detailed configuration of the pixel circuit 303 will be described with reference to FIG.

The pixel circuit 303 includes a sampling transistor T _WS , a drive transistor T _DRV , a storage capacitor C 1, and an organic EL element ELP.

Here, if the pixel circuit 303 is the pixel circuit 303 _{m, n in} the m-th row and the n-th column (n = 1, 2,..., N, m = 1, 2,..., M). The writing scanning line WSL connected to the pixel circuit 303 is the writing scanning line WSL _m . Moreover, the power scanning line DSL for the pixel circuits 303 m, _n are power scanning line DSL _m, the video signal line DTL is the video signal line DTL _n.

The gate of the sampling transistor T _WS is connected to the writing scanning line WSL, a drain of the sampling transistor T _WS is is connected to the video signal line DTL, the source is connected to the gate g of the drive transistor T _DRV.

One of the source s and the drain d of the driving transistor _TDRV is connected to the anode of the organic EL element ELP, and the other is connected to the power source scanning line DSL. The storage capacitor C1 is connected to the gate g of the drive transistor _TDRV and the anode of the organic EL element ELP. The cathode of the organic EL element ELP is connected to the cathode potential Vcat which is the ground potential.

The sampling transistor T _WS and the drive transistor T _DRV are both N-channel transistors, and can be made of amorphous silicon that can be made at a lower cost than low-temperature polysilicon, thereby lowering the manufacturing cost of the pixel circuit. Can do.

In the pixel circuit 303 configured as described above, the sampling transistor _TWS is turned on (conductive) in response to a control signal from the writing scanning line WSL, and the signal potential Vsig corresponding to the gray level via the video signal line DTL. The video signal is sampled. The holding capacitor C1 accumulates and holds charges supplied from the video signal output circuit 52 via the video signal line DTL. The drive transistor T _DRV receives a current from the power supply scanning line DSL at the high potential V _{DSL_H} and causes the drive current Ids to flow to the organic EL element ELP according to the signal potential Vsig held in the holding capacitor C1 (supply). To do). When a predetermined drive current Ids flows through the organic EL element ELP, the pixel circuit 303 emits light.

The pixel circuit 303 has a threshold correction function. The threshold value correcting function is a function of holding a voltage corresponding to the threshold voltage Vth of the driving transistor T _{DRV in} the holding capacitor C1, and thereby the threshold value of the driving transistor T _DRV causing the variation for each pixel of the display device 300. The influence of the voltage Vth can be canceled.

Further, the pixel circuit 303 has a mobility correction function in addition to the above-described threshold correction function. A mobility correction function, when holding the signal potential Vsig into the storage capacitor C1, a function of adding the correction for the mobility μ of the driving transistor T _DRV to the signal potential Vsig.

Further, the pixel circuit 303 has a bootstrap function. Bootstrap The function is a function that links the gate potential Vg to the variation of the source potential Vs of the driving transistor T _DRV, thereby, the driving transistor T _DRV can be maintained gate-source voltage Vgs at a constant.

  The threshold value correction function, mobility correction function, and bootstrap function will also be described with reference to FIGS. 27, 31, and 32, which will be described later.

[Description of Operation of Pixel Circuit 303]
FIG. 23 is a timing chart for explaining the operation of the pixel circuit 303.

FIG. 23 shows potential changes of the write scanning line WSL, the power supply scanning line DSL, and the video signal line DTL with respect to the same time axis, and corresponding changes in the gate potential Vg and source potential Vs of the driving transistor _TDRV . .

In FIG. 23, a period until time t ₅₁ is a light emission period T ₁ during which light emission is performed in the previous horizontal period (1H).

From time t ₅₁ to time t ₅₄ when the light emission period T ₁ ends, a threshold correction preparation period T _{2 in} which the gate potential Vg and the source potential Vs of the drive transistor T _DRV are initialized to prepare for the threshold voltage correction operation. is there.

In the threshold value correction preparation period T _2, at time t _51, the power supply scanning circuit 301 switches the potential of the power scanning line DSL from the high potential V _{DSL_H} to the low potential V _{DSL_L.} Then, at time t _52, the video signal output circuit 52 switches the potential of the video signal line DTL from the signal potential Vsig to the reference potential Vofs. Next, at time t ₅₃ , the write scanning circuit 54 switches the potential of the write scanning line WSL to the high potential V _{WSL_H} to turn on the sampling transistor T _WS . Accordingly, the gate potential Vg of the driving transistor T _DRV is reset to the reference potential Vofs, and the source potential Vs is reset to the low potential V _{DSL_L} of the video signal line DTL.

From the time t ₅₄ to time t ₅₅ is a threshold correction period T ₃ to perform the threshold value correction operation. In the threshold correction period T ₃ , at time t ₅₄ , the power supply scanning circuit 301 switches the potential of the power supply scanning line DSL to the high potential V _{DSL_H} . As a result, a voltage corresponding to the threshold voltage Vth is written to the storage capacitor C1.

In the writing + mobility correction preparation period T ₄ from time t ₅₅ to time t ₅₇ , the potential of the writing scanning line WSL is once switched from the high potential V _{WSL_H} to the low potential V _{WSL_L} . At time t ₅₆ the previous time t _57, the video signal output circuit 52 is switched to the signal potential Vsig corresponding to the gradation potential of the video signal line DTL from the reference potential Vofs.

Then, in the writing + mobility correction period T ₅ from time t ₅₇ to time t ₅₈ , video signal writing and mobility correction operation are performed. That is, from time t ₅₇ to time t _58, the potential of the write scanning line WSL is set to the high potential V _{WSL_H} , whereby the storage capacitor C1 is added in such a manner that the signal potential Vsig of the video signal is added to the threshold voltage Vth. Is written to. In addition, the mobility correction voltage ΔV _μ is subtracted from the voltage held in the holding capacitor C1.

In writing + mobility correction period T ₅ after the end of the time t _58, the potential of the write scanning line WSL is set to the low potential V _{WSL_L,} later, as a light-emitting period T _6, the organic light-emitting luminance corresponding to the signal voltage Vsig The EL element ELP emits light. Since the signal voltage Vsig is adjusted by the voltage corresponding to the threshold voltage Vth and the mobility correction voltage ΔV _μ , the light emission luminance of the organic EL element ELP is the threshold voltage Vth or mobility μ of the drive transistor T _DRV . Unaffected by variation.

The light emitting period beginning bootstrap operation of T ₆ is performed, while maintaining the gate-source voltage _Vgs = Vsig + Vth-ΔV μ of the driving transistor T _DRV constant, the gate potential Vg and the source potential Vs of the driving transistor T _DRV Rises.

At time t ₅₉ after a predetermined time from the time t _58, the potential of the video signal line DTL is dropped from the signal potential Vsig to the reference potential Vofs. 23, the period from time t ₅₂ to time t ₅₉ corresponds to the horizontal period (IH).

As described above, in the pixel circuit 303, the organic EL element ELP can emit light without being affected by variations in the threshold voltage Vth and mobility μ of the drive transistor _TDRV .

[Detailed Operation of Pixel Circuit 303]
The operation of the pixel circuit 303 will be described in more detail with reference to FIGS.

FIG. 24 shows a state of the pixel circuit 303 in the light emission period T ₁ .

In the light emission period T ₁ , the sampling transistor T _WS is off (the potential of the writing scanning line WSL is low), the potential of the power source scanning line DSL is high potential V _{DSL_H} , and the driving transistor T _{DRV reduces the} driving current Ids. Supplying to the organic EL element ELP. At this time, since the drive transistor T _DRV is set to operate in the saturation region, the drive current Ids flowing through the organic EL element ELP is expressed by the equation (1) according to the gate-source voltage Vgs of the drive transistor T _DRV. Takes a value that is

Then, at the first time t ₅₁ of the threshold value correction preparation period T _2, as shown in FIG. 25, the power supply scanning circuit 301 switches the potential of the power scanning line DSL from the high potential V _{DSL_H} to the low potential V _{DSL_L.} If the potential V _{DSL_L} this time power scanning line DSL is smaller than the sum of the threshold voltage Vthel and the cathode potential Vcat of the organic EL element _{ELP (V DSL_L <Vthel + Vcat} ), the organic EL element ELP is quenched, the power of the driving transistor T _DRV The side connected to the scanning line DSL is the source s. Further, the anode of the organic EL element ELP is charged to the potential V _{DSL_L} .

Next, as shown in FIG. 26, at time t _52, after the video signal output circuit 52 has a potential of the video signal line DTL to the reference potential Vofs, at time t _53, the writing scanning circuit 54, the write scanning line WSL _Is switched to the high potential V _{WSL_H} . As a result, the gate potential Vg of the drive transistor T _DRV becomes Vofs, and the gate-source voltage Vgs takes a value of Vofs−V _{DSL_L} . Here, the gate-source voltage Vgs of the driving transistor T _DRV (Vofs−V _{DSL —L} ) is larger than the threshold voltage Vth because the threshold correction operation is performed in the next threshold correction period T ₃ (Vofs−V _{DSL_L} > Vth). In other words, the potentials Vofs and _{VDSL_L} are set so as to satisfy the condition of (Vofs− _{VDSL_L} > Vth).

Then, at the first time t ₅₄ the threshold value correction period T _3, as shown in FIG. 27, the power supply scanning circuit 301 switches the potential of the power scanning line DSL from the low potential V _{DSL_L} to the high potential V _{DSL_H.} Then, the side connected to the anode of the organic EL element ELP of the driving transistor T _DRV becomes the source s, and a current flows as shown by a one-dot chain line in FIG.

Here, the organic EL element ELP can be equivalently expressed by _a diode ELP _a and an organic EL capacitor ELP _b of a parasitic capacitor Cel. Under the condition that the leakage current of the organic EL element ELP is much smaller than the current flowing through the drive transistor T _DRV (Vel ≦ Vcat + Vthel is satisfied), the current flowing through the drive transistor T _DRV causes the holding capacitor C1 and the organic EL capacitor ELP _b to flow. Used to charge. As shown in FIG. 28, the anode potential Vel of the organic EL element ELP (the source potential Vs of the drive transistor T _DRV ) rises according to the current flowing through the drive transistor T _DRV . After a predetermined time has elapsed, the gate-source voltage Vgs of the drive transistor _TDRV takes a value Vth. At this time, the anode potential Vel of the organic EL element ELP is (Vofs−Vth). The anode potential Vel is equal to or lower than the sum of the threshold voltage Vthel and the cathode potential Vcat of the organic EL element ELP (Vel = (Vofs−Vth) ≦ (Vcat + Vthel)).

Then, at time t _55, the potential of the write scanning line WSL are switched from the high potential V _{WSL_H} to the low potential V _{WSL_L,} as shown in FIG. 29, the sampling transistor T _WS is off to the threshold value correction operation (the threshold correction period T ₃ ) is completed.

At time t ₅₆ a write + mobility correction preparation period T _4, the video signal output circuit 52, the potential of the video signal line DTL is, from the reference potential Vofs, is switched to the signal potential Vsig corresponding to the gradation (Fig. 29) . Thereafter, the writing + mobility correction period T ₅ is entered, and as shown in FIG. 30, the sampling transistor T _WS is turned on by setting the potential of the writing scanning line WSL to the high potential V _{WSL_H} at time t ₅₇ . Thus, video signal writing and mobility correction operations are performed. The gate potential Vg of the driving transistor T _DRV becomes the signal potential Vsig because the sampling transistor T _WS is turned on, but since the current from the power supply scanning line DSL flows, the source potential Vs of the driving transistor T _DRV is changed with time. It rises.

The threshold correction operation of the drive transistor T _DRV has already been completed. Therefore, the term (Vgs−Vth) ^{2 on} the right side of the equation (1) is (Vgs−Vth) ² = {(Vsig− (Vofs−Vth)) − Vth} ² = (Vsig−Vofs) ² , There is no influence of the term of voltage Vth. Therefore, the current Ids supplied by the driving transistor T _DRV reflects the mobility μ. Specifically, as shown in FIG. 31, when the mobility μ is large, the current Ids flowing through the drive transistor T _DRV increases and the source potential Vs rises quickly. On the other hand, when the mobility μ is small, the current Ids flowing through the drive transistor T _DRV is small, and the increase in the source potential Vs is slow. In other words, when the mobility μ is large after a certain time has elapsed, the increase amount ΔV _μ (potential correction value) of the source potential Vs of the drive transistor T _DRV is large, and when the mobility μ is small, The increase amount ΔV _μ (potential correction value) of the source potential Vs of the drive transistor T _DRV becomes small. As a result, the variation in the gate-source voltage Vgs of the drive transistor T _DRV of each pixel circuit 303 is reduced reflecting the mobility μ, and the gate-source voltage Vgs of each pixel circuit 303 after the lapse of a certain time is shifted. The voltage is completely corrected for variations in degree μ.

At time t ₅₈ , the potential of the writing scan line WSL is set to the low potential V _{WSL_L} , so that the sampling transistor T _WS is turned off, the writing + mobility correction period T ₅ ends, and the light emission period T ₆ ( FIG. 32).

In the emission period T _6, the gate-source voltage Vgs of the driving transistor T _DRV is constant, the driving transistor T _DRV supplies a constant current Ids' to the organic EL element ELP. The anode potential Vel of the organic EL element ELP rises to a voltage Vx where a constant current Ids ′ flows through the organic EL element ELP, and the organic EL element ELP emits light. When the source potential Vs of the driving transistor T _DRV rises by the bootstrap function of the storage capacitor C1, also rises in conjunction with the gate potential Vg of the driving transistor T _DRV.

Due to the IV characteristics of the organic EL element ELP, as the light emission time becomes longer, the potential at the point Bx shown in FIG. 32 changes with time (deteriorates with time). However, since the gate-source voltage Vgs of the drive transistor T _DRV is maintained at a constant value, the current flowing through the organic EL element ELP does not change. Therefore, even if the organic EL element ELP deteriorates with time due to the IV characteristics, the constant current Ids ′ continues to flow, so that the luminance of the organic EL element ELP does not change.

  As described above, in the display device 300 of FIG. 21 including the pixel circuit 303, the difference between the threshold voltage Vth and the mobility μ for each pixel circuit 303 can be corrected by the threshold correction function and the mobility correction function. In addition, it is possible to correct the temporal change (deterioration) of the organic EL element ELP.

  As a result, the display device 300 using the pixel circuit 303 can obtain higher image quality than when the pixel circuit 21 is used.

[Explanation of light detection operation]
FIG. 33 is a drive timing chart showing the operations of the light receiving circuit 61 and the sensor output detection circuit 56 of the display device 300.

  That is, FIG. 33 shows changes in the potentials of the power supply scanning line DSL and the write scanning line WSL of FIG. 23, the control lines in the light receiving circuit 61 and the sensor output detection circuit 56 shown in FIG. The change in potential is shown.

  33, the initialization scanning line AZ, the reading scanning line RSL, the reset scanning line RST, the potential Va at the point a, and the potential Vb at the point b are changed with respect to changes in the potentials of the power supply scanning line DSL and the writing scanning line WSL. The changes are basically the same as the corresponding ones in FIG.

However, FIG. 33 is different from FIG. 9 in that the detection period is not a period in which the potential of the power supply scanning line DSL is set to the high potential V _{DSS_H} . In the third embodiment, the detection period is terminated at time t ₇₈ which starts from the time t ₇₇ to the write + mobility correction period T ₅ is completed, the potential of the read scanning lines RSL is set to the low potential V _{RSL_L} To do.

The potential Va at the point a increases as the amount of received light increases. When a current flows from the output transistor T _OUT to the point b as the potential Va at the point a increases, the potential Vb at the point b also increases. The voltage detection unit 56a detects the potential Vb at the point b as the output voltage Vout at a predetermined timing before performing the next ab point initialization process.

  Therefore, even when the power supply scanning line DSS is shared with the power supply scanning line DSL that controls the light emission period of the pixel circuit, light detection in the plus leak mode is possible.

  Although not shown, the sensor scanning circuit 302 regards the potential change of the power supply scanning line DSS in FIG. 15 as the potential change of the power supply scanning line DSL, and initializes the scanning line AZ, the readout scanning line RSL, and the reset scanning line. It is also possible to control the potential of RST as shown in FIG. That is, the sensor scanning circuit 302 can detect light in the minus leak mode even when the power scanning line DSS is shared with the power scanning line DSL that controls the light emission period of the pixel circuit.

  Therefore, also in the third embodiment, as in the first embodiment, a sufficient detection period of the amount of received light can be ensured even when the light emission period of the pixel is shortened.

  Further, as the third embodiment, when the portion other than the portion shown in FIG. 21 is configured similarly to the second embodiment, the plus leak mode is selected according to the length of the light emission period of the pixel. And minus leak mode can be switched. Accordingly, it is possible to always ensure a sufficient detection period of the received light amount without depending on the light emission period of the pixel.

  Furthermore, in the third embodiment, since the power supply scanning line DSS of the first and second embodiments is shared with the power supply scanning line DSL for controlling the light emission period of the pixel circuit 303, the number of wirings The manufacturing cost can be reduced.

The third embodiment described above is an example in which the power supply scanning line DSS of the first and second embodiments is shared by the power supply scanning line DSL of the pixel circuit 303. The same applies to the case where the power supply scanning line DSL of the pixel circuit 303 is shared. That is, power scanning circuit 301 is omitted, the connected power scanning line DSS and sensor scanning circuit 302 is capable of similar control is connected to the driving transistor T _DRV of the pixel circuit 303.

<5. Other examples of the third embodiment of the present invention>
FIG. 34 is a block diagram showing another example in which the power supply scanning line DSS is shared with a control line for controlling the light emission period of the pixel circuit.

  The display device 300 of FIG. 34 employs a pixel circuit 21 ′ obtained by modifying the pixel circuit 21 of the first and second embodiments as the pixel circuit of the display unit 53.

Similar to the pixel circuit 21, the pixel circuit 21 ′ includes an n-channel TFT sampling transistor T _WS , a storage capacitor C1, a p-channel TFT drive transistor T _DRV , and an organic EL element ELP, and a light emission control transistor T _DS. Have been added.

Emission control transistor T _DS is provided between the power source Vcc and driving transistor T _DRV, in accordance with the potential of the power scanning line DSL, serves as a switch. That is, when the potential of the power supply scanning line DSL is the high potential V _{DSL_H} , the light emission control transistor T _DS is turned on, and a current flows through the organic EL element ELP. On the other hand, when the potential of the power scanning line DSL is the low potential V _{DSL_L,} the light emission control transistor T _DS is turned off, no current flows through the organic EL element ELP. Therefore, the light emission control transistor T _DS controls the light emission period of the organic EL element ELP emits light.

Power scanning circuit 301, the power scanning line DSL, a high potential by supplying switching the potential V _{DSL_L} potential V _{DSL_H} and low potential, turning on or off the light emission control transistor T _DS.

The power scanning line DSL is connected to the drain of the sensor transistor T _SE of the light receiving circuit 61, with the drain of the output transistor T _OUT. Thus, in Figure 34, power scanning line DSL for controlling on and off of the light emission control transistor T _DS, are common to the first and second embodiments power scanning line DSS for.

[Explanation of light detection operation]
FIG. 35 is a drive timing chart showing operations of light receiving circuit 61 and sensor output detection circuit 56 of display device 300 shown in FIG.

  The change in potential of the write scan line WSL is the same as the change in potential of the write scan line WSL in the pixel circuit 21 shown in FIG.

  34, the initialization scanning line AZ, the reading scanning line RSL, the reset scanning line RST, the potential Va at the point a, and the potential Vb at the point b are changed with respect to changes in the potentials of the power supply scanning line DSL and the writing scanning line WSL. The change is basically the same as each corresponding one in FIG.

However, FIG. 34 is different only in that the detection period is different from the period from time t ₉₆ to time t ₉₈ when the potential of the power supply scanning line DSL is set to the high potential V _{DSS_H} . In FIG. 34, the detection period starts at time t ₉₆ and ends at time t ₉₇ before the time t _{98 when} the potential of the read scanning line RSL is set to the low potential V _{RSL_L} .

The potential Va at the point a increases as the amount of received light increases. When a current flows from the output transistor T _OUT to the point b as the potential Va at the point a increases, the potential Vb at the point b also increases. The voltage detection unit 56a detects the potential Vb at the point b as the output voltage Vout at a predetermined timing before performing the ab point initialization process.

  Therefore, even when the power supply scanning line DSS is shared with the power supply scanning line DSL that controls the light emission period of the pixel circuit, light detection in the plus leak mode is possible.

  Although not shown, the sensor scanning circuit 302 regards the potential change of the power supply scanning line DSS in FIG. 15 as the potential change of the power supply scanning line DSL, and initializes the scanning line AZ, the readout scanning line RSL, and the reset scanning line. It is also possible to control the potential of RST as shown in FIG. That is, light detection in the minus leak mode is also possible.

  Therefore, also in the third embodiment shown in FIG. 34, as in the first embodiment, a sufficient detection period of the amount of received light is ensured even when the light emission period of the pixel is shortened. Can do.

  Further, as the third embodiment, when the portion other than the portion shown in FIG. 34 is configured in the same manner as the second embodiment, the plus leak mode is selected according to the length of the light emission period of the pixel. And minus leak mode can be switched. Accordingly, it is possible to always ensure a sufficient detection period of the received light amount without depending on the light emission period of the pixel.

  In the first to third embodiments described above, the configuration of the pixel circuit is not limited to the above example, and various other configurations can be employed. That is, the present invention is a display device that employs a pixel circuit that performs a light emission operation regardless of the pixel circuit configuration, and can be widely applied to display devices that include a light receiving circuit that detects the amount of light separately from the pixel circuit.

  The embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

21, 21 ′ pixel circuit, 56a voltage detection unit, 57 comparison unit, 100 display device, 101 sensor scanning circuit, T _SE sensor transistor, T _AMP amplification transistor, Cse holding capacitor, T _OUT output transistor, 200 display device, 201 sensor Operation setting unit, 202 sensor scanning circuit, 203 comparison unit, 300 display device, 301 power supply scanning circuit, 303 pixel circuit

Claims (7)

A pixel circuit that emits light by an internal light emitting element according to a video signal, and a display unit that includes a plurality of light receiving circuits that detect light arranged in a matrix,
The light receiving circuit is
A sensor transistor that functions as a switch element and functions as an optical sensor that passes a current corresponding to the detected amount of light in an off state;
A holding capacitor connected to the sensor transistor and holding a predetermined potential;
An output transistor that outputs a photodetection signal corresponding to the changed potential held by the holding capacitor by changing in a direction that the potential held in the holding capacitor in advance decreases due to a current that flows when the sensor transistor is off. And a display device. Power supply potential control means for controlling the potential of a connection line connected to the storage capacitor via the sensor transistor;
The power supply potential control means sets the potential of the connection line to a first potential when the sensor transistor is off, and sets the potential of the connection line higher than the first potential when the sensor transistor is on. The display device according to claim 1, wherein the display device is set to a second potential. The power supply potential control means sets the potential of the connection line to the first potential when the sensor transistor is on, and sets the potential of the connection line to the second potential when the sensor transistor is off. By setting, the first mode for changing the potential held in the holding capacitor by the current that flows when the sensor transistor is off, and the potential of the connection line when the sensor transistor is off is changed. The first potential is set, and the potential of the connection line is set to a second potential that is higher than the first potential when the sensor transistor is on, and the potential held in the storage capacitor is decreased. The display device according to claim 2, wherein the second mode for changing the direction is switched according to the length of the light emission period of the pixel circuit. The display device according to claim 2, wherein the connection line is also a control line for controlling a light emission period of the pixel circuit, and a light emission period of the pixel circuit is controlled by a period of the second potential. The display device according to claim 1, further comprising detection means for detecting an amount of change in potential due to the light detection signal. The light receiving circuit is arranged in one-to-one correspondence with the pixel circuit,
The display device according to claim 1, further comprising a calculation unit that calculates a correction amount of a luminance value of the pixel circuit based on a change amount of the potential detected by the detection unit. The light receiving circuit of the display device including a display unit in which a plurality of pixel circuits that emit light by an internal light emitting element according to a video signal and a light receiving circuit that detects light is arranged in a matrix function as a switch element and is turned off. A sensor transistor that functions as an optical sensor that passes a current according to the detected amount of light in the state, a storage capacitor connected to the sensor transistor, and an output transistor connected to the storage capacitor,
The holding capacitor holds a predetermined potential by a current that flows when the sensor transistor is on,
The output transistor changes in a direction in which the potential held in the storage capacitor decreases due to a current flowing when the sensor transistor is off, and generates a light detection signal corresponding to the changed potential held by the storage capacitor. Output method of light detection of display device.

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