JP2011151057A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a silicon carbide thin film from being lost or peeling with respect to a method of manufacturing a semiconductor device by enhancing mechanical strength of the silicon carbide thin film. <P>SOLUTION: The method of manufacturing the semiconductor device includes the processes of: forming the silicon carbide thin film using a material, which has a functional group having a -CH<SB>2</SB>- bond combined cyclically with Si and including double bonds, on a porous low-dielectric-constant insulating film; forming a hard mask by etching the silicon carbide thin film into a predetermined pattern; and forming at least one of a groove for wiring formation and a via hole by etching the low-dielectric-constant insulating film using the hard mask as an etching mask. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a method of manufacturing a semiconductor device, for example, to a multilayer wiring formation process of a highly integrated semiconductor device using a low-k film including a logic semiconductor integrated circuit device of a 32 nm node or later. .

In recent years, with the miniaturization and speeding up of semiconductor integrated circuit devices, a damascene method using copper as a conductive material for wiring has been widely used for forming multilayer wiring. At the same time, the effective dielectric constant of the interlayer insulating film is required to be reduced, and a low-k film made of SiCO has been widely used.

As such a low-k film, it has been proposed to form a film having a low dielectric constant by introducing a raw material having an annular structure into a CVD apparatus and forming holes using the structure. (For example, refer to Patent Document 1).

Here, a conventional buried wiring structure will be described with reference to FIG. FIG. 26 is a conceptual cross-sectional view of a conventional buried wiring. Here, the explanation is made as a buried wiring by a dual damascene process in which a Cu via 85 and a Cu buried wiring 86 are collectively formed through a barrier metal film 84. To do. The interlayer insulating film is composed of a SiCN-based Cu diffusion preventing film 81 / a porous SiCO-based porous Low-k film 82 / a high-density SiCO-based Low-k cap film 83, and the Cu diffusion preventing film 81 is a porous Low-k film. Also serves as a dry etching stop layer 82.

However, when the process of etching the wiring trench with a resist mask is employed, the side wall of the porous Low-k film 82 is altered when the resist is removed by ashing, and the effective dielectric constant of the interlayer insulating film increases. Has occurred.

In order to solve such a problem, it has been proposed to transfer a resist pattern to SiC (silicon carbide) and to etch a low-k film with a SiC hard mask (see, for example, Patent Document 2). In this proposal, the side wall of the low-k film is not exposed to the ashing of the resist, so that there is no possibility that the low-k film is altered.

Further, by using a SiC hard mask having a lower etching rate than that of the low-k material, it is possible to suppress a change in the pattern shape of the hard mask during the low-k etching, so that a good etching shape can be obtained. .

International Publication WO2003 / 019645 JP 2009-004665 A

In recent years, low-k materials have a method of increasing the number of SiCH ₃ bonds in the film in order to lower the dielectric constant. Therefore, SiC (silicon carbide) is used as a hard mask as the dielectric constant of low-k materials decreases. There is a problem that it is difficult to function.

That is, when the SiCH ₃ bond is increased, the C / Si composition ratio in the low-k film approaches 2. On the other hand, the stoichiometric SiC used for the hard mask has a C / Si composition ratio of 2, so that the dry etching rate between the interlayer insulating film and the hard mask is close, and the SiC of the hard mask is also reduced during the low-k etching. It will be etched.

For this reason, in the above-mentioned proposal in Patent Document 2, the shape of the trench formed by etching is deteriorated, and there is a concern that the leakage between wirings or the deterioration of TDDB (Time Dependent Dielectrics Breakdown) characteristics between the wirings.

Further, as described above, SiCO having a low dielectric constant has been used as the interlayer insulating film in the Cu embedded wiring, but there is a problem that the reliability of the multilayer wiring is lowered. In other words, since the conventional SiCO film has low mechanical strength, it cannot withstand stress in the CMP (Chemical Mechanical Polishing) process in the multilayer wiring process or the wire bonding process in the package process, and the film is broken and the film peels off. End up.

For example, in the proposal of the above-mentioned patent document 1, it is necessary to deposit with low energy in order to form the ring structure of the raw material as it is in the film. However, in order to form a film having high mechanical strength, a film having high energy and a strong bond must be deposited. Therefore, in the method proposed in Patent Document 1, a film having high mechanical strength is formed. It was difficult.

Accordingly, an object of the present invention is to increase the mechanical strength of a silicon carbide thin film and prevent the disappearance and peeling of the film.

From one disclosed aspect, a silicon carbide thin film is formed on a porous low dielectric constant insulating film by using a raw material having a functional group containing a double bond and a —CH ₂ — bond that is cyclic and bonded to Si. Forming a hard mask by etching the silicon carbide thin film into a predetermined pattern; and etching the low dielectric constant insulating film using the hard mask as an etching mask to form at least one of a wiring forming groove or a via hole A method for manufacturing a semiconductor device is provided.

From another point of view, silicon carbide is formed by a plasma chemical vapor deposition method using a raw material having a functional group including a double bond and a Si—CH ₂ — bond in a cyclic form on a base. Forming a thin film as an anti-diffusion film for Cu, and forming a SiCO thin film as an interlayer insulating film on the diffusion preventive film by plasma chemical vapor deposition using the same raw material and oxygen-containing gas as the raw material And a step of etching the interlayer insulating film to form at least one of a trench for forming a wiring or a via hole.

According to the disclosed method for manufacturing a semiconductor device, the annular structure can be decomposed, and a high mechanical strength can be realized by a strong network of —C ₂ H ₄ — in the silicon carbide thin film, thereby preventing the disappearance and peeling of the film. it can.

It is explanatory drawing of the basic manufacturing process of the semiconductor device of embodiment of this invention. It is explanatory drawing of C / Si composition ratio dependence of the etching selection ratio with respect to a low dielectric constant insulating film. It is explanatory drawing of RF power dependence of the dielectric constant of the silicon carbide thin film of this invention. It is a notional block diagram of the plasma CVD apparatus used for each Example of the present invention. It is explanatory drawing to the middle of the manufacturing process of the semiconductor device of Example 1 of this invention. FIG. 6 is an explanatory view after FIG. 5 of the manufacturing process of the semiconductor device of Example 1 of the present invention. It is a conceptual block diagram of the semiconductor device to which the manufacturing process of Example 1 of this invention is applied. It is explanatory drawing to the middle of the manufacturing process of the semiconductor device of Example 2 of this invention. FIG. 9 is an explanatory diagram of the semiconductor device manufacturing process of Example 2 of the present invention after FIG. 8. It is explanatory drawing of the dielectric constant reduction effect by the structure of Example 2 of this invention. It is explanatory drawing to the middle of the manufacturing process of the semiconductor device of Example 3 of this invention. FIG. 11 is an explanatory view after FIG. 11 of the manufacturing process of the semiconductor device of Example 3 of the present invention. It is explanatory drawing of oxygen concentration dependence of the etching selection ratio of the SiCO type | system | group Low-k film | membrane of Example 3 of this invention. It is explanatory drawing of the oxygen concentration dependence of the via | veer yield of Example 3 of this invention. It is explanatory drawing of oxygen flow ratio dependence of the oxygen concentration in the SiCO type | system | group Low-k film | membrane of Example 3 of this invention. It is explanatory drawing of the mechanical strength of the SiCO type | system | group Low-k film | membrane of Example 3 of this invention. It is explanatory drawing of the manufacturing process of the semiconductor device of Example 4 of this invention. It is a time chart of the manufacturing process of Example 4 of this invention. It is explanatory drawing of post-processing time dependence in the Si-H peak intensity | strength in Example 4 of this invention. It is explanatory drawing of the atmospheric standing time dependence of the Si-OH peak intensity in Example 4 of this invention. It is explanatory drawing of the atmospheric standing time dependence of the dielectric constant change in Example 4 of this invention. It is explanatory drawing of the oxygen addition dependence of the Si-H peak intensity | strength in Example 4 of this invention. It is explanatory drawing of the ultraviolet-ray processing dependence of the Si-OH peak intensity in Example 4 of this invention. It is explanatory drawing of the ultraviolet-ray process dependence of the dielectric constant change in Example 4 of this invention. It is a model figure of the cure effect in Example 4 of this invention. It is a conceptual sectional view of a conventional embedded wiring.

  Here, with reference to FIGS. 1 to 3, a manufacturing process of the semiconductor device according to the embodiment of the present invention will be described. FIG. 1 is an explanatory diagram of a manufacturing process of a semiconductor device according to an embodiment of the present invention, and will be described here as a single damascene process. First, as shown in FIG. 1A, after a diffusion prevention film 2 and a porous low dielectric constant insulating film 3 are formed on a base 1, a silicon carbide thin film 4 which is a feature of the present invention is formed. To do. The base 1 is made of, for example, a high density SiCO-based Low-k cap film, and the porous low dielectric constant insulating film 3 is typically a porous SiCO film.

The silicon carbide thin film 4 is a raw material, typically 1-1, divinyl-1-silacyclopentane (DVScP), in which —CH ₂ — bonds are cyclic and bonded to Si and have a functional group including a double bond. : 1-1, divine-silacyclopentane).

Next, as shown in FIG. 1B, the silicon carbide thin film 4 is etched into a predetermined pattern to form a hard mask 5. Next, as shown in FIG. 1C, the low dielectric constant insulating film 3 is dry-etched using the hard mask 5 as an etching mask to form a wiring forming groove 6.

Next, as shown in FIG. 1D, the exposed portion of the diffusion prevention film 2 is removed using a process of removing the hard mask 5. Thereafter, the wiring forming groove 6 is filled with a Cu buried layer through a barrier metal film, and then polished by CMP (chemical mechanical polishing) until the surface of the low dielectric constant insulating film 3 is exposed. A lead-in wiring is formed.

Since the conventional SiC film is formed by a network such as —Si—CH ₂ —Si—, the C / Si composition ratio approaches 2, whereas in the present invention, a network such as —Si—CH ₂ —CH ₂ —Si is mainly used. Therefore, the C / Si ratio in the silicon carbide thin film 4 approaches 4. For this reason, the C / Si composition ratio is greatly different from various low dielectric constant insulating films, and the etching rate is greatly different.

FIG. 2 is an explanatory diagram of the C / Si composition dependence of the etching selectivity with respect to the low dielectric constant insulating film. FIG. 2A is an explanatory diagram of the composition of each SiC film. ¹ SiC is a silicon carbide thin film (dielectric constant: 3.5) according to the present invention, and ² SiC is DMDMOS (dimethyldimethoxysilane: Si). It is a SiCO film (dielectric constant: 3.7) made of (CH ₃ ) ₂ (OCH ₃ ) ₂ ). ³ SiC is a SiCO film (dielectric constant: 4.5) composed of 4MS (tetramethylsilane: Si (CH ₃ ) ₄ ) and CO ₂ , and ⁴ SiC is a SiCO film (dielectric constant) composed of 4MS and NH _3. : 5.5).

FIG. 2B shows the etching selectivity of each SiC film with respect to the low dielectric constant insulating film in the etching with CF ₄ gas, C ₅ F ₈ gas, and C ₄ F ₈ gas. As is apparent from the figure, a material having a high C / Si composition ratio has a low etch rate and a high etching selectivity with Low-k. That is, the etching selectivity varies greatly depending on the C / Si composition ratio, and the etching selectivity can be increased by increasing the C / Si ratio according to the present invention.

here,
The depth of the trench 6 for wiring formation is t ₁
The thickness of the hard mask 5 is t ₂
The etching rate of the low dielectric constant insulating film 3 is set to r ₁
The etching rate of the hard mask 5 is r ₂
Then, in order for the hard mask 5 to function as an etching mask,
t ₁ / r ₁ <t ₂ / r ₂
Is necessary.

The etching selectivity s is
s = r ₂ / r ₁
So
t ₁ / t ₂ <s
The relationship holds. Since the hard mask 5 must be finally removed, it is preferable that the hard mask 5 is thin so that the low dielectric constant insulating film 3 is not damaged when the hard mask 5 is removed. That, _{t 2} is small is preferred. In this regard, in the present invention, since s increases, t ₂ can be reduced.

In order to prevent the hard mask 5 from disappearing during the etching, it is desirable that the etching selectivity s to the low dielectric constant insulating film 3 is at least 5. The silicon carbide thin film 4 according to the present invention has a large etching selectivity as shown in FIG. 2B, and the selectivity 5 can be ensured by optimizing the etching conditions of the fluorocarbon-based gas. Since the etching rate depends on the etching gas rather than the reaction chamber pressure and RF power during etching, the selection ratio can be easily ensured as long as at least C ₄ F ₈ gas is used.

In the present invention, the diffusion prevention film 2 may also be formed by the same film formation method as the silicon carbide thin film 4. In this case, the diffusion prevention film 2 can be etched simultaneously with the hard mask 5. In particular, since the silicon carbide thin film 4 of the present invention has a lower dielectric constant than other diffusion prevention films as described above, the dielectric constant of the entire interlayer insulating film can be reduced.

FIG. 3 is an explanatory diagram of the RF power dependency of the dielectric constant of the silicon carbide thin film of the present invention, and shows the dielectric constant of the silicon carbide thin film when the 13 MHz RF power is changed. As other film formation conditions, the DVScP flow rate is 30 cc / min, the He carrier gas flow rate is 70 cc / min, the chamber pressure is 1.0 Torr, and the film formation temperature is 350 ° C. Within this film forming condition, the C / Si composition ratio in the silicon carbide thin film 4 is maintained at 4.

As shown in FIG. 3, it can be seen that the dielectric constant increases with increasing RF power. Therefore, since the dielectric constant can be changed while maintaining the C / Si composition ratio at 4, it is possible to adjust the dielectric constant of the silicon carbide thin film 4 without changing the etching selectivity with respect to the low dielectric constant insulating film 3. Become.

Further, -CH ₂ - material bonds with functional groups containing bound and double bonded to Si becomes circular, typically 1-1, Jibiniru-1-silacyclopentane (DVScP: 1-1 The low dielectric constant insulating film 3 may be formed by a plasma CVD method using an oxidative gas. The oxidizing gas may be an alcohol such as methyl alcohol, ethyl alcohol, or isopropyl alcohol, but is typically O ₂ gas.

Incidentally, when using DVScP and O ₂ gas, the flow rate ratio of O ₂ / DVScP is set to 4 or more and the film forming temperature is set to 350 ° C. By setting the flow rate ratio to 4 or more, the yield at the time of via formation is significantly improved, and by setting the film formation temperature to 350 ° C. or more, the mechanical strength can be increased even with a film having the same refractive index.

In this case, the low dielectric constant insulating film 3 and the silicon carbide thin film 4 may be formed in a series of steps in the same reaction chamber. When the diffusion prevention film 2 is also a silicon carbide thin film of the present invention, the diffusion prevention film 2 may be formed in a series of steps in the same reaction chamber.

In the case where a silicon carbide thin film is used as the diffusion preventing film 2, after the formation of the diffusion preventing film 2, plasma treatment with an oxidizing gas or ultraviolet irradiation treatment may be performed. By performing such a process, it is possible to greatly reduce the deterioration over time of the dielectric constant of the diffusion preventing film 2.

In this case as well, film formation and plasma treatment or ultraviolet irradiation treatment may be performed in the same reaction chamber. In this case, it is desirable to use an alcohol such as methyl alcohol, ethyl alcohol, or isopropyl alcohol, which has a mild oxidation reaction, as the oxidizing gas.

The substrate temperature for the ultraviolet irradiation treatment is preferably 200 ° C. or higher. Further, in order to significantly reduce the time-dependent change in dielectric constant, it is desirable that the shrinkage rate of the silicon carbide thin film after the ultraviolet irradiation treatment is 3% or more. It is desirable to use a reactive atmosphere, for example, a mixed atmosphere of nitrogen gas and oxygen gas.

Based on the above, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described next with reference to FIGS. FIG. 4 is a conceptual configuration diagram of a plasma CVD apparatus used in each embodiment of the present invention. This plasma CVD apparatus is a single-wafer type general parallel plate type vacuum chamber. Specifically, in the vacuum chamber 11, a wafer stage 12 that also serves as a lower electrode that heats the substrate 13 to be processed and a shower head 14 that also serves as an upper electrode are accommodated.

For example, a 27 MHz high frequency RF oscillator 15 and a 400 KHz low frequency RF oscillator 16 are connected to the parallel plate type electrodes. The 27 MHz high frequency RF oscillator 15 is switched to a 13 MHz RF oscillator as necessary.

From the raw material pipe 19, for example, DVScP that is liquid at normal temperature is supplied as a raw material to the vaporizer 17, and is heated and vaporized in the vaporizer 17. The vaporized DVScP gas is supplied to the shower head 14 using He gas supplied from the He gas pipe 18 as a carrier gas. The O ₂ gas pipe 20 is used when a film containing O such as SiCO is formed, or when plasma treatment or ultraviolet irradiation treatment is performed in an oxidizing atmosphere.

Next, with reference to FIGS. 5 and 6, the manufacturing process of the semiconductor device of Example 1 of the present invention will be described. Here, a damascene process corresponding to a device of hp (high performance) 32 nm node will be described. First, as shown in FIG. 5A, a plasma CVD method using trimethylsilane (Si (CH ₃ ) ₄ ) and NH ₃ gas on a low-k cap film 21 made of high-density SiCO as a base. A Cu barrier film 22 having a thickness of, for example, 25 nm made of SiCN is formed.

Next, a low-k film 23 made of porous SiCO having a thickness of, for example, 60 nm and a low-k film having a thickness of, for example, 40 nm made of high-density SiCO are formed on the Cu barrier film 22 by using a plasma CVD method. A cap film 24 is sequentially formed.

Next, a silicon carbide thin film 25 having a thickness of, for example, 20 nm serving as a hard mask is formed on the low-k cap film 24 by plasma CVD using DVScP. The film formation conditions at this time were 13 MHz RF power of 500 mW / cm ² , 400 KHz RF power of 80 W / cm ² , DVScP flow rate of 30 cc / min, He carrier gas flow rate of 70 cc / min, and chamber pressure of 1.0 Torr. The film forming temperature is 350 ° C.

Next, as shown in FIG. 5B, the silicon carbide thin film 25 is etched using the resist pattern 26 as a mask to form a hard mask 27. Next, as shown in FIG. 5C, the resist pattern 26 is removed by ashing to expose the hard mask 27. At this time, since the porous Low-k film 23 is covered with the Low-k cap film 24 and is not exposed to oxygen plasma, it is not altered by ashing.

Next, as shown in FIG. 5D, the low-k cap film 24 and the porous low-k film 23 are selectively etched sequentially using the hard mask 27 as a mask and C ₄ F ₈ as an etching gas. 28 is formed.

Next, as shown in FIG. 6E, the hard mask 27 is removed by dry etching. At this time, the exposed portion of the Cu barrier film 22 is simultaneously removed by etching.

Next, as shown in FIG. 6F, a barrier metal film 29 made of Ta / TaN is formed by sputtering. Next, after forming a Cu plating seed layer by electroless Cu plating, the Cu film is plated by an electrolytic plating method, thereby completely filling the trench 28 with the Cu buried layer 30.

Next, as shown in FIG. 6G, polishing is performed by CMP until the low-k cap film 24 is exposed to remove the excess barrier metal film 29 and the Cu buried layer 30, and the buried wiring 31. Form. Next, as shown in FIG. 6H, a Cu barrier film 32 made of SiCN is again provided using the plasma CVD method, thereby completing a buried wiring structure for one layer.

  Thus, in Example 1 of the present invention, the silicon carbide thin film having a C / Si composition ratio of 4 is used as the hard mask, so that the etching selection ratio s with respect to the porous Low-k film 23 is set to 5 or more. This makes it possible to form the trench 28 with high accuracy.

In addition, since the etching selectivity s increases, the thickness of the silicon carbide thin film 25 can be reduced, thereby reducing the damage caused to the porous Low-k film 23 in the removal process of the hard mask 27. Can do.

FIG. 7 is a conceptual configuration diagram of a semiconductor device to which the manufacturing process according to the first embodiment of the present invention is applied. First, after forming the element isolation insulating film 42 on the silicon substrate 41, the gate insulating film 43 is formed on the surface of the element formation region surrounded by the element isolation insulating film 42. Next, after depositing a gate electrode material, the gate electrode 44 is formed by etching to a predetermined width.

Next, an extension region 45 is formed by introducing impurities using the gate electrode 44 as a mask. Next, after depositing an insulating film on the entire surface, sidewalls 46 are formed by anisotropic etching, and impurities are introduced using the sidewalls 46 as a mask, thereby forming a source region 47 and a drain region 48.

Next, after the interlayer insulating film 49 is formed, via holes reaching the source region 47 and the drain region 48 are formed (only the drain region 48 side is shown in the figure). Next, a W film is provided through a barrier metal 50 made of TiN, and is polished by a CMP method to be flattened, thereby forming a W plug 51.

Next, the embedded wiring 31 is formed by applying the manufacturing process shown in FIGS. Next, a Cu via 52 and a Cu buried wiring 53 are formed simultaneously using a dual damascene process. In this case, the layer structure of the interlayer insulating film in which the Cu embedded wiring 53 is embedded has the same stacking order as the interlayer insulating film in which the embedded wiring 31 is embedded.

Next, the dual damascene process is repeated for the number of layers that require it, and then the surface thereof is covered with the Cu barrier film 32, whereby the multilayer wiring structure forming process is completed. In the figure, each Cu embedded wiring 53 and Cu via 52 are connected at the same location, but are actually at different locations.

Next, with reference to FIGS. 8 to 10, a method for manufacturing a semiconductor device according to Example 2 of the present invention will be described. In Example 2, the Cu barrier film in Example 1 was formed using DVScP. It is replaced with a silicon carbide thin film. Also here, a damascene process corresponding to a hp 32 nm node device will be described.

First, as shown in FIG. 8A, the thickness of the Cu barrier film is, for example, 15 nm on the Low-k cap film 21 made of high-density SiCO as a base by the plasma CVD method using DVScP. The silicon carbide thin film 54 is formed. The film forming conditions in this case are the same as the film forming conditions for the silicon carbide thin film 25 in the first embodiment.

Thereafter, similarly to Example 1, the thickness is formed on the silicon carbide thin film 54 using the plasma CVD method, for example, the porous Low-k film 23 made of porous SiCO of 60 nm and the thickness made of high-density SiCO. For example, a low-k cap film 24 of 40 nm is sequentially formed. Next, a silicon carbide thin film 25 having a thickness of, for example, 20 nm serving as a hard mask is formed on the low-k cap film 24 by plasma CVD using DVScP.

Next, as shown in FIG. 8B, the silicon carbide thin film 25 is etched using the resist pattern 26 as a mask to form a hard mask 27. Next, as shown in FIG. 8C, the resist pattern 26 is removed by ashing to expose the hard mask 27.

Next, as shown in FIG. 8D, the low-k cap film 24 and the porous low-k film 23 are sequentially and selectively etched using the hard mask 27 as a mask and C ₄ F ₈ as an etching gas. 28 is formed.

Next, as shown in FIG. 9E, the hard mask 27 is removed by dry etching. At this time, the exposed portion of the silicon carbide thin film 54 is simultaneously removed by etching. Next, as shown in FIG. 9F, after forming a barrier metal film 29 made of Ta / TaN, the Cu film is plated to completely bury the trench 28 with the Cu buried layer 30.

Next, as shown in FIG. 9G, the embedded wiring 31 is formed by the CMP method. Next, as shown in FIG. 9 (h), a silicon carbide thin film 55 serving as a Cu barrier film is provided again by plasma CVD using DVScP, thereby completing a buried wiring structure for one layer. Thereafter, by repeating the same process, a stacked structure similar to that of the semiconductor device shown in FIG. 7 can be obtained.

  Thus, in Example 2 of the present invention, since the hard mask and the Cu barrier film are formed of the same silicon carbide thin film, it becomes easy to remove them simultaneously by dry etching. The integration of 90 nm to 65 nm, 45 nm, and 32 nm nodes has continued, and the film thickness of the Cu barrier film has always been kept about one fifth of the depth of the trench 28.

That is, generally, the side and bottom surfaces of the Cu embedded wiring are protected by the barrier metal film, but the top surface is not protected. Therefore, the Cu barrier film uses a high-density film, for example, a high-density SiCN film, in order to maintain the performance of Cu, and protects Cu from moisture and various gases in the wiring process. However, if the density is high, the inter-wiring capacitance increases, so it is limited to about one fifth of the trench depth.

However, when a silicon carbide thin film is used, since the dielectric constant is low, an increase in inter-wiring capacitance is suppressed even if the film thickness is increased to improve the protection performance. On the other hand, if the film thickness is kept thin, the interwiring capacitance can be further reduced. This situation will be described with reference to FIG.

10A and 10B are diagrams for explaining the effect of reducing the dielectric constant by the structure of the second embodiment of the present invention. FIG. 10A is a conceptual cross-sectional view of the multilayer wiring structure, and FIG. It is explanatory drawing of rate dependence. As shown in FIG. 10A, here, the buried wiring 63 is formed on the plasma SiO ₂ film 61 via the SiCN—Cu barrier film 62, and then the Cu barrier film 64 of the present invention is provided. On top of this, porous low-k films 66 and 65 and a low-k cap film 67 are provided, and an embedded wiring 68 made of Cu with a width of 50 nm and an interval of 50 nm is provided perpendicular to the porous low-k film 65.

Next, a porous Low-k film 72 is provided via the Cu barrier film 69 of the present invention, then an embedded wiring 73 is formed thereon, and finally a Cu barrier film 74 of the present invention is provided. The Cu barrier films 64, 69 and 74 of the present invention will be described by using the Cu barrier film 69 as a representative. As shown in the enlarged view on the right side, the Cu barrier film 69 has a dielectric constant of 5.5 as an adhesion layer and a thickness of, for example, a 5 nm SiCN film 70 and a silicon carbide thin film 71 formed using DVScP. It has a two-layer structure.

FIG. 10B plots the inter-wiring capacitance when the film thickness of the upper layer of the Cu barrier film is 10 nm and 20 nm, while changing the dielectric constant of the upper layer. For example, when a SiCO film having a thickness of 20 nm and a dielectric constant of 4.5 is changed to a thickness of 10 nm by using the silicon carbide thin film according to the present invention having a dielectric constant of 3.5, the capacitance between wirings is 4.3%. Can be reduced.

To reduce the inter-wiring capacitance by reducing only the dielectric constant of the porous Low-k film, it is necessary to change the dielectric constant from 2.4 to 2.1 or less. There is a concern that the mechanical strength of the multilayer wiring is reduced due to the accompanying reduction in mechanical strength. On the other hand, in Example 2 of the present invention, by using a silicon carbide thin film for the Cu barrier film, the capacitance between wirings can be reduced without changing the dielectric constant of the porous Low-k film.

Next, with reference to FIGS. 11 to 16, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described. The third embodiment is a porous low-k film and a low-k cap film according to the second embodiment. Is replaced with a SiCO-based Low-k film using DVScP. Also here, a damascene process corresponding to a hp 32 nm node device will be described.

First, as shown in FIG. 11 (a), the thickness of the Cu barrier film formed on the base made of the SiCO Low-k film 56 using DVScP of the present invention by the plasma CVD method using DVScP is as follows. For example, a 15 nm silicon carbide thin film 54 is formed. The film forming conditions in this case are the same as the film forming conditions for the silicon carbide thin film 25 in the first embodiment.

Subsequently, in the same vacuum chamber, a SiCO Low-k film 57 using DVScP having a thickness of, for example, 80 nm and a silicon carbide thin film 25 having a thickness of, for example, 15 nm serving as a hard mask are sequentially formed.

The deposition conditions of the SiCO-based Low-k films 56 and 57 are, for example, a DVSCP flow rate of 20 cc / min, oxygen of 80 cc / min, a vacuum chamber pressure of 1 Torr, and a high frequency RFR bias of 1.0 W / cm ² at 27 MHz. To do. The film forming temperature is 350 ° C. or higher, for example, 390 ° C.

Next, as shown in FIG. 11B, the hard mask 27 is formed by etching the silicon carbide thin film 25 using the resist pattern 26 as a mask. Next, as shown in FIG. 11C, the resist pattern 26 is removed by ashing to expose the hard mask 27.

Next, as shown in FIG. 11D, the trench 28 is formed by selectively etching the SiCO-based Low-k film 57 using the hard mask 27 as a mask and using C ₄ F ₈ as an etching gas.

Next, as shown in FIG. 12E, the hard mask 27 is removed by dry etching. At this time, the exposed portion of the silicon carbide thin film 54 to be the Cu barrier film is also removed by etching. Next, as shown in FIG. 12 (f), a barrier metal film 29 made of Ta / TaN is formed, and then the Cu film is plated to completely bury the trench 28 with the Cu buried layer 30.

Next, as shown in FIG. 12G, the embedded wiring 31 is formed by the CMP method. Next, as shown in FIG. 12H, a silicon carbide thin film 55 serving as a Cu barrier film is provided again by a plasma CVD method using DVScP, thereby completing a buried wiring structure for one layer. Thereafter, by repeating the same process, a stacked structure similar to that of the semiconductor device shown in FIG. 7 can be obtained.

  As described above, in Example 3 of the present invention, the porous Low-k film is also formed by the plasma CVD method using DVScP. Therefore, the same material is used to form the Cu barrier film, the porous Low-k film, and the hard mask. Can be formed in a series of film forming steps.

In addition, the porous Low-k film is formed using DVScP, which is a raw material having a functional group containing a double bond and a Si—C ₂ — bond in a cyclic form, under a condition of higher energy than conventional. is doing. As a result, a mechanically high-strength porous SiCO film can be formed using a high-strength Si— (CH ₂ ) _n —Si network.

FIG. 13 is an explanatory diagram of the oxygen concentration dependence of the etching selectivity of the SiCO-based Low-k film of Example 3 of the present invention. Here, the oxygen concentration [atm%] in the porous SiCO film when a mixed gas of CF ₄ and Ar is used as an etching gas and an RF power of 0.6 W / cm ² is applied at 13 MHz under a pressure of 50 mTorr. The ratio of SiC to etching rate is plotted. As shown in the figure, the etching selectivity has a linear relationship with the oxygen concentration in the porous SiCO film.

FIG. 14 is an explanatory diagram of the dependency of via yield on oxygen concentration in Example 3 of the present invention. Here, the via yield relationship when a 140-nm-pitch Cu double-layer wiring having a SiC film thickness of 25 nm, a porous SiCO film thickness of 100 nm, and a barrier metal Ta / TaN laminated structure is prepared. Is shown.

As shown in FIG. 13, when the oxygen concentration is low, the etching selectivity is small and the amount of over-etching becomes large. As a result, as shown in FIG. 14, the barrier metal coverage deteriorates and the via yield decreases. On the other hand, the porous SiCO film according to the present invention has higher mechanical strength than the conventional low-k film, as will be described later, so that the yield is improved because there is less mechanical damage such as scratches due to over polishing in the CMP process of the barrier metal. To do.

FIG. 15 is an explanatory diagram of the oxygen flow ratio dependence of the oxygen concentration in the SiCO-based Low-k film of Example 3 of the present invention. At this time, the pressure of the vacuum chamber is 1 Torr, and the RF bias is 1.0 W / cm ² at 27 MHz. As is apparent from the figure, the oxygen concentration in the porous SiCO film can be adjusted to 40 atom% or more by adjusting the oxygen flow rate ratio to 4 times or more. As a result, as shown in FIG. 14, the via yield is 100%.

FIG. 16 is an explanatory diagram of the mechanical strength of the SiCO-based Low-k film of Example 3 of the present invention. A conventional low-k film is formed by plasma CVD using TMS (tetramethylsilane) and CO ² gas as source gases, a film forming temperature of 390 ° C., a pressure of 4 Torr, an RF bias of 13 MHz, and 1.0 W / cm. ² is a porous SiCO film formed under the condition ( ² ). On the other hand, in the present invention, as described above, the DVScP flow rate is 20 cc / min, oxygen is 80 cc / min, the vacuum chamber pressure is 1 Torr, and the high-frequency RF bias is 1.0 W / cm ^{2 at} 27 MHz. The film forming temperatures were 350 ° C. and 390 ° C.

As is apparent from FIG. 16, the porous Low-k film of the present invention can obtain higher mechanical strength than the conventional porous SiCO film. Actually, when a four-layer wiring is formed as shown in FIG. 7 above, the first Low-k in the structure using the conventional Low-k film having a dielectric constant of 2.7 and the conventional SiCO film having a dielectric constant of 3.7. The peeling occurred at the interface between the k film and the Cu barrier film. However, when a Cu barrier film composed of a porous SiCOLow-k film having a dielectric constant of 2.5 and a silicon carbide thin film having a dielectric constant of 3.5 is continuously formed in the same plasma CVD apparatus in the present invention, no peeling is observed. There wasn't.

Next, with reference to FIGS. 17 to 25, a method for manufacturing a semiconductor device according to Example 4 of the present invention will be described. Here, the process of forming a SiC-based Cu barrier film in Example 2 described above will be described. This will be described as a post-processing step. As shown in FIG. 17A, the embedded wiring is covered with a Cu barrier film made of the silicon carbide thin film 55 as in FIG. As shown in the time chart of FIG. 18, the deposition conditions in this case are as follows: DVScP flow rate is 50 cc / min, vacuum chamber pressure is 1 Torr, high frequency RF bias is 27 mhz, 700 mW / cm ² , low frequency RF bias is 400 KHz. 80 W / cm ² . The film forming temperature is 350 ° C.

Subsequently, in the same vacuum chamber, a high frequency RF bias of 500 mW / cm ² at 27 MHz and a low frequency RF bias of 80 W / cm ² at 400 KHz are applied with CH ₃ OH flowing at 70 cc / min to 0.7 Torr. Is generated. The substrate is exposed to the generated CH ₃ OH atmosphere 58 for about 30 seconds. As a result, the silicon carbide thin film 55 is converted into a SiCO film 59 as shown in FIG.

FIG. 19 is an explanatory diagram of the post-processing time dependency of the Si—H peak intensity in Example 4 of the present invention. As is clear from the figure, the Si-H peak intensity in FT-IR decreases with the post-treatment time, and the Si-H peak intensity in FT-IR disappears by the post-treatment for 30 seconds.

FIG. 20 is an explanatory diagram of the dependency of the Si—OH peak intensity on the atmospheric standing time in Example 4 of the present invention. As is apparent from the figure, when no post-treatment is performed, the Si—OH peak intensity in FT-IR increases with time. On the other hand, when post-treatment was performed for 30 seconds as in Example 4, the Si—OH peak intensity in FT-IR disappeared and no change over time was observed. Note that this Si—OH peak intensity represents the amount of moisture adhering to the film.

FIG. 21 is an explanatory diagram of the dependence of the change in dielectric constant on the atmospheric standing time in Example 4 of the present invention.
As is apparent from the figure, the dielectric constant increases with time when no post-processing is performed, but almost no change with time in the dielectric constant is observed when post-processing is performed for 30 seconds. Considering the results shown in FIGS. 20 and 21 together, it can be seen that the amount of moisture adsorbed is suppressed by post-processing, and the change in dielectric constant with time is suppressed.

UV cure by ultraviolet irradiation is effective when considering the damage of the substrate due to the plasma after RF plasma treatment or the heating temperature. In other words, the processing temperature can be reduced by using UV cure energy. In the case of UV cure, the energy is large. Therefore, when oxygen with strong oxidation is used, the Si—H bond can be changed to a Si—O—Si network.

FIG. 22 is an explanatory diagram of the oxygen addition dependence of the Si—H peak intensity in Example 4 of the present invention. The pressure in UV cure was 50 Torr, and when 5% oxygen was included relative to nitrogen, the Si-H peak disappeared when the shrinkage (shrinkage) of the silicon carbide thin film was 3% or more, but there was no oxygen. If only nitrogen is used, the Si—H peak does not disappear completely.

FIG. 23 is an explanatory diagram of the ultraviolet treatment dependency of the Si—OH peak intensity in Example 4 of the present invention. As shown in the figure, when UV curing is performed in an oxygen-containing atmosphere, the Si—H bond is eliminated by the oxygen atmosphere, so that the effect of reducing the adhesion of moisture can be seen.

FIG. 24 is an explanatory diagram of the ultraviolet treatment dependency of the change in dielectric constant in Example 4 of the present invention. As shown in the figure, since the Si-H bond disappears due to the oxygen atmosphere, the adhesion of moisture is reduced and the dielectric constant is suppressed.

FIG. 25 is a model diagram of the cure effect in the fourth embodiment of the present invention. Subsequent etching or wet processing in the wiring process causes Si—H bonds to become Si—OH, which causes adverse effects such as adsorption of moisture and an increase in dielectric constant. However, in Example 4 of the present invention, the Si—H bond is changed to Si—O—Si bond by UV treatment in an atmosphere containing oxygen, and is not changed by etching or wet treatment in the subsequent wiring process. The performance will be stable.

The silicon carbide thin film of the present invention forms an insulating film having a low dielectric constant because of the structure containing a lot of hydrogen. However, when the dielectric constant is extremely lowered, not only C—H bonds but also Si— H bonds increase. As described above, the Si—H bond becomes Si—OH in the air atmosphere, adsorbs moisture, and increases the dielectric constant. In order to prevent such characteristic deterioration in the air atmosphere, it has been found effective to eliminate the Si—H bond by post-treatment plasma treatment.

Here, the following additional notes are disclosed regarding the embodiment of the present invention including Examples 1 to 4.
(Appendix 1) A step of forming a silicon carbide thin film using a raw material having a functional group containing a double bond and a —CH ₂ — bond in a cyclic form on a porous low dielectric constant insulating film.
Etching the silicon carbide thin film into a predetermined pattern to form a hard mask;
And a step of etching the low dielectric constant insulating film using the hard mask as an etching mask to form at least one of a wiring forming groove or a via hole.
(Additional remark 2) The manufacturing method of the semiconductor device of Additional remark 1 which has the process of forming into a film the said silicon carbide thin film also as a diffusion prevention film with respect to Cu.
(Additional remark 3) The manufacturing method of the semiconductor device of Additional remark 2 which removes the said hard mask simultaneously in the process of etching the said diffusion prevention film.
(Additional remark 4) The manufacturing method of the semiconductor device of any one of Additional remark 1 thru | or Additional remark 3 whose said raw material is 1-1 and divinyl-1-silacyclopentane.
(Supplementary note 5) The semiconductor device according to any one of supplementary notes 1 to 3, wherein the hard mask does not contain oxygen and an equivalent dielectric constant combined with the low dielectric constant insulating film is 5 or less. Production method.
(Supplementary note 6) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 5, wherein a fluorocarbon gas is used as an etching gas in the etching step of the low dielectric constant insulating film.
(Supplementary Note 7) The fluorocarbon gas, a method of manufacturing a semiconductor device according to note 6 is a CF ₄ gas.
(Supplementary Note 8) Prevention of diffusion of silicon carbide thin film to Cu by plasma chemical vapor deposition method using a raw material having a functional group containing a double bond and a functional group containing a double bond and Si bonded with a cyclic form of —CH ₂ — Forming a film as a film;
Forming a SiCO thin film as an interlayer insulating film on the diffusion barrier film by plasma chemical vapor deposition using the same raw material as the raw material and an oxygen-containing gas;
And a step of etching the interlayer insulating film to form at least one of a wiring forming groove or a via hole.
(Additional remark 9) The manufacturing method of the semiconductor device of Additional remark 8 which forms the said diffusion prevention film and the said interlayer insulation film in the same reaction chamber.
(Supplementary note 10) The source material is 1-1, divinyl-1-silacyclopentane, the oxygen-containing gas is oxygen, and the flow rate of the oxygen gas is set to be four times or more the flow rate of the source material. The manufacturing method of the semiconductor device according to appendix 8 or appendix 9.
(Supplementary note 11) The semiconductor device according to any one of supplementary notes 8 to 10, wherein a deposition temperature in the deposition process of the interlayer insulating film is 350 ° C. or higher.
(Additional remark 12) The manufacturing method of the semiconductor device of Additional remark 8 or Additional remark 9 whose said oxygen containing gas is either methyl alcohol, ethyl alcohol, or isopropyl alcohol.
(Supplementary Note 13) In the step of etching the interlayer insulating film, SiC is mainly used as an etching mask by using a raw material having a functional group including a double bond and a —CH ₂ — bond that is cyclic and bonded to Si. 9. The method for manufacturing a semiconductor device according to appendix 8, wherein a hard mask made of a silicon carbide thin film having the composition as described above is used.
(Supplementary note 14) The supplementary note 1 or supplementary note 13, further comprising a step of oxidizing the silicon carbide thin film by performing plasma treatment in an oxidizing gas atmosphere after forming the silicon carbide thin film serving as the hard mask. Semiconductor device manufacturing method.
(Additional remark 15) The manufacturing method of the semiconductor device of Additional remark 14 which performs the film-forming process of the said silicon carbide thin film, and the plasma processing in the said oxidation system gas in the same reaction chamber.
(Additional remark 16) The manufacturing method of the semiconductor device of Additional remark 14 or Additional remark 15 whose said oxidation type gas is either methyl alcohol, ethyl alcohol, or isopropyl alcohol.
(Additional remark 17) The process of forming a silicon carbide thin film by the plasma chemical vapor deposition method using the raw material which has a functional group containing a functional group containing a double bond including Si and a —CH ₂ — bond in the form of a ring When,
And a step of subjecting the silicon carbide thin film to an ultraviolet treatment in an oxidizing gas atmosphere.
(Supplementary note 18) The method for manufacturing a semiconductor device according to supplementary note 17, wherein the oxidizing gas atmosphere is a mixed atmosphere of nitrogen gas and oxygen gas.
(Additional remark 19) The manufacturing method of the semiconductor device of Additional remark 17 or Additional remark 18 which makes substrate temperature in the said ultraviolet-ray process process 200 degreeC or more.

DESCRIPTION OF SYMBOLS 1 Base 2 Diffusion prevention film 3 Low dielectric constant insulating film 4 Silicon carbide thin film 5 Hard mask 6 Wiring forming groove 11 Vacuum chamber 12 Wafer stage 13 Substrate 14 Shower head 15 High frequency RF oscillator 16 Low frequency RF oscillator 17 Vaporizer 18 He gas pipe 19 Raw material pipe 20 O ₂ gas pipe 21 Low-k cap film 22, 32 Cu barrier film 23 Porous Low-k film 24 Low-k cap film 25 Silicon carbide thin film 26 Resist pattern 27 Hard mask 28 Trench 29 Barrier metal film 30 Cu buried layer 31 Embedded wiring 41 Silicon substrate 42 Element isolation insulating film 43 Gate insulating film 44 Gate electrode 45 Extension region 46 Side wall 47 Source region 48 Drain region 49 Interlayer insulating film 50 Barrier metal 51 W Plug 52 Cu via 53 Cu embedded wiring 54, 55 Silicon carbide thin film 56, 57 SiCO system Low-k film 58 CH ₃ OH atmosphere 59 SiCO film 61 Plasma SiO ₂ film 62 SiCN-Cu barrier film 63, 68, 73 Embedded wiring 64, 69 , 74 Cu barrier film 65, 66, 72 Porous low-k film 67 Low-k cap film 70 SiCN film 71 Silicon carbide thin film 81, 87 Cu diffusion prevention film 82 Porous low-k film 83 Low-k cap film 84 Barrier metal Film 85 Cu via 86 Cu embedded wiring

Claims (5)

Forming a silicon carbide thin film on a porous low dielectric constant insulating film using a raw material having a functional group containing a double bond and a —CH ₂ — bond in a cyclic form and bonded to Si;
Etching the silicon carbide thin film into a predetermined pattern to form a hard mask;
And a step of etching the low dielectric constant insulating film using the hard mask as an etching mask to form at least one of a wiring forming groove or a via hole. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming the silicon carbide thin film as a diffusion prevention film for Cu.   The method of manufacturing a semiconductor device according to claim 1, wherein the raw material is 1-1, divinyl-1-silacyclopentane. A silicon carbide thin film is formed as an anti-diffusion film for Cu by plasma enhanced chemical vapor deposition using a raw material having a functional group including a double bond and a functional group containing a double bond and a —CH ₂ — bond in the form of a ring. And a process of
Forming a SiCO thin film as an interlayer insulating film on the diffusion barrier film by plasma chemical vapor deposition using the same raw material as the raw material and an oxygen-containing gas;
And a step of etching the interlayer insulating film to form at least one of a wiring forming groove or a via hole.   5. The method according to claim 1, further comprising a step of oxidizing the silicon carbide thin film by performing plasma treatment in an oxidizing gas atmosphere after forming the silicon carbide thin film serving as the hard mask. A method for manufacturing the semiconductor device according to the item.

Images