JP2011146972A - Output circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress an increase in power consumption by minimizing the number of components, and to suppress crossover distortion during transient response. <P>SOLUTION: In an output circuit including N-channel MOS transistors M1, M2, M6 and P-channel MOS transistors M3, M4, M5, a MOS transistor M7 having drain and gate connected to a drain of the MOS transistor M2 and a gate of the transistor M5, respectively, and a sources connected to a drain of the MOS transistor M4. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an output circuit constituting an output stage or the like of an operational amplifier.

  2. Description of the Related Art Conventionally, a circuit configuration as shown in FIG. 2 is widely known as an output circuit that has a small mounting area and realizes low current consumption (see, for example, Non-Patent Document 1). In the output circuit shown in FIG. 2, M1, M2, and M6 are N channel MOS transistors, and M3, M4, and M5 are P channel MOS transistors. V + is a positive power supply terminal, V− is a negative power supply terminal, IN + and IN− are differential input terminals, and OUT is an output terminal. Transistors M1 and M2 constitute an input stage, transistors M3 and M4 constitute a current mirror circuit, and transistors M5 and M6 constitute an output stage. This output circuit obtains an output voltage at the output terminal OUT by driving the gate potentials of the transistors M5 and M6 in phase by the difference between the voltages input to the input terminals IN + and IN−.

  In this output circuit, a state is considered in which a negative input potential is applied to the input terminal IN +, a positive input potential is applied to the input terminal IN−, and a sink current flows from the output terminal OUT to the transistor M6. When a positive input potential is applied to the input terminal IN−, the gate potentials of the transistors M1 and M6 increase. On the other hand, when a negative input is applied to the input terminal IN +, the gate potential of the transistor M2 decreases and the gate potential of the transistor M5 increases. Therefore, a sink current flows from the output terminal OUT to the transistor M6.

  At this time, the gate potential of the transistor M1 is high, and the drain current of the transistor M1 increases unless limited by the drain-source voltage or the element size. This current leads to an increase in current consumption.

  As another problem, when transient input signals such as sine waves and pulses are applied to the input terminals IN + and IN− in opposite phases, crossover distortion occurs in the output voltage obtained at the output terminal OUT. There's a problem.

  In FIG. 2, when a negative transient signal is applied to the input terminal IN + and a positive transient signal is applied to the input terminal IN−, the sink current flows through the output terminal OUT as described above. At this time, the transistor M1 increases the drain current, and the gate potentials of the transistors M3 and M4 decrease. On the other hand, since a negative input potential is applied to the gate of the transistor M2, the drain current of the transistor M2 decreases.

  Under these conditions, the drain potential of the transistor M4 is increased and the gate potential of the transistor M5 is increased, whereby the transistor M5 is completely turned off. When the input terminal IN + is switched to the positive input potential and the input terminal IN− is switched to the negative input potential instantaneously from the state in which the transistor M5 is turned off, the element M2 is turned on from the state in which the transistor M5 is completely turned off. A delay occurs. This delay causes crossover distortion in the output signal output from the output terminal OUT.

  An output circuit shown in FIG. 3 is an output circuit that solves the problems of increase in current consumption and crossover distortion. In this circuit, an N-channel MOS transistor M12 is additionally connected between the drain of the transistor M1 and the drain of the transistor M3. Further, an N-channel MOS transistor M13 whose gate and drain are connected to the gate of the transistor M12, a P-channel MOS transistor M14 whose gate is connected to the gate of the transistor M5, and a current source I4 are connected to a positive power supply terminal + V and a negative power supply. It is connected in series between the terminal -V.

  In the output circuit shown in FIG. 3, when the potential of the input terminal IN− is high and the potential of the input terminal IN + is low, the drain current of the transistor M1 increases, the gate potentials of the transistors M3 and M4 decrease, and the transistor The drain voltage of M4 increases and the gate voltage of the transistor M14 increases. Therefore, the drain voltage of the transistor M14 is lowered, the gate voltages of the transistors M12 and M13 are lowered, the internal resistance of the transistor M12 is increased, and the increase in the drain current of the transistor M1 is limited. This improves the increase in current consumption when the output current is sucked.

  Further, by appropriately setting the current value of the current source I4 and the element size ratio of the transistors M5 and M14, the drain current of the transistor M5 can be controlled when the output current is sucked, and the transistor M5 can be prevented from being turned off at this time. . For this reason, the crossover distortion at the time of shifting from the suction of the output current to the discharge can be improved.

R. Jacob Baker "CMOS Circuit Design, Layout, and Simulation" second Edition, IEEE Press, pp.819, 2005, USA

  However, the output circuit shown in FIG. 3 has four constituent elements as compared with the circuit of FIG. 2, and has the disadvantage of causing an increase in current consumption that exceeds the reduction in current consumption in the stationary state. .

  An object of the present invention is to provide an output circuit that suppresses an increase in current consumption by minimizing the number of constituent elements and improves crossover distortion during transient response.

  To achieve the above object, an output circuit according to a first aspect of the present invention includes a first conductivity type first circuit having a gate connected to a first input terminal and a source connected to a first power supply terminal. A MOS transistor; a second MOS transistor of a first conductivity type having a gate connected to a second input terminal; a source connected to the first power supply terminal; and a gate and a drain having the first MOS transistor A third MOS transistor of the second conductivity type, the source of which is connected to the second power supply terminal, the gate of which is connected to the gate of the third MOS transistor, and the source of which is the second MOS transistor. A fourth MOS transistor of the second conductivity type connected to the power supply terminal, and a fifth MOS transistor of the second conductivity type having a source connected to the second power supply terminal and a drain connected to the output terminal. And a sixth MOS transistor of the first conductivity type having a gate connected to the first input terminal, a source connected to the first power supply terminal, and a drain connected to the output terminal. In the output circuit, the drain and gate are connected to the drain of the second MOS transistor and the gate of the fifth transistor, and the source is connected to the drain of the fourth MOS transistor. A MOS transistor is provided.

  The invention according to claim 2 is the output circuit according to claim 1, wherein each of the MOS transistors is replaced with a bipolar transistor, the gate is used as a base, the source is replaced with an emitter, and the drain is replaced with a collector. And

  According to the present invention, the number of constituent elements can be greatly reduced as compared with the circuit of FIG. 3, so that an increase in current consumption can be improved, and crossover when shifting from suction of output current to discharge is achieved. Distortion can be improved. That is, it is possible to improve the crossover distortion of the output transient response while suppressing the overall current consumption.

1 is a circuit diagram of an operational amplifier having an output circuit according to one embodiment of the present invention. FIG. It is a circuit diagram of the conventional output circuit. It is a circuit diagram of another conventional output circuit. It is a pulse response characteristic figure of the operational amplifier of a present Example.

  FIG. 1 shows an embodiment of the present invention, which is an operational amplifier configured by connecting a folded cascode circuit to the output circuit of the present invention.

  In FIG. 1, VIN− is an inverting input terminal, and VIN + is a non-inverting input terminal. Folded cascode circuit 10 includes P-channel MOS transistors M8 and M9, N-channel MOS transistors M10 and M11, resistors R1 and R2, and current sources I1, I2 and I3. The transistors M8 and M9 constitute a differential input stage, and the transistors M10 and M11 constitute a gate ground circuit. Since the folded cascode circuit 10 is a general circuit, further detailed description is omitted.

  The output circuit 20 includes N channel MOS transistors M1, M2, and M6, P channel MOS transistors M3, M4, M5, and M7, and a resistor R3. 2 differs from the output circuit described in FIG. 2 in that the source is connected to the drain of the transistor M4, the drain and the gate are connected to the gate of the transistor M5 and the drain of the transistor M2, and the source of the transistor M2. The point is that a current-adjusting resistor R3 connected to is added. The resistor R3 is for current adjustment.

  Next, the operation of the operational amplifier in the above configuration will be described. First, when a positive voltage is applied to the inverting input terminal VIN− and a negative voltage is applied to the non-inverting input terminal VIN +, the potential of the inverting input terminal VIN− is higher than that of the non-inverting input terminal VIN +. Since this is a typical folded cascode circuit 10, the potential of the input terminal IN− of the output circuit 20 is increased and the potential of the input terminal IN + is decreased.

Next, the operation of the output circuit 20 having the above configuration will be described. Here, the output quiescent current in the DC characteristic during the suction operation will be described with reference to FIG. The output quiescent current Io flowing through the transistor M6 of the output circuit 20 is determined by the effect of negative feedback and is given by the following equation. k ′ is a coefficient, W5 / L5 is a size ratio of the transistor M5, Vsg5 is a source-gate voltage of the transistor M5, and Vt is a threshold voltage.

であたえられるので、式（1）は、

となる。 When Vsg7 is the source-gate voltage of the transistor M7 and Vsd4 is the source-drain voltage of the transistor M4, the source-gate voltage Vsg5 of the transistor M5 is

So that equation (1) is

It becomes.

Further, Vsd4 = Ron4 × Id2. Here, Ron5 is a linear resistance value when the transistor M4 is conductive, and Id2 is a drain current of the transistor M2. Therefore, equation (2) is given as:

Ｗ４／Ｌ４はトランジスタＭ４のサイズ比、Ｖsg4はトランジスタＭ５のソース・ゲート間電圧である。 Ron4 is given by the following equation.

W4 / L4 is the size ratio of the transistor M4, and Vsg4 is the source-gate voltage of the transistor M5.

Ｗ３／Ｗ３はトランジスタＭ３のサイズ比、Ｉd1はトランジスタＭ１のドレイン電流である。 If Vsg3 is the voltage between the source and gate of the transistor M3, Vsg4 = Vsg3, which is given by the following equation.

W3 / W3 is the size ratio of the transistor M3, and Id1 is the drain current of the transistor M1.

Ｗ１／Ｌ１はトランジスタＭ１のサイズ比、Ｗ６／Ｌ６はトランジスタＭ６のサイズ比である。 This Id1 is given by the following equation.

W1 / L1 is the size ratio of the transistor M1, and W6 / L6 is the size ratio of the transistor M6.

この式(８)は、両辺に出力静止電流Ｉｏが介在し、負帰還の効果で出力静止電流が決まることを示す。 As a result, if equation (7) is substituted into equation (6), equation (6) is substituted into equation (5), and equation (5) is substituted into equation (4), the following equation can be obtained. it can.

This equation (8) indicates that the output quiescent current Io is present on both sides, and the output quiescent current is determined by the negative feedback effect.

  Next, the transient response characteristics in the above configuration will be described with reference to FIG. First, as a precondition, the entire circuit is connected to a voltage follower configuration in which the input terminal VIN− and the output terminal OUT are connected and the input terminal VIN + is an input, and a sine wave or pulse that is a transient signal is input to the input terminal VIN +. An input signal such as Hereinafter, the operation in a state in which the output terminal OUT is flowing the suction current will be described.

At the time of sink current output, the gate voltage of the transistor M6 and the gate voltage of the transistor M1 increase, the drain current of the transistor M1 increases, and the gate potentials of the transistors M3 and M4 decrease. As the gate potential of the transistor M4 decreases, the drain potential of the transistor M4 increases. On the other hand, the gate voltage of the transistor M2 decreases, the drain current of the transistor M2 decreases, and the gate potential of the transistor M7 increases. The source-gate voltage Vsg7 of the transistor M7 is determined by the drain current Id2 of the transistor M2, and is given by the following equation. W7 / L7 is the size ratio of the transistor M7.

The source-gate voltage Vsg5 of the transistor M5 is given by the above equation (2).

  Therefore, the source-gate voltage Vsg5 of the transistor M5 can be controlled by the drain current Id2 of the transistor M2 and the transistor size (L7 / W7) of the transistor M7 due to the effect of the transistor M7 added in the present invention. Without completely turning off the transistor M5, it is possible to improve the crossover distortion when the output shifts from current suction to current discharge.

  As described above, in the output circuit of the present invention, compared to the conventional circuit shown in FIG. 3, the increase in current consumption is suppressed by minimizing the number of elements and eliminating unnecessary current paths, and the transistor M7. This improves crossover distortion.

  FIG. 4 shows pulse response characteristics when the operational amplifier circuit of FIG. 1 and the conventional circuit of FIG. 2 are connected to the subsequent stage of the folded cascode circuit 10 of FIG. 1 as characteristics representing the effects of the present invention. This characteristic was obtained by simulation, and the conditions were both in a voltage follower configuration, positive power supply terminal V + = 1.5 V, negative power supply terminal V − = − 1.5 V, voltage gain Gv = 0 dB, The load resistance RL = 10 kΩ, the load capacitance CL (not shown) = 20 pF, and the ambient temperature Ta = 25 ° C. In the output circuit of the present invention, the crossover distortion is greatly improved as compared with the conventional circuit.

  In the above, the member, arrangement, connection, and the like to be used do not limit the present invention, and various modifications can be made within the scope of the present invention. For example, the N channel MOS transistors M1, M2, M6, M10, and M11 can be replaced with P channel transistors, and the P channel MOS transistors M3, M4, M5, M7, M8, and M9 can be replaced with N channel transistors. In this case, the positive power supply terminal + V and the negative power supply terminal −V may be reversed. The MOS transistors M1 to M11 can be replaced with bipolar transistors. In this case, the gate is replaced by the base, the drain is replaced by the collector, and the source is replaced by the emitter.

Claims (2)

A first MOS transistor of a first conductivity type having a gate connected to a first input terminal and a source connected to a first power supply terminal, a gate connected to a second input terminal, and a source connected to the first input terminal A second MOS transistor of the first conductivity type connected to one power supply terminal, a second MOS transistor having a gate and a drain connected to the drain of the first MOS transistor, and a source connected to a second power supply terminal; A third MOS transistor of conductivity type, a fourth MOS transistor of second conductivity type having a gate connected to the gate of the third MOS transistor and a source connected to the second power supply terminal, A fifth MOS transistor of the second conductivity type having a source connected to the second power supply terminal, a drain connected to the output terminal, a gate connected to the first input terminal, and a source connected to the first input terminal Is connected to the power supply terminal, the output circuit and a sixth MOS transistor of the first conductivity type having a drain connected to said output terminal,
There is provided a seventh conductivity type seventh MOS transistor having a drain and a gate connected to the drain of the second MOS transistor and the gate of the fifth transistor, and a source connected to the drain of the fourth MOS transistor. An output circuit characterized by that. The output circuit according to claim 1,
An output circuit, wherein each MOS transistor is replaced with a bipolar transistor, the gate is used as a base, the source is used as an emitter, and the drain is used as a collector.

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