JP2011141433A - Display device, method for driving the same and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of achieving high image quality, and to provide a method for driving the same and electronic equipment. <P>SOLUTION: When video signal voltage Vsig is written, a scanning line-driving circuit 23 finishes application of a selection pulse to a scanning line WSL in an application period of the video signal voltage Vsig. The application period is adjusted so that the application period of the selection pulse may be longer by delaying application finish timing of the selection pulse according as a distance from a signal line-driving circuit 24 in an extending direction of a signal line DTL to each pixel 11 gets longer. Variation of display luminance according to a pixel position is reduced or avoided, and deterioration in image quality (the occurrence of what is called a shading phenomenon in a perpendicular direction, or the occurrence of display irregularity) in accordance with the pixel position is reduced or avoided. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a display device that displays an image using a light-emitting element arranged for each pixel, a driving method thereof, and an electronic apparatus including such a display device.

  2. Description of the Related Art In recent years, in the field of display devices that perform image display, a display device (organic EL) that uses a current-driven optical element whose emission luminance changes according to a flowing current value, for example, an organic EL (Electro Luminescence) element, as a light-emitting element. Display devices) have been developed and commercialized.

  Unlike a liquid crystal element or the like, the organic EL element is a self-luminous element. Therefore, since the organic EL display device does not require a light source (backlight), the image visibility is high, the power consumption is low, and the response speed of the element is fast compared with a liquid crystal display device that requires a light source.

  In the organic EL display device, similarly to the liquid crystal display device, the driving method includes a simple (passive) matrix method and an active matrix method. Although the former has a simple structure, there is a problem that it is difficult to realize a large-sized and high-definition display device. Therefore, at present, the latter active matrix method is actively developed. In this method, the current flowing in the organic EL element arranged for each pixel is controlled by an active element (generally a TFT (Thin Film Transistor)) in a drive circuit provided for each organic EL element. .

  By the way, it is generally known that the current-voltage (IV) characteristics of an organic EL element deteriorate (deteriorate with time) as time elapses. In a pixel circuit that current-drives an organic EL element, when the IV characteristic of the organic EL element changes with time, the current value that flows through the drive transistor changes. Therefore, the current value that flows through the organic EL element itself also changes. The emission brightness also changes.

  Further, the threshold voltage Vth and mobility μ of the driving transistor may change with time, or the threshold voltage Vth and mobility μ may vary from pixel circuit to pixel circuit due to variations in manufacturing processes. When the threshold voltage Vth and mobility μ of the driving transistor are different for each pixel circuit, the value of the current flowing through the driving transistor varies for each pixel circuit. For this reason, even if the same voltage is applied to the gate of the driving transistor, the light emission luminance of the organic EL element varies, and the uniformity of the screen is impaired.

  Therefore, even if the IV characteristic of the organic EL element changes with time, or the threshold voltage Vth or mobility μ of the driving transistor changes with time or differs for each pixel circuit, the organic EL element is not affected by the change. Proposals have been made to keep the light emission luminance of the EL element constant. Specifically, a display device is proposed that incorporates a compensation function for variations in IV characteristics of organic EL elements and a correction function for variations in threshold voltage Vth and mobility μ of the drive transistor (for example, a patent). Reference 1).

JP 2008-33193 A

  By the way, especially in a large display panel, as the distance from the data driver to the pixel increases, the waveform of the signal pulse of the video signal voltage may be lost due to wiring resistance or capacitance in the signal line. Many. Specifically, a pixel with a small distance from the data driver (a pixel near the signal input end) has a sharp rise and fall of the signal pulse, while a pixel with a large distance (a pixel near the panel end) The rise and fall of the signal pulse will be smooth.

  As described above, when the signal pulse waveform varies depending on the pixel position in the display panel, the substantial length of the video signal writing period varies depending on the pixel position due to the difference in the pulse waveform. There is. In that case, the display luminance varies depending on the pixel position (so-called shading phenomenon or display unevenness) occurs, and the display image quality is deteriorated. Such a problem is not limited to the organic EL display device, and can occur in other display devices using self-luminous elements.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a display device capable of achieving high image quality, a driving method thereof, and an electronic device.

  In the display device of the present invention, a plurality of pixels each including a light emitting element, a scanning line and a signal line connected to each pixel, and a selection pulse for sequentially selecting the plurality of pixels with respect to the scanning line are applied. A scanning line driving circuit and a signal line driving circuit for writing a video signal to a pixel selected by the scanning line driving circuit by applying a video signal voltage to the signal line are provided. Here, the scanning line driving circuit ends the application of the selection pulse within the application period of the video signal voltage, and the distance from the signal line driving circuit to each pixel along the extending direction of the signal line increases. Accordingly, the application period is adjusted so that the application period of the selection pulse becomes longer by delaying the application end timing of the selection pulse.

  An electronic apparatus according to the present invention includes the display device according to the present invention.

  The display device driving method according to the present invention includes a light emitting element, for sequentially selecting a plurality of pixels with respect to a scanning line when driving a plurality of pixels connected to the scanning line and the signal line. The video signal is written to the selected pixel by applying the video signal voltage to the signal line while applying the selection pulse, and the video signal voltage is selected during the video signal writing period. When the pulse application is finished and the distance from the drive circuit of this signal line to each pixel along the extending direction of the signal line increases, the selection pulse application finishes at a later timing, thereby selecting pulse. The application period is adjusted so that the application period becomes longer.

  In the display device, the driving method thereof, and the electronic apparatus of the present invention, a video signal voltage is applied to the signal line while a selection pulse for sequentially selecting a plurality of pixels is applied to the scanning line. A video signal is written to the selected pixel. At this time, application of the selection pulse is completed within the application period of the video signal voltage, whereby the end timing of the video signal writing period is defined by the application end timing of the selection pulse. Here, as the distance from the signal line driver circuit to each pixel along the extending direction of the signal line increases, the selection pulse application period becomes longer as the selection pulse application end timing is delayed. Thus, the application period is adjusted. This suppresses (or avoids) variations due to pixel positions in the apparatus in the length of the video signal writing period. That is, since the end timing of the video signal writing period is adjusted to be delayed as the distance increases, the pulse waveform of the video signal voltage (specifically, as the distance increases). Specifically, even when the video signal writing start timing is delayed due to the rise of the rising waveform), the length of the actual video signal writing period is substantially constant regardless of the pixel position. (A difference due to the pixel position of the length of the actual video signal writing period is reduced or avoided). As a result, variations in display luminance due to pixel positions (occurrence of so-called shading phenomenon and occurrence of display unevenness) are reduced or avoided.

  According to the display device, the driving method thereof, and the electronic apparatus of the present invention, at the time of writing the video signal, the application of the selection pulse is finished within the application period of the video signal voltage, and the signal line along the extending direction of the signal line As the distance from the drive circuit to each pixel increases, the application period is adjusted so that the application period of the selection pulse becomes longer by delaying the application end timing of the selection pulse. The variation due to the pixel position can be reduced or avoided. Therefore, image quality deterioration according to the pixel position can be reduced or avoided, and high image quality can be achieved.

It is a block diagram showing an example of the display apparatus which concerns on the 1st Embodiment of this invention. FIG. 2 is a circuit diagram illustrating an example of an internal configuration of each pixel illustrated in FIG. 1. FIG. 2 is a circuit diagram illustrating a detailed configuration example of a main part of the scanning line driving circuit illustrated in FIG. 1. FIG. 6 is a timing waveform diagram illustrating an example of operation of the display device according to the first embodiment. FIG. 5 is a circuit diagram illustrating an example of an operation state in the operation of the display device illustrated in FIG. 4. FIG. 6 is a circuit diagram illustrating an example of an operation state following FIG. 5. FIG. 7 is a circuit diagram illustrating an example of an operation state following FIG. 6. It is a characteristic view for demonstrating the time-dependent deterioration of the IV characteristic in a display apparatus. FIG. 8 is a circuit diagram illustrating an example of an operation state following FIG. 7. It is a characteristic view showing an example of the time change of the source potential in a drive transistor. FIG. 10 is a circuit diagram illustrating an example of an operation state following FIG. 9. FIG. 12 is a circuit diagram illustrating an example of an operation state following FIG. 11. It is a characteristic view showing an example of the relationship between the time change of the source potential and the mobility in the drive transistor. FIG. 13 is a circuit diagram illustrating an example of an operation state following FIG. 12. It is a figure for demonstrating the difference in the voltage waveform of the signal line | wire in the signal input end of a display panel, and a panel end. 12 is a characteristic diagram for explaining a video signal writing period at a signal input end, a middle region, and a panel end of a display panel in a display device according to Comparative Example 1. FIG. 12 is a characteristic diagram for explaining video signal writing periods at a signal input end, a middle region, and a panel end of a display panel in a display device according to Comparative Example 2. FIG. It is a schematic diagram for demonstrating the display image quality in the display panel which concerns on the comparative example 2 and 1st Embodiment. FIG. 4 is a timing waveform diagram illustrating an example of the operation of the scanning line driving circuit illustrated in FIG. 3. FIG. 6 is a characteristic diagram for explaining a video signal writing period at a signal input end, a middle region, and a panel end of the display panel in the display device according to the first embodiment. It is a schematic diagram showing an example of the some division | segmentation display area in a display panel. It is a timing waveform diagram showing an example of the operation of the display device according to the second embodiment. FIG. 11 is a characteristic diagram for explaining a video signal writing period at a signal input end, a middle region, and a panel end of a display panel in a display device according to Comparative Example 3. FIG. 10 is a characteristic diagram for explaining a video signal writing period at a signal input end, a middle region, and a panel end of a display panel in a display device according to a second embodiment. It is a timing waveform diagram for comparing and explaining an example of the length of one vertical period according to the first and second embodiments. It is a top view showing schematic structure of the module containing the display apparatus of 1st and 2nd embodiment. It is a perspective view showing the external appearance of the application example 1 of the display apparatus of 1st and 2nd embodiment. (A) is a perspective view showing the external appearance seen from the front side of the application example 2, (B) is a perspective view showing the external appearance seen from the back side. 12 is a perspective view illustrating an appearance of application example 3. FIG. 14 is a perspective view illustrating an appearance of application example 4. FIG. (A) is a front view of the application example 5 in an open state, (B) is a side view thereof, (C) is a front view in a closed state, (D) is a left side view, and (E) is a right side view, (F) is a top view and (G) is a bottom view.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The description will be given in the following order.

1. First Embodiment (Example in which video signal writing period is defined by rising and falling timings of scanning line voltage)
2. Second Embodiment (Example in which video signal writing period is defined by signal line voltage rise timing and scan line voltage fall timing)
3. Module and application example 4. Modified example

<First Embodiment>
[Configuration of display device]
FIG. 1 is a block diagram showing a schematic configuration of a display device (display device 1) according to a first embodiment of the present invention. The display device 1 includes a display panel 10 (display unit) and a drive circuit 20.

(Display panel 10)
The display panel 10 includes a pixel array unit 13 in which a plurality of pixels 11 are arranged in a matrix, and performs image display by active matrix driving based on a video signal 20A and a synchronization signal 20B input from the outside. Is. Here, each pixel 11 includes a red pixel 11R, a green pixel 11G, and a blue pixel 11B. Hereinafter, the pixel 11 is appropriately used as a general term for the pixels 11R, 11G, and 11B.

  The pixel array unit 13 also includes a plurality of scanning lines WSL arranged in rows, a plurality of signal lines DTL arranged in columns, and a plurality of power supply lines DSL arranged in rows along the scanning lines WSL. Have. One end side of each of the scanning line WSL, the signal line DTL, and the power supply line DSL is connected to a drive circuit 20 described later. The pixels 11R, 11G, and 11B described above are arranged in a matrix (matrix arrangement) corresponding to the intersections between the scanning lines WSL and the signal lines DTL.

  FIG. 2 illustrates an example of the internal configuration of the pixels 11R, 11G, and 11B. In the pixels 11R, 11G, and 11B, organic EL elements 12R, 12G, and 12B (light emitting elements) and a pixel circuit 14 are provided. Hereinafter, the organic EL element 12 is appropriately used as a general term for the organic EL elements 12R, 12G, and 12B.

  The pixel circuit 14 includes a writing (sampling) transistor Tr1 (first transistor), a driving transistor Tr2 (second transistor), and a storage capacitor element Cs, and has a so-called “2Tr1C” circuit configuration. ing. Here, each of the write transistor Tr1 and the drive transistor Tr2 is formed of, for example, an n-channel MOS (Metal Oxide Semiconductor) TFT. The type of TFT is not particularly limited, and may be, for example, an inverted stagger structure (so-called bottom gate type) or a stagger structure (so-called top gate type).

  In this pixel circuit 14, the gate of the writing transistor Tr1 is connected to the scanning line WSL, the drain is connected to the signal line DTL, and the source is connected to the gate of the driving transistor Tr2 and one end of the storage capacitor element Cs. The drain of the drive transistor Tr2 is connected to the power supply line DSL, and the source is connected to the other end of the storage capacitor element Cs and the anode of the organic EL element 12. The cathode of the organic EL element 12 is set to a fixed potential, and here is set to the ground (ground potential) by being connected to the ground line GND. Note that the cathode of the organic EL element 12 functions as a common electrode of the organic EL elements 12, and is formed continuously over the entire display region of the display panel 10 to form a flat electrode, for example. Yes.

(Drive circuit 20)
The drive circuit 20 drives the pixel array unit 13 (display panel 10) (performs display drive). Specifically, although details will be described later, a video signal voltage based on the video signal 20A is applied to the selected pixel 11 while sequentially selecting a plurality of pixels 11 (11R, 11G, 11B) in the pixel array unit 13. By writing, display driving is performed on the plurality of pixels 11. As shown in FIG. 1, the drive circuit 20 includes a video signal processing circuit 21, a timing generation circuit 22, a scanning line drive circuit 23, a signal line drive circuit 24, and a power supply line drive circuit 25.

  The video signal processing circuit 21 performs predetermined correction on the digital video signal 20A input from the outside, and outputs the corrected video signal 21A to the signal line drive circuit 24. Examples of the predetermined correction include gamma correction and overdrive correction.

  The timing generation circuit 22 generates and outputs a control signal 22A based on a synchronization signal 20B input from the outside, whereby the scanning line driving circuit 23, the signal line driving circuit 24, and the power supply line driving circuit 25 are interlocked. Control to operate.

  The scanning line driving circuit 23 sequentially selects a plurality of pixels 11 (11R, 11G, 11B) by sequentially applying selection pulses to the plurality of scanning lines WSL according to (synchronously) the control signal 22A. is there. Specifically, the voltage Von to be applied when the write transistor Tr1 is set to the on state and the voltage Voff to be applied when the write transistor Tr1 is set to the off state are selectively output to thereby select the above-described selection. A pulse is generated. Note that the voltage Von is a value (a constant value) equal to or higher than the on-voltage of the write transistor Tr1, and the voltage Voff is a value (a constant value) lower than the on-voltage of the write transistor Tr1.

  Here, the scanning line driving circuit 23 starts application of a selection pulse after application of a video signal voltage (video signal voltage Vsig, which will be described later) starts, as will be described in detail later, and within the application period of the video signal voltage. The application of the selection pulse is terminated. Further, as the distance from the signal line driving circuit 24 to each pixel 11 along the extending direction (vertical direction (V direction)) of the signal line DTL increases, the selection pulse application period described later is adjusted. The operation is to be performed.

  FIG. 3 is a circuit diagram showing a detailed configuration example of the main part of the scanning line driving circuit 23. The scanning line driving circuit 23 includes a shift register 231, n (n: integer of 2 or more) logical product (3AND) circuits 232-1 to 232-n corresponding to the number of scanning lines WSL, Buffer circuits 233-1 to 233-n are included. Further, as shown in the figure, the scanning line driving circuit 23 is supplied with a clock signal ck, a clock inversion signal xck, a start pulse signal sp, and an enable signal en as the control signal 22A.

  The shift register 231 is configured by alternately arranging two types of flip-flop (FF) circuits 231A and 231B. In the drawing, the FF circuit 231A is shown as “FFa” and the FF circuit 231B is shown as “FFb”. The FF circuits 231A and 231B are configured to receive the clock signal ck, the clock inversion signal xck, the start pulse signal sp, or the output signal of the preceding FF circuit, respectively.

  As shown in the figure, the AND circuit 232-1 includes an output pulse signal SRout1 from the first stage FF circuit 231A and an output pulse signal SRout2 from the second stage FF circuit 231B in the shift register 231. The enable signal en is input. Similarly, the AND circuit 232-2 includes an output pulse signal SRout2 from the second stage FF circuit 231B, an output pulse signal from the third stage FF circuit 231A, and an enable signal en in the shift register 231. Have been entered. The AND circuit 232- (n−1) includes an output pulse signal from the (n−1) th stage FF circuit 231B in the shift register 231, an output pulse signal SRoutn from the nth stage FF circuit 231A, and An enable signal en is input. The AND circuit 232-n includes an output pulse signal SRoutn from the nth stage FF circuit 231A in the shift register 231 and an output pulse signal SRout (n + 1) from the (n + 1) th stage (final stage) FF circuit 231B. And an enable signal en.

  The output signals from the AND circuits 232-1 to 232-n are input to the buffer circuits 233-1 to 232-n, respectively. Output lines from these buffer circuits 233-1 to 233-n are scanning lines WSL 1 to WSLn as a plurality of scanning lines WSL, respectively.

  The signal line drive circuit 24 generates an analog video signal corresponding to the video signal 21A input from the video signal processing circuit 21 according to the control signal 22A (synchronously), and applies it to each signal line DTL. . Specifically, by applying an analog video signal voltage based on the video signal 21A to each signal line DTL, the pixel 11 (11R, 11G, 11B), a video signal is written. Note that writing the video signal means applying a predetermined voltage between the gate and source of the drive transistor Tr2.

  The signal line driving circuit 24 can output two kinds of voltages, that is, a video signal voltage Vsig based on the video signal 20A and a reference voltage Vofs. ) The signal lines DTL are alternately applied to each period. Here, the reference voltage Vofs is a voltage applied to the gate of the drive transistor Tr2 when the organic EL element 12 is extinguished. Specifically, the reference voltage Vofs is obtained from a voltage value (Vthel + Vcat) obtained by adding (Vofs−Vth) the threshold voltage Vthel and the cathode voltage Vcat in the organic EL element 12 when the threshold voltage of the driving transistor Tr2 is Vth. Is set to be a low voltage value (constant value).

  The power supply line driving circuit 25 controls the light emitting operation and the quenching operation of each organic EL element 12 by sequentially applying control pulses to the plurality of power supply lines DSL in accordance with (in synchronization with) the control signal 22A. It is. Specifically, by selectively outputting the voltage Vcc applied when the current Id is supplied to the drive transistor Tr2 and the voltage Vini applied when the current Ids is not supplied to the drive transistor Tr2, the control pulse described above is output. Is supposed to generate. Here, the voltage Vini is set to be a voltage value (constant value) lower than a voltage value (Vthel + Vcat) obtained by adding the threshold voltage Vthel and the cathode voltage Vcat in the organic EL element 12. On the other hand, the voltage Vcc is set to be a voltage value (constant value) equal to or higher than the voltage value (Vthel + Vcat).

[Operation and effect of display device]
Then, the effect | action and effect of the display apparatus 1 of this Embodiment are demonstrated.

(1. Outline of display operation)
In this display device 1, as shown in FIGS. 1 and 2, the drive circuit 20 applies video signals 20 </ b> A and 20 </ b> A to each pixel 11 (11 </ b> R, 11 </ b> G, 11 </ b> B) in the display panel 10 (pixel array unit 13). Display driving based on the synchronization signal 20B is performed. As a result, a drive current is injected into the organic EL element 12 in each pixel 11, and holes and electrons are recombined to emit light. The light emitted by this light emission is multiple-reflected between an anode (not shown) and a cathode (not shown) in the organic EL element 12, and passes through the cathode and is extracted outside. As a result, the display panel 10 displays an image based on the video signal 20A.

(2. Details of display operation)
FIG. 4 is a timing chart showing an example of various waveforms during the display operation in the display device 1 (in the display drive by the drive circuit 20). Here, FIGS. 4A to 4C show voltage waveforms of the scanning line WSL, the power supply line DSL, and the signal line DTL, respectively. Specifically, the voltage of the scanning line WSL periodically changes between the voltages Voff and Von (FIG. 4A), and the voltage of the power supply line DSL is between the voltages Vcc and Vini. A state of periodically changing (FIG. 4B) and a state of the voltage of the signal line DTL periodically changing between the reference voltage Vofs and the video signal voltage Vsig (FIG. 4C). And respectively. 4D and 4E show waveforms of the gate potential Vg and the source potential Vs in the drive transistor Tr2, respectively.

(Light emission period T0: before t1)
First, in the light emission period T0 of the organic EL element 12, the voltage of the scanning line WSL, the voltage of the power supply line DSL, and the voltage of the signal line DTL are the voltage Voff, the voltage Vcc, and the video signal voltage Vsig, respectively (FIG. 4 ( A) to (C)). Therefore, as shown in FIG. 5, the write transistor Tr1 is set to an off state. At this time, since the drive transistor Tr2 is set to operate in the saturation region, the current Ids flowing through the drive transistor Tr2 and the organic EL element 12 can be expressed by the following equation (1). In the equation (1), μ, W, L, Cox, Vgs, and Vth are mobility, channel width, channel length, gate oxide film capacity per unit area, and gate-source voltage in the drive transistor Tr2, respectively. (Refer FIG. 5) and the threshold voltage is shown.
Ids = (1/2) × μ × (W / L) × Cox × (Vgs−Vth) (1)

(Vth correction preparation period T1: t1 to t4)
Next, the drive circuit 20 ends the light emission period T0 at timing t1, and prepares for correction of the threshold voltage Vth (Vth correction) in the drive transistor Tr2 in each pixel 11. Specifically, first, at the timing t1, the power supply line drive circuit 25 lowers the voltage of the power supply line DSL from the voltage Vcc to the voltage Vini (FIG. 4B). Then, the source potential Vs of the driving transistor Tr2 is lowered and finally becomes a voltage Vini corresponding to the voltage of the power supply line DSL (FIG. 4E). Further, the gate potential Vg of the drive transistor Tr2 also falls due to capacitive coupling via the storage capacitor element Cs as the source potential Vs falls (see current Ia in FIG. 4D and FIG. 6). . For this reason, the anode voltage (voltage Vini) of the organic EL element 12 becomes smaller than the voltage value (Vthel + Vcat) obtained by adding the threshold voltage Vthel and the cathode voltage Vcat in the organic EL element 12, and the current between the anode and the cathode is reduced. Id stops flowing. As a result, after this timing t1, the organic EL element 12 is extinguished (shifts to the following extinction period T10). Note that a period from timing t1 to timing t8 at which a light emission operation described later is started is an extinction period T10 in which the organic EL element 12 is in the extinction state.

  Next, at the timing t2, the signal line driving circuit 24 lowers the voltage of the signal line DTL from the video signal voltage Vsig to the reference voltage Vofs (FIG. 4C). Then, the scanning line driving circuit 23 detects that the voltage of the scanning line WSL at timings t3 to t4 during a period in which the voltage of the signal line DTL is the reference voltage Vofs and the voltage of the power supply line DSL is the voltage Vini. Is set to be raised from the voltage Voff to the voltage Von (FIG. 4A). As a result, as shown in FIG. 7, the write transistor Tr1 is turned on and the current Ib flows, so that the gate potential Vg of the drive transistor Tr2 finally corresponds to the voltage of the signal line DTL at this time. The reference voltage Vofs is obtained (FIG. 4D). Then, as shown in FIG. 4, the gate-source voltage Vgs (= Vofs−Vini) in the driving transistor Tr2 at this time becomes larger than the threshold voltage Vth of the driving transistor Tr2 (Vgs> Vth). ), Preparation for Vth correction described below is completed.

(Vth correction period T2: t4 to t5)
Next, the drive circuit 20 performs Vth correction in the drive transistor Tr2. For example, as shown in FIG. 8, even when the threshold voltage Vth of the drive transistor Tr2 varies from pixel 11 to pixel 11 due to deterioration of IV characteristics over time, the light emission luminance of the organic EL element 12 is high. This is for reducing or avoiding variations.

  Specifically, first, at the timing t4 during the period in which the voltage of the signal line DTL is the reference voltage Vofs and the voltage of the scanning line WSL is the voltage Von, the power supply line driving circuit 25 is connected to the power supply line DSL. Is raised from the voltage Vini to the voltage Vcc (FIG. 4B). Then, as shown in FIG. 9, a current Ic flows between the drain and source of the drive transistor Tr2, and the source potential Vs rises (see FIGS. 4E and 10). As shown in FIG. 9, the organic EL element 12 can represent an equivalent circuit by a parallel circuit of a diode component Di and a capacitance component Cel.

  At this time, as shown in FIG. 10, when the source potential Vs of the drive transistor Tr2 is lower than the voltage value (Vofs (= Vg) −Vth) (Vs <(Vg−Vth)), in other words, the gate− When the source-to-source voltage Vgs is still larger than the threshold voltage Vth (Vgs> Vth; Vth correction is not yet completed), the voltage across the storage capacitor Cs is generated by the current Ic shown in FIG. Is charged to a threshold voltage Vth. That is, until the drive transistor Tr2 is cut off (until Vgs = Vth), the current Ic flows between the drain and source of the drive transistor Tr2, and the source potential Vs rises (FIG. 4E). Here, as shown in FIG. 4, Vgs = Vth at timing t5 at the end of the Vth correction period T2, and Vth correction is completed.

  Thereafter, the scanning line drive circuit 23 changes the voltage of the scanning line WSL from the voltage Von to the voltage Von at the timing t5 during the period in which the voltages of the signal line DTL and the power supply line DSL are maintained as the reference voltage Vofs and the voltage Vcc, respectively. The voltage is lowered to Voff (FIG. 4A). As a result, as shown in FIG. 11, since the write transistor Tr1 is turned off, the gate of the drive transistor Tr2 becomes floating, and the Vth correction is stopped (the process proceeds to the following Vth correction pause period T3). As a result, the gate-source voltage Vgs is held at the threshold voltage Vth regardless of the subsequent voltage of the signal line DTL.

(Vth correction suspension period T3: t5 to t7)
In the Vth correction suspension period T3, the signal line drive circuit 24 operates the signal line DTL at timing t6 during the period when the voltage of the scanning line WSL is the voltage Voff and the voltage of the power supply line DSL is the voltage Vcc. Is increased from the reference voltage Vofs to the video signal voltage Vsig (FIG. 4C). Then, at timing t6, a shift is made to a mobility correction / signal writing period T4 described below.

  In this way, by setting the gate-source voltage Vgs to the threshold voltage Vth in the Vth correction period T2 and the Vth correction pause period T3 (by performing Vth correction), the following effects can be obtained. That is, even when the threshold voltage Vth of the drive transistor Tr2 varies for each pixel 11 (11R, 11G, 11B) due to deterioration of IV characteristics over time (see FIG. 8), the light emission of the organic EL element 12 It is possible to avoid variations in luminance.

(Mobility correction / signal writing period T4: t7 to t8)
Next, as described below, the drive circuit 20 corrects the mobility μ (mobility correction) in the drive transistor Tr2 while writing the video signal voltage Vsig (writing the video signal). Specifically, first, at a timing t7 during a period in which the voltage of the signal line DTL is the video signal voltage Vsig and the voltage of the power supply line DSL is the voltage Vcc, the scanning line driving circuit 23 scans. The voltage of the line WSL is increased from the voltage Voff to the voltage Von (FIG. 4A). As a result, the write transistor Tr1 is turned on as shown in FIG. 12, and the gate potential Vg of the drive transistor Tr2 corresponds to the voltage of the signal line DTL at this time from the reference voltage Vofs by the current Id. The voltage rises to the video signal voltage Vsig (FIG. 4D).

  At this time, since the anode voltage of the organic EL element 12 is still smaller than the voltage value (Vthel + Vcat) obtained by adding the threshold voltage Vthel and the cathode voltage Vcat in the organic EL element 12 at this stage, the organic EL element 12 is cut. It is off. That is, at this stage, no current flows between the anode and the cathode of the organic EL element 12 (the organic EL element 12 does not emit light). Therefore, the current Ie supplied from the drive transistor Tr2 flows to the capacitive component Cel existing in parallel between the anode and the cathode of the organic EL element 12, and the capacitive component Cel is charged. As a result, the source potential Vs of the drive transistor Tr2 increases by the potential difference ΔV (FIG. 4E), and the gate-source voltage Vgs becomes (Vsig + Vth−ΔV).

  At this time, for example, as shown in FIG. 13, when the mobility μ of the drive transistor Tr2 is large, the increase in the source potential Vs (potential difference ΔV) also increases. Therefore, as described above, the gate-source voltage Vgs is reduced by this potential difference ΔV before light emission, which will be described later (by applying feedback), thereby removing variations in mobility μ for each pixel 11. Can do.

(Light emission period T8 (T0): after t8)
Next, at timing t8 during a period in which the voltage of the signal line DTL and the power supply line DSL is maintained as the video signal voltage Vsig and the voltage Vcc, the scanning line driving circuit 23 changes the voltage of the scanning line WSL to the voltage Von. To the voltage Voff (FIG. 4A). As a result, as shown in FIG. 14, the write transistor Tr1 is turned off, and the gate of the drive transistor Tr2 becomes floating. Then, a current Ids flows between the drain and source of the drive transistor Tr2 in a state where the gate-source voltage Vgs of the drive transistor Tr2 is kept constant. As a result, the source potential Vs of the drive transistor Tr2 rises (FIG. 4E), and the gate potential Vg of the drive transistor Tr2 also rises in conjunction with the capacitive coupling via the storage capacitor element Cs. (FIG. 4D).

  As a result, the anode voltage of the organic EL element 12 becomes larger than the voltage value (Vthel + Vcat) obtained by adding the threshold voltage Vthel and the cathode voltage Vcat in the organic EL element 12. In other words, the source potential Vs of the drive transistor Tr2 rises to the voltage Vx (FIG. 4E). Therefore, the current Ids flows between the anode and the cathode of the organic EL element 12, and the organic EL element 12 emits light with a desired luminance (light emission period T8 (T0)). Thereafter, at the timing t9, the signal line driving circuit 24 reduces the voltage of the signal line DTL from the video signal voltage Vsig to the reference voltage Vofs.

(repetition)
After that, the drive circuit 20 performs display drive so that the periods T1 to T5 (T0) described so far are periodically repeated for each frame period. At the same time, the drive circuit 20 scans the selection pulse applied to the power supply line DSL and the control pulse applied to the scanning line WSL in the row direction, for example, every one horizontal period (1H period). As described above, the display operation in the display device 1 (display drive by the drive circuit 20) is performed.

(3. Selection pulse application period adjustment operation)
Subsequently, a comparative example (Comparative Examples 1 and 2) regarding the adjustment operation of the selection pulse application period by the scanning line driving circuit 23, which is one of the characteristic parts in the display operation of the display device 1 of the present embodiment. ) And will be described in detail.

  First, as shown in FIG. 15, for example, in the case of a large display panel 10, as the distance from the signal line driving circuit 24 to the pixel 11 (the distance in the vertical direction (V direction)) increases, The signal pulse waveform of the signal voltage Vsig is often distorted. Specifically, as shown in the figure, the rise and fall of the signal pulse PLSn are steep in the pixel having a small distance from the signal line driving circuit 24 (pixel 11 near the signal input end). On the other hand, in the pixel having a large distance from the signal line driving circuit 24 (pixel 11 near the end of the panel), the rise and fall of the signal pulse PLSf becomes gentle.

  This is due to the following reason. That is, first, in the signal (control pulse) applied to the power supply line DSL, the high potential (voltage Vcc) and the low potential (voltage Vini) are switched within one horizontal period (1H period), so that the voltage drop, etc. Therefore, the power supply line DSL needs to be wired in the horizontal (horizontal) direction using a low resistance material. For this reason, the signal line DTL wired in the vertical (vertical) direction has a higher resistance than the power supply line DSL. As a result, due to wiring resistance and capacitance in the signal line DTL, the rounding of the signal pulse waveform of the video signal voltage Vsig becomes large.

  Here, in the present embodiment, as indicated by arrows and diagonal lines in FIGS. 4A and 4C, the length of the writing period of the video signal voltage Vsig is defined as follows. That is, it is defined by the rising timing (timing t7) and falling timing (timing t8) of the applied voltage (selection pulse) to the scanning line WSL within the application period (timing t6 to t9) of the video signal voltage Vsig. . In other words, it is defined by the timing at which the voltage applied to the scanning line WSL is switched from the voltage Voff to the voltage Von and the timing at which the voltage Von is subsequently switched to the voltage Voff. In other words, the start timing and end timing of the writing period of the video signal voltage Vsig are respectively defined by the application start timing and the application end timing of the selection pulse applied to the scanning line WSL. In this embodiment, the scanning line driving circuit 23 starts applying the selection pulse after starting the application of the video signal voltage Vsig, and ends the application of the selection pulse within the application period of the video signal voltage Vsig. It is because it is made to let it.

(Comparative Example 1)
For these reasons, for example, in the display device 101 according to the comparative example 1 shown in FIG. 16, the length of the actual video signal voltage Vsig writing period is substantially constant regardless of the pixel position in the display panel 10. Yes. That is, in the first comparative example, even when the waveform of the signal pulse of the video signal voltage Vsig on the signal line DTL differs depending on the pixel position in the display panel 10, the actual result caused by such a difference in the pulse waveform. There is almost no difference in the length of the writing period of the video signal voltage Vsig.

  Specifically, first, in the pixel P101n (pixel 11 near the signal input end) having a small distance from the signal line driving circuit 24, the rise and fall of the signal pulse of the video signal voltage Vsig is steep. Further, in the pixel P101m (intermediate position pixel 11) having a medium distance, the rising and falling edges of the signal pulse of the video signal voltage Vsig are somewhat smooth. In the pixel P101f (pixel 11 near the panel edge) having a large distance, the rise and fall of the signal pulse of the video signal voltage Vsig become large and gentle. However, in Comparative Example 1, the start timing t107 of the selection pulse applied from the scanning line driving circuit 103 to the scanning line WSL is after the rising of the signal pulse of the video signal voltage Vsig in the signal line DTL. Therefore, unlike Comparative Example 2 described below, the actual video signal voltage Vsig writing period is determined in each of the pixels P101n, P101m, and P101f regardless of the distance from the signal line driving circuit 24 to each pixel 11. The lengths ΔT104 are substantially equal to each other. Note that timings t102, t106, t107, t108, and t109 in FIG. 16 respectively correspond to timings t2, t6 to t9 shown in FIG.

(Comparative Example 2)
However, as in the display device 201 according to the comparative example 2 shown in FIG. 17, for example, the start timing t207 of the selection pulse applied from the scanning line driving circuit 203 to the scanning line WSL is equal to the video signal voltage Vsig on the signal line DTL. If the signal pulse rises before it occurs, the following problem occurs.

  Specifically, in the second comparative example, first, as in the first comparative example, in the pixel P201n (pixel 11 near the signal input end) whose distance from the signal line driving circuit 24 is small, the signal pulse of the video signal voltage Vsig is used. The rise and fall of is steep. In addition, in the pixel P201m (the pixel 11 at the intermediate position) having a medium distance, the rise and fall of the signal pulse of the video signal voltage Vsig become slightly smooth. Then, in the pixel P201f (pixel 11 near the panel end) having a large distance, the rise and fall of the signal pulse of the video signal voltage Vsig become large and gentle.

  Here, in the comparative example 2, in the pixels P201m and P201f, the start timing t207 of the selection pulse applied to the scanning line WSL is before the rise of the signal pulse of the video signal voltage Vsig in the signal line DTL. Yes. Therefore, in Comparative Example 2, the length of the actual video signal voltage Vsig writing period is shortened as the distance from the signal line driving circuit 24 to each pixel 11 is increased. Specifically, the lengths ΔT204n, ΔT204m, and ΔT204f of the actual video signal voltage Vsig writing period are gradually shortened in the order of the pixels P201n, P201m, and P201f in FIG. Note that timings t202, t206, t207, t208, and t209 in FIG. 17 respectively correspond to the timings t2, t6 to t9 shown in FIG.

  Thereby, in the comparative example 2, the length of the writing period of the video signal voltage Vsig differs depending on the pixel position in the display panel 10, and the display luminance also differs depending on the pixel position. Specifically, the pixel 11 closer to the panel end is shorter than the pixel 11 closer to the signal input end because the video signal voltage Vsig writing period is shorter (ΔT204n> ΔT204m> ΔT204f), so that the display luminance is relatively dark. Becomes lower). As a result, for example, as shown in FIG. 18A, a so-called shading phenomenon or display unevenness (see reference numeral P202 in the figure) occurs, and the display image quality deteriorates.

(This embodiment)
On the other hand, in the display device 1 according to the present embodiment, unlike the comparative examples 1 and 2, for example, as shown in FIGS. 19 and 20, the scanning line driving circuit 23 performs the selection pulse application period. The adjustment operation is performed to reduce or avoid the problem in the second comparative example. Here, FIG. 19 shows an example of the operation of the scanning line driving circuit 23 shown in FIG. 3 in a timing waveform diagram. Specifically, (A) is a clock signal ck, (B) is a start pulse signal sp, (C) to (F) are output pulse signals SRout1, SRout2, SRoutn, SRout (n + 1), (n + 1), ( G shows an enable signal en, and (H) and (I) show voltage waveforms of the scanning lines WSL1 and WSLn, respectively.

  In this scanning line driving circuit 23, first, in the shift register 231, the clock signal ck (FIG. 19A), the clock inversion signal xck and the start pulse sp (FIG. 19B) are input, and the output pulse signal SRout1, SRout2,..., SRoutn, SRout (n + 1) are output (FIGS. 19C to 19F). Next, in the AND circuits 232-1 to 232-n, two signals out of these output pulse signals SRout1, SRout2,..., SRoutn, SRout (n + 1) and the enable signal en (FIG. 19G). ) And a logical operation (3 AND operation).

  At this time, as shown in FIG. 19G, the enable signal en is pulsed by delaying the application end timing as the distance from the signal line driver circuit 24 to each scanning line WSL increases. It consists of a plurality of applied pulses configured to be longer in width. Specifically, compared to the pulse width Tenn of the applied pulse corresponding to the scanning line WSLn whose distance is small (near the signal input end), the applied pulse corresponding to the scanning line WSL1 whose distance is large (near the panel end). The pulse width Ten1 is longer. As a result, as shown in FIGS. 19H and 19I, in the scanning lines WSL1 to WSLn generated via the AND circuits 232-1 to 232-n and the buffer circuits 233-1 to 233-n. The following also applies to the selection pulse. That is, as the distance from the signal line driving circuit 24 to each scanning line WSL increases, the application end timing is delayed to increase the pulse width.

  For these reasons, in the present embodiment, the scanning line drive circuit 23 performs the adjustment operation of the application period of the selection pulse in the scanning line WSL, for example, as shown in FIG. That is, as the distance from the signal line driving circuit 24 to each pixel 11 along the extending direction (vertical direction (V direction)) of the signal line DTL increases, the application pulse finish timing of the selection pulse is delayed. Thus, the application period is adjusted so that the application period of the selection pulse becomes longer. Specifically, here, the scanning line driving circuit 23 adjusts the application period so that the application period of the selection pulse continuously (analogously) becomes longer as the distance increases. ing.

  More specifically, first, as in Comparative Examples 1 and 2, the pixel P1n (the pixel 11 near the signal input end) having a small distance from the signal line driving circuit 24 has a signal pulse of the video signal voltage Vsig. The rise and fall are steep. In addition, in the pixel P1m (intermediate position pixel 11) having an intermediate distance, the rise and fall of the signal pulse of the video signal voltage Vsig become slightly smooth. Then, in the pixel P1f (pixel 11 near the end of the panel) having a large distance, the rise and fall of the signal pulse of the video signal voltage Vsig become large and gentle.

  Here, also in the present embodiment, as in the comparative example 2, in the pixels P1m and P1f, the start timing t7 of the selection pulse applied to the scanning line WSL is the signal pulse of the video signal voltage Vsig on the signal line DTL. It is before the rise. However, in the present embodiment, unlike Comparative Example 2, as described above, the selection pulse application end timing is delayed as the distance from the signal line driving circuit 24 to each pixel 11 increases. The application period is adjusted so that the application period of the selection pulse becomes longer. Thereby, as will be described below, variations due to pixel positions in the display panel 10 in the length of the writing period of the video signal voltage Vsig are suppressed (or avoided).

  That is, here, the end timing of the writing period of the video signal voltage Vsig is adjusted so as to be delayed as the distance increases (see the double-lined arrow in FIG. 20). Therefore, as the distance increases, the write start timing of the video signal voltage Vsig is delayed by the pulse waveform (specifically, the rising waveform) of the video signal voltage Vsig being lost. However, the length of the actual video signal voltage Vsig writing period is substantially constant regardless of the pixel position. In other words, the difference due to the pixel position of the length of the actual video signal voltage Vsig writing period is reduced or avoided.

  Specifically, in FIG. 20, the writing start timing of the video signal voltage Vsig is delayed in the order of the pixels P1n, P1m, and P1f, while the writing end timing of the video signal voltage Vsig is adjusted to be delayed in this order. Has been. Accordingly, in any of the pixels P1n, P1m, and P1f, the length ΔT41 of the actual video signal voltage Vsig writing period is substantially constant. As a result, in the display device 1 of the present embodiment, as shown in FIG. 18B, for example, as compared with the comparative example 2, the display luminance varies depending on the pixel position (so-called shading phenomenon or display unevenness). Occurrence) is reduced or avoided. In general, when the luminance difference is within 10 to 20%, shading is not visually recognized in the entire panel. Therefore, the adjustment range of the application end timing in the selection pulse described above applies the video signal voltage Vsig to the signal line DTL. It may be shorter than the width of the period to be performed.

  Further, in FIGS. 19 and 20, the application period is adjusted so that the application period of the selection pulse continuously (analogously) becomes longer as the distance becomes larger. As the distance increases, the selection pulse application period may be adjusted stepwise (digitally).

  Specifically, in FIG. 21, for example, the scanning line driving circuit 23 adjusts the application period so that the application period of the selection pulse becomes longer in multiple steps as the distance increases. . That is, in this case, in the display panel 10, the selection pulse application period is increased in multiple steps in the order of the panel lower region 10n (signal input end side), the panel middle region 10m, and the panel upper region 10f (panel end side). As described above, the application period is adjusted. Even in such a configuration, as shown in FIG. 18C, for example, as compared with Comparative Example 2 described above, variation in display luminance due to the pixel position (occurrence of so-called shading phenomenon and occurrence of display unevenness) Reduced or avoided.

  As described above, in the present embodiment, the scanning line driving circuit 23 ends the application of the selection pulse to the scanning line WSL within the application period of the video signal voltage Vsig and writes the signal line DTL during the writing of the video signal voltage Vsig. As the distance from the signal line driving circuit 24 to each pixel 11 along the extending direction of each of the pixels 11 increases, the selection pulse application period is delayed so that the selection pulse application period is extended. Since the period is adjusted, variations in display luminance due to pixel positions can be reduced or avoided. Therefore, it is possible to reduce or avoid image quality deterioration (occurrence of a so-called shading phenomenon along the vertical direction and occurrence of display unevenness) according to the pixel position, and high image quality can be achieved.

  Further, as shown in FIGS. 3 and 19, the application period of the selection pulse as described above is adjusted only by adjusting the pulse widths of the plurality of applied pulses in the enable signal en input to the scanning line driving circuit 23. Therefore, the above-described effect can be obtained with a simple configuration (at low cost).

  Further, when the application period is adjusted so that the application period of the selection pulse continuously (analogously) increases as the distance from the signal line driving circuit 24 to each pixel 11 increases. Therefore, it is possible to suppress the image quality deterioration according to the pixel position described above with higher accuracy.

  On the other hand, when the application period is adjusted so that the application period of the selection pulse is increased stepwise (digitally) as the distance from the signal line driving circuit 24 to each pixel 11 increases. Since the adjustment of the pulse widths of the plurality of applied pulses in the enable signal en input to the scanning line driving circuit 23 is easier than in the case where the adjustment is made so as to be continuously (analogically) longer, The above-described effects can be obtained with a simple configuration (at a low cost).

<Second Embodiment>
Next, a second embodiment of the present invention will be described. In addition, the same code | symbol is attached | subjected to the same component as the said 1st Embodiment, and description is abbreviate | omitted suitably.

  FIG. 22 is a timing chart showing an example of various waveforms during the display operation in the display device (display device 1A) according to the present embodiment. Here, the types of voltage waveforms shown in FIGS. 22A to 22E are the same as those shown in FIGS. 4A to 4E in the first embodiment. The block configuration of the display device 1A and the configuration of the pixel circuit in the pixel 11 are basically the same as those in the first embodiment, and a description thereof will be omitted. The basic part of the display operation (period from timing t11 to t15) is the same as the display operation (part of timing t1 to t5) in the first embodiment shown in FIG. To do.

  In the present embodiment, unlike the first embodiment, the Vth correction pause period T3 is not provided between the Vth correction period T2 and the mobility correction / signal writing period T4. Therefore, the mobility correction / signal writing period T4 at the timings t15 to t16 corresponds to the mobility correction / signal writing period T4 at the timings t7 to t8 in the first embodiment. The light emission period T5 (T0) after the timing t16 corresponds to the light emission period T5 (T0) after the timing t8 in the first embodiment.

  Accordingly, in the present embodiment, unlike the first embodiment, the scanning line driving circuit 23A starts applying the selection pulse before starting the application of the video signal voltage Vsig, and this video signal. The application of the selection pulse is terminated within the application period of the voltage Vsig. Therefore, as indicated by the arrows and hatched lines in FIGS. 22A and 22C, in this embodiment, the length of the writing period of the video signal voltage Vsig is defined as follows. That is, it is defined by the application start timing (timing t15) of the video signal voltage Vsig and the falling timing (timing t16) of the applied voltage (selection pulse) to the scanning line WSL. In other words, it is defined by the timing at which the applied voltage to the signal line DTL switches from the reference voltage Vofs to the video signal voltage Vsig and the timing at which the applied voltage to the scanning line WSL subsequently switches from the voltage Von to the voltage Voff. In other words, the start timing and end timing of the writing period of the video signal voltage Vsig are respectively the application start timing of the video signal voltage Vsig to the signal line DTL, and the application end timing of the selection pulse applied to the scanning line WSL. It is prescribed by.

(Comparative Example 3)
Also in this case, for example, like the display device 301 according to the comparative example 3 shown in FIG. 23, the video signal voltage Vsig is written depending on the pixel position in the display panel 10 as in the comparative example 2 described above. The length of the period is different, and the display luminance may be different depending on the pixel position.

  Specifically, in Comparative Example 3, first, as in Comparative Examples 1 and 2, the pixel P301n (pixel 11 near the signal input end) having a small distance from the signal line driving circuit 24 has the video signal voltage Vsig. The rise and fall of the signal pulse are steep. In addition, in the pixel P301m (intermediate position pixel 11) having a medium distance, the rise and fall of the signal pulse of the video signal voltage Vsig become slightly smooth. In the pixel P301f (pixel 11 near the panel edge) having a large distance, the rising and falling edges of the signal pulse of the video signal voltage Vsig become large and gentle.

  Here, in Comparative Example 3, as described above, the start timing of the writing period of the video signal voltage Vsig is defined by the application start timing of the video signal voltage Vsig to the signal line DTL as described above. Therefore, as the distance from the signal line driving circuit 24 increases, the length of the actual video signal voltage Vsig writing period is shortened when the rise of the signal pulse of the video signal voltage Vsig becomes gentle. End up. Specifically, the lengths ΔT304n, ΔT304m, and ΔT304f of the actual video signal voltage Vsig writing period are gradually shortened in the order of the pixels P301n, P301m, and P301f in FIG. Note that timings t302, t303, t305, t306, and t307 in FIG. 23 correspond to timings t2, t3, and t5 to t7 shown in FIG. 22, respectively.

  Thereby, also in this comparative example 3, the length of the writing period of the video signal voltage Vsig differs depending on the pixel position in the display panel 10, and the display luminance also differs depending on the pixel position. Specifically, the pixel 11 closer to the panel end than the pixel 11 closer to the signal input end has a shorter writing period of the video signal voltage Vsig (ΔT304n> ΔT304m> ΔT304f), and therefore becomes relatively dark (display luminance). Becomes lower). As a result, like the comparative example 2, so-called shading phenomenon and display unevenness occur, and the display image quality deteriorates. Further, particularly in the present embodiment, unlike the first and second comparative examples, when the rise of the signal pulse of the video signal voltage Vsig becomes gentle as the distance from the signal line driving circuit 24 increases, Such a problem will always arise.

  On the other hand, in the present embodiment, as in the first embodiment, for example, as shown in FIG. 24, the scanning line driving circuit 23A performs the adjustment operation of the selection pulse application period. The problem in Comparative Example 3 is reduced or avoided. That is, as the distance from the signal line driving circuit 24 to each pixel 11 along the extending direction (vertical direction (V direction)) of the signal line DTL increases, the application pulse finish timing of the selection pulse is delayed. Thus, the application period is adjusted so that the application period of the selection pulse becomes longer.

  That is, the end timing of the video signal voltage Vsig writing period is adjusted so as to be delayed as the distance increases (see the double-lined arrow in FIG. 24). Therefore, as the distance increases, the write start timing of the video signal voltage Vsig is delayed by the pulse waveform (specifically, the rising waveform) of the video signal voltage Vsig being lost. However, the length of the actual video signal voltage Vsig writing period is substantially constant regardless of the pixel position. In other words, the difference due to the pixel position of the length of the actual video signal voltage Vsig writing period is reduced or avoided.

  Specifically, in FIG. 24, the video signal voltage Vsig write start timing is delayed in the order of the pixels P2n, P2m, and P2f, and the video signal voltage Vsig write end timing is adjusted to be delayed in this order. Has been. Therefore, in any of the pixels P2n, P2m, and P2f, the length ΔT42 of the actual video signal voltage Vsig writing period is substantially constant. As a result, also in the display device 1A of the present embodiment, as compared with the comparative example 3, the variation in display luminance due to the pixel position (occurrence of so-called shading phenomenon or display unevenness) is reduced or avoided.

  As described above, also in this embodiment, the same effect can be obtained by the same operation as that of the first embodiment. That is, it is possible to reduce or avoid image quality deterioration (occurrence of a so-called shading phenomenon along the vertical direction and occurrence of display unevenness) according to the pixel position, and high image quality can be achieved.

  Further, as described above, in the present embodiment, unlike the comparative examples 1 and 2 and the first embodiment, the video signal voltage Vsig is changed as the distance from the signal line driving circuit 24 increases. Such a problem may occur whenever the rising edge of the signal pulse becomes gentle. Therefore, it can be said that the advantage of suppressing the image quality deterioration according to the pixel position is particularly great.

  Further, in the present embodiment, the Vth correction pause period T3 is not provided, and the application of the selection pulse is started before the application of the video signal voltage Vsig is started, and the selection pulse is applied within the application period of the video signal voltage Vsig. Therefore, compared with the first embodiment, the length of one horizontal (1H) period can be shortened. Specifically, for example, compared with the length ΔTH1 of the 1H period in the first embodiment shown in FIGS. 25A and 25B, the second shown in FIGS. 25C and 25D, for example. The length ΔTH2 of the 1H period in the embodiment is shorter (ΔTH2 <ΔTH1). As a result, the writing of the video signal within the 1H period can be performed in a short time, so that the display panel 10 can be increased in size and definition, and the display drive speed can be increased.

<Modules and application examples>
Next, application examples of the display devices 1 and 1A described in the first and second embodiments will be described with reference to FIGS. The display device of each of the above embodiments can be applied to electronic devices in various fields such as a television device, a digital camera, a notebook personal computer, a mobile terminal device such as a mobile phone, or a video camera. In other words, these display devices can be applied to electronic devices in various fields that display a video signal input from the outside or a video signal generated inside as an image or video.

(module)
The display device of each of the above embodiments is incorporated into various electronic devices such as application examples 1 to 5 described later, for example, as a module shown in FIG. In this module, for example, a region 210 exposed from the sealing substrate 32 is provided on one side of the substrate 31, and the wiring of the drive circuit 20 is extended to the exposed region 210 to provide an external connection terminal (not shown). Formed. The external connection terminal may be provided with a flexible printed circuit (FPC) 220 for signal input / output.

(Application example 1)
FIG. 27 illustrates an appearance of a television device to which the display device of each of the above embodiments is applied. This television apparatus has, for example, a video display screen unit 300 including a front panel 310 and a filter glass 320, and the video display screen unit 300 is configured by the display device of each of the above embodiments.

(Application example 2)
FIG. 28 shows the appearance of a digital camera to which the display device of each of the above embodiments is applied. The digital camera includes, for example, a flash light emitting unit 410, a display unit 420, a menu switch 430, and a shutter button 440, and the display unit 420 is configured by the display device of each of the above embodiments.

(Application example 3)
FIG. 29 shows the appearance of a notebook personal computer to which the display device of each of the above embodiments is applied. This notebook personal computer has, for example, a main body 510, a keyboard 520 for inputting characters and the like, and a display unit 530 for displaying an image. This display unit 530 is obtained by the display device of each of the above embodiments. It is configured.

(Application example 4)
FIG. 30 shows the appearance of a video camera to which the display device of each of the above embodiments is applied. This video camera includes, for example, a main body 610, a subject photographing lens 620 provided on the front side surface of the main body 610, a start / stop switch 630 at the time of photographing, and a display 640. And this display part 640 is comprised by the display apparatus of said each embodiment.

(Application example 5)
FIG. 31 shows the appearance of a mobile phone to which the display device of each of the above embodiments is applied. For example, the mobile phone is obtained by connecting an upper housing 710 and a lower housing 720 with a connecting portion (hinge portion) 730, and includes a display 740, a sub-display 750, a picture light 760, and a camera 770. Yes. Of these, the display 740 or the sub-display 750 is configured by the display device of each of the above embodiments.

<Modification>
The present invention has been described above with some embodiments and application examples. However, the present invention is not limited to these embodiments and the like, and various modifications are possible.

  For example, in the above embodiment and the like, the case where the display device 1 is an active matrix type has been described. However, the configuration of the pixel circuit 14 for driving the active matrix is not limited to that described in the above embodiment and the like. . That is, a capacitor element, a transistor, or the like may be added to the pixel circuit 14 as necessary. In that case, a necessary drive circuit may be added in addition to the scanning line drive circuit 23, the signal line drive circuit 24, and the power supply line drive circuit 25 described above in accordance with the change of the pixel circuit 14.

  In the above-described embodiment and the like, the case where the timing generation circuit 22 controls the driving operation in the scanning line driving circuit 23, the signal line driving circuit 24, and the power supply line driving circuit 25 has been described. The drive operation may be controlled. The scanning line driving circuit 23, the signal line driving circuit 24, and the power supply line driving circuit 25 may be controlled by hardware (circuit) or software (program). May be.

  Furthermore, although the case where the pixel circuit 14 has a so-called “2Tr1C” circuit configuration has been described in the above embodiment and the like, the circuit configuration of the pixel circuit 14 is not limited to this. That is, as long as the transistor includes a circuit configuration connected in series to the organic EL element 12, the pixel circuit 14 may have a circuit configuration other than “2Tr1C”.

  In addition, in the above-described embodiment and the like, the case where the write transistor Tr1 and the drive transistor Tr2 are each formed by an n-channel transistor (for example, an n-channel MOS type TFT) has been described. However, the present invention is limited to this case. Absent. That is, each of the write transistor Tr1 and the drive transistor Tr2 may be formed of a p-channel transistor (for example, a p-channel MOS type TFT).

  DESCRIPTION OF SYMBOLS 1,1A ... Display apparatus, 10 ... Display panel, 10n ... Panel lower area (divided display area), 10m ... Panel middle area (divided display area), 10f ... Panel upper area (divided display area), 11, 11R, 11G , 11B: Pixel, 12, 12R, 12G, 12B ... Organic EL element, 13: Pixel array section, 14 ... Pixel circuit, 20 ... Drive circuit, 20A, 21A ... Video signal, 20B ... Synchronization signal, 21 ... Video signal processing Circuit, 22 ... Timing generation circuit, 22A ... Control signal, 23, 23A ... Scan line drive circuit, 231A, 231B ... Flip-flop (FF) circuit, 232-1 to 232-n ... Logical product (3AND) circuit, 233- 1-233-n ... buffer circuit, 24, 24 A ... signal line drive circuit, 25 ... power supply line drive circuit, WSL, WSL 1-WSLn ... scanning line, DTL ... signal Line, DSL ... Power supply line, Tr1 ... Write transistor, Tr2 ... Driving transistor, Cs ... Retention capacitor element, Di ... Diode component, Cel ... Capacitance component, Ids, Ia to Ie ... Current, Vg ... Gate potential, Vs ... Source potential , Vgs, gate-source voltage, Vth, threshold voltage, Vsig, video signal voltage, Vofs, Von, Voff, Vcc, Vini, Cx, voltage, ΔV, potential difference, ck, clock signal, xck, clock inverted signal, sp ... start pulse signal, en ... enable signal, SRout1, SRout2, SRoutn, SRout (n + 1) ... output pulse signal, PLSn, PLSf ... signal pulse, t1 to t9, t11 to t17 ... timing, T0, T5 ... light emission period, T1 ... Vth correction preparation period, T2 ... Vth correction period, T3 ... Vth correction pause period, T4 ... Mobility correction / signal writing period , T10 ... extinction period, ΔTen1, ΔTenn ... pulse width, ΔT41, ΔT42 ... signal write period, ΔTH1, ΔTH2 ... 1H (1 vertical) period.

Claims (10)

A plurality of pixels each including a light emitting element;
A scanning line and a signal line connected to each pixel;
A scanning line driving circuit that applies a selection pulse for sequentially selecting the plurality of pixels to the scanning line;
A signal line driving circuit for writing a video signal to the pixels selected by the scanning line driving circuit by applying a video signal voltage to the signal line;
The scanning line driving circuit includes:
Ending the application of the selection pulse within the application period of the video signal voltage,
As the distance from the signal line driver circuit to each pixel along the signal line extending direction increases, the selection pulse application period becomes longer by delaying the selection pulse application end timing. Display device for adjusting the application period. 2. The display according to claim 1, wherein the scanning line driving circuit starts application of the selection pulse before starting application of the video signal voltage, and ends application of the selection pulse within an application period of the video signal voltage. apparatus. 2. The display device according to claim 1, wherein the scanning line driving circuit starts application of the selection pulse after application of the video signal voltage is started, and ends application of the selection pulse within an application period of the video signal voltage. . The scanning line driving circuit adjusts the application period so that the application period of the selection pulse continuously increases as the distance increases. The display device described. The scanning line driving circuit adjusts the application period so that the application period of the selection pulse becomes longer stepwise as the distance becomes larger. The display device described. The scanning line driving circuit includes:
A shift register;
A plurality of pulse signals output from the shift register, and an enable signal composed of a plurality of applied pulses configured to increase the pulse width by delaying the application end timing as the distance increases. 4. The display device according to claim 1, further comprising: a plurality of logical product circuits that generate a selection pulse corresponding to each scanning line by performing a logical product operation. 5. A power line connected to each pixel;
The display according to any one of claims 1 to 3, further comprising: a power line driving circuit that applies a control pulse for controlling a light emitting operation and a quenching operation of the light emitting element to the power line. apparatus. Each pixel includes an organic electroluminescent element as the light emitting element, first and second transistors, and a storage capacitor element,
The gate of the first transistor is connected to the scan line;
One of the drain and the source in the first transistor is connected to the signal line, and the other is connected to the gate of the second transistor and one end of the storage capacitor element,
Of the drain and source in the second transistor, one is connected to the power line, and the other is connected to the other end of the storage capacitor element and the anode of the organic electroluminescence element,
The display device according to claim 7, wherein a cathode of the organic electroluminescent element is set to a fixed potential. Each of them includes a light emitting element, and when driving a plurality of pixels connected to the scanning line and the signal line,
A video signal is written to the selected pixel by applying a video signal voltage to the signal line while applying a selection pulse for sequentially selecting the plurality of pixels to the scanning line. Done
During the writing of the video signal, the application of the selection pulse is terminated within the application period of the video signal voltage,
As the distance from the signal line driving circuit to each pixel in the signal line extending direction increases, the selection pulse application end time is delayed, thereby extending the selection pulse application period. A method for driving a display device, in which the application period is adjusted. A display device,
The display device
A plurality of pixels each including a light emitting element;
A scanning line and a signal line connected to each pixel;
A scanning line driving circuit that applies a selection pulse for sequentially selecting the plurality of pixels to the scanning line;
A signal line driving circuit for writing a video signal to the pixels selected by the scanning line driving circuit by applying a video signal voltage to the signal line;
The scanning line driving circuit includes:
Ending the application of the selection pulse within the application period of the video signal voltage,
As the distance from the signal line driver circuit to each pixel along the signal line extending direction increases, the selection pulse application period becomes longer by delaying the selection pulse application end timing. Electronic devices that adjust the application period.

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