JP2011139177A - Reception device and communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reception device and a communication system which do not cause the deterioration of the execution efficiency of main processing by noise on a transmission route, and do not need an external interruption port for communication processing in a CPU etc. <P>SOLUTION: The CPU 11 prepares a first sampling unit 21 and a second sampling unit 22, and the first sampling unit 21 and the second sampling unit 22 perform the sampling of a binary signal input to an input port 11a in a sampling period which is equal to a bit width of each bit of a preamble and in timing shifted temporally by a half of the bit width. When at least one of the first sampling unit 21 and the second sampling unit 22 detects the preamble, the CPU 11 can start the reception of the data. A remote controller 3 and a UHF reception IC 12 send signals to the CPU 11 so that an error of the preamble falls within an allowable range. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  According to the present invention, in digital communication such as serial communication, data reception is performed by detecting a predetermined number of repetitions of a high level / low level of a binary signal (digital signal) output from a transmission device prior to the start of data transmission / reception. The present invention relates to a receiving apparatus that starts processing, and a communication system including the receiving apparatus.

  Conventionally, in a relatively small electronic device, a processing device such as a CPU (Central Processing Unit) or a microcomputer (microcomputer) transmits and receives data between a control program for controlling the operation of the device and another device. In many cases, a communication program is executed. In this case, the processing device mainly performs processing related to device operation control by execution of the control program, and effectively uses the processing capability of the processing device by performing communication processing with other devices as interrupt processing or the like. be able to.

  In Patent Document 1, a microcomputer having a small number of processing bits coexists with a program for controlling device operation and a program for controlling communication, and there is little decrease in execution efficiency of main processing due to interrupt processing. A serial data transmission system capable of high-speed data transmission and a low bit error rate has been proposed. In this system, the CPU on the receiving side performs external interrupt processing in response to an input to the external interrupt port, and activates the receiving serial clock. Thereafter, the CPU samples the data input to the serial data input port in synchronization with the rising of the receiving serial clock, and sequentially stores the data in the serial register. The CPU determines the data in the serial register when data of a predetermined number of bits enters the serial register.

JP-A-11-219338

  However, in the serial data transmission system described in Patent Document 1, when noise or the like is generated on the serial data transmission path, the noise is detected at the external interrupt port of the receiving CPU. There is a problem that the external interrupt process is performed in the process, and the execution efficiency of the main process in the receiving CPU is reduced. As the short pulse noise is repeatedly input to the external interrupt port, the external interrupt processing in the receiving CPU is more frequent, and in the worst case, the main processing may not be executed.

  In the serial data transmission system described in Patent Document 1, the CPU on the receiving side requires a dedicated external interrupt port to detect the rising edge of the serial data in addition to the serial data input port. There is a problem of incurring an increase in size and cost. In particular, in a small-scale system, it is not easy to provide a dedicated external interrupt port for the CPU.

  The present invention has been made in view of such circumstances, and an object of the present invention is to prevent the execution efficiency of the main processing from being reduced due to noise on the transmission path and to perform communication processing on the CPU or the like. It is an object of the present invention to provide a receiving apparatus and a communication system that do not require external interrupt ports.

  According to the present invention, in a receiving apparatus that starts data reception processing after detecting a predetermined number of repetitions of a high level / low level of a binary signal, sampling according to the data transfer rate of the binary signal is performed. A plurality of sampling means for sampling the signal level of the binary signal at a period; and a detection means for detecting that a sampling result by at least one of the sampling means includes a predetermined number of repetitions of high level / low level; And the plurality of sampling means perform sampling at the same sampling period and perform sampling at different timings.

  The receiving apparatus according to the present invention includes N sampling means, and the N sampling means sequentially perform sampling at a time interval of 1 / N times the sampling period.

  The receiving apparatus according to the present invention is a receiving apparatus that starts data reception processing after detecting a predetermined number of repetitions of a high level / low level of a binary signal, according to the data transfer rate of the binary signal. Two sampling means for sampling the signal level of the binary signal at a sampling period, and detection for detecting that the sampling result by at least one of the sampling means includes a predetermined number of repetitions of high level / low level The two sampling means perform sampling at the same sampling period, and sequentially perform sampling at a time interval that is ½ times the sampling period.

  The communication system according to the present invention includes the above-described receiving device and a transmitting device that starts a data transmission process after outputting a predetermined number of repetitions of a high level / low level of a binary signal. The apparatus is characterized by outputting a predetermined number of repetitions of high level / low level so that the increase / decrease of the signal width of the binary signal is within ± 25%.

Further, in the communication system according to the present invention, when the number of times that the transmission device detects the repetition of the high level / low level of the binary signal is M times, the transmission apparatus repeats M times of the high level / low level. A high-level / low-level repetition is output a predetermined number of times so that the rate of increase / decrease P with respect to the required time satisfies the following (formula 1).
P <0.25 / M (Formula 1)

In the present invention, by detecting a predetermined number of repetitions of a high level / low level signal level on a transmission path of a binary signal (digital signal) (hereinafter, the repetition of the signal level is referred to as a preamble), It is determined that the transmission apparatus performs data transmission, and data reception processing is started. The receiving device is provided with a plurality of sampling means for sampling the signal level of the digital signal on the transmission line at a sampling period corresponding to the data transfer rate of the digital signal (for example, a sampling period substantially the same as the data transfer rate of the digital signal). However, the plurality of sampling means perform sampling at different timings. When the preamble on the transmission path is detected by any one of the plurality of sampling units, the receiving apparatus can start the data receiving process.
By adopting a configuration in which the preamble is detected not by an external interrupt port but by periodic sampling, even if noise occurs on the transmission line, the reception processing of the receiving device is erroneously performed. And the execution efficiency of other processing by the receiving apparatus is not reduced.
In addition, since sampling is performed by a plurality of sampling means and the preamble is detected by any one of the sampling means, the data reception process is started. Therefore, due to various factors on the transmission side device and the transmission path, Even when an error occurs in the data transfer rate and signal width of the preamble, the preamble can be reliably detected.

  In the present invention, when the receiving apparatus includes N sampling means, each sampling means performs sampling at the same sampling period, and each of the N sampling means has a time that is 1 / N times the sampling period. Sampling is performed sequentially at intervals (that is, N sampling means sample at equal time intervals). As a result, the preamble can be efficiently detected without deviation by a plurality of sampling means, and the preamble detection accuracy can be improved.

  Further, in the present invention, when the receiving apparatus includes two sampling means, each sampling means performs sampling at the same sampling period corresponding to the data transfer rate, and the two sampling means each have a half of the sampling period. At double time intervals (ie, two sampling means sample alternately at equal time intervals). In this configuration, the error related to each signal width (hereinafter referred to as bit error) in repetition of the high level / low level of the preamble is within ± 25%, and the time required for the entire repetition of the high level / low level for a predetermined number of times. Is less than ± 2.5% (when the number of repetitions is 10), the receiving apparatus can reliably detect the preamble. Therefore, with a simple configuration having only two sampling means, accurate preamble detection by the receiving apparatus can be realized, and the data reception process can be started reliably.

  In the present invention, the transmitting apparatus that transmits the preamble to the receiving apparatus transmits the preamble so that the bit error is within ± 25%. Thereby, in the receiving device including two sampling means as described above, the preamble transmitted by the transmitting device can be reliably detected, and the transmission and reception of data by the transmitting device and the receiving device can be reliably performed.

In the present invention, the signal width of the high level / low level of the digital signal is W, the number of repetitions of the high level / low level is M, and M times of the high level / low level are repeated. When the ratio of the preamble error is P, the transmission device outputs high level / low level repetition so as to satisfy the following (Equation 1).
P <0.25 / M (Formula 1)
For example, when M = 10, P <0.025 and the allowable preamble error is less than ± 2.5%. Thereby, in a receiving device provided with two sampling means, the preamble transmitted by the transmitting device can be reliably detected.

  According to the present invention, the preamble is detected using a plurality of sampling means, so that if the error related to the preamble is within a certain range, the receiving apparatus reliably detects the preamble and receives the data. It can be performed. In addition, since this configuration does not require an external interrupt port, it is possible to suppress an increase in size and cost of the receiving device. In addition, since the sampling is periodically performed, even when noise or the like occurs on the transmission path, the reception process of the reception apparatus is not erroneously performed, and the execution efficiency of other processes by the reception apparatus Will not drop. Therefore, it is possible to realize a receiving device and a communication system that are inexpensive and have high communication accuracy.

It is a block diagram for demonstrating the structure of the keyless entry system which concerns on this Embodiment. It is a schematic diagram which shows an example of the digital signal input into the input port of CPU. It is a schematic diagram for demonstrating the detection method of a preamble. It is a schematic diagram which shows the example of a preamble detection when a bit error arises. It is a schematic diagram for demonstrating the tolerance | permissible_range of a bit error. It is a schematic diagram for demonstrating the tolerance | permissible_range of a bit error. It is a schematic diagram for demonstrating the tolerance | permissible_range of a preamble error. It is a schematic diagram for demonstrating the allowable range of the preamble error in consideration of the bit error.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof. In this embodiment, an example in which the communication system and the receiving apparatus of the present invention are applied to a keyless entry of a vehicle will be described. However, the application of the present invention is not limited to this, and other various apparatuses and systems, etc. Applicable. FIG. 1 is a block diagram for explaining a configuration of a keyless entry system according to the present embodiment. In the figure, reference numeral 1 denotes an ECU (Electronic Control Unit) that is mounted on a vehicle (not shown) and performs various control processes related to the keyless entry system. In the figure, reference numeral 3 denotes a remote controller (hereinafter simply referred to as a remote controller) of a keyless entry system, which is a portable device possessed by a user such as a vehicle driver.

  The remote control 3 includes a CPU 31, a UHF (Ultra High Frequency) transmission unit 32, a UHF antenna 33, and the like. The remote controller 3 allows the CPU 31 to accept a user operation using a switch or the like (not shown), and the UHF transmission unit 32 can transmit the received operation content from the UHF antenna 33 to the ECU 1 mounted on the vehicle as a radio signal. As a result, operations such as locking / unlocking the vehicle door performed by the user on the remote controller 3 are transmitted to the ECU 1 of the vehicle.

  The ECU 1 is a device that performs operation control processing on various devices mounted on the vehicle, and includes a CPU 11, a UHF receiving IC (Integrated Circuit) 12, a UHF antenna 13, and the like. The UHF reception IC 12 receives the UHF band radio signal transmitted from the remote controller 3 by the UHF antenna 13, demodulates the received radio signal and converts it into digital data, and transmits the digital data to the CPU 11 by serial communication. An IC that performs processing. The CPU 11 has an input port 11a for serial communication. The input port 11 of the CPU 11 and the UHF receiving IC 12 are connected via wiring on the circuit board, and the serial signal output from the UHF receiving IC 12 is input to the CPU 11. Input to port 11a.

  The communication system of the present invention relates to serial communication performed between the CPU 11 and the UHF receiving IC 12, and the CPU 11 of the ECU 1 in the present embodiment corresponds to the receiving device of the present invention, and the UHF receiving IC 12 of the ECU 1 is used. The remote controller 3 corresponds to the transmission device of the present invention.

  The remote controller 3 generates serial digital data prefixed with a preamble composed of a predetermined number of high-level / low-level digital signals indicating the start of data transmission as transmission data to the ECU 1. Data is modulated by the UHF transmitter 32 and transmitted from the UHF antenna 33 as a radio signal. The ECU 1 demodulates the radio signal received by the UHF receiving IC 12 and inputs the demodulated digital data to the input port 11 a of the CPU 11. At this time, the serial data input from the UHF receiving IC 12 to the input port 11 a of the CPU 11 is the same data as the transmission data with the preamble generated by the remote controller 3.

  However, since the UHF receiver IC 12 of the ECU 1 is configured to simply demodulate and output the radio signal received via the UHF antenna 13, the noise received by the UHF antenna 13 is also demodulated as a received signal, Output to the CPU 11 as digital data. FIG. 2 is a schematic diagram illustrating an example of a digital signal input to the input port 11 a of the CPU 11.

  Even when the remote control 3 is not transmitting a wireless signal and the remote control 3 and the ECU 1 are not performing wireless communication, the UHF antenna 13 of the ECU 1 receives a weak radio wave around it as noise. The IC 12 outputs a digital signal corresponding to the noise to the CPU 11. The signal waveform of the digital signal corresponding to the noise is shown at the left end of FIG. 2, but the signal corresponding to the noise has a waveform with a random period and width. When such a digital signal is input to a CPU or the like having an external interrupt port, there is a problem that interrupt processing occurs frequently. However, in the ECU 1 according to the present embodiment, the CPU 11 has an input port 11a for serial communication. Since this signal is only input, the CPU 11 does not perform processing according to the noise signal.

  When the remote control 3 transmits a radio signal and the UHF antenna 13 of the ECU 1 receives the radio signal, the surrounding radio wave that becomes noise is weak compared to the radio signal transmitted and received between the remote control 3 and the ECU 1. Therefore, the influence of noise can be almost ignored in the digital signal output from the UHF receiving IC 12. In the example of the received signal shown in FIG. 2, the high level / low level signal having a relatively short predetermined signal width is repeated 20 times (high level is 10 times, low level) after the high level and low level signals for a relatively long period. Level (10 times) is performed (preamble), and an arbitrary data waveform is received after the preamble.

  The CPU 11 of the ECU 1 detects a high level / low level repetition (preamble) a predetermined number (20 times) from a signal input from the UHF receiving IC 12 to the input port 11a, and then starts data reception processing. By receiving data from the remote controller 3, processing relating to locking / unlocking of the door of the vehicle can be performed. Details of the preamble detection method performed by the CPU 11 will be described below.

  FIG. 3 is a schematic diagram for explaining a preamble detection method, and shows an enlarged part of a preamble waveform. The CPU 11 includes two sampling means (a first sampling unit 21 and a second sampling unit 22) that acquire (sample) the signal level of the signal input to the input port 11a at a predetermined cycle. In signals transmitted and received between the remote controller 3 and the ECU 1, the signal width (data transfer rate) and the number of repetitions of a high level / low level signal transmitted and received as a preamble are predetermined as a communication protocol.

  The first sampling unit 21 and the second sampling unit 22 of the CPU 11 perform sampling at the same sampling period as the preamble data transfer rate, that is, the signal width W of one waveform of high level or low level (hereinafter referred to as bit width W). . The sampling timing of the first sampling unit 21 and the second sampling unit 22 is shifted so that the time difference is ½ times the bit width (W / 2). That is, the first sampling unit 21 and the second sampling unit 22 alternately sample the signal level of the input signal with a time difference of W / 2. In FIG. 3, the sampling timing by the first sampling unit 21 is indicated by a solid arrow (A), and the sampling timing by the second sampling unit 22 is indicated by a broken arrow (B).

  When there is no error in the preamble of the signal input to the input port 11a of the CPU 11, both the first sampling unit 21 and the second sampling unit 22 detect high level / low level repetition. The CPU 11 determines that a preamble has been received when at least one of the first sampling unit 21 and the second sampling unit 22 has detected a high level / low level repetition a predetermined number of times, and receives data following the preamble To start.

  FIG. 4 is a schematic diagram illustrating an example of detection of a preamble when a bit error occurs. Here, one waveform of high level or low level is called a bit, and one set of high level and low level is called a pulse. Bit error means that the width of one pulse is constant, but the ratio between the high level and the low level of the signal width of the high level and the low level is not uniform when the ratio between the high level and the low level is not uniform. To do. In the example shown in FIG. 4, the high level width in one pulse is reduced by 25% and the low level width is increased by 25%, and the high level width in one pulse is increased by 25% and the low level width is increased. This is a signal waveform in the case where the preamble includes that whose width is reduced by 25%.

  At this time, if an error (bit error and preamble error) generated in the preamble is within an allowable range, at least one of the first sampling unit 21 and the second sampling unit 22 repeats the high level / low level a predetermined number of times. Detected. In the example shown in the figure, the first sampling unit 21 has a portion that continuously detects the low level, and an error occurs in the detection of repeated high / low levels. In contrast, the second sampling unit 22 can correctly detect repetition of high level / low level. Therefore, the CPU 11 can start a data reception process following the preamble.

  FIG. 5 is a schematic diagram for explaining an allowable range of bit error, and shows a part of a preamble waveform in an enlarged manner. In this figure, the high level start time of the first bit of the preamble is t = 0, the normal preamble high level without bit error and the low level bit width W are time 1 widths, and the bit error high level The level increase / decrease width is x. Further, the sampling timing by the first sampling unit 21 is indicated by a solid arrow, the first sampling timing is S (A1), the second sampling timing is S (A2), the third sampling timing is S (A3), The fourth sampling timing is S (A4). Similarly, the sampling timing by the second sampling unit 22 is indicated by a dashed arrow, the first sampling timing is S (B1), the second sampling timing is S (B2), and the third sampling timing is S (B3). The fourth sampling timing is S (B4).

  The CPU 11 can perform sampling twice in one bit by the first sampling unit 21 and the second sampling unit 22. In this case, the most affected by the bit error is when the high level / low level with the shortest bit width continues or when the high level / low level with the longest bit width continues. FIG. 4 shows a preamble waveform when the high level / low level of the shortest bit width continues, and this case will be described below. In the case where the high level / low level of the longest bit width continues, the allowable range of the bit error is obtained by the same method, and thus illustration and description are omitted.

The timing of the first sampling S (A1) by the first sampling unit 21 is performed in the range of t = 0 to 0.5. FIG. 5A shows the case where the timing of sampling S (A1) is t = 0, and FIG. 5B shows the case where t = 0.5. In FIG. 5A, when the second sampling timing S (B2) and the third sampling timing S (A3) of the second sampling unit 22 satisfy the following expression, the second sampling unit 22 Since the detection result is a normal repetition of high level / low level, the preamble can be detected.
1 + x <S (B2) and S (B3) <3-x

Further, in FIG. 5B, when the second sampling timing S (A2) and the third sampling timing S (A3) of the first sampling unit 21 satisfy the following equations, the first sampling unit 21 Since the detection result of the above is a normal repetition of high level / low level, the preamble can be detected.
1 + x <S (A2) and S (A3) <3-x

Which of the above two conditional expressions is applied depends on whether the second sampling timing S (A2) of the first sampling unit 21 is earlier or later than the first high-level signal falling timing (1 + x). Depends on. Therefore, when the above two conditional expressions are put together, the following conditional expression is obtained.
When S (A2) ≦ 1 + x 1 + x <S (B2) and S (B3) <3-x
When S (A2)> 1 + x 1 + x <S (A2) and S (A3) <3-x

The relationship among S (A1), S (A2), S (A3), S (B2) and S (B3) is as follows.
0 ≦ S (A1) <0.5
S (A2) = S (A1) +1
S (A2) = S (A1) +2
S (B2) = S (A1) +1.5
S (B3) = S (A1) +2.5

When these are put together, the following three conditional expressions (Condition 1) to (Condition 3) can be derived.
(Condition 1) 0 ≦ S (A1) <0.5
(Condition 2) S (A1) ≦ x and S (A1) <− x + 0.5
(Condition 3) S (A1)> x and S (A1) <− x + 1

  FIG. 6 is a schematic diagram for explaining the allowable range of bit error, and shows the above (Condition 1) to (Condition 3) as a graph. Note that (Condition 1) is an indispensable condition, and either (Condition 2) or (Condition 3) may be satisfied. In the illustrated graph, the preamble can be detected by the first sampling unit 21 or the second sampling unit 22 even if a bit error occurs in a range where (Condition 1) to (Condition 3) are satisfied. The range is hatched. From this graph, S (A1) is 0 to. In any case of 5, the condition is satisfied when x ≦ 0.25 is satisfied. That is, if the bit error is 25% or less, the CPU 11 can detect a predetermined number of repetitions of high level / low level by either the first sampling unit 21 or the second sampling unit 22 and can detect a preamble. it can.

  FIG. 7 is a schematic diagram for explaining the allowable range of the preamble error, taking as an example a case where the preamble is repeated at high level / low level 10 times (high level is 5 times, low level is 5 times). It is shown. The data transfer rate of signals transmitted and received in the remote controller 3 and the ECU 1 is determined in advance. However, due to the influence of the clock error of each device or the difference in hardware configuration, the width of each waveform of the high level / low level of the preamble is set. An error may occur, and an error may occur in the length of the entire preamble. Here, an increase / decrease in the length of the entire preamble with respect to the normal value is defined as a preamble error.

  When no preamble error has occurred (see FIG. 7A), the sampling period by the first sampling unit 21 and the second sampling unit 22 is the same as the width of each high level / low level bit constituting the preamble. Therefore, the sampling timing for each bit is relatively the same for all bits. On the other hand, when a preamble error has occurred (see FIG. 7B), the sampling timing for each bit gradually shifts. In the example shown in FIG. 7, the width of each bit is smaller than the normal value, the length of the entire preamble is shorter than the normal value, and the sampling timing is gradually shifted with respect to each bit. A preamble error is obtained by adding such a shift amount for each bit to the entire preamble (10 bits in FIG. 7).

The CPU 11 performs sampling twice per bit in the first sampling unit 21 and the second sampling unit 22, but the high level / low level error is detected in the sampling of both the first sampling unit 21 and the second sampling unit 22. When the detection occurs, the CPU 11 cannot detect the preamble. That is, in the last bit of the preamble with the largest deviation, when the deviation more than the sampling timing difference (1/2 of the bit width W) between the first sampling unit 21 and the second sampling unit 22 occurs, the detection of the preamble is performed. It becomes impossible to do. Therefore, if the number of bits of the preamble is M and the ratio of the increase / decrease amount of the length of the entire preamble due to the preamble error is P, the allowable range of the preamble error is
“1/2 of bit width”> “Preamble error amount”
And
W / 2> M × W × P
That is,
P <0.5 / M
It can be expressed by the following formula. For example, if the number of bits M of the preamble is M = 10, P <0.05, and the allowable range of the preamble error is less than ± 5% with respect to the entire length of the preamble.

Note that the above-described preamble error does not take into account a bit error occurring in each bit. Hereinafter, the allowable range of the preamble error in consideration of the bit error will be described. FIG. 8 is a schematic diagram for explaining an allowable range of a preamble error in consideration of a bit error. Since the bit error is such that the bit width in one pulse increases or decreases, the bit error having the greatest influence on the preamble error is a bit error generated in the last bit (10th bit) of the preamble. Therefore, considering the maximum bit error in the last bit of the preamble, the allowable range of preamble error is
“1/2 of bit width”> “preamble error amount” + “maximum bit error”
And the maximum bit error is 25%,
W / 2> M × W × P + 0.25 × W
That is,
P <0.25 / M (Formula 1)
It can be expressed by the following formula. For example, if the number of bits M of the preamble is M = 10, P <0.025, and the allowable range of the preamble error is less than ± 2.5% with respect to the entire length of the preamble.

  In the communication system having the above configuration, the CPU 11 includes the first sampling unit 21 and the second sampling unit 22, and the first sampling unit 21 and the second sampling unit 22 have the same sampling period as the bit width W of each bit of the preamble. In addition, if the digital signal input to the input port 11a is sampled at a timing shifted by a half of the bit width W, the preamble error of the input signal is within an allowable range. The preamble can be detected by at least one of the first sampling unit 21 and the second sampling unit 22, and the CPU 11 can start receiving data. Therefore, the remote controller 3 and the UHF receiver IC 12 perform data transmission to the CPU 11 so that the error related to the preamble is within an allowable range, that is, the bit error is within 25% and the preamble error satisfies (Equation 1). Can reliably receive and process data. Further, the CPU 11 does not need to have an external interrupt port for serial communication, and other processes are not stopped even when a signal based on noise is input.

  In the present embodiment, an example in which the communication system of the present invention is applied to a keyless entry of a vehicle is shown. However, the application of the present invention is not limited to this, and serial communication or the like from a transmission device to a reception device is possible. When data transmission is performed, the present invention can be applied to various systems and apparatuses configured to repeat a high level / low level a predetermined number of times prior to data transmission.

  In addition, the CPU 11 is configured to include the two sampling units of the first sampling unit 21 and the second sampling unit 22, but is not limited thereto, and may be configured to include three or more sampling units. For example, when N sampling means are provided, the N sampling means perform sampling at the same cycle as the preamble data transfer rate (that is, the bit width W of each bit of the preamble), and each sampling means has a time difference of W / A configuration may be adopted in which sampling is performed sequentially while being shifted to N. In this case, although detailed explanation is omitted, when the bit error is (N-1) / 2N or less and the preamble error is less than (N-1) / 2NM, the preamble is obtained by at least one sampling means. Can be detected.

1 ECU
3 Remote control 11 CPU
12 UHF receiver IC
13 UHF antenna 21 First sampling unit 22 Second sampling unit 31 CPU
32 UHF transmitter 33 UHF antenna

Claims (5)

In a receiving apparatus that starts data reception processing after detecting a predetermined number of repetitions of high level / low level of a binary signal,
A plurality of sampling means for sampling the signal level of the binary signal at a sampling period corresponding to the data transfer rate of the binary signal;
Detecting means for detecting that the sampling result by at least one of the sampling means includes a predetermined number of repetitions of high level / low level, and
The plurality of sampling means perform sampling at the same sampling period, and perform sampling at different timings. The receiving apparatus according to claim 1, wherein N sampling means are provided, and the N sampling means sequentially perform sampling at a time interval of 1 / N times the sampling period. In a receiving apparatus that starts data reception processing after detecting a predetermined number of repetitions of high level / low level of a binary signal,
Two sampling means for sampling the signal level of the binary signal at a sampling period corresponding to the data transfer rate of the binary signal;
Detecting means for detecting that the sampling result by at least one of the sampling means includes a predetermined number of repetitions of high level / low level, and
The receiving apparatus characterized in that the two sampling means respectively sample at the same sampling period, and sequentially perform sampling at a time interval that is ½ times the sampling period. A receiving device according to claim 3;
A transmission device for starting a data transmission process after outputting a predetermined number of repetitions of a high level / low level of a binary signal;
The communication system is characterized in that it outputs a predetermined number of repetitions of high level / low level so that the increase / decrease of the signal width of the binary signal is within ± 25%. When the number of times the high-level / low-level repetition of the binary signal is detected is M times, the transmission apparatus has a ratio P of increase / decrease with respect to the time required to repeat the high-level / low-level M times as follows: The communication system according to claim 4, wherein a repetition of a predetermined number of high / low levels is output so as to satisfy (Equation 1).
P <0.25 / M (Formula 1)

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