JP2005142643A - Interface circuit and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interface circuit enabling the proper sampling of data on the basis of a transfer clock while achieving low power consumption, and to provide electronic equipment. <P>SOLUTION: The interface circuit includes: a sampling circuit 90 for sampling data DTO transferred via a differential signal line for data transfer on the basis of a clock CLK transferred via a differential signal line for clock transfer; and a preamble error detection circuit 100 for carrying out the detection processing of a preamble code on the basis of the sampled data to inform the sampling circuit 90 about a preamble error when no preamble code is detected. When the detection circuit 100 informs the sampling circuit 90 about the preamble error by data sampled at either of a leading edge and a trailing edge of the clock, the sampling circuit 90 outputs the data sampled by the other edge as sampling data SPD. The preamble error detection circuit 100 does not detect the preamble code being a positive code but detects the preamble code being a negative code. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an interface circuit and an electronic device.

  In recent years, high-speed serial transfer interfaces such as LVDS (Low Voltage Differential Signaling) have attracted attention as interfaces aimed at reducing EMI noise. In this high-speed serial transfer interface, the transmitter circuit transmits the serialized data using differential signals, and the receiver circuit differentially amplifies the differential signals to realize data transfer. As such a high-speed serial transfer interface, DVI (Digital Visual Interface) and the like are known.

  In such a high-speed serial interface, the receiver side needs to sample and synchronize data transmitted from the transmitter side with a clock. As a first method for realizing such synchronization, the transmitter side transfers a clock that can sample the transfer data at both the rising edge and the falling edge to the receiver side, and the receiver side transfers data at both edges based on this transfer clock. There is a double edge method for sampling. However, in this double edge method, the clock needs to be doubled by the PLL circuit on the transmitter side, and the current consumption of the PLL circuit increases.

As a second method, the receiver side multiplies the clock transferred from the transmitter side by a PLL circuit, oversamples the data with the multiplied clock, detects the data transition point, and adjusts the skew. is there. However, this method requires a complicated skew adjustment circuit and PLL circuit for detecting a transition point on the receiver side, which causes problems such as an increase in circuit scale and an increase in power consumption.
JP 2003-218843 A

  The present invention has been made in view of the above technical problems, and an object of the present invention is to provide an interface circuit and an electronic apparatus that can realize proper sampling of data by a transfer clock while realizing low power consumption. Is to provide.

  The present invention is an interface circuit having a differential signal interface, in which data transferred via a differential signal line for data transfer is converted to a clock transferred via a differential signal line for clock transfer. A sampling circuit that performs sampling based on the data, and a preamble error detection circuit that performs a preamble code detection process based on the data sampled by the sampling circuit and notifies a preamble error when a preamble code is not detected, and When the sampling circuit is notified of the preamble error for the data sampled at one of the rising edge and falling edge of the clock transferred via the clock transfer differential signal line, the one is Sample on the other edge different The grayed data, related to the interface circuit to output as the sampling data.

  According to the present invention, a preamble code detection process is performed, and a preamble error is notified when a preamble code is not detected. When a preamble error is notified about data sampled at one of the rising edge and falling edge of the clock, the data sampled at the other edge is output as sampling data. For example, when a preamble error is detected and notified of data sampled at the rising edge, the data sampled at the falling edge is output as sampling data to a subsequent circuit (for example, a serial / parallel conversion circuit). As described above, in the present invention, since a single edge method is employed, low power consumption can be expected. In addition, since the sampling edge is switched using the preamble code that can be serially transferred by the differential signal line, the circuit can be reduced in size and power consumption can be reduced.

  According to the present invention, the preamble error detection circuit detects a plus code preamble code when a minus code preamble code is transferred via a differential signal line for data transfer following a plus code preamble code. It is also possible to perform a minus code preamble code detection process without performing the process, and to notify a preamble error when a minus code preamble code is not detected.

  The present invention also provides an interface circuit having a differential signal interface, wherein a clock transferred via a differential signal line for clock transfer is transferred to the data transferred via the differential signal line for data transfer. A sampling circuit that performs sampling based on the data, and a preamble error detection circuit that performs a preamble code detection process based on data sampled by the sampling circuit and notifies a preamble error when no preamble code is detected, The preamble error detection circuit does not perform the detection process of the plus code preamble code when the minus code preamble code is transferred via the differential signal line for data transfer following the plus code preamble code. Minus chord preamble Performs detection processing of the code, related to the interface circuit to notify a preamble error if preamble code minus code is not detected.

  According to the present invention, the detection process of the minus code preamble code is performed ignoring the plus code preamble code, and the preamble error is notified when the minus code preamble code is not detected. If only the minus code preamble code is detected in this way, even if a detection error occurs without being able to follow the level change at the first bit of the plus code preamble code, the preamble error is caused by the detection error. The situation where it is notified can be prevented. Thereby, the reliability of data transfer can be improved.

  In the present invention, after the preamble error detection circuit changes the data from the first level representing the idle state to the second level, the period required for transferring the plus code preamble code and the minus code preamble code is exceeded. Until a given detection period elapses, a minus code preamble code is detected, and if no minus code preamble code is detected within the detection period, a preamble error is notified. Good.

  As described above, if the detection period of the minus code preamble code is set to a period longer than the period required for transferring the plus code preamble code and the minus code preamble code, the first bit of the plus code preamble code, etc. Even when a detection error occurs, it becomes possible to reliably detect a minus code preamble code.

  In the present invention, the preamble error detection circuit may include an error count circuit that counts the number of times the preamble code has not been detected, and may notify a preamble error when the number of times of non-detection reaches a given number. .

  In this way, it is possible to prevent a situation in which a preamble error is erroneously notified even when a preamble code cannot be detected due to noise on the transmission path or the like.

  Also, in the present invention, the sampling circuit transfers the data transferred via the differential signal line for data transfer to the rising edge and the falling edge of the clock transferred via the differential signal line for clock transfer. The first sampling circuit for sampling at one edge and the one of the clocks transferred via the differential signal line for clock transfer with the one of the clocks transferred via the differential signal line for clock transfer A second sampling circuit that samples at the other different edge, data sampled by the first sampling circuit, and data sampled by the second sampling circuit are selected and output as sampling data The preamble error detection circuit is a first sampling circuit. A first preamble error detection circuit for performing a preamble code detection process based on the sampled data and notifying a preamble error when no preamble code is detected; and the data sampled by the second sampling circuit. And a second preamble error detection circuit that performs a preamble code detection process based on the result and notifies a preamble error when a preamble code is not detected, and the data selector receives a preamble from the first preamble error detection circuit. When an error is notified, the data sampled by the second sampling circuit may be selected and output as sampling data.

  With such a configuration, it becomes possible to reliably detect the preamble error based on the sampling data and select the sampling data based on the detection result.

  In the present invention, the data selector selects the data sampled by the first sampling circuit when no preamble error is notified from either of the first and second preamble error detection circuits. Thus, it may be output as sampling data.

  In this way, if no preamble error is notified from either the first or second preamble error detection circuit, the data sampled at one edge is prioritized and output as sample data. It becomes like this.

  In the present invention, the first preamble error detection circuit counts a given detection period after the data has changed from the first level representing the idle state to the second level. Including a detection period count circuit, which notifies a preamble error when a preamble code is not detected within the detection period, and the second preamble error detection circuit changes from a first level representing an idle state to a second level. A second detection period counting circuit that counts a given detection period after the data has changed, and notifies a preamble error when no preamble code is detected within the detection period; Good.

  In this way, it is possible to detect and notify a preamble error by setting an appropriate detection period.

  Also, in the present invention, the first and second detection period counting circuits may perform a plus operation when a minus code preamble code is transferred via a differential signal line for data transfer following a plus code preamble code. The passage of a detection period longer than the period required for the transfer of the code preamble code and the minus code preamble code is counted, and the first and second preamble error detection circuits detect the minus code preamble code within the detection period. If no error is detected, a preamble error may be notified.

  As described above, if the detection period of the minus code preamble code is set to a period longer than the period required for transferring the plus code preamble code and the minus code preamble code, the first bit of the plus code preamble code, etc. Even when a detection error occurs, it becomes possible to reliably detect a minus code preamble code.

  In the present invention, the preamble code may be a code that is assigned to a special code obtained by an encoding method that extends a bit width and transferred via a differential signal line for data transfer.

  Employing such an encoding method makes it possible to serially transfer a preamble code and use it for detection and notification of a preamble error.

  The present invention also relates to an electronic apparatus including any one of the interface circuits described above and at least one of a communication device, a processor, an imaging device, and a display device.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Data Transfer Method Using Differential Signal First, the outline of the data transfer method of this embodiment will be described with reference to FIG. In this embodiment, the host device 10 is a side that supplies a clock, and the target device 30 is a side that operates using the supplied clock as a system clock.

  In FIG. 1, DTO + and DTO− are data (OUT data) output from the host device 10 (device in a broad sense) to a target device 30 (device in a broad sense). CLK + and CLK− are clocks supplied from the host device 10 to the target device 30. The host device 10 outputs DTO +/− in synchronization with an edge of CLK +/− (for example, a rising edge or a falling edge). Therefore, the target device 30 can sample and capture DTO +/− using CLK +/−. Further, in FIG. 1, the target device 30 operates based on the clock CLK +/− supplied from the host device 10. That is, CLK +/− becomes the system clock of the target device 30. Therefore, a PLL (Phase Locked Loop) circuit 12 (clock generation circuit in a broad sense) is provided in the host device 10 and is not provided in the target device 30.

  DTI + and DTI− are data (IN data) output from the target device 30 to the host device 10. STB + and STB− are strobes (clocks in a broad sense) that the target device 30 supplies to the host device 10. The target device 30 generates and outputs STB +/− based on CLK +/− supplied from the host device 10. The target device 30 outputs DTI +/− in synchronization with the STB +/− edge (for example, a rising edge or a falling edge). Therefore, the host device 10 can sample and capture DTI +/− using STB +/−.

  Each of DTO +/−, CLK +/−, DTI +/−, and STB +/− is transmitted by causing the transmitter circuit (driver circuit) to drive, for example, differential signal lines corresponding to each of them. The In order to realize faster transfer, two or more pairs of DTO +/− and DTI +/− differential signal lines may be provided.

  The interface circuit 20 of the host device 10 is for OUT transfer (data transfer in a broad sense), transmitter circuits 22 and 24 for clock transfer, IN transfer (data transfer in a broad sense), and strobe transfer (in a broad sense). Includes receiver circuits 26 and 28 for clock transfer). The interface circuit 40 of the target device 30 includes receiver circuits 42 and 44 for OUT transfer and clock transfer, and transmitter circuits 46 and 48 for IN transfer and strobe transfer. Note that a configuration in which some of these circuit blocks are not included may be employed.

  The transmitter circuits 22 and 24 for OUT transfer and clock transfer transmit DTO +/− and CLK +/− by driving the differential signal lines of DTO +/− and CLK +/−, respectively. The receiver circuits 42 and 44 for OUT transfer and clock transfer perform current / voltage conversion based on the current flowing through the differential signal lines of DTO +/− and CLK +/−, respectively, and are obtained by current / voltage conversion. By performing a comparison process (differential amplification process) of the differential voltage signals (first and second voltage signals), DTO +/− and CLK +/− are received.

  The IN transfer and clock transfer transmitter circuits 46 and 48 transmit DTI +/− and STB +/− by driving the differential signal lines of DTI +/− and STB +/−, respectively. The IN transfer and strobe transfer receiver circuits 26 and 28 perform current / voltage conversion based on currents flowing through the differential signal lines of DTI +/− and STB +/−, respectively, and are obtained by current / voltage conversion. By performing a comparison process (differential amplification process) of the differential voltage signals (first and second voltage signals), DTI +/− and STB +/− are received.

2. Configuration Example of Interface Circuit FIGS. 2 and 3 show detailed configuration examples of the interface circuit. Note that the interface circuit of the present embodiment is not limited to the configurations of FIGS. 2 and 3, and may be configured by omitting some of the circuit blocks of FIGS. That is, in the interface circuit of this embodiment, at least the sampling circuit and the preamble error detection circuit may be included (or the sampling circuit, the preamble error detection circuit, and the receiver circuit may be included), and other circuit blocks may be omitted.

  FIG. 2 shows a configuration example of the interface circuit 20 on the host side. In FIG. 2, the transaction layer circuit 50 performs processing related to the data transfer transaction layer. Specifically, a packet transfer instruction such as a request packet or an acknowledge packet is issued.

  The packet generation & transfer abort circuit 52 performs processing for generating a packet (packet header) instructed by the transaction layer circuit 50 and processing for aborting data transfer. Specifically, the packet generation & transfer abort circuit 52 receives TxStrobe from the 8B / 10B encoding circuit 54 and outputs TxData, TxValid, and TxAbort. Here, TxData is transmission data constituting a packet, for example, 8-bit parallel data. TxValid is a signal that becomes active during the period from the start to the end of the transmission packet, and is a signal that indicates that transmission preparation is complete. TxStrobe is a signal indicating completion of data reception. TxAbort is a signal that becomes active when data transmission is stopped.

  The 8B / 10B encoding circuit 54 performs an encoding process using an 8B / 10B encoding method (encoding method that extends the bit width in a broad sense). The code adding circuit 55 included in the 8B / 10B encoding circuit 54 performs processing for adding a preamble code, a start code, and an abort code obtained by 8B / 10B encoding.

  In 8B / 10B encoding, 8-bit data is converted into 10-bit data. According to the 8B / 10B encoding, even if data having “0” or “1” continues, the bit change of the signal increases after the encoding, and the occurrence of a transfer error due to noise or the like can be reduced. . Further, according to 8B / 10B encoding, the bit width is expanded from 8 bits to 10 bits, so that it is possible to transmit a special code (control code) as shown in FIG. 4 in addition to data. The code adding circuit 55 of the 8B / 10B encoding circuit 54 performs processing for adding a preamble code, a start code, and an abort code using the 8B / 10B encoding. Note that the encoding method for extending the bit width is not limited to the 8B / 10B encoding method, and may be any encoding method for extending K bits to L (L> K) bits, for example.

  In this embodiment, a preamble code, a stop code, and an abort code are assigned to a special code obtained by 8B / 10B encoding (encoding that expands the bit width), and a differential signal line (DTO, DTI) for data transfer is assigned. ) Is being transferred through. For example, in FIG. 4, the codes K28.1, K28.2, and K28.3 are assigned to the preamble code, stop code, and abort code, respectively, via the differential signal lines (DTO, DTI) for data transfer. Forwarded. Then, the receiver side performs a decoding process in the 8B / 10B encoding system and detects K28.1, K28.2, and K28.3 codes, thereby detecting a preamble code, a stop code, and an abort code. Here, the preamble code is a code for indicating the head of a packet transferred first after an idle state, for example.

  As shown in FIG. 4, each code includes a plus code (positive symbol code) and a minus code (negative symbol code). The minus code is a code obtained by inverting each bit of the plus code. For example, a minus code preamble code (0011111001) is a code obtained by inverting each bit of a plus code preamble code (1110000101). In the plus code preamble code (hereinafter referred to as PRE + as appropriate), the first bit is 1, while in the minus code preamble code (hereinafter referred to as PRE− as appropriate), the first bit is “0”. It has become. Therefore, when PRE + is transferred following an idle state in which data of “0” (first level) continues, data is changed from “0” (first level) to “1” (first level) in the first bit of PRE +. 2 level).

  The parallel / serial conversion circuit 56 converts the parallel data received from the 8B / 10B encoding circuit 54 into serial data. The OUT transfer transmitter circuit 22 receives the serial data from the parallel / serial conversion circuit 56, drives the DTO +/− differential signal line, and transmits the data. The clock transfer transmitter circuit 24 receives the clock generated by the PLL circuit 12, drives the differential signal line of CLK +/−, and transmits the clock. These transmitter circuits 22 and 24 are constituted by analog circuits for current driving (or voltage driving) the differential signal lines. The clock generated by the PLL circuit 12 is frequency-divided by the frequency dividing circuit 14 and supplied to a circuit block (block for processing parallel data) in the interface circuit.

  The IN transfer receiver circuit 26 receives data transferred via the DTI +/− differential signal line, and outputs the received serial data to the serial / parallel conversion circuit 60. The strobe transfer receiver circuit 28 receives the strobe (clock) transferred via the STB +/− differential signal line and outputs the received strobe. These receiver circuits 26 and 28 are constituted by analog circuits that detect the drive current (or drive voltage) of the differential signal line.

  The serial / parallel conversion circuit 60 converts serial data transferred via the DTI +/− differential signal lines into parallel data. More specifically, the sampling circuit 91 included in the serial / parallel conversion circuit 60 strobes the data transferred via the DTI +/− differential signal line via the STB +/− differential signal line. Sampling based on (clock). The serial / parallel conversion circuit 60 converts the sampled serial data into parallel data. The preamble error detection circuit 101 included in the serial / parallel conversion circuit 60 performs a preamble code detection process based on the data sampled by the sampling circuit 91, and detects a preamble error which is an error state in which no preamble code is detected.

  The 8B / 10B decoding circuit 62 performs decoding processing in the 8B / 10B encoding method. The code / idle detection circuit 63 included in the 8B / 10B decode circuit 62 performs a start code and abort code detection process and a differential signal line idle state detection process.

  When the preamble error detection circuit 101 detects a preamble error or the code / idle detection circuit 63 detects a disparity error or a decode error, the error signal generation circuit 64 generates an error signal RxError to generate a transaction layer circuit 50. Output to.

  The FIFO 65 receives the decoded data from the 8B / 10B decoding circuit 62 and outputs it to the packet analysis & header / data separation circuit 68 as RxData. The I / F signal generation circuit 66 generates interface signals such as RxValid and RxStrobe, and outputs them to the packet analysis & header data separation circuit 68. Here, RxData is received data after 8B / 10B decoding, for example, 8-bit parallel data. RxValid is a signal that becomes active during the period from the start to the end of the received packet, and is a signal that indicates that data exists. RxStrobe is a strobe signal for supplying data to the transaction layer circuit 50.

  The packet analysis & header / data separation circuit 68 performs processing for analyzing a received packet and processing for separating the header and data of the received packet.

  FIG. 3 shows a configuration example of the interface circuit 40 on the target side. The configuration and operation of the circuits 70, 72, 74, 75, 76, 80, 90, 100, 82, 83, 84, 85, 86, 88 of FIG. 3 are the same as those of the circuits 50, 52, 54, 55, 56 of FIG. , 60, 91, 101, 62, 63, 64, 65, 66, and 68, the description thereof will be omitted. TxSpeed is a signal for instructing a transfer rate of transmission data. The strobe control & frequency dividing circuit 16 receives the clock received by the clock transfer receiver circuit 44, divides the clock, etc., and outputs it as a strobe signal to the strobe transfer transmitter circuit 48. The frequency divider 18 receives the clock received by the clock transfer receiver circuit 44 and supplies the frequency-divided clock to the circuit block in the interface circuit.

  FIG. 5A is a timing waveform example showing the relationship between the clock CLK and the data DTO. As shown in FIG. 5A, the transmitter circuit on the host side transmits the clock CLK and the data DTO synchronized with the rising edge (or falling edge) of the CLK to the receiver circuit on the target side. Therefore, the target-side receiver circuit normally samples the data DTO at the rising edge of the transmitted clock CLK.

  By adopting the single edge method as shown in FIG. 5A, the clock frequency of the PLL circuit 12 of the host side interface circuit of FIG. Power consumption can be reduced. Further, since it is not necessary to provide a PLL circuit for clock multiplication and a skew adjustment circuit having a complicated configuration in the target side interface circuit, the circuit can be reduced in scale and power consumption can be reduced.

  As shown in FIG. 5A, in this embodiment, 0 (first level) data is transferred in the idle state. Then, after the idle state, a plus code preamble code PRE + is transferred, followed by a minus code preamble code PRE−. Thereafter, the data packet is transferred, and when the transfer is completed, the stop code STOP +/− is transferred. Further, a period TIDLE corresponding to one or more codes after encoding by 8B / 10B encoding is provided at the break between packets. In 8B / 10B encoding, “0” does not continue for more than 10 bits. Therefore, even if there is an error in the stop code at the end of the transfer, the synchronization can be ensured again in the next packet transfer.

  In FIG. 5A, the combination of PRE + and PRE− is transferred only once prior to the transfer of the data packet, but the combination of PRE + and PRE− may be transferred a plurality of times. FIG. 5B is a timing waveform diagram showing the relationship between the strobe STB and the IN data DTI.

3. Switching of Sampling Clock Edge Next, details of the sampling circuit and preamble error detection circuit of this embodiment will be described. Hereinafter, the configuration and operation of the target-side sampling circuit 90 and the preamble error detection circuit 100 in FIG. 3 will be mainly described. However, the configuration and operation of the host-side sampling circuit 91 and the preamble error detection circuit 101 in FIG. It is.

  In this embodiment, an interface circuit having a differential signal interface employs a one-edge method as shown in FIGS. 5A and 5B, thereby successfully reducing the circuit scale and reducing power consumption. ing. However, with this one-edge method, due to skew in the circuit or transmission path, it is not possible to secure sufficient setup time and hold time during data sampling, and sampling errors (setup errors and hold errors) may occur. is there. For example, when the sampling edge of the clock coincides with the data transition point, proper sampling cannot be performed. In particular, if the transfer rate on the differential signal line is fast, the possibility of sampling errors increases. Therefore, in order to prevent the occurrence of such a sampling error, the method described below is adopted in the present embodiment.

  In FIG. 6A, the sampling circuit 90 clock-transfers data DTO (data after being converted to the CMOS voltage level by the data transfer receiver circuit) transferred via the differential signal line for data transfer. Sampling is performed based on a clock CLK (clock after being converted to a CMOS voltage level by a clock transfer receiver circuit) transferred via a differential signal line for use. The preamble error detection circuit 100 performs a preamble code detection process, and notifies a preamble error to the sampling circuit 90 or the like when no preamble code is detected. This preamble error is notified using, for example, an error notification signal PREER.

  When the preamble error of the data sampled at one of the rising edge and the falling edge of the clock CLK is notified from the preamble error detection circuit 100, the sampling circuit 90 is different from the other edge. The data sampled in is output as sampling data SPD. The output sampling data SPD is converted into parallel data.

  For example, in FIG. 6A, data DTO (DTI) is sampled at the rising edge of CLK (STB). In the present embodiment, when a preamble error is notified about data sampled at the rising edge (one edge) in this way, the edge of the sampling clock is switched to the falling edge. Then, as shown in FIG. 6C, data sampled at the falling edge is output as sampling data SPD. In this way, a setup time and a hold time can be sufficiently secured even in the single edge method, and a sampling error can be prevented from occurring. Therefore, it is possible to achieve both a reduction in circuit size and power consumption and appropriate data sampling.

  When sampling is performed by switching to the falling edge (the other edge in a broad sense) based on the notification of the preamble error, the sampling data SPD is re-sampled at the rising edge (one edge in a broad sense). It is desirable to output to a subsequent circuit (serial / parallel conversion circuit or the like).

  In parallel transfer without using a differential signal line, a sampling error hardly occurs when data is sampled by transferring a clock by the one-edge method. Further, since the serial preamble code as shown in FIG. 4 cannot be transferred in parallel transfer, the edge switching method based on the preamble error as in this embodiment cannot be realized.

  On the other hand, in serial transfer using a differential signal line, the transmitter circuit and receiver circuit are analog circuits, and the differential signal line is driven by current drive or the like, so there is a large skew between the transfer data and the transfer clock. Is likely to occur. For this reason, in conventional serial transfer using differential signal lines, a PLL circuit that multiplies the clock to generate an oversampling clock is provided on the receiver side, detects the data transition point, performs skew adjustment, and samples the data The technique to do was common.

  However, with this method, the power consumption of the PLL circuit that generates the oversampling clock is increased, and the scale of the skew adjustment circuit is increased. Therefore, it is difficult to reduce the circuit scale and power consumption.

  On the other hand, in the present embodiment, since the single edge method as shown in FIGS. 5A and 5B is adopted while serial transfer using a differential signal line is performed, a PLL for multiplying the clock is used. There is no need to provide a circuit on the transmitter side, and low power consumption can be realized. Also, in the present embodiment, focusing on the fact that serial preamble codes as shown in FIG. 4 can be transferred in serial transfer unlike parallel transfer, a method of switching the edge of the sampling clock on condition that a preamble error has occurred is adopted. ing. Therefore, it is not necessary to provide a skew adjustment circuit having a complicated configuration, and it is possible to realize both prevention of sampling error and low power consumption.

  FIG. 7A shows a configuration example of the sampling circuit 90. The flip-flop FF1 (first holding circuit) samples and holds the data DTO at the rising edge of the clock CLK. On the other hand, since the signal level of the clock CLK is inverted by the inverter circuit INV1, the flip-flop FF2 (second holding circuit) samples and holds the data DTO at the falling edge of the clock CLK.

  When the error notification signal PREER is inactive (when no preamble error is notified), the data selector 96 selects the data SPD1 sampled by the flip-flop FF1 and outputs it as final sampling data SPD. Also, flip-flop FF1 is enabled and flip-flop FF2 is disabled.

  On the other hand, when the error notification signal PREER is active (when a preamble error is notified), the data selector 96 selects the data SPD2 sampled by the flip-flop FF2 and outputs it as final sampling data SPD. . Also, flip-flop FF2 is enabled and flip-flop FF1 is disabled. In this way, sampling clock edge switching based on a preamble error notification can be realized.

  As shown in FIG. 7B, the preamble error detection circuit 100 may include an error count circuit 110. The error count circuit 110 counts the number of times the preamble code (for example, PRE−) is not detected (the number of preamble errors). The preamble error detection circuit 100 activates the error notification signal PREER to notify a preamble error when the number of preamble code non-detections (the number of preamble errors) reaches a given number (for example, two or more). To do. By doing so, it is possible to prevent a situation in which the edge of the sampling clock is switched due to erroneous detection of a preamble error.

  That is, in serial transfer using a differential signal line, data bit inversion may occur due to noise or the like generated in the transmission path, and a preamble error may be detected. In such a case, if a preamble error is notified only by detecting a preamble error once and the edge of the sampling clock is switched, the data is originally sampled at the correct edge, but it is incorrect. There is a possibility that data may be sampled at the edge.

  If the error count circuit 110 as shown in FIG. 7B is provided and the preamble error is notified to the sampling circuit 90 or the like on the condition that the preamble error is detected a plurality of times, the occurrence of the above-described situation can be prevented. And the reliability of data transfer can be improved.

4). Detection of Negative Code Preamble Code In this embodiment, as shown in FIGS. 5A and 5B, when the differential signal line is in an idle state, data “0” is transferred. After the idle state, a plus code preamble code PRE + is transferred, followed by a minus code preamble code PRE−, and then a data packet is transferred. As shown in FIG. 4, the first bit of the preamble code PRE + is “1”. Therefore, when the preamble code PRE + is transferred after an idle state for a long period, the data changes rapidly to “1” after “0” continues for a long time. There is a possibility that a receiver circuit, which is a circuit, cannot be detected properly. If a change in data from “0” to “1” cannot be properly detected as described above, a preamble error is erroneously notified even though the preamble code PRE + is sampled at the correct sampling edge. A situation occurs in which the sampling edge is erroneously switched.

  Therefore, in this embodiment, as shown in FIG. 8, only the minus code preamble code PRE− is detected without ignoring the plus code preamble code PRE +. Then, on the condition that the preamble code PRE- has not been detected (provided that PRE- has not been detected one or more times), the error notification signal PREER is activated to notify the preamble error.

  If only the preamble code PRE− is detected in this way, PRE + is ignored even if a change in data from “0” to “1” in the first bit of PRE + cannot be detected. No preamble error is detected. Therefore, it is possible to prevent a situation in which the sampling edge is erroneously switched due to erroneous notification of a preamble error.

  In FIG. 8, a period TPRE is a period necessary for transferring the preamble codes PRE + and PRE− after the data changes from “0” representing the idle state to “1”. For example, when PRE + and PRE− are 10-bit codes as shown in FIG. 4, the period TPRE is a period necessary for transferring 20-bit data. In this case, it is desirable that the detection process of the preamble code PRE− is performed until the detection period TDEC longer than the period TPRE elapses after the data changes from “0” to “1”. When PRE- is not detected within this detection period TDEC (when PRE- is not detected one or more times), a preamble error is notified. In this way, PRE- can be reliably detected.

  That is, as described above, if the data suddenly changes from “0” to “1” in the first bit of PRE +, the receiver circuit which is an analog circuit cannot follow the change and a detection error may occur. . Therefore, if the detection period TDEC is set to the same length as the period TPRE, the last bit of PRE- and the like cannot be detected, and an erroneous preamble error is notified.

  On the other hand, as shown in FIG. 8, if the detection period TDEC is set to a period longer than the period TPRE, even if a detection error occurs in the first bit of PRE +, the last bit of PRE- and the like can be detected properly. The occurrence of the above situation can be prevented.

  The progress of the detection period TDEC can be measured by a detection period counting circuit as will be described later. Specifically, since the period TPRE is a 20-bit period, for example, a period of 21 bits or more is set as the detection period TDEC, and the passage of the detection period TDEC of 21 bits or more is counted by the detection period counting circuit. . Further, the method of notifying the preamble code PRE + but only detecting the PRE− to notify the preamble error can be applied not only to the configuration in which the sampling edge is switched, but also to the configuration in which the sampling edge is not switched.

5). Detailed Configuration Example FIG. 9 shows a detailed configuration example of the sampling circuit 90 and the preamble error detection circuit 100. In FIG. 9, the sampling circuit 90 includes first and second sampling circuits 92-1 and 92-2, a data selector 96, and a selection signal generation circuit 98. Some of these circuit blocks may be omitted.

  Here, the first sampling circuit 92-1 uses the data DTO (DTI) transferred through the differential signal line for data transfer, and the clock CLK transferred through the differential signal line for clock transfer. Sampling is performed at the rising edge (in a broad sense, one of the rising edge and the falling edge). On the other hand, the second sampling circuit 92-2 samples the DTO at the falling edge of CLK (in other words, the other edge different from the above).

  The data selector 96 selects either the data SPD1 sampled by the first sampling circuit 92-1 or the data SPD2 sampled by the second sampling circuit 92-2, and outputs it as the sampling data SPD.

  The selection signal generation circuit 98 receives the error notification signals PREER1 and PREER2 from the preamble error detection circuit 100 and generates a selection signal SEL. The data selector 96 selects either SPD1 or SPD2 based on the generated selection signal SEL and outputs it as an SPD.

  The preamble error detection circuit 100 includes first and second preamble error detection circuits 102-1 and 102-2. The first preamble error detection circuit 102-1 performs a preamble code (eg, PRE-) detection process based on the data SPD1 sampled by the first sampling circuit 92-1, and no preamble code is detected. In this case, the error notification signal PREER1 is activated to notify a preamble error. On the other hand, the second preamble error detection circuit 102-2 performs a preamble code (eg, PRE-) detection process based on the data SPD2 sampled by the second sampling circuit 92-2, and no preamble code is detected. If the error is detected, the error notification signal PREER2 is activated to notify the preamble error.

  In this embodiment, when the data selector 96 receives a preamble error from the first preamble error detection circuit 102-1, the data selector 96 selects the SPD2 from the second sampling circuit 92-2 and outputs it as an SPD. . Specifically, when the error notification signal PREER1 becomes active, the selection signal generation circuit 98 generates a selection signal SEL that causes the data selector 96 to select SPD2.

  The data selector 96 is sampled by the first sampling circuit 92-1, when no preamble error is notified from either the first or second preamble error detection circuits 102-1, 102-2. Data SPD1 is selected and output as SPD. Specifically, when neither of the error notification signals PREER1 and PREER2 is active, the selection signal generation circuit 98 generates a selection signal SEL that causes the data selector 96 to select SPD1.

  With the configuration as shown in FIG. 9, it is possible to reliably perform sampling of data using a clock, detection of a preamble error based on these sampling data, and selection of sampling data based on the detection result.

  FIG. 10 shows a detailed configuration example of the first and second sampling circuits 92-1 and 92-2, and the first and second preamble error detection circuits 102-1 and 102-2.

  The first sampling circuit 92-1 includes a shift register that receives data DTO (DTI) at the first stage and includes a plurality of flip-flops FF11 to FF20. The clock CLK is input to the clock terminals of these flip-flops FF11 to FF20, and the FF11 to FF20 hold (sample) data at the rising edge of CLK. The second sampling circuit 92-2 includes a shift register in which data DTO (DTI) is input to the first stage and includes a plurality of flip-flops FF21 to FF30. Since the inverted signal of CLK by the inverter circuit INV2 is input to the clock terminals of these flip-flops FF21 to FF30, the FF21 to FF30 hold (sample) data at the falling edge of CLK.

  The first preamble error detection circuit 102-1 includes a first head bit detection circuit 103-1, a first detection period count circuit 104-1, a first preamble code detection circuit 105-1, and a first idle detection. A circuit 106-1, a first edge detection circuit 107-1, and a first error count circuit 110-1 are included. On the other hand, the second preamble error detection circuit 102-2 includes a second head bit detection circuit 103-2, a second detection period count circuit 104-2, a second preamble code detection circuit 105-2, and a second It includes an idle detection circuit 106-2, a second edge detection circuit 107-2, and a second error count circuit 110-2. A part of these circuit blocks may be omitted.

  The first and second head bit detection circuits 103-1 and 103-2 detect the head bit of the preamble code PRE +. Specifically, the outputs of the first flip-flops FF11 and FF21 are input to the first and second leading bit detection circuits 103-1 and 103-2, and data is transferred from “0” to “1” indicating the idle state. When the change occurs, the change is detected and the count start signals CST1 and CST2 are activated.

  When the count start signals CST1 and CST2 become active, the first and second detection period count circuits 104-1 and 104-2 start an operation of counting the passage of the detection period. Specifically, as shown in FIG. 8, the detection period TDEC is set to a period longer than the period TPRE, for example, a period of 22 bits. The first and second detection period count circuits 104-1 and 104-2 start a count-up operation in synchronization with the clock CLK when CST1 and CST2 become active, and when the count value exceeds 22, for example, CQ1 and CQ2 are made active ("1"). The count operations of the first and second detection period count circuits 104-1 and 104-2 are cleared (reset) when the signals RVD1 and RVD2 become active (“1”).

  Preamble code detection circuits 105-1 and 105-2 detect the preamble code PRE-. Specifically, the preamble code detection circuit 105-1 activates the code detection signal CDEC1 (“1”) when the bit values of the flip-flops FF20 to FF11 coincide with the PRE-code (0011111001) in FIG. To. On the other hand, the preamble code detection circuit 105-2 activates the code detection signal CDEC2 (“1”) when the bit values of the flip-flops FF30 to FF21 coincide with the code (0011111001) of PRE−. These preamble code detection circuits 105-1 and 105-2 are configured by a NOR circuit, an AND circuit, etc. connected as shown in FIG. 10 (may be configured by an exclusive OR circuit).

  The idle detection circuits 106-1 and 106-2 are circuits that detect an idle state of data transfer. Specifically, the idle detection circuits 106-1 and 106-2 activate the idle detection signals IDEC1 and IDEC2 ("1") when the bit values of the flip-flops FF20 to FF11 and FF30 to FF11 become (0000000). ). As shown in FIG. 10, these idle detection circuits 106-1 and 106-2 can be constituted by NOR (OR) circuits to which outputs of flip-flops FF20 to FF11 and FF30 to FF21 are input.

  The first and second edge detection circuits 107-1 and 107-2 are reset when the idle detection signals IDEC 1 and IDEC 2 become active (“1”) and make the signals EQ 1 and EQ 2 inactive (“0”). . On the other hand, when the code detection signals CDEC1 and CDEC2 become active (“1”), the signals EQ1 and EQ2 become active (“1”).

  The first and second error count circuits 110-1 and 110-2 reset the count values when the preamble code PRE- is detected within the detection period TDEC. That is, when the signals CQ1 and CQ2 are “0” (within the detection period TDEC) and the signals EQ1 and EQ2 are “1” (when PRE− is detected), the count value is reset. Further, the first and second error count circuits 110-1 and 110-2 increment the count value when the preamble code PRE- is not detected even though the detection period TDEC has elapsed. That is, when the signals CQ1 and CQ2 are “1” and the signals EQ1 and EQ2 are “0” (when PRE− is not detected), the count value is counted up. The first and second error count circuits 110-1 and 110-2 activate the error notification signals PREER1 and PREER2 when the count value reaches a given number (for example, 2 or more).

  When both error notification signals PREER1 and PREER2 are inactive, the selection signal generation circuit 98 sets the selection signal SEL to “1” and causes the data selector 96 to select the data SPD1. That is, in the normal case, the rising edge is prioritized and the data SPD1 sampled at the rising edge is output. On the other hand, when the error notification signal PREER1 becomes active, the selection signal SEL is set to “0” to cause the data selector 96 to select SPD2 instead of SPD1. That is, when PRE- is detected a predetermined number of times in the data sampled at the rising edge, the sampling edge is switched, and the data SPD2 sampled at the falling edge is output as the sampling data SPD. .

  With the configuration as shown in FIG. 10, it is possible to realize sampling clock edge switching based on a preamble error notification. If the technique of FIG. 8 in which PRE + is ignored and only PRE− is detected is adopted, but the edge switching of the sampling clock is not performed, the second sampling circuit 92-2 in FIGS. 9 and 10, for example, The data selector 96, the selection signal generation circuit 98, the second preamble error detection circuit 102-2, and the like may be omitted.

6). Electronic Device FIG. 11 shows a configuration example of the electronic device of this embodiment. This electronic apparatus includes the interface circuits 502, 512, 514, 522, and 532 described in this embodiment. Further, it includes a baseband engine 500 (a communication device in a broad sense), an application engine 510 (a processor in a broad sense), a camera 540 (an imaging device in a broad sense), or an LCD 550 (a display device in a broad sense). Note that some of these may be omitted. According to the configuration shown in FIG. 11, a mobile phone having a camera function and an LCD (Liquid Crystal Display) display function can be realized. However, the electronic device of the present embodiment is not limited to a mobile phone, and can be applied to various electronic devices such as a digital camera, a PDA, an electronic notebook, an electronic dictionary, or a portable information terminal.

  As shown in FIG. 11, the data transfer described in this embodiment is performed between the host-side interface circuit 502 provided in the baseband engine 500 and the target-side interface circuit 512 provided in the application engine 510 (graphic engine). And clock transfer. The data transfer and clock transfer described in this embodiment are also performed between the host-side interface circuit 514 provided in the application engine 510 and the target-side interface circuits 522 and 532 provided in the camera interface 520 and the LCD interface 530. Done.

  According to the configuration of FIG. 11, EMI noise can be reduced and mounting can be facilitated as compared with a conventional electronic device that performs data transfer via a parallel bus. Further, by realizing a reduction in the size and power consumption of the interface circuit, it is possible to further reduce the power consumption of the electronic device.

  The present invention is not limited to that described in the above embodiment, and various modifications can be made. For example, terms in the specification or drawings have broad or synonymous terms (one edge, the other edge, an encoding method for extending the bit width, device, clock, data transfer, communication device, processor, imaging device, display device) Etc.) (rising edge, falling edge, 8B / 10B encoding method, host device / target device, strobe, IN transfer / OUT transfer, baseband engine, application engine, camera, LCD, etc.) In other descriptions in the specification or drawings, terms can be replaced with broad or synonymous terms.

  Further, the configuration of the interface circuit of the present embodiment is not limited to the configuration described with reference to FIGS. 1 to 3 and the configuration of the sampling circuit and the preamble error detection circuit is not limited to the configuration described with reference to FIGS.

Explanatory drawing of the data transfer control method of this embodiment using a differential signal line. 3 is a configuration example of a host-side interface circuit. 3 shows a configuration example of a target side interface circuit. Explanatory drawing of the special code of 8B / 10B encoding system. 5A and 5B are explanatory diagrams of the relationship between data and a clock. 6A and 6B are explanatory diagrams of a sampling circuit and a preamble error detection circuit. 7A and 7B are explanatory diagrams of a sampling circuit and a preamble error detection circuit. Explanatory drawing of the method of ignoring PRE + and detecting only PRE-. A detailed example of a sampling circuit and a preamble error detection circuit. A detailed example of a sampling circuit and a preamble error detection circuit. Configuration example of an electronic device.

Explanation of symbols

10 host device, 12 PLL circuit, 20 interface circuit,
22, 24 Transmitter circuit for OUT transfer, clock transfer,
26, 28 Receiver circuit for IN transfer, strobe transfer,
30 target devices, 40 interface circuits,
42, 44 Receiver circuit for OUT transfer, clock transfer,
46, 48 IN transmitter, strobe transfer transmitter circuit,
50, 70 Transaction layer circuit, 52, 72 Packet generation & transfer abort circuit,
54, 74 8B / 10B encoding circuit, 55, 75 code addition circuit,
56, 76 Parallel / serial conversion circuit, 60, 80 Serial / parallel conversion circuit,
62, 828 8B / 10B decoding circuit, 63, 83 code idle detection circuit,
65, 85 FIFO, 66, 86 I / F signal generation circuit,
68, 88 Packet analysis & header data separation circuit,
90, 91 sampling circuit, 92-1, 92-2 first and second sampling circuits, 96 data selector, 98 selection signal generation circuit, 100, 101 preamble error detection circuit, 102-1, 102-2 first, Second preamble error detection circuit, 103-1, 103-2 First and second head bit detection circuits, 104-1 and 104-2 First and second detection period count circuits, 105-1, 105- 2 1st, 2nd preamble code detection circuit, 106-1, 106-2 1st, 2nd idle detection circuit, 107-1, 106-2 1st, 2nd edge detection circuit, 110-1, 110-2 first and second error count circuits;

Claims (11)

An interface circuit having a differential signal interface,
A sampling circuit that samples data transferred via a differential signal line for data transfer based on a clock transferred via a differential signal line for clock transfer;
A preamble error detection circuit for performing a preamble code detection process based on the data sampled by the sampling circuit and notifying a preamble error when no preamble code is detected,
The sampling circuit is
When a preamble error is notified about data sampled at one of the rising edge and falling edge of the clock transferred via the differential signal line for clock transfer, the other edge different from the one is said An interface circuit characterized by outputting the data sampled in step 1 as sampling data. In claim 1,
The preamble error detection circuit is
Detection of a minus code preamble code without performing a plus code preamble code detection process when a minus code preamble code is transferred via a differential signal line for data transfer following a plus code preamble code. An interface circuit that performs processing and notifies a preamble error when a minus code preamble code is not detected. An interface circuit having a differential signal interface,
A sampling circuit that samples data transferred via a differential signal line for data transfer based on a clock transferred via a differential signal line for clock transfer;
A preamble error detection circuit for performing a preamble code detection process based on the data sampled by the sampling circuit and notifying a preamble error when no preamble code is detected,
The preamble error detection circuit is
Detection of the minus code preamble code without performing the plus code preamble code detection process when the minus code preamble code is transferred via the differential signal line for data transfer following the plus code preamble code. An interface circuit that performs processing and notifies a preamble error when a minus code preamble code is not detected. In claim 2 or 3,
The preamble error detection circuit is
After the data changes from the first level representing the idle state to the second level, until a given detection period has elapsed that is longer than the period required to transfer the plus code preamble code and the minus code preamble code, An interface circuit that performs a detection process of a minus code preamble code and notifies a preamble error when a minus code preamble code is not detected within the detection period. In any one of Claims 1 thru | or 4,
The preamble error detection circuit is
An interface circuit including an error count circuit for counting the number of times a preamble code is not detected, and notifying a preamble error when the number of times of non-detection reaches a given number. In any one of Claims 1 thru | or 5,
The sampling circuit is
First sampling for sampling data transferred through a differential signal line for data transfer at one edge of a rising edge and a falling edge of a clock transferred through a differential signal line for clock transfer Circuit,
A second sampling circuit for sampling data transferred through the differential signal line for data transfer at the other edge different from the one of the clocks transferred through the differential signal line for clock transfer; ,
A data selector that selects one of the data sampled by the first sampling circuit and the data sampled by the second sampling circuit and outputs the selected data as sampling data;
The preamble error detection circuit is
A first preamble error detection circuit for performing a preamble code detection process based on the data sampled by the first sampling circuit and notifying a preamble error when no preamble code is detected;
A second preamble error detection circuit that performs a preamble code detection process based on the data sampled by the second sampling circuit and notifies a preamble error when no preamble code is detected;
The data selector is
An interface circuit, wherein when a preamble error is notified from the first preamble error detection circuit, data sampled by the second sampling circuit is selected and output as sampling data. In claim 6,
The data selector is
When a preamble error is not notified from either of the first and second preamble error detection circuits, the data sampled by the first sampling circuit is selected and output as sampling data. Interface circuit. In claim 6 or 7,
The first preamble error detection circuit comprises:
A first detection period counting circuit that counts a given detection period after the data changes from the first level representing the idle state to the second level, and the preamble code is detected within the detection period If not, it will report a preamble error
The second preamble error detection circuit comprises:
A second detection period counting circuit that counts a given detection period after the data has changed from the first level representing the idle state to the second level, and the preamble code is detected within the detection period An interface circuit for notifying a preamble error when not performed. In claim 8,
The first and second detection period counting circuits are:
When a minus code preamble code is transferred via a differential signal line for data transfer following a plus code preamble code, it is longer than the period required for transferring the plus code preamble code and the minus code preamble code. Counts the long detection period,
The first and second preamble error detection circuits include:
An interface circuit for notifying a preamble error when a minus code preamble code is not detected within the detection period. In any one of Claims 1 thru | or 9,
An interface circuit, wherein the preamble code is a code that is assigned to a special code obtained by an encoding method for extending a bit width and transferred via a differential signal line for data transfer. The interface circuit according to any one of claims 1 to 10,
At least one of a communication device, a processor, an imaging device, and a display device;
An electronic device comprising:

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