JP4190399B2 - Channel clear access signal generation circuit and electronic apparatus - Google Patents

Description

  The present invention relates to a radio transmission control signal, and more particularly to a channel clear access signal generation circuit and an electronic apparatus that generate a channel clear access (CCA) signal for determining the possibility of transmission in a wireless LAN system.

  In a wireless LAN system, a plurality of wireless devices perform wireless communication by transmitting wireless packet signals on radio waves having the same frequency. When a radio packet is transmitted, if radio waves of the same frequency are used by another radio device, interference occurs, the other party's communication is disturbed, and one's own communication cannot be performed. Therefore, it is necessary to confirm whether or not radio waves of the same frequency are being used by other wireless devices before transmission.

  This confirmation work is performed by receiving a signal in the frequency band to be used and comparing the level of the received signal with a preset threshold value, and the confirmation result is a channel clear access (CCA) signal. Is output. When the level of the received signal is higher than the threshold value, the CCA signal becomes “H”, and the radio enters a channel busy state in which a signal in the frequency band cannot be transmitted. On the other hand, when the level of the received signal is lower than the threshold, the CCA signal becomes “L”, and the radio enters a channel clear state in which a signal in the frequency band can be transmitted.

  The sensitivity of this CCA signal is as follows in the “Low Power Data Communication System / Wideband Mobile Access System (CSMA)” standard of the American Industrial Standards IEEE 802.11a and the Japanese Radio Industry Standards ARIB STD-T71. There are such regulations (see, for example, Non-Patent Document 1). “When the receiving side receives an OFDM signal conforming to the standard at a reception sensitivity (−82 dBm) level at 6 Mbit / s or higher, Busy is displayed on the CCA within 4 μs with a probability of 90% or higher. Is not received, the CCA signal Busy is held for a level (−62 dBm) exceeding the reception sensitivity at 6 Mbit / s by 20 dBm. ”

  Here, OFDM is one of modulation schemes called orthogonal frequency division multiplexing. 6 Mbit / s indicates that the data transfer amount per second is 6 Mbit. The preamble is a signal having a certain length added separately from the data originally transferred at the head of the normal packet. The receiving-side radio detects the preamble signal to determine that the received signal is a normal packet, and performs synchronization timing such as valid data transmission recognition, receiving-side activation, and internal operation timing control. Is detected. Therefore, a certain amount of time is required from the reception of the normal packet to the detection of the synchronization timing. If the preamble signal cannot be detected, the received signal is not a normal packet, so that the synchronization timing cannot be detected.

  FIG. 3 shows a conventional channel clear access (CCA) signal generation circuit that satisfies the above definition. The conventional CCA signal generation circuit 31 includes a comparison circuit 32, a register 33, and a synchronization timing detection circuit 34. Then, the comparison circuit 32 compares the level of the reception signal received by the antenna 35 with the first threshold value −82 dBm stored in the register 33 in advance, and outputs when the level of the reception signal is equal to or higher than the first threshold value. The CCA signal is set to “H” within 4 μsec. In this state, when the synchronization timing detection circuit 34 cannot receive the preamble signal from the reception signal and cannot detect the synchronization timing, the synchronization timing detection circuit 34 notifies the processor 36 provided outside the CCA signal generation circuit 31 to that effect. The processor 36 then controls to update the threshold data stored in the register 33 from the first threshold value −82 dBm to the second threshold value −62 dBm. Next, the comparison circuit 32 changes the CCA signal from “H” to “L” when the level of the received signal is less than the second threshold, while when the level of the received signal is equal to or higher than the second threshold, The CCA signal is kept “H”.

  Specifically, the CCA signal is as follows depending on the type and level of the received signal. First, as a first state, when noise of −82 dBm or more and less than −62 dBm is received, the CCA signal is “H” because the first threshold is equal to or greater than 82 dBm. Next, because of noise, the synchronization timing cannot be detected, and the threshold value is changed to the second threshold value −62 dBm. Then, since the level of the received signal is less than the second threshold value −62 dBm, the CCA signal changes from “H” to “L”.

  Next, as a second state, when noise of -62 dBm or more is received, the threshold is changed to the second threshold -62 dBm as in the first state, but the level of the received signal is more than the threshold -62 dBm. Therefore, the CCA signal is continuously held in the “H” state.

As a third state, when a normal packet of −82 dBm or higher is received, the CCA signal becomes “H” because the first threshold is −82 dBm or higher. Further, since the normal packet is received and the synchronization timing can be detected, the threshold value is not changed, and the CCA signal “H” is held while the normal packet is being received.
Supervised by Matsue and Morikura, “802.11 High-Speed Wireless LAN Textbook” IDG Japan Co., Ltd. March 2003, pp. 67-68

  In the conventional CCA signal generation circuit, when the synchronization timing cannot be detected, the threshold value stored in the register needs to be updated from −82 dBm to −62 dBm. Since the threshold value is updated via a processor outside the CCA signal generation circuit, it takes a time of several hundreds nsec to several μsec, and there is a problem in that a delay in subsequent processing is caused. Further, it is necessary to provide a circuit for updating and controlling the threshold data in the processor, which causes a problem that the circuit becomes complicated.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a channel clear access signal generation circuit capable of preventing processing delay and simplifying the circuit.

  The channel clear access signal generation circuit according to the present invention includes a first carrier sense signal generation circuit that outputs a first carrier sense signal for a predetermined time when the level of the reception signal is equal to or higher than a first threshold, When the level is equal to or higher than the second threshold higher than the first threshold, the second carrier sense signal is output, and when the level of the received signal becomes lower than the second threshold, the output of the second carrier sense signal is stopped. A second carrier sense signal generation circuit; a synchronization timing signal generation circuit that outputs a synchronization timing signal when synchronization timing is detected from the received signal; and a first carrier sense signal, a second carrier sense signal, and a synchronization timing signal A channel clear access signal determination circuit for outputting a logical sum as a channel clear access signal. Other features of the present invention will become apparent below.

  According to the present invention, processing delay can be prevented and the circuit can be simplified.

  A channel clear access (CCA) signal generation circuit according to an embodiment of the present invention is shown in FIG. The CCA signal generation circuit 11 that is a channel clear access signal generation circuit includes a CS1 signal generation circuit 12 that is a first carrier sense signal generation circuit, a first register 13, and a CS2 that is a second carrier sense signal generation circuit. It includes a signal generation circuit 14, a second register 15, an SQ signal generation circuit 16 that is a synchronization timing signal generation circuit, and a CCA signal determination circuit 17 that is a channel clear access signal determination circuit.

  When the level of the received signal received by the antenna 18 is equal to or higher than the first threshold value −82 dBm stored in the first register 13, the CS1 signal generation circuit 12 receives the CS1 signal that is the first carrier sense signal. Is output at “H”, and the CS1 signal is forcibly set to “L” when a predetermined time elapses. That is, the CS1 signal generation circuit 12 outputs the CS1 signal for a predetermined time when the level of the received signal is equal to or higher than the first threshold value −82 dBm.

  In addition, when the level of the received signal is equal to or higher than the second threshold value −62 dBm stored in the second register 15, the CS2 signal generation circuit 14 outputs the CS2 signal that is the second carrier sense signal as “H”. When the level of the received signal becomes less than the second threshold value −62 dBm, the CS2 signal is set to “L”. That is, the CS2 signal generation circuit 14 outputs the CS2 signal when the level of the received signal is equal to or higher than the second threshold value −62 dBm, and outputs the CS2 signal when the level of the received signal becomes lower than the second threshold value −62 dBm. stop.

  When the SQ signal generation circuit 16 receives the preamble signal from the received signal and detects the synchronization timing, the SQ signal generation circuit 16 outputs the SQ signal, which is the synchronization timing signal, at “H”, and completes the reception processing of the received signal data. The SQ signal is set to “L”. That is, when the SQ signal generation circuit 16 detects the synchronization timing from the received signal, it outputs the SQ signal. For example, when the received signal is noise or a radio signal of another system, the synchronization timing is not detected, so the SQ signal remains “L”.

  Then, the CCA signal determination circuit 17 outputs a logical sum of the CS1 signal, the CS2 signal, and the SQ signal as a CCA signal.

  Here, when the SQ signal generation circuit 16 receives the preamble signal within a predetermined time, the SQ signal generation circuit 16 detects the synchronization timing and outputs an “H” SQ signal. Therefore, the timing at which the CS1 signal returns from “H” to “L” is shifted by one clock after the timing at which the SQ signal generation circuit 16 outputs the SQ signal. Thus, the CCA signal does not become “L” before the SQ signal is output, and the channel is not cleared. Although the timing to shift later is not limited to one clock, it is preferably one clock because the preset time for detecting the synchronization timing is fixed.

  FIG. 2 shows a timing chart of the received signal, the CS1 signal, the CS2 signal, the SQ signal, and the CCA signal. FIG. 2 shows first to fourth states with different types and levels of received signals. In these four states, the CCA signal is as follows:

  First, the first state is a state in which noise of −82 dBm or more and less than −62 dBm is received. Since the level of the received signal is −82 dBm or higher, the CS1 signal becomes “H”, and the CCA signal also becomes “H” accordingly. Thereafter, the CS1 signal becomes “L” when a predetermined time elapses. Further, since the level of the received signal is less than −62 dBm, the CS2 signal remains “L”. Since the received signal is noise, the synchronization timing is not detected, and the SQ signal remains “L”. Therefore, as the CS signal becomes “L”, the CCA signal also becomes “L”.

  Next, the second state is a state in which noise of −62 dBm or more is received. Since the level of the reception signal is −82 dBm or more, the CS1 signal becomes “H”. Thereafter, the CS1 signal becomes “L” when a predetermined time elapses. Since the level is −62 dBm or more, the CS2 signal becomes “H” during the reception period. Since noise is received, the synchronization timing is not detected, and the SQ signal remains “L”. Therefore, as the reception of noise ends and the CS2 signal becomes “L”, the CCA signal also becomes “L”.

  The third state is a state where a normal packet of −82 dBm or more and less than −62 dBm is received. Since the level of the reception signal is −82 dBm or more, the CS1 signal becomes “H”. Thereafter, the CS1 signal becomes “L” when a predetermined time elapses. Further, since the level of the received signal is less than −62 dBm, the CS2 signal remains “L”. Since the received signal is a normal packet, the preamble signal is received within a predetermined time, the synchronization timing is detected, the SQ signal becomes “H” at that time, and remains “H” until the normal packet reception processing is completed. To do. Therefore, the CCA signal becomes “H” as the CS1 signal becomes “H”, and becomes “L” as the reception process is completed and the SQ signal becomes “L”.

  Next, the fourth state is a state in which a normal packet of −62 dBm or more is received. Since the level of the reception signal is −82 dBm or more, the CS1 signal becomes “H”. Thereafter, the CS1 signal becomes “L” when a predetermined time elapses. Since the level is −62 dBm or more, the CS2 signal becomes “H” during the reception period. Since the received signal is a normal packet, the preamble signal is received within a predetermined time and the synchronization timing is detected, so that the SQ signal becomes “H” at that time and remains “H” until the normal packet receiving process is completed. To maintain. Accordingly, the CCA signal becomes “H” along with “H” of the CS1 signal and “H” of the CS2 signal, and becomes “L” as the reception processing is completed and the SQ signal becomes “L”.

  In the above first to fourth states, when the level of the received signal is −82 dBm or more, the CS1 signal becomes “H”, and the CCA signal also becomes “H” accordingly. In general, the level detection time can be ordered within 1 μsec or less. Further, in the first state, since the received signal is noise, the synchronization timing cannot be detected. In the second state, since the level of the received signal is −62 dBm or higher, the CS2 signal is set to “H”, and the CCA The signal is busy. Therefore, the channel clear access signal generation circuit according to the embodiment of the present invention can satisfy the specifications of the CCA signal of the American Industrial Standards IEEE 802.11a and the Japanese Radio Industry Standard ARIB STD-T71.

  As described above, the channel clear access signal generation circuit according to the present invention changes the threshold data of the register even when the synchronization timing cannot be detected and the threshold to be compared with the level of the received signal needs to be changed. There is no need. As a result, the change time of several hundred ns to several μs, which was necessary in the prior art, can be omitted, so that processing delay can be prevented. In addition, since a circuit for performing update control of threshold data, which has conventionally been necessary, can be omitted, the circuit can be simplified.

  Further, if an electronic device such as a radio device is configured to include the above-described channel clear access signal generation circuit, the same effect can be obtained.

It is the schematic which shows the channel clear access (CCA) signal generation circuit based on embodiment of this invention. It is a timing chart of a received signal, a CS1 signal, a CS2 signal, an SQ signal, and a CCA signal. FIG. 2 is a schematic diagram illustrating a conventional channel clear access (CCA) signal generation circuit.

Explanation of symbols

11 CCA signal generation circuit (channel clear access signal generation circuit)
12 CS1 signal generation circuit (first carrier sense signal generation circuit)
14 CS2 signal generation circuit (second carrier sense signal generation circuit)
16 SQ signal generation circuit (synchronous timing signal generation circuit)
17 CCA signal determination circuit (channel clear access signal determination circuit)

Claims (2)

A first carrier sense signal generation circuit that outputs a first carrier sense signal for a predetermined time when the level of the received signal is equal to or higher than a first threshold;
When the level of the received signal is equal to or higher than a second threshold value higher than the first threshold value, a second carrier sense signal is output, and when the level of the received signal becomes less than the second threshold value, A second carrier sense signal generation circuit for stopping the output of the carrier sense signal of
A synchronization timing signal generating circuit that outputs a synchronization timing signal when detecting the synchronization timing from the received signal;
A channel clear access signal generation circuit comprising: a channel clear access signal determination circuit that outputs a logical sum of the first carrier sense signal, the second carrier sense signal, and the synchronization timing signal as a channel clear access signal. circuit. An electronic device comprising the channel clear access signal generation circuit according to claim 1.

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