JP2011138893A - Method of manufacturing semiconductor light-emitting element, semiconductor light-emitting element, lamp, electronic device and mechanical apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor light-emitting element, capable of manufacturing the semiconductor light-emitting element capable of obtaining a high emission output by impressing a large current. <P>SOLUTION: The method of manufacturing the semiconductor light-emitting element 1 includes a process of successively laminating a first n-type semiconductor layer 12a; a second n-type semiconductor layer 12b; a light-emitting layer 13 and a p-type semiconductor layer 14 on a substrate 11, and in the process of forming the second n-type semiconductor layer 12b, the temperature of the substrate 11 is turned to a low temperature below the temperature of the substrate 11, when the light-emitting layer 13 is formed, and the second n-type semiconductor layer 12b is doped with Si, at a high concentration which exceeds that of the first n-type semiconductor layer 12a. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor light-emitting element and a semiconductor light-emitting element, a lamp, an electronic device, and a mechanical device. Particularly, the present invention is preferably used when a large current is applied, and has a high light emission output when the large current is applied. The present invention relates to a method for manufacturing a semiconductor light-emitting element that can be obtained, a semiconductor light-emitting element manufactured by using this manufacturing method, a lamp, an electronic device, and a mechanical device.

  2. Description of the Related Art Conventionally, as a semiconductor light emitting element used for a light emitting diode or the like, there is one in which an n type semiconductor layer, a light emitting layer, and a p type semiconductor layer are sequentially stacked on a substrate. As a method for manufacturing such a semiconductor light emitting device, an n-type semiconductor layer, a light emitting layer, and a p layer are formed on a substrate made of a sapphire single crystal by a metal organic chemical vapor deposition (MOCVD) method. There is a method of successively and successively stacking a type semiconductor layer.

Recently, in order to improve the light emission output of the semiconductor light emitting device, a large current is often applied to the semiconductor light emitting device.
For example, in Patent Document 1, the first electrode includes a first pedestal portion and two or more first extending portions extending in the same direction from the first pedestal portion, and the second electrode is a second pedestal portion. And a semiconductor light emitting device including a second extending portion that extends in substantially the same direction as the first extending portion so as to approach the first pedestal portion from the second pedestal portion, and has high luminous efficiency in a high current density state. It is described that there is.

JP 2008-016809 A

  However, the light emission output of the conventional semiconductor light emitting element increases as the applied current increases, but the effect of improving the light emission output by increasing the applied current decreases as the applied current increases. . Therefore, when a large current is applied to the semiconductor light emitting device, the effect of improving the light emission output by increasing the applied current is insufficient. For this reason, as a semiconductor light emitting device, a light emitting output can be effectively improved by applying a large current, and there has been a demand for a semiconductor light emitting device that can be suitably used when a large current is applied.

  The present invention has been made in view of the above problems, and a semiconductor light emitting device manufacturing method capable of manufacturing a semiconductor light emitting device capable of obtaining a high light emission output when a large current is applied, and manufactured using this manufacturing method. Another object of the present invention is to provide a lamp, an electronic device, and a mechanical device including the semiconductor light emitting element.

As a result of intensive studies to solve the above problems, the present inventor has completed the present invention. That is, the present invention relates to the following.
(1) A step of sequentially laminating a first n-type semiconductor layer, a second n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a substrate, and in the step of forming the second n-type semiconductor layer, the substrate The semiconductor is characterized in that the second n-type semiconductor layer is doped with Si at a higher concentration than the first n-type semiconductor layer at a temperature lower than the temperature of the substrate when forming the light emitting layer. Manufacturing method of light emitting element.

(2) The method for manufacturing a semiconductor light-emitting element according to (1), wherein in the step of forming the second n-type semiconductor layer, the substrate temperature is set to 700 ° C. to 750 ° C.
(3) The concentration of Si doped in the step of forming the second n-type semiconductor layer is in the range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ (1) or (2) The manufacturing method of the semiconductor light emitting element of description.
(4) The method according to any one of (1) to (3), further including a step of forming a buffer layer on the substrate using a sputtering method before the step of forming the first n-type semiconductor layer. The manufacturing method of the semiconductor light emitting element of description.
(5) The step of forming the second n-type semiconductor layer is a step of forming the second n-type semiconductor layer having a superlattice structure obtained by alternately and repeatedly growing two types of thin film layers having different compositions. The layer thickness of the light emitting layer underlayer composed of the thin film layer disposed closest to the light emitting layer in the lattice structure is at least twice the maximum layer thickness of the thin film layer other than the light emitting layer underlayer of the superlattice structure. The method for producing a semiconductor light-emitting element according to any one of (1) to (4), wherein:
(6) The method for manufacturing a semiconductor light-emitting element according to (5), wherein the layer thickness of the light-emitting layer base layer is in the range of 2 nm to 20 nm.

(7) The step of sequentially laminating the first n-type semiconductor layer, the second n-type semiconductor layer, the light emitting layer, and the p-type semiconductor layer on the substrate is performed on the substrate in the first metal organic chemical vapor deposition apparatus. In the first step of laminating the first n-type semiconductor layer and the second metal organic chemical vapor deposition apparatus, a regrowth layer, a second n-type semiconductor layer, a light emitting layer, and a p-type layer are formed on the first n-type semiconductor layer. The method for manufacturing a semiconductor light-emitting element according to any one of (1) to (6), further comprising a second step of sequentially stacking a type semiconductor layer.
(8) A semiconductor light-emitting device manufactured by using the method for manufacturing a semiconductor light-emitting device according to any one of (1) to (7), wherein at least a first n-type semiconductor layer and a second n-type are formed on a substrate. A semiconductor light emitting device, comprising: a semiconductor layer, a light emitting layer, and a p-type semiconductor layer, wherein the second n-type semiconductor layer is doped with Si at a higher concentration than the first n-type semiconductor layer.
(9) A lamp comprising the semiconductor light emitting device according to (8).
(10) An electronic device in which the lamp according to (9) is incorporated.
(11) A mechanical device in which the electronic device according to (10) is incorporated.

  In the method for manufacturing a semiconductor light emitting device of the present invention, in the step of forming the second n-type semiconductor layer, the temperature of the substrate is set to a temperature lower than the temperature of the substrate when forming the light-emitting layer, and the second n-type semiconductor layer is formed. Since the semiconductor layer is doped with Si at a higher concentration than the first n-type semiconductor layer, the n-type doping concentration of the second n-type semiconductor layer can be increased and a crystalline property is formed on the first n-type semiconductor layer. A good second n-type semiconductor layer can be formed, and a light-emitting layer capable of obtaining strong light emission intensity can be formed on the second n-type semiconductor layer. As a result, according to the method for manufacturing a semiconductor light emitting device of the present invention, a semiconductor light emitting device capable of obtaining a high light emission output by applying a large current exceeding, for example, 20 mA can be obtained.

FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor light emitting device of the present invention manufactured using the method for manufacturing a semiconductor light emitting device of the present invention. FIG. 2 is a schematic cross-sectional view for explaining a process for manufacturing the semiconductor light emitting element shown in FIG. FIG. 3 is a schematic cross-sectional view showing an example of a lamp including the semiconductor light emitting element shown in FIG. FIG. 4 is a graph for explaining the relationship between the substrate temperature when forming the n-clad layer and the substrate temperature when forming the light-emitting layer in the method for manufacturing a semiconductor light-emitting device of this embodiment. FIG. 5 is a graph showing the relationship between applied current and power efficiency.

  Hereinafter, a method for manufacturing a semiconductor light emitting device will be described in detail with reference to the drawings as appropriate. The drawings referred to in the following description are for explaining the present invention, and the size, thickness, dimensions, etc. of each part shown in the drawings are different from the dimensional relationships of actual semiconductor light emitting elements, lamps, etc. Yes.

"Semiconductor light emitting device"
FIG. 1 is a schematic cross-sectional view showing an example of a semiconductor light emitting device of the present invention manufactured using the method for manufacturing a semiconductor light emitting device of the present invention.
A semiconductor light emitting device 1 of this embodiment shown in FIG. 1 includes a substrate 11, a laminated semiconductor layer 20 laminated on the substrate 11, a p-type electrode 18 formed on the laminated semiconductor layer 20, and a laminated semiconductor layer 20. And an n-type electrode 17 stacked on the exposed surface 20a.

The stacked semiconductor layer 20 is configured by stacking an n-type semiconductor layer 12, a light emitting layer 13, and a p-type semiconductor layer 14 in this order from the substrate 11 side. The laminated semiconductor layer 20 may include a buffer layer 21 and a base layer 22. As shown in FIG. 1, the p-type semiconductor layer 14, the light emitting layer 13, and the n-type semiconductor layer 12 are partially removed by means such as etching. The exposed portion is the exposed surface 20 a of the laminated semiconductor layer 20. An n-type electrode 17 is formed on the exposed surface 20 a of the laminated semiconductor layer 20.
A translucent electrode 15 is laminated on the upper surface of the p-type semiconductor layer 14, and a p-type bonding pad electrode 16 is laminated on the translucent electrode 15. The translucent electrode 15 and the p-type bonding pad electrode 16 constitute a p-type electrode 18.

As a semiconductor constituting the n-type semiconductor layer 12, the light emitting layer 13, and the p-type semiconductor layer 14, a group III nitride semiconductor is preferably used, and a gallium nitride compound semiconductor is more preferably used. As the gallium nitride-based compound semiconductor constituting the n-type semiconductor layer 12, the light emitting layer 13, and the p-type semiconductor layer 14 in the present invention, a general formula Al _x In _y Ga _1-xy N (0 ≦ x <1,0) Semiconductors having various compositions represented by ≦ y <1, 0 ≦ x + y <1) can be used without any limitation.

  The semiconductor light emitting device 1 of the present embodiment can emit light from the light emitting layer 13 constituting the laminated semiconductor layer 20 by passing a current between the p-type electrode 18 and the n-type electrode 17. Although it is a face-up mount type light emitting element that extracts light from the light emitting layer 13 from the side where the p-type bonding pad electrode 16 is formed, a flip chip type light emitting element that extracts light from the substrate 11 side may be used.

(substrate)
Examples of the substrate 11 include sapphire, SiC, silicon, zinc oxide, magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, and lithium oxide. A substrate formed of aluminum, neodymium gallium oxide, lanthanum strontium aluminum tantalum, strontium titanium oxide, titanium oxide, hafnium, tungsten, molybdenum, or the like can be used. Among the above substrates, it is particularly preferable to use a sapphire substrate having a c-plane as a main surface.

  Among the above substrates, an oxide substrate or a metal substrate that is known to cause chemical modification by contact with ammonia at a high temperature is used, and a buffer layer 21 described later is formed without using ammonia. In addition, when the underlayer 22 described later is formed by a method using ammonia, the buffer layer 21 functions as a coat layer, which is effective in preventing chemical alteration of the substrate 11.

(Buffer layer)
The buffer layer 21 may not be provided, but the difference in lattice constant between the substrate 11 and the base layer 22 is alleviated to form a C-axis oriented single crystal layer on the (0001) C plane of the substrate 11. It is preferable that it is provided to improve the crystallinity of the n-type semiconductor layer 12, the light emitting layer 13, and the p-type semiconductor layer 14. When the single crystal base layer 22 is stacked on the buffer layer 21, the n-type semiconductor layer 12, the light emitting layer 13, and the p-type semiconductor layer 14 with better crystallinity can be stacked.

The buffer layer 21 is preferably made of polycrystalline Al _x Ga _1-x N (0 ≦ x ≦ 1), and more preferably made of single crystal Al _x Ga _1-x N (0 ≦ x ≦ 1). preferable. In the specification, the composition ratio of each element may be omitted and described as AlGaN, GaN, or the like.
The buffer layer 21 can have a thickness of 0.01 to 0.5 μm. If the thickness of the buffer layer 21 is less than 0.01 μm, the buffer layer 21 may not sufficiently obtain an effect of relaxing the difference in lattice constant between the substrate 11 and the base layer 22. On the other hand, when the thickness of the buffer layer 21 exceeds 0.5 μm, although the function as the buffer layer 21 is not changed, the film forming process time of the buffer layer 21 becomes long and the productivity is lowered.

  The buffer layer 21 may have a polycrystalline structure or a single crystal structure. When the buffer layer 21 having such a polycrystalline structure or a single crystal structure is formed on the substrate 11 by the MOCVD method or the sputtering method, the buffer function of the buffer layer 21 works effectively. The group III nitride semiconductor thus formed becomes a crystal film having good orientation and crystallinity.

(Underlayer)
_{Examples of the} underlayer 22 include Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, x + y + z = 1), and Al _x Ga _1-x N (0 ≦ x <1) is preferable because the base layer 22 having good crystallinity can be formed.
The film thickness of the underlayer 22 is preferably 0.1 μm or more, more preferably 0.5 μm or more, and most preferably 1 μm or more. The Al _x Ga _1-x N layer with good crystallinity is more easily obtained when the thickness of the underlayer 22 is greater than or equal to the above thickness. Further, the film thickness of the underlayer 22 is preferably 10 μm or less.
In order to improve the crystallinity of the underlayer 22, it is desirable that the underlayer 22 is not doped with impurities. However, when p-type or n-type conductivity is required, acceptor impurities or donor impurities can be added to the base layer 22.

"Laminated semiconductor layer"
(N-type semiconductor layer)
The n-type semiconductor layer 12 includes an n-contact layer 12a (first n-type semiconductor layer) and an n-cladding layer 12b (second n-type semiconductor layer).

The n contact layer 12 a is a layer for providing the n-type electrode 17.
The n-contact layer 12a is preferably composed of an Al _x Ga _1-x N layer (0 ≦ x <1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1), Si is doped as an n-type impurity (dopant). When Si is contained in the n-contact layer 12a at a concentration of 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ , preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ , good with the n-type electrode 17 From the standpoint of maintaining a good ohmic contact. The n-type impurity used for the n-contact layer 12a is most preferably Si, but may be Si, Ge, Sn, etc., for example, and is not particularly limited.
The film thickness of the n contact layer 12a is preferably 0.1 μm or more, and more preferably 1 μm or more. The film thickness of the n contact layer 12a is desirably 10 μm or less. When the film thickness of the n contact layer 12a is 0.1 μm or more, an Al _x Ga _1-x N layer with good crystallinity is easily obtained.
Further, it is desirable that the n contact layer 12a is doped with an impurity. For example, when n-type conductivity is required, a donor impurity such as Si can be added.

  The n clad layer 12 b is provided between the n contact layer 12 a and the light emitting layer 13. The n-clad layer 12b is a layer for injecting carriers into the light-emitting layer 13 and confining carriers, and also serves as a buffer layer for the light-emitting layer 13 that alleviates the crystal lattice mismatch between the n-contact layer 12a and the light-emitting layer 13. Function. The n clad layer 12b can be formed of AlGaN, GaN, GaInN, or the like. Needless to say, when the n-cladding layer 12b is formed of GaInN, it is desirable to make it larger than the band gap of GaInN of the light emitting layer 13.

The n-clad layer 12b is doped with Si as an n-type impurity (dopant). The concentration of Si doped in the n-clad layer 12b is higher than that of the n-contact layer 12a, and is preferably in the range of 1.2 to 1.5 times that of the n-contact layer 12a. Specifically, the Si doping concentration of the n-clad layer 12b is preferably 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ , more preferably 1 × 10 ¹⁸ to 2 × 10 ¹⁹ / cm ³ . A dope concentration in the range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the light-emitting element.

In the present embodiment, the n-clad layer 12b may be a single layer, but preferably has a superlattice structure formed by alternately and repeatedly growing two types of thin film layers having different compositions.
When the n clad layer 12b is a single layer, the film thickness of the n clad layer 12b is preferably 5 to 500 nm, more preferably 5 to 100 nm.

  When the n clad layer 12b has a superlattice structure, the number of thin film layers is preferably 10 pairs (20 layers) to 40 pairs (80 layers). If the number of stacked thin film layers is 10 pairs or more, the crystal lattice mismatch between the n-clad layer 12b and the light-emitting layer 13 can be more effectively alleviated, and the output of the semiconductor light-emitting element can be further improved. Become prominent. However, if the number of stacked thin film layers exceeds 40 pairs, the superlattice structure may be easily disturbed, and the light emitting layer 13 may be adversely affected. In addition, the deposition time for the n-clad layer 12b is lengthened and productivity is lowered.

  The superlattice structure constituting the n-clad layer 12b includes an n-side first layer made of a group III nitride semiconductor and an n-side second layer made of a group III nitride semiconductor having a composition different from that of the n-side first layer. It is preferable that they are laminated, and it is more preferable that they include a structure in which n-side first layers and n-side second layers are alternately and repeatedly laminated.

  The n-side first layer and the n-side second layer (n-side first layer / n-side second layer) constituting the superlattice structure of the n-cladding layer 12b are an alternating structure of GaInN / GaN and an alternating structure of AlGaN / GaN. , GaInN / AlGaN alternate structure, GaInN / GaInN alternate structure with different compositions (in the present invention, the description “different composition” refers to different elemental composition ratios), AlGaN / AlGaN with different compositions The n-side first layer and / or the n-side second layer are preferably made of a gallium nitride-based compound semiconductor containing In, specifically, a GaInN / GaN alternating structure. Alternatively, an alternate structure of GaInN / GaInN having different compositions is preferable. Further, the n-side first layer and the n-side second layer constituting the superlattice structure have the same composition represented by GaInN, AlGaN, and GaN, and are a combination of a doped structure and an undoped structure. Also good.

  The n-side first layer and the n-side second layer may each have a doped structure, or a combination of a doped structure and an undoped structure. Si is used as an n-type impurity (dopant) to be doped.

When the n-side first layer and / or the n-side second layer constituting the n-clad layer 12b has a superlattice structure made of a gallium nitride-based compound semiconductor containing In, the In composition ratio is the In composition of the light emitting layer. It is preferable to make it smaller than the ratio. When the gallium nitride compound semiconductor containing In that constitutes the n-clad layer 12b is Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 <z ≦ 1, x + y + z = 1), The value of z is preferably in the range of 0.01 to 0.1, and more preferably in the range of 0.01 to 0.05. If the value of z exceeds 0.1, the reverse current of the semiconductor light emitting device 1 increases, which is not preferable.

  The thicknesses of the n-side first layer and the n-side second layer are each preferably 100 angstroms or less, more preferably 60 angstroms or less, further preferably 40 angstroms or less, and each 10 angstroms to 40 angstroms. Most preferably, it is in the angstrom range. If the film thickness of the n-side first layer and / or the n-side second layer forming the superlattice structure is more than 100 angstroms, crystal defects are likely to occur, which is not preferable.

  The layer thickness of the light-emitting layer underlayer consisting of the n-side first layer or the n-side second layer arranged closest to the light-emitting layer 13 of the superlattice structure is the n-th layer thickness other than the light-emitting layer underlayer of the superlattice structure. It is preferably at least twice the maximum layer thickness of the first layer and the n-side second layer, and more preferably in the range of 2 to 20 times. Specifically, the layer thickness of the light emitting layer underlayer is preferably in the range of 2 nm to 20 nm.

(Light emitting layer)
The light emitting layer 13 preferably has a multiple quantum well structure in which barrier layers 13a and well layers 13b are alternately and repeatedly stacked. The number of stacked layers in the multiple quantum well structure is preferably 3 to 10 layers, more preferably 4 to 7 layers. The well layer and / or the barrier layer constituting the light emitting layer 13 is preferably made of a gallium nitride compound semiconductor containing In.

The thickness of the well layer 13b is preferably in the range of 15 angstroms or more and 50 angstroms or less. When the thickness of the well layer 13b is in the above range, higher light emission output can be obtained.
The well layer 13b is preferably a gallium nitride compound semiconductor containing In. A gallium nitride compound semiconductor containing In is preferable because it emits strong light in the blue wavelength region. The well layer 13b can be doped with impurities. As the dopant, it is preferable to use Si or Ge which enhances the emission intensity. The dope amount is preferably about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . When the doping amount is in the above range, the emission intensity is stronger.

The thickness of the barrier layer 13a is preferably in the range of 20 angstroms or more and less than 100 angstroms. If the thickness of the barrier layer 13a is too thin, flattening of the upper surface of the barrier layer 13a is hindered, resulting in a decrease in light emission efficiency and a decrease in aging characteristics. Moreover, when the film thickness of the barrier layer 13a is too thick, a drive voltage rises and light emission falls. Therefore, the thickness of the barrier layer 13a is more preferably 70 angstroms or less.
In addition to GaN and AlGaN, the barrier layer 13a may be formed of InGaN having a smaller In ratio than InGaN constituting the well layer 13b. Among these, GaN is preferable.

The well layer 13a and / or the barrier layer 13b constituting the light-emitting layer 13 is formed of a gallium nitride-based compound semiconductor Al _x Ga _y In _z N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 <z ≦ 1) containing In. , X + y + z = 1), the value of z is preferably in the range of 0.03 to 0.3, and more preferably in the range of 0.05 to 0.2.

  Note that the n-clad layer 12b has a superlattice structure in which n-side first layers and n-side second layers are alternately and repeatedly stacked, and the n-side first layer and / or the n-side second layer is In. The light emitting layer 13 has a multi-well structure in which barrier layers 13a and well layers 13b are alternately and repeatedly stacked, and the well layers 13a and / or barrier layers 13b Is made of a gallium nitride compound semiconductor containing In, the content of In contained in the gallium nitride compound semiconductor constituting the n-cladding layer 12b is included in the gallium nitride compound semiconductor constituting the light emitting layer 13. The content of In is preferably less than the In content.

(P-type semiconductor layer)
The p-type semiconductor layer 14 is generally composed of a p-cladding layer 14a and a p-contact layer 14b. Further, the p contact layer 14b can also serve as the p clad layer 14a.

The p-cladding layer 14a is a layer for confining carriers in the light emitting layer 13 and injecting carriers. The p-cladding layer 14a is not particularly limited as long as it has a composition larger than the band gap energy of the light-emitting layer 13 and can confine carriers in the light-emitting layer 13, but Al _x Ga _1-x N (0 < x ≦ 0.4) is preferable. When the p-cladding layer 14a is made of such AlGaN, it is preferable in terms of confining carriers in the light-emitting layer 13.

The thickness of the p-cladding layer 14a is not particularly limited, but is preferably 1 to 400 nm, and more preferably 5 to 100 nm. The p-type doping concentration of the p-cladding layer 14a is preferably 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ . When the p-type dope concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity. The p-cladding layer 14a may have a superlattice structure in which thin films are stacked a plurality of times.

    When the p-cladding layer 14a includes a superlattice structure, the p-side first layer made of a group III nitride semiconductor and the p-side second made of a group III nitride semiconductor having a composition different from that of the p-side first layer. The layers may be stacked. When the p-cladding layer 14a includes a superlattice structure, the p-cladding layer 14a may include a structure in which p-side first layers and p-side second layers are alternately and repeatedly stacked.

    The p-side first layer and the p-side second layer constituting the superlattice structure of the p-cladding layer 14a may have different compositions, for example, any composition of AlGaN, GaInN, or GaN. GaInN / GaN Alternatively, an alternate structure of AlGaN / GaN, or an alternate structure of GaInN / AlGaN may be used. In the present invention, the p-side first layer and the p-side second layer preferably have an AlGaN / AlGaN or AlGaN / GaN alternating structure.

    The thicknesses of the p-side first layer and the p-side second layer are each preferably 200 angstroms or less, more preferably 100 angstroms or less, even more preferably 40 angstroms or less, and each 10 angstroms to 40 angstroms. Most preferably, it is in the angstrom range. If the thickness of the p-side first layer and the p-side second layer forming the superlattice layer is more than 200 angstroms, crystal defects are likely to occur, which is not preferable.

  Each of the p-side first layer and the p-side second layer may have a doped structure, or a combination of a doped structure and an undoped structure. As the impurity to be doped, conventionally known impurities can be applied to the material composition without any limitation. For example, when a superlattice structure having an AlGaN / GaN alternating structure or an AlGaN / AlGaN alternating structure having a different composition is used as the p-cladding layer, Mg is suitable as the impurity. Further, the p-side first layer and the p-side second layer constituting the superlattice structure have the same composition represented by GaInN, AlGaN, and GaN, and are a combination of a doped structure and an undoped structure. Also good.

The p contact layer 14b is a layer for providing a positive electrode. The p contact layer 14b is preferably made of Al _x Ga _1-x N (0 ≦ x ≦ 0.4) in terms of maintaining good crystallinity and good ohmic contact with the p ohmic electrode. . The p contact layer 14b contains a p-type impurity (dopant) at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ / cm ^3. When it is, it is preferable in terms of maintaining good ohmic contact, preventing the generation of cracks, and maintaining good crystallinity. Although it does not specifically limit as a p-type impurity, For example, it is preferable to use Mg. The thickness of the p contact layer 14b is not particularly limited, but is preferably 10 to 500 nm, and more preferably 50 to 200 nm. When the film thickness of the p contact layer 14b is within this range, it is preferable in terms of light emission output.

(N-type electrode)
The n-type electrode 17 also serves as a bonding pad, and is formed in contact with the n-type semiconductor layer 12 of the laminated semiconductor layer 20. Therefore, when forming the n-type electrode 17, at least a part of the p-semiconductor layer 14 and the light-emitting layer 13 is removed to expose the n-type semiconductor layer 12, and on the exposed surface 20 a of the n-type semiconductor layer 12. An n-type electrode 17 also serving as a bonding pad is formed. As the n-type electrode 17, various compositions and structures are known, and these known compositions and structures can be used without any limitation, and can be provided by conventional means well known in this technical field.

(Translucent electrode)
The translucent electrode 15 is laminated on the p-type semiconductor layer 14 and preferably has a small contact resistance with the p-type semiconductor layer 14. Further, the translucent electrode 15 is preferably excellent in light transmissivity in order to efficiently extract light from the light emitting layer 13 to the outside of the semiconductor light emitting element 1. In addition, the translucent electrode 15 preferably has excellent conductivity in order to diffuse current uniformly over the entire surface of the p-type semiconductor layer 14.

As a constituent material of the translucent electrode 15, any one of conductive oxide containing any one of In, Zn, Al, Ga, Ti, Bi, Mg, W, and Ce, zinc sulfide, or chromium sulfide is used. A translucent conductive material selected from the group consisting of: For example, as the conductive oxide, ITO (indium tin oxide (In ₂ O ₃ —SnO ₂ )), IZO (indium zinc oxide (In ₂ O ₃ —ZnO)), AZO (zinc aluminum oxide (ZnO—Al ₂ O ₃ )), GZO (gallium zinc oxide (ZnO—Ga ₂ O ₃ )), fluorine-doped tin oxide, titanium oxide and the like.

  Moreover, the structure of the translucent electrode 15 may be any structure including a conventionally known structure. The translucent electrode 15 may be formed so as to cover almost the entire surface of the p-type semiconductor layer 14 or may be formed in a lattice shape or a tree shape with a gap.

(P-type bonding pad electrode)
The p-type bonding pad electrode 16 also serves as a bonding pad, and is laminated on the translucent electrode 15. As the p-type bonding pad electrode 16, various compositions and structures are known, and these known compositions and structures can be used without any limitation, and can be provided by conventional means well known in this technical field.
The p-type bonding pad electrode 16 can be formed anywhere as long as it is on the translucent electrode 15. For example, it may be formed at a position farthest from the n-type electrode 17 or may be formed at the center of the semiconductor light emitting device 1. However, if it is formed at a position too close to the n-type electrode 17, it is not preferable because a short circuit between wires and balls occurs when bonding.

  Also, the electrode area of the p-type bonding pad electrode 16 is as large as possible to facilitate the bonding operation, but it prevents the emission of light emission. For example, when a large area exceeding half of the area of the chip surface is covered, the extraction of light emission is hindered, and the output is significantly reduced. Conversely, if the electrode area of the p-type bonding pad electrode 16 is too small, the bonding operation becomes difficult and the product yield is reduced. Specifically, it is preferably slightly larger than the diameter of the bonding ball, and generally has a circular shape with a diameter of 100 μm.

(Protective film layer)
The protective film layer includes, as necessary, the upper surface and side surfaces of the translucent electrode 15, the exposed surface 20a of the n-type semiconductor layer 12, the side surfaces of the light emitting layer 13 and the p-type semiconductor layer 14, the n-type electrode 17 and the p-type bonding. The pad electrode 16 is formed so as to cover the side surface and the peripheral portion. By forming the protective film layer, it is possible to prevent moisture and the like from entering the inside of the semiconductor light emitting element 1 and to suppress deterioration of the semiconductor light emitting element 1.
As the protective film layer, it is preferable to use an insulating material having a transmittance of 80% or more at a wavelength in the range of 300 to 550 nm. For example, silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), niobium oxide (Nb ₂ O ₅ ), tantalum oxide (Ta ₂ O ₅ ), silicon nitride (Si ₃ N ₄ ), aluminum nitride (AlN), or the like can be used. Among these, SiO ₂ and Al ₂ O ₃ are more preferable because a dense film can be easily formed by CVD film formation.

"Manufacturing method of semiconductor light emitting device"
In order to manufacture the semiconductor light emitting device 1 shown in FIG. 1, first, the laminated semiconductor layer 20 shown in FIG. 2 is manufactured. In order to manufacture the laminated semiconductor layer 20 shown in FIG. 2, first, the substrate 11 such as a sapphire substrate is prepared, and the buffer layer 21 is laminated on the substrate 11 by sputtering.
In the present embodiment, since the buffer layer 21 is formed using a sputtering method, for example, compared with a case where the buffer layer 21 is formed by a method other than the sputtering method such as a MOCVD (metal organic chemical vapor deposition) method, A buffer layer 21 with good properties can be obtained. It is preferable that the crystallinity of the buffer layer 21 is good because the crystallinity of each layer provided on the buffer layer 21 is good. In particular, in the present embodiment, as will be described later, the n-clad layer 12b is doped with Si at a high concentration exceeding the n-contact layer 12a. If Si is doped in the n-cladding layer 12b at a high concentration, the crystallinity of the n-cladding layer 12b is lowered. Therefore, the Si is doped at a high concentration by forming the buffer layer 21 having good crystallinity by sputtering. By doing so, it is preferable to obtain an n-clad layer 12b having sufficiently good crystallinity even when the crystallinity is lowered.

  The buffer layer 21 is preferably formed by a sputtering method in order to obtain the buffer layer 21 with good crystallinity. However, the buffer layer 21 is formed by a method other than the sputtering method such as MOCVD (metal organic chemical vapor deposition). Also good. When the buffer layer 21 is formed by the MOCVD method, the buffer layer 21 can be formed using the same apparatus as each layer provided on the buffer layer 21, and it is not necessary to move the laminated semiconductor layer 20 in the manufacturing process. The semiconductor layer 20 can be formed easily and efficiently.

  Next, the substrate 11 provided with the buffer layer 21 is placed in the growth chamber of the MOCVD apparatus, and the base layer 22, the n contact layer 12a (first n-type semiconductor layer), and the n clad are formed on the buffer layer 21 by MOCVD. The layer 12b (second n-type semiconductor layer), the light emitting layer 13, and the p-type semiconductor layer 14 are sequentially stacked.

  When growing the n-contact layer 12a, it is preferable to set the temperature of the substrate 11 in the range of 1000 ° C. to 1200 ° C. in a hydrogen atmosphere. By making the temperature of the substrate 11 when growing the n-contact layer 12a within the above range, the crystallinity of the n-cladding layer 12b and the light-emitting layer 13 formed on the n-contact layer 12a is further improved. Can do. On the other hand, when the temperature of the substrate 11 when the n-contact layer 12a is grown is less than 1000 ° C., the reverse current (IR) is not sufficiently lowered, or the electrostatic discharge (ESD) breakdown voltage is insufficient. There is a fear. Further, when the temperature of the substrate 11 when the n contact layer 12a is grown exceeds 1200 ° C., the output of the semiconductor light emitting device 1 may be insufficient.

In the present invention, the step of sequentially stacking the first n-type semiconductor layer, the second n-type semiconductor layer, the light emitting layer, and the p-type semiconductor layer is performed in the first metal organic chemical vapor deposition apparatus up to the base layer 22. In the first step of stacking the first n-type semiconductor layer constituting the n contact layer 12a on the substrate 11 on which each layer is formed, and in the second metal organic chemical vapor deposition apparatus, on the first n-type semiconductor layer, A second step of sequentially stacking a regrowth layer of the first n-type semiconductor layer constituting the n-contact layer 12a, a second n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer may be included.
Such a manufacturing method is preferable in terms of productivity. More specifically, the total film thickness of the base layer 22 and the n contact layer 12a formed on the substrate 11 may be set larger than the total film thickness from the n clad layer 12b to the p-type semiconductor layer 14. In many cases, in this case, the productivity of the semiconductor light-emitting element 1 can be improved by using both the first metal organic chemical vapor deposition apparatus and the second metal organic chemical vapor deposition apparatus.

Here, it is preferable that the film formation temperature when forming the first n-type semiconductor layer constituting the n contact layer 12a is 1000 ° C. or higher. When the film forming temperature for forming the first n-type semiconductor layer is set to 1000 ° C. or higher, pits do not appear, so that a regrowth layer with high crystallinity can be obtained.
The regrowth layer formed in the second metal organic chemical vapor deposition apparatus is preferably made of the same material as the first n-type semiconductor layer formed in the first metal organic chemical vapor deposition apparatus. The regrowth layer is preferably thinner than the thickness of the first n-type semiconductor layer formed in the first metal organic chemical vapor deposition apparatus, and is preferably 0.2 μm to 1 μm. If the thickness of the regrown layer 12d is less than 0.2 μm, the planarization effect may not be sufficiently obtained. Further, when the film thickness of the regrowth layer exceeds 1 μm, there is a problem that the film formation processing time of the regrowth layer becomes long and productivity is lowered.

The materials for growing the n-contact layer 12a include trimethylgallium (TMG) or triethylgallium (TEG) as a Ga source which is a group III source, trimethylaluminum (TMA) or triethylaluminum (TEA) as an Al source, and trimethyl as an In source. Indium (TMI) or triethylindium (TEI), ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ) or the like is used as an N source which is a group V raw material. As the n-type impurity (dopant) material, monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ), which is a Si material, is used.

After growing the n contact layer 12a in this way, the n clad layer 12b is laminated on the n contact layer 12a.
When growing the n-clad layer 12b, the temperature of the substrate 11 is set to a temperature lower than the temperature of the substrate 11 when the light-emitting layer 13 is formed, and the n-clad layer 12b has a high concentration of Si exceeding the n-contact layer 12a. Dope.

As a raw material for growing the n-clad layer 12b, trimethylgallium (TMG) or triethylgallium (TEG) is used as a Ga source which is a group III raw material, and trimethylaluminum (TMA) or triethylaluminum is used as an Al source, similarly to the n-contact layer 12a (TEA), trimethylindium (TMI) or triethylindium (TEI) as an In source, ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), or the like as an N source as a group V source. As the n-type impurity (dopant) material, monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ), which is a Si material, is used.
The carrier gas used when growing the n-clad layer 12b may be only nitrogen gas or a mixed gas of hydrogen gas and nitrogen gas.

The flow rate of Si raw material supplied into the MOCVD apparatus when growing the n-clad layer 12b is appropriately adjusted so that the concentration of Si doped in the n-clad layer 12b is higher than the n-contact layer 12a. . The flow rate of the Si raw material is preferably adjusted so that the Si concentration in the n-clad layer 12b is in the range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ³ . When the Si concentration in the solid phase of the n-cladding layer 12b is within the above range, the concentration of Si doped in the n-cladding layer 12b can be easily reduced to n while ensuring good crystallinity of the n-cladding layer 12b. The concentration can be higher than that of the contact layer 12a. When the Si concentration in the solid phase of the n-cladding layer 12b is less than the above range, the concentration of Si doped in the n-cladding layer 12b is low and carriers may not be sufficiently injected into the light emitting layer. Further, when the Si concentration in the solid phase of the n-cladding layer 12b exceeds the above range, the concentration of Si doped in the n-cladding layer 12b becomes too high, and the n-cladding layer 12b with good crystallinity is obtained. There may not be.

  Further, the concentration of Si doped in the step of forming the n-clad layer 12b may be a high concentration exceeding the n-contact layer 12a, but in the range of 1.2 to 1.5 times that of the n-contact layer 12a. Preferably there is.

  The pressure in the growth chamber of the MOCVD apparatus when the n-clad layer 12b is grown is not particularly limited, but is preferably 15 to 100 kPa in order to obtain the n-clad layer 12b with good crystallinity, and 15 to 80 kPa. More preferably.

  Further, in the present embodiment, the step of forming the n-clad layer 12b is a step of forming the n-clad layer 12b having a superlattice structure in which two types of thin film layers having different compositions are alternately and repeatedly grown. preferable. The n-cladding layer 12b having a superlattice structure includes an n-side first layer made of a group III nitride semiconductor having a film thickness of 100 angstroms or less and a group III nitride having a film thickness of 100 angstroms or less having a different composition from the n-side first layer It is preferable to form a structure in which 20 to 40 layers of n-side second layers made of a semiconductor are alternately laminated. The n-side first layer and / or the n-side second layer is preferably made of a gallium nitride compound semiconductor containing In.

In the present embodiment, the layer thickness of the light-emitting layer underlayer composed of the n-side first layer or the n-side second layer arranged closest to the light-emitting layer 13 of the superlattice structure is set below the light-emitting layer of the superlattice structure. The maximum thickness of the n-side first layer and the n-side second layer other than the base layer is preferably at least twice the maximum thickness, and more preferably in the range of 2 to 20 times. Specifically, the layer thickness of the light emitting layer underlayer is preferably in the range of 2 nm to 20 nm, and preferably about 4 nm.
Note that the layer thickness of the n-side first layer and the n-side second layer may be the same or different. When the layer thickness of the n-side first layer and the n-side second layer is different, the layer thickness of the light emitting layer underlayer is the layer thickness of the larger one of the n-side first layer and the n-side second layer. It is preferable to make it 2 times or more.

  The underlying layer of the light emitting layer is the layer arranged closest to the light emitting layer 13 among the n-side first layer and the n-side second layer constituting the superlattice structure, and is therefore affected by heat when the light emitting layer 13 is formed. It is easy to receive. More specifically, the light emitting layer underlayer exposed on the surface of the n-clad layer 12b at the time when the formation of the light emitting layer 13 is started is for forming the light emitting layer 13 until it is covered with the light emitting layer 13. Exposed to heat. Thus, when the light emitting layer underlayer reaches a high temperature, In contained in the n clad layer 12b is sublimated from the light emitting layer underlayer, and the composition ratio of the n clad layer 12b changes. If In sublimates and the content of In contained in the n-clad layer 12b is insufficient, the output of the semiconductor light emitting device 1 may be hindered.

  In the present embodiment, when the layer thickness of the light emitting layer underlayer is set to be twice or more the maximum layer thickness of the n-side first layer and the n-side second layer other than the light emitting layer underlayer having the superlattice structure, the layer thickness is Compared to the n-side first layer and the n-side second layer other than the light-emitting layer underlayer, it is less susceptible to deterioration due to heat when the light-emitting layer 13 is formed because it is twice or more thick. Therefore, the light-emitting layer underlayer can function as a barrier layer that prevents the heat applied to the light-emitting layer 13 from affecting the n-clad layer 12b, and the n-clad layer 12b is deteriorated and the n-clad layer 12b The influence on the semiconductor light emitting device 1 due to the change in the composition ratio can be prevented.

  When the layer thickness of the light emitting layer underlayer is less than twice the maximum layer thickness of the n-side first layer and the n-side second layer other than the light emitting layer underlayer having the superlattice structure, In some cases, it cannot function sufficiently as a barrier layer for preventing the n clad layer 12b from being affected by heat when forming 13. Further, when the layer thickness of the light emitting layer underlayer exceeds 20 times the maximum thickness of the n-side first layer and the n-side second layer other than the superlattice light-emitting layer underlayer, the effect as a barrier layer is improved. Although not shown, the time required for forming the n-clad layer 12b is undesirably long. Therefore, the layer thickness of the light emitting layer underlayer is preferably in the range of 2 to 20 times the maximum layer thickness of the n-side first layer and the n-side second layer other than the light emitting layer underlayer having the superlattice structure.

  After growing the n-clad layer 12b in this way, the light emitting layer 13 is laminated on the n-clad layer 12b. In the present embodiment, it is preferable to form the light emitting layer 13 having a multiple quantum well structure as the light emitting layer 13.

The step of forming the light emitting layer 13 having the multiple quantum well structure can be a step of alternately and repeatedly laminating the well layers 13b and the barrier layers 13a. The barrier layer is formed on the n-type semiconductor layer 12 side and the p-type semiconductor layer 14 side. It is preferable to laminate so that the layer 13a is arranged.
The well layer 13b and / or the barrier layer 13a are preferably made of a gallium nitride compound semiconductor containing In, and the composition and thickness of the well layer 13b and / or the barrier layer 13a have a predetermined emission wavelength. Can be determined as appropriate.

In the present embodiment, as shown in FIG. 4, the substrate temperature T ₁ of the time of forming the n-cladding layer 12b, it has a low temperature below the substrate temperature T ₂ at the time of forming the light emitting layer 13. As a result, the n-cladding layer 12b with good crystallinity can be formed on the n-contact layer 12a, and the light-emitting layer 13 with good crystallinity can be formed on the n-cladding layer 12b. As a result, an n-cladding layer 12b that can satisfactorily inject and confine carriers (electrons) into the light-emitting layer 13 is obtained, and a light-emitting layer 13 that provides a high light-emission output is obtained. Further, the substrate temperature T ₁ of the time of forming the n-cladding layer 12b, the high concentration exceeding by a low temperature of less than the substrate temperature T ₂ at the time of forming the light emitting layer 13, the n-contact layer 12a to the n-cladding layer 12b Thus, Si can be doped, so that the n-type doping concentration of the n-clad layer 12b can be increased, and carriers can be efficiently injected into the light-emitting layer 13. Therefore, according to the method for manufacturing the semiconductor light emitting device 1 of the present embodiment, the semiconductor light emitting device 1 that can obtain a high light emission output when a large current is applied is obtained.

substrate temperatures T ₁ for growing the n-cladding layer 12b is, if it is the substrate temperature T ₂ or more when forming the light-emitting layer 13, the crystalline by doping a high concentration of Si in the n-clad layer 12b is deteriorated For this reason, the concentration of Si doped in the n-clad layer 12b may not be higher than that of the n-contact layer 12a.

substrate temperatures T ₁ during formation of the n clad layer 12b may be less than the substrate temperature T ₂ at the time of forming the light emitting layer 13 is not particularly limited, is preferably 700 ° C. to 750 ° C.. If the substrate temperature T ₁ of the time of forming the n-cladding layer 12b is within the above range, more obtained more excellent crystallinity n-cladding layer 12b, n-side first forming the superlattice structure of the n-clad layer 12b The interface between the first layer and the n-side second layer becomes clear, and the carrier injection efficiency into the light emitting layer 13 is excellent. Further, the substrate temperature _{T 1} of the time of forming the n-cladding layer 12b is preferably a 710 ℃ ~730 ℃.

Further, substrate temperatures T ₁ in the above range, the substrate temperature T ₁ of the time of growing the n-cladding layer 12b, the substrate temperature during formation of the easily-emitting layer 13 when growing the n-cladding layer 12b can be less than T _2, the concentration of Si is doped in the n-cladding layer 12b, easily can be the high concentration exceeding n contact layer 12a, is sufficiently low reverse current (IR) A high-power semiconductor light emitting device 1 can be easily obtained.
In contrast, when the substrate temperature T ₁ of the time of growing the n-cladding layer 12b is less than the above range, or not become reverse current (IR) is sufficiently low, electrostatic discharge (ESD) breakdown voltage is insufficient or There is a fear. Also, when the substrate temperature T ₁ of the time of growing the n-cladding layer 12b is more than the above range, the concentration of Si is doped in the n-clad layer 12b can not be a high concentration exceeding n contact layer 12a, There is a risk that the output of the semiconductor light emitting device 1 will be insufficient.

As shown in FIG. 4, the substrate temperature when forming the n-side first layer constituting the n-cladding layer 12b and the substrate temperature when forming the n-side second layer constituting the n-cladding layer 12b are as follows: , May be the same or different. As shown in FIG. 4, the substrate temperature when forming the barrier layer 13a constituting the light emitting layer 13 and the substrate temperature when forming the well layer 13b constituting the light emitting layer 13 are the same. It may be different or different. When the substrate temperature when forming the barrier layer 13a constituting the light emitting layer 13 and the substrate temperature when forming the well layer 13b constituting the light emitting layer 13 are different, the substrate temperature when forming the n clad layer 12b Is T ₁ , T _{3 is} the substrate temperature when forming the barrier layer 13 a, and T ₄ is the substrate temperature when forming the well layer 13 b, T ₁ <T ₃ and T ₁ <T _4. it can.

Further, the substrate temperature T ₂ at the time of forming the light emitting layer 13 may be higher than the substrate temperature T ₁ of the time of forming the n-cladding layer 12b, it is not particularly limited, so even higher light emission output can be obtained It is preferable that it is 750 degreeC-1000 degreeC, and it is more preferable that it is 750 degreeC-930 degreeC.
In the case of forming a barrier layer 13a and the well layer 13b constituting the light-emitting layer 13 at different temperatures, the substrate temperature _{T 3} for forming the barrier layer 13a is preferably from 750 ° C. to 1000 ° C., 770 ° C., more preferably to 950 ° C., the substrate temperature _{T 4} during formation of the well layer 13b is preferably 730 ° C. to 800 ° C..

In the present embodiment, for example, the n-clad layer 12b and the light emitting layer 13 include a gallium nitride compound semiconductor, and the content of In contained in the gallium nitride compound semiconductor is n higher than that of the light emitting layer 13. If there are fewer of the clad layer 12b, and the substrate temperature T ₁ of the time of forming the n-cladding layer 12b, the the substrate temperature T ₂ at the time of forming the light emitting layer 13 to be the same, there is a problem described below.
That is, if the substrate temperature is set to an optimum temperature for forming the n-clad layer 12b, the light emission output of the light emitting layer 13 may be insufficient. In addition, when the substrate temperature is set to an optimum temperature for forming the light emitting layer 13, it becomes difficult to control In of the gallium nitride compound semiconductor constituting the n-clad layer 12b with a low composition ratio. As a result, the interface between the n-side first layer and the n-side second layer constituting the superlattice structure of the n-clad layer 12b becomes rough and unclear, and the efficiency of carrier injection into the light emitting layer 13 becomes insufficient. There is.

In contrast, in the present embodiment, the substrate temperature T ₁ of the time of forming the n-cladding layer 12b, and a low temperature of less than the substrate temperature T ₂ at the time of forming the light emitting layer 13, forming the n-cladding layer 12b Since In is easy to enter into the gallium nitride compound semiconductor, the n-clad layer 12b having good crystallinity is obtained, and the n-side first layer and the n-side second layer constituting the superlattice structure of the n-clad layer 12b. The interface between and becomes clearer. As a result, the n-clad layer 12b having excellent carrier injection efficiency into the light emitting layer 13 is obtained.
In the present embodiment, the substrate temperature T ₁ of the time of forming the n-cladding layer 12b, since the low temperature of less than the substrate temperature T ₂ at the time of forming the light emitting layer 13, high emission light-emitting layer 13 Output Can be manufactured at an appropriate substrate temperature. Incidentally, the light-emitting layer 13, when the content of In contained in the gallium nitride compound semiconductor is assumed greater than n cladding layer 12b, the substrate temperature T ₂ is n-cladding layer 12b at the time of forming the light-emitting layer 13 be higher than the substrate temperature T ₁ of the time of forming, a problem due to in is not easily enter the gallium nitride-based compound semiconductor constituting the light-emitting layer 13 is less likely to occur.

In order to stack the p-type semiconductor layer 14 on the light emitting layer 13 thus obtained, the p-cladding layer 14a and the p-contact layer 14b may be sequentially stacked. When the p-cladding layer 14a is a layer including a superlattice structure, the p-side first layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less and a film having a composition different from that of the p-side first layer are used. A p-side second layer made of a group III nitride semiconductor having a thickness of 100 angstroms or less may be alternately and repeatedly stacked.
In this embodiment, since the p-clad layer 14a is formed by MOCVD, a superlattice structure can be formed more efficiently than when the p-clad layer 14a is formed by sputtering or the like.
As described above, the laminated semiconductor layer 20 shown in FIG. 2 is manufactured.

Thereafter, a transparent material layer that becomes the translucent electrode 15 is laminated on the p-type semiconductor layer 14 of the laminated semiconductor layer 20, and the transparent material layer other than the predetermined region is removed by, for example, a generally known photolithography technique. The light transmitting electrode 15 is used.
Subsequently, patterning is performed by, for example, a photolithography technique, a part of the laminated semiconductor layer 20 in a predetermined region is etched to expose a part of the n contact layer 12a, and an n-type is formed on the exposed surface 20a of the n contact layer 12a. The electrode 17 is formed.
Next, a p-type bonding pad electrode 16 is formed on the translucent electrode 15.
Thereafter, the substrate 11 is divided (chiped), whereby the semiconductor light emitting device 1 shown in FIG. 1 is manufactured.

In the manufacturing method of the semiconductor light emitting device 1 of the present embodiment, in the step of forming the n-cladding layer 12b, and the substrate temperature T ₁ of the time of forming the n-cladding layer 12b, the substrate temperature during the formation of the light-emitting layer 13 T ₂ Since the n-clad layer 12b is doped with Si at a high concentration exceeding the n-contact layer 12a at a low temperature of less than the n-type, the n-type doping concentration of the n-clad layer 12b can be increased and the n-type cladding layer 12b In addition, the n-clad layer 12b having good crystallinity can be formed, and the light-emitting layer 13 having good crystallinity capable of obtaining strong emission intensity can be formed on the n-clad layer 12b. As a result, according to the method for manufacturing the semiconductor light emitting device 1 of the present embodiment, the semiconductor light emitting device 1 that can obtain a high light emission output by applying a large current exceeding 20 mA, for example, is obtained.

  Further, the semiconductor light emitting device 1 of the present embodiment is a semiconductor light emitting device manufactured by using the method for manufacturing the semiconductor light emitting device 1 of the present embodiment, and the n contact layer 12a and the n clad layer 12b are formed on the substrate 11. And the light emitting layer 13 and the p-type semiconductor layer 14 are laminated, and the n clad layer 12b is doped with Si at a high concentration exceeding the n contact layer 12a. The semiconductor light emitting device 1 can be injected and a high light emission output can be obtained by applying a large current.

"lamp"
The lamp of the present embodiment includes the semiconductor light emitting device of the present invention, and is a combination of the above semiconductor light emitting device and a phosphor. The lamp of the present embodiment can be configured as known to those skilled in the art by means known to those skilled in the art. For example, in the lamp of this embodiment, a technique for changing the emission color by combining a semiconductor light emitting element and a phosphor can be adopted without any limitation.

  FIG. 3 is a schematic cross-sectional view showing an example of a lamp including the semiconductor light emitting element 1 shown in FIG. The lamp 3 shown in FIG. 3 is a shell type, and the semiconductor light emitting element 1 shown in FIG. 1 is used. As shown in FIG. 3, the p-type bonding pad electrode 16 of the semiconductor light emitting device 1 is bonded to one of the two frames 31 and 32 (the frame 31 in FIG. 3) with a wire 33, and n of the semiconductor light emitting device 1. The semiconductor light emitting element 1 is mounted by bonding the mold electrode 17 (bonding pad) to the other frame 32 with a wire 34. Further, the periphery of the semiconductor light emitting element 1 is sealed with a mold 35 made of a transparent resin.

  Since the lamp 3 of the present embodiment uses the semiconductor light emitting element 1 described above, a high light emission output can be obtained.

  In addition, electronic devices such as backlights, mobile phones, displays, various panels, computers, game machines, and lighting incorporating the lamp 3 of the present embodiment, and mechanical devices such as automobiles incorporating such electronic devices are expensive. The semiconductor light emitting device 1 capable of obtaining a light emission output is provided. In particular, in an electronic device driven by a battery such as a backlight, a mobile phone, a display, a game machine, and an illumination, an excellent product including the semiconductor light emitting element 1 capable of obtaining a high light emission output can be provided, which is preferable.

Hereinafter, the method for producing a semiconductor light emitting device of the present invention will be described in more detail with reference to Examples, but the present invention is not limited to these Examples.
(Example 1)
The semiconductor light emitting device 1 shown in FIG. 1 was manufactured by the following method.

First, a buffer layer 21 made of AlN was formed on a circular substrate 11 made of sapphire by a sputtering method. Next, the substrate 11 provided with the buffer layer 21 is placed in the growth chamber of the MOCVD apparatus, and the base layer 22 made of undoped GaN having a thickness of 5 μm, the n contact layer 12a made of Si-doped n-type GaN having a thickness of 3 μm, n The n-cladding layer 12b, the barrier layer and the well layer having a superlattice structure obtained by repeatedly growing 20 pairs of thin film layers composed of the first side layer and the second n-side layer were stacked six times, and finally the barrier layer was provided. A light emitting layer 13 having a multiple quantum well structure, a 0.01 μm thick Mg-doped single layer Al _0.07 Ga _0.93 N p-cladding layer 14 a, and a 0.15 μm-thick Mg doped p-type GaN p-contact layer 14 b Laminated in order.

  In the semiconductor light emitting device 1 of Example 1, the n contact layer 12a, the n cladding layer 12b, and the light emitting layer 13 were grown under the growth conditions shown in Table 1 and below.

“Deposition conditions for n-contact layer 12a”
The flow rate of the Si raw material was adjusted so that the Si concentration was 5 × 10 ^18, and the n-contact layer 12a made of GaN having the Si concentration shown in Table 1 was grown.

“Deposition conditions for n-clad layer 12b”
A superlattice having a thickness of 80 nm is formed by alternately and repeatedly stacking a 2 nm thick n-side first layer made of Ga _0.99 In _0.01 N and a 2 nm thick n-side second layer made of GaN. An n-cladding layer 12b having a structure was grown. In addition, as shown in Table 1, the layer thickness (4 nm) of the light emitting layer underlayer disposed closest to the light emitting layer 13 in the superlattice structure is the thickness of the first layer and the second layer other than the light emitting layer underlayer. (2 nm).
The substrate temperature for growing the n-side first layer and the n-side second layer was 750 ° C. as shown in Table 1. For the film formation of the n-side first layer, triethylgallium (TEG) as a Ga source and trimethylindium (TMI) as an In source are used as Group III materials, and triethylgallium (TMI) is used for the film formation of the n-side second layer. TEG) was used. Further, monosilane (SiH ₄ ) was used as an n-type impurity (dopant) raw material, and an n-clad layer 12b having a Si concentration of 7 × 10 ¹⁸ / cm ³ was grown.

“Film formation conditions of the light emitting layer 13”
A multi-well light-emitting layer 13 is formed by alternately and repeatedly stacking a 5 nm thick barrier layer made of Si-doped GaN and a 3.5 nm thick well layer made of Ga _0.85 In _0.15 N. Grown up. The substrate temperature for forming the barrier layer and the well layer was 770 ° C. as shown in Table 1.

  The buffer layer 21, the base layer 22, the n contact layer 12a, the p clad layer 14a, and the p contact layer 14b were formed under normal conditions well known in the technical field.

Thereafter, a translucent electrode 15 made of ITO having a thickness of 200 nm was formed on the p-contact layer 14b by a generally known photolithography technique.
Next, etching is performed using a photolithography technique to expose the n-contact layer 12a in a desired region, and the Ti / Au double-layer n-type electrode 17 is formed on the exposed surface 20a of the n-contact layer 12a. Formed.
Further, on the translucent electrode 15, a p-type bonding pad structure 16 having a three-layer structure composed of a metal reflective layer made of 200 nm Al, a barrier layer made of 80 nm Ti, and a bonding layer made of 1100 nm Au, It formed using the technique of photolithography.
Thereafter, the substrate 11 was divided (chiped) to obtain the semiconductor light emitting device 1 of Example 1 shown in FIG.

In the semiconductor light emitting device 1 of Example 1 obtained in this way, the Si doping concentration of the n contact layer 12a is 5 × 10 ¹⁸ cm ⁻³ as shown in Table 1, and the Si doping concentration of the n cladding layer 12b. Is 7 × 10 ¹⁸ cm ⁻³ as shown in Table 1, the Mg doping concentration of the p contact layer 14 b is 5 × 10 ¹⁹ cm ⁻³ , and the Mg doping concentration of the p cladding layer 14 a is 1 × 10 ¹⁹ cm 3. ^-3 .

(Example 2)
A semiconductor light emitting device 1 was manufactured in the same manner as in Example 1 except that the substrate temperature when forming the n-clad layer 12b was 730 ° C. as shown in Table 1.

(Example 3)
In the first metal organic chemical vapor deposition apparatus, a first step of laminating a first n-type semiconductor layer having a film thickness of 5 μm constituting the n contact layer 12a, and in the second metal organic chemical vapor deposition apparatus, the first n-type semiconductor A second layer of a regrowth layer having a thickness of 0.2 μm, an n-cladding layer 12b, a light-emitting layer 13, a p-cladding layer 14a, and a p-contact layer 14b, which constitute the n-contact layer 12a, is sequentially stacked on the layer. The semiconductor light emitting device 1 was manufactured in the same manner as in Example 1 except that the steps were performed and the substrate temperature when forming the n-clad layer 12b was 710 ° C. as shown in Table 1.
The first n-type semiconductor layer stacked in the first metal organic chemical vapor deposition apparatus and the regrowth layer stacked in the second metal organic chemical vapor deposition apparatus are both made of GaN having the Si concentration shown in Table 1. The same composition was used.

(Example 4) (Example 5)
A semiconductor light emitting device 1 was manufactured in the same manner as in Example 1 except that the Si concentration of the n-clad layer 12b was changed to the Si concentration shown in Table 1.
(Example 6) (Example 7)
The layer thickness of the light emitting layer underlayer disposed closest to the light emitting layer 13 of the superlattice structure is set to the thickness shown in Table 1, and the light emitting layer underlayer with respect to the thickness of the first layer and the second layer other than the light emitting layer underlayer A semiconductor light emitting device 1 was manufactured in the same manner as in Example 1 except that the film thickness was a multiple (magnification) shown in Table 1.
(Example 8)
The semiconductor light emitting device 1 was manufactured in the same manner as in Example 1 except that the n-cladding layer 12b was a single layer having a thickness of 20 nm made of GaN having a Si concentration shown in Table 1.

(Comparative Example 1)
The semiconductor light emitting device 1 was manufactured in the same manner as in Example 1 except that the substrate temperature when forming the n-clad layer 12b was 780 ° C. as shown in Table 1.
(Comparative Example 2)
The semiconductor light emitting device 1 was manufactured in the same manner as in Example 1 except that the substrate temperature when forming the n-clad layer 12b was 800 ° C. as shown in Table 1.

(Comparative Example 3)
A semiconductor light emitting device 1 was manufactured in the same manner as in Example 1 except that the Si concentration of the n-clad layer 12b was 1 × 10 ¹⁸ cm ⁻³ as shown in Table 1.

  As shown in Table 1, in Examples 1 to 8, the substrate temperature during the growth of the n-clad layer 12 b is lower than the substrate temperature during the growth of the light emitting layer 13. On the other hand, in Comparative Example 1 and Comparative Example 2, the substrate temperature during the growth of the n-clad layer 12 b is higher than the substrate temperature during the growth of the light emitting layer 13. Further, in Comparative Example 3, the Si concentration of the n-clad layer 12b is lower than those in Examples 1 to 8.

  The semiconductor light emitting devices 1 of Examples 1 to 8 and Comparative Examples 1 to 3 thus obtained were mounted in a TO-18 can package, and the light emission output in the range of applied current 0 to 100 mA by a tester. (Po; mW) was measured. The results are shown in Table 2.

In addition, for the semiconductor light emitting devices of Examples 1 to 8 and Comparative Examples 1 to 3, the probe needle is energized to measure the forward voltage at a current application value of 20 mA and apply a voltage of 20 V in the reverse direction. The current (reverse current IR) flowing through the device at the time of measurement was measured. The results are shown in Table 2.
Further, power efficiency (%) {light emission output (mW) / (forward voltage (V) × applied current (mA))} was calculated using the forward voltage, the applied current, and the light emission output. The result is shown in FIG .

As shown in Table 2, in Examples 1 to 8, the reverse current (IR) is sufficiently low, the light emission output (Po) at an applied current of 20 mA is 23 mW or more, high brightness and low power consumption. there were.
Further, as shown in Table 2 and FIG. 5, in Examples 1 to 8, the light emission output (Po) and the power efficiency at the applied current of 80 mA and the applied current of 100 mA are compared with those of Comparative Examples 1 to 3. It turns out that it is excellent.

  Moreover, as shown in Table 2, in Examples 1 to 8 and Comparative Examples 1 to 3, the light emission output (Po) increases as the applied current increases. However, in Comparative Examples 1 to 3, the effect of improving the light emission output by increasing the applied current is reduced as the applied current is increased. The difference in light emission output (Po) from 8 is large. In particular, when the applied current was 80 mA or more, the difference in light emission output between Examples 1 to 8 and Comparative Examples 1 to 3 was significant.

  Further, as shown in FIG. 5, in Examples 1 to 8 and Comparative Examples 1 to 3, when the applied current is larger than the normally used applied current of 20 mA, the power is increased as the applied current is increased. Efficiency is getting smaller. However, the power efficiency of Examples 1 to 8 is higher than that of Comparative Examples 1 to 3, and the larger the applied current, the greater the difference between Examples 1 to 8 and Comparative Examples 1 to 3. The difference in power efficiency is increasing. In particular, when the applied current was 80 mA or more, the difference in power efficiency between Example 1 to Example 8 and Comparative Example 1 to Comparative Example 3 was significant.

  From FIG. 5, the semiconductor light emitting devices of Examples 1 to 8 can effectively improve the light emission output by applying a large current, and compared with the semiconductor light emitting devices of Comparative Examples 1 to 3. Thus, it was confirmed that a high light emission output can be obtained by applying a large current.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor light-emitting device, 3 ... Lamp, 12 ... n-type semiconductor layer, 12a ... n contact layer (1st n-type semiconductor layer), 12b ... n clad layer (2nd n-type semiconductor layer), 13 ... Light-emitting layer, 14 ... p-type semiconductor layer.

Claims (11)

Comprising sequentially stacking a first n-type semiconductor layer, a second n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on a substrate;
In the step of forming the second n-type semiconductor layer, the temperature of the substrate is set to a temperature lower than the temperature of the substrate when forming the light-emitting layer, and the first n-type semiconductor layer is formed on the second n-type semiconductor layer. A method for manufacturing a semiconductor light emitting device, comprising doping Si at a high concentration exceeding.   2. The method of manufacturing a semiconductor light emitting device according to claim 1, wherein in the step of forming the second n-type semiconductor layer, the substrate temperature is set to 700 ° C. to 750 ° C. 3. 3. The semiconductor according to claim 1, wherein a concentration of Si doped in the step of forming the second n-type semiconductor layer is in a range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ / cm ^3. Manufacturing method of light emitting element.   4. The semiconductor according to claim 1, further comprising a step of forming a buffer layer on the substrate using a sputtering method before the step of forming the first n-type semiconductor layer. 5. Manufacturing method of light emitting element. The step of forming the second n-type semiconductor layer is a step of forming the second n-type semiconductor layer having a superlattice structure in which two types of thin film layers having different compositions are alternately grown.
The layer thickness of the light emitting layer underlayer composed of the thin film layer disposed closest to the light emitting layer of the superlattice structure is twice the maximum thickness of the thin film layer other than the light emitting layer underlayer of the superlattice structure. It is set as the above, The manufacturing method of the semiconductor light-emitting device in any one of Claims 1-4 characterized by the above-mentioned.   6. The method for manufacturing a semiconductor light-emitting element according to claim 5, wherein the layer thickness of the light-emitting layer underlayer is in the range of 2 nm to 20 nm. A step of sequentially stacking a first n-type semiconductor layer, a second n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer on the substrate;
In the first organometallic chemical vapor deposition apparatus, a first step of laminating the first n-type semiconductor layer on a substrate;
In the second metalorganic chemical vapor deposition apparatus, a regrowth layer made of an n-type semiconductor, a second n-type semiconductor layer, a light emitting layer, and a p-type semiconductor layer are sequentially stacked on the first n-type semiconductor layer. The method for manufacturing a semiconductor light emitting element according to claim 1, further comprising a second step. A semiconductor light-emitting device manufactured using the method for manufacturing a semiconductor light-emitting device according to claim 1,
On the substrate, at least a first n-type semiconductor layer, a second n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer are stacked, and the second n-type semiconductor layer has a higher concentration of Si than the first n-type semiconductor layer. Is a semiconductor light emitting device.   A lamp comprising the semiconductor light emitting device according to claim 8.   An electronic device comprising the lamp according to claim 9 incorporated therein.   11. A mechanical apparatus in which the electronic device according to claim 10 is incorporated.

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