JP2011138803A - Method of manufacturing semiconductor device, reticle, and semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently conduct inspection of a transfer pattern where a specific semiconductor element pattern of a reticle is exposed by finding out the specific semiconductor element pattern on a semiconductor substrate easily and correctly in a short time, even if there are many semiconductor element patterns of the reticle. <P>SOLUTION: By using a reticle 11 having a plurality of semiconductor element patterns 12, and a pattern 13 for identification which indicates the direction and distance from the semiconductor element pattern 12 to at least one of the plurality of semiconductor element patterns 12 to be observed, i.e., the specific semiconductor element pattern 12A, a photoresist on a semiconductor substrate is exposed and the transfer pattern of the specific semiconductor element pattern 12A is inspected using the transfer pattern of the pattern 13 for identification. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device using reduced projection exposure, a reticle, and a semiconductor substrate.

  In a semiconductor integrated circuit element (hereinafter, simply referred to as a semiconductor element), a plurality of functional elements such as transistors and resistance elements are disposed on one main surface of a semiconductor substrate, and the functional elements are interconnected. An electronic circuit is formed with layers.

When manufacturing the semiconductor element, a so-called photolithography technique is applied to form various patterns such as an element isolation region, an electrode, an impurity implantation mask layer, a contact hole, and a wiring.
In the photolithography technology, a plurality of reticles (photo masks) corresponding to each of the semiconductor element patterns such as the element isolation region, the electrode, the selective impurity implantation layer, the contact hole, or the wiring are applied. Is done.
Then, in the exposure apparatus, the semiconductor element pattern on the reticle is exposed and transferred to the photoresist layer on the semiconductor substrate.

In recent years, in order to increase the functionality, size, and speed of electronic devices, there is a demand for further miniaturization and higher integration of semiconductor elements mounted on the electronic devices.
On the other hand, for the mass production of the semiconductor element, the size of the semiconductor substrate has been increased, and for example, a Φ300 mm silicon substrate is applied.
A large number of semiconductor element patterns are formed on such a large-sized semiconductor substrate by a so-called reduction projection exposure method.

That is, a reticle including a plurality of semiconductor element patterns is used, and the semiconductor element pattern included in the reticle is laterally and vertically aligned with respect to a photoresist layer formed on a semiconductor substrate by a reduction projection exposure method. Arrange multiple exposures and transfer.
In such an exposure process, an exposed area formed by one exposure process using one reticle is referred to as an “exposure shot area”. The exposure shot area includes a plurality of semiconductor element patterns.
That is, by applying the reduced projection exposure method, a plurality of the exposure shot regions are formed in the photoresist layer formed on the semiconductor substrate.

After the exposure process using the reticle, the semiconductor element pattern obtained by developing the exposed photoresist is inspected. In addition, a semiconductor element manufactured through a semiconductor manufacturing process is also inspected. As the inspection of the semiconductor element pattern, there is an inspection for observing and measuring whether or not the photo resist pattern constituting the semiconductor element pattern is formed in a desired size and shape. As an inspection of a semiconductor element, there is an inspection for measuring and judging whether or not an electrical characteristic or the like of a manufactured semiconductor element satisfies a desired reference value.
An example in which an inspection mark is provided in a so-called scribe region of a semiconductor substrate in order to inspect a semiconductor element pattern is described in Prior Literature 1.

JP 2007-335459 A

In the photolithography process, a large number of semiconductor element patterns are formed on a semiconductor substrate. When all the semiconductor element patterns are inspected when the semiconductor element pattern is inspected, the inspection takes a very long time and the inspection efficiency is inferior. Therefore, when inspecting a semiconductor element pattern, a specific semiconductor element pattern (hereinafter referred to as a specific semiconductor element pattern) among a plurality of semiconductor element patterns on a semiconductor substrate is taken into consideration in consideration of inspection efficiency and the like. Often targeted for inspection. As the specific semiconductor element pattern, one or several semiconductor element patterns formed at a predetermined position are selected from a plurality of semiconductor element patterns on the semiconductor substrate, and all the semiconductor element patterns formed on the semiconductor substrate are selected. As a representative one, it is an inspection object.
Similarly, one or several specific semiconductor elements (hereinafter referred to as specific semiconductor elements) selected from a plurality of semiconductor elements on a semiconductor substrate are also used for the semiconductor elements manufactured through the semiconductor manufacturing process. Often targeted for inspection.
Hereinafter, a case where a specific semiconductor element pattern is an inspection target will be described as an example.

An optical microscope or a scanning electron microscope (SEM) is used for defect inspection of a semiconductor element pattern formed on a semiconductor substrate. (Hereinafter referred to as a microscope.)
At the time of defect inspection, the semiconductor substrate to be inspected and the semiconductor element are observed within the inspection visual field of the microscope. The inspection visual field is a range that can be visually recognized when observing an object in a microscope, and is determined by the magnification, the numerical aperture of the lens, and the like.

  When the number of semiconductor element patterns belonging to the exposure shot is small during observation with a microscope, it is relatively easy to detect the specific semiconductor element pattern to be observed in the exposure shot. However, when the number of semiconductor element patterns belonging to the exposure shot is several hundred or more, it is extremely difficult to detect a specific semiconductor element pattern in the exposure shot. The specific semiconductor element pattern is about one to several in the exposure shot. For example, out of several hundred semiconductor element patterns, it takes a long time to fit the specific semiconductor element pattern within the narrow inspection field of view of the microscope. In short, it is considered to be a factor in delaying the semiconductor manufacturing process.

  The present invention has been made to solve the above-described problems, and when inspecting a transfer pattern in which a specific semiconductor element pattern of a reticle is exposed, even when there are a large number of semiconductor element patterns of the reticle, the present invention An object of the present invention is to provide a method of manufacturing a semiconductor device, a reticle, and a semiconductor substrate capable of easily and accurately finding a specific semiconductor element pattern in a short time and performing an extremely efficient inspection.

  One aspect of a method for manufacturing a semiconductor device includes a step of forming a photoresist layer on one main surface of a semiconductor substrate, a plurality of semiconductor element patterns, and a plurality of the semiconductor element patterns from the semiconductor element patterns. A step of performing an exposure process on the photoresist layer using a reticle having an identification pattern indicating a direction and a distance to a specific semiconductor element pattern to be observed. A step of developing a photoresist layer, and a step of detecting the specific semiconductor element pattern using the identification pattern as an index.

  One aspect of the reticle is a plurality of semiconductor element patterns, and directions and distances from the semiconductor element patterns to a specific semiconductor element pattern to be observed, which is at least one of the plurality of semiconductor element patterns. And an identification pattern indicating the above.

  In one aspect of the semiconductor substrate, on one main surface, a plurality of semiconductor elements and a direction from the semiconductor elements to at least one of the plurality of semiconductor elements and a specific semiconductor element to be observed And an identification pattern indicating a distance.

  According to each of the above aspects, when inspecting a transfer pattern in which a specific semiconductor element pattern on a reticle is exposed, even if there are many reticle semiconductor element patterns, the specific semiconductor element pattern can be easily and accurately formed on a semiconductor substrate. This makes it possible to find out in a short time and perform inspection very efficiently.

1 is a schematic plan view showing a reticle according to a first embodiment. FIG. 6 is a schematic plan view showing another example of the first identification pattern in the reticle according to the first embodiment. FIG. 2 is a schematic plan view showing an enlarged part of a semiconductor substrate exposed using the reticle of FIG. 1. FIG. 2 is a schematic plan view showing an enlarged part of a semiconductor substrate exposed using the reticle of FIG. 1. FIG. 5 is a schematic plan view showing one exposure shot area in FIG. 4. It is a block diagram which shows schematic structure of the automatic inspection apparatus of this embodiment. FIG. 6 is a flowchart for producing a plurality of reticles including a reticle having a first identification pattern according to the first embodiment. It is a flowchart which shows the manufacturing method of the semiconductor device by 1st Embodiment in order of a process. It is a schematic plan view which expands and shows a part of semiconductor substrate by 1st Embodiment. It is a schematic plan view which expands and shows a part of semiconductor substrate by 1st Embodiment. FIG. 11 is a schematic plan view showing one exposure shot region in FIG. 9 or FIG. 10. It is a schematic plan view which shows the specific formation site | part of each identification pattern in a semiconductor element area | region. It is a schematic plan view which shows the other example of the reticle by 1st Embodiment. It is a schematic plan view which shows the reticle by 2nd Embodiment. FIG. 15 is a schematic plan view showing one exposure shot region in a semiconductor substrate exposed using the reticle of FIG. 14. It is a schematic plan view which shows the other example of the reticle by 2nd Embodiment. It is a schematic plan view which shows the reticle by 3rd Embodiment. FIG. 18 is a schematic plan view showing one exposure shot region in a semiconductor substrate exposed using the reticle of FIG. 17. It is a schematic plan view which shows the reticle by 4th Embodiment. FIG. 20 is a schematic plan view showing one exposure shot region in a semiconductor substrate exposed using the reticle of FIG. 19. It is a schematic plan view which expands and shows a part of semiconductor substrate by 4th Embodiment. FIG. 22 is a schematic plan view showing a part of the semiconductor region of FIG. 21 taken out. It is a schematic plan view which expands and shows a part of semiconductor region of FIG.

Hereinafter, preferred embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following embodiments.
Hereinafter, “inspection” in this embodiment refers to inspection of a semiconductor element pattern obtained by developing an exposed photoresist and inspection of a semiconductor element manufactured through a semiconductor manufacturing process. As the inspection of the semiconductor element pattern, there is an inspection for observing and measuring whether or not the photo resist pattern constituting the semiconductor element pattern is formed in a desired size and shape. As an inspection of a semiconductor element, there is an inspection for measuring and judging whether or not an electrical characteristic or the like of a manufactured semiconductor element satisfies a desired reference value.
In the following description, “adjacent two semiconductor element patterns” means that no other semiconductor element pattern exists between the two semiconductor element patterns.

(First embodiment)
FIG. 1 is a schematic plan view showing a single reticle according to the first embodiment, and FIGS. 3 and 4 are schematic plan views showing a semiconductor substrate exposed using the reticle of FIG.
In the present embodiment, at least one of the plurality of reticles is the reticle shown in FIG. FIG. 3 and FIG. 4 show a state where the photo resist is transferred to the photo resist on the semiconductor substrate by the reticle of FIG.

  In the reticle 11 according to the present embodiment, as shown in FIG. 1, for example, 11 × 11 (121) semiconductor element patterns 12 are arranged vertically and horizontally apart from each other. The reticle 11 forms one exposure shot area in the reduction projection exposure process. In the reticle 11, each semiconductor element pattern 12 has a size and shape corresponding to the formation of one semiconductor element, and one pattern applied in the manufacturing process of the semiconductor element, for example, an element isolation region ( A pattern defining an isolation region). However, the pattern is not displayed here.

  The 121 semiconductor element patterns 12 are arranged separately from each other across the scribe region 16. The scribe region 16 has the same width in both the vertical direction (Y-axis direction) and the horizontal direction (X-axis direction). A scribe region 18 having a width equal to that of the scribe region 16 is disposed around the 121 semiconductor element patterns 12.

  Among the 121 semiconductor element patterns 12, for example, when the semiconductor element pattern 12 in the central portion is transferred to the semiconductor substrate, a specific semiconductor element pattern (hereinafter referred to as a specific semiconductor element pattern 12A) to be observed at the time of inspection. ). The specific semiconductor element pattern 12A is defined as a semiconductor element pattern for an observation target at the time of inspection from the design stage of the reticle 11.

Each semiconductor element pattern 12 excluding the specific semiconductor element pattern 12A is formed with an identification pattern 13 indicating the direction and distance from the semiconductor element pattern 12 to the specific semiconductor element pattern 12A, for example, at the periphery. The identification pattern 13 is preferably provided on all the semiconductor element patterns 12 except the specific semiconductor element pattern 12A from the viewpoint of reliably performing the inspection in a short time. However, it is not always necessary to provide the identification pattern 13 for every semiconductor element pattern 12.
Hereinafter, the case where the identification pattern 13 is provided in all the semiconductor element patterns 12 except the specific semiconductor element pattern 12A will be described as an example.
For example, rectangular shot recognition patterns 17 are formed at the four corners of the reticle 11 to identify exposure shot areas when exposed.

  The identification pattern 13 has two arrows having a predetermined width along the peripheral edge, starting from one of the four corners of the semiconductor element pattern 12. Of the four corners of the semiconductor element pattern 12, the corner that is the starting point of the identification pattern 13 corresponds to the corner of the reticle 11 that is closest to the semiconductor element pattern 12. For example, if the position of the semiconductor element pattern 12 in the reticle 11 is closest to the upper right corner (lower right, upper left, lower left) of the four corners of the reticle 11, the corner that is the starting point of the identification pattern 13 is also upper right. (Lower right, upper left, lower left) corners.

  For example, among the semiconductor element patterns 12 of the reticle 11, the semiconductor element pattern 12 located at the third from the upper right corner to the left in the horizontal direction and the fourth at the lower side in the vertical direction (referred to as 12a in FIG. 1). Pay attention to. From the semiconductor element pattern 12a to the specific semiconductor element pattern 12A, there are three semiconductor element patterns 12 on the left in the horizontal direction and two semiconductor element patterns 12 on the lower side in the vertical direction. In the semiconductor element pattern 12a, an identification pattern 13 corresponding to the positional relationship with the specific semiconductor element pattern 12A is formed. The identification pattern 13 starts from the upper right corner of the semiconductor element pattern 12 and has an arrow 13a having a length corresponding to “3” to the left in the horizontal direction and a length corresponding to “2” in the lower vertical direction. And an arrow 13b.

  Further, attention is focused on the semiconductor element pattern 12 (referred to as 12b in FIG. 1) located in the lower right corner among the semiconductor element patterns 12 of the reticle 11. From the semiconductor element pattern 12b to the specific semiconductor element pattern 12A, there are five semiconductor element patterns 12 on the left in the horizontal direction and five semiconductor element patterns 12 on the upper side in the vertical direction. In the semiconductor element pattern 12b, an identification pattern 13 corresponding to the positional relationship with the specific semiconductor element pattern 12A is formed. The identification pattern 13 starts from the lower right corner of the semiconductor element pattern 12 and has an arrow 13a having a length corresponding to “5” on the left side in the horizontal direction and a length corresponding to “5” on the upper side in the vertical direction. And an arrow 13b.

  Further, among the semiconductor element patterns 12 of the reticle 11, the fourth semiconductor element pattern 12 located in the horizontal direction from the upper left corner and the sixth in the lower vertical direction (referred to as 12 c in FIG. 1). Pay attention to. From the semiconductor element pattern 12c to the specific semiconductor element pattern 12A, there are two semiconductor element patterns 12 on the right side in the horizontal direction. In the semiconductor element pattern 12c, an identification pattern 13 corresponding to the positional relationship with the specific semiconductor element pattern 12A is formed. The identification pattern 13 includes an arrow 13a having a length corresponding to “2” on the right side in the horizontal direction starting from the upper left corner of the semiconductor element pattern 12.

  The semiconductor element pattern 12c is located directly beside the specific semiconductor element pattern 12A. Therefore, when searching for the specific semiconductor element pattern 12A from the position of the semiconductor element pattern 12c, only the horizontal movement is sufficient, and there is no need to move in the vertical direction. Consists of. In the semiconductor element pattern 12c, the closest corner among the four corners of the reticle 11 is the upper left or lower left corner, and the corner that is the starting point of the identification pattern 13 is the upper left or lower left corner. Here, the case where the upper left corner is the starting point of the identification pattern 13 is illustrated.

  In addition, in the semiconductor element pattern 12 located, for example, directly above (directly below) the specific semiconductor element pattern 12A, when searching for the specific semiconductor element pattern 12A from the position of the semiconductor element pattern 12, only movement in the vertical direction is sufficient. Since there is no need to move in the horizontal direction, the identification pattern 13 is composed of only the vertical arrow 13b. In this case, the closest corner of the four corners of the reticle 11 is the upper left or upper right (lower left or lower right) corner, and therefore, the corner serving as the starting point of the identification pattern 13 in the semiconductor element pattern 12 is The upper left or upper right (lower left or lower right) corner.

  Further, among the semiconductor element patterns 12 of the reticle 11, the semiconductor element pattern 12 located at the third laterally rightward from the lower left corner and the fourth vertically upward (referred to as 12 d in FIG. 1). Pay attention to. From the semiconductor element pattern 12d to the specific semiconductor element pattern 12A, there are three semiconductor element patterns 12 on the right side in the horizontal direction and two semiconductor element patterns 12 on the upper side in the vertical direction. In the semiconductor element pattern 12d, an identification pattern 13 corresponding to the positional relationship with the specific semiconductor element pattern 12A is formed. The identification pattern 13 starts from the lower left corner of the semiconductor element pattern 12 and has an arrow 13a with a length corresponding to “3” in the horizontal direction and a length corresponding to “2” in the vertical direction. And an arrow 13b.

  In FIG. 1, the semiconductor element pattern 12 is indicated by a rectangle surrounded by a broken line, but actually, a reticle pattern corresponding to a corresponding layer is formed in the rectangle. For example, if the corresponding layer is a wiring layer, a wiring-shaped reticle pattern is formed in the rectangle. The same applies to FIGS. 13, 14, 16, and 17, which will be described later.

The lengths of the arrows 13a and 13b of the identification pattern 13 need only relatively indicate the distance to the specific semiconductor element pattern 12A in accordance with a predetermined rule.
The identification pattern 13 may be other than an arrow shape as long as the direction and distance from the semiconductor element pattern 12 on which the identification pattern 13 is formed to the specific semiconductor element pattern 12A can be recognized. For example, the identification pattern 13 may be L-shaped consisting of a straight line that does not have a tip portion of an arrow. For example, in the semiconductor element pattern 12a, an example of the identification pattern 13 formed in an L shape consisting of a straight line is shown in FIG.

In the photolithographic processing, reduction projection exposure is performed on the photo resist layer formed on one main surface of the semiconductor substrate using the reticle 11 having such a configuration.
That is, here, the semiconductor element pattern, the identification pattern, and the scribe region included in the reticle 11 are applied as one exposure unit. Using the reticle 11, exposure and transfer are performed a plurality of times in the horizontal direction and the vertical direction to form a plurality of exposure shot areas.

At this time, the exposure shot region 11-A given by the reticle 11 is formed as shown in FIG. That is, the exposure shot region 11-A is a scribe region 18-A disposed so as to surround a semiconductor element pattern with respect to a photoresist layer (not shown) formed on one main surface of the semiconductor substrate 100. Are formed adjacent to each other in the vertical direction (Y-axis direction) and the horizontal direction (X-axis direction).
In FIG. 3, 121 semiconductor element patterns in each exposure shot region 11-A are not shown.

In FIG. 3, the exposure shot area 11-A1 is provided with a right-down hatching, and the exposure shot area 11-A2 is provided with a left-down hatching, so that the positional relationship and superposition of adjacent exposure shot areas are superimposed. The relationship is illustrated.
In addition, the scribe region 18-A disposed so as to surround the semiconductor element pattern is indicated by a one-dot chain line. As described above, the scribe region 18-A has a width equal to the scribe region between 121 semiconductor element patterns. Here, the “semiconductor element pattern” is a portion that is provided in each exposure shot region 11-A and later becomes a semiconductor element (semiconductor chip), and the “scribe region” is a region between adjacent semiconductor element patterns. is there.

  As described above, the exposure shot region 11-A overlaps the scribe region 18-A disposed so as to surround the 121 semiconductor element patterns 12-A, and in the vertical direction (Y-axis direction) and the horizontal direction. A plurality of photo resist layers on one main surface of the semiconductor substrate 100 are continuously formed adjacent to each other in the direction (X-axis direction).

FIG. 4 shows a state in which four exposure shot areas 11A are arranged vertically and horizontally.
Here, the exposure shot area 11-Aa is given a right-downward hatching, and the exposure shot area 11-Ab is given a left-downward hatching to show the positional relationship and the overlapping relationship of adjacent exposure shot areas. Yes.
In the four exposure shot regions 11-A, semiconductor element patterns 12-A, each of which 121 semiconductor element patterns 12 of the reticle 11 are transferred, are formed. In the four exposure shot regions on the semiconductor substrate 100, 121 are formed. × 4 (484) semiconductor element patterns 12-A are formed.

One exposure shot area 11-A is shown in FIG.
The semiconductor element pattern 12-A in the central portion of the exposure shot region 11-A is a specific semiconductor element pattern 12A-A to which the specific semiconductor element pattern 12A is transferred. The specific semiconductor element pattern 12A-A may be used only for inspection without being provided as a product, or may be provided as a product. A region between adjacent semiconductor element patterns 12-A is a scribe region 16-A to which the region 16 of the reticle 11 is transferred. The scribe regions 16-A and 18-A serve as a dicing portion when individual semiconductor elements are separated. The shot recognition pattern 17-A is a pattern to which the shot recognition pattern 17 of the reticle 11 has been transferred, and is a marker for identifying an exposure shot area when exposed.

In the exposure shot region 11-A, an identification pattern 13-A, in which the identification pattern 13 of the reticle 11 is transferred, is formed on the periphery of each semiconductor element pattern 12-A.
The identification pattern 13-A is formed on the periphery of each semiconductor element pattern 12-A in each of the exposure shot regions 11-A, and is defined as an observation target at the time of inspection from the semiconductor element pattern 12-A. This is an index indicating the direction and distance to the specific semiconductor element pattern 12A-A.
Here, a case where photolithography is performed on 121 semiconductor element patterns 12 using the reticle 11 provided with the identification pattern 13 on all except the specific semiconductor element pattern 12A is illustrated. Therefore, in the exposure shot region 11-A, the identification pattern 13-A is similarly formed on all the semiconductor element patterns 12-A except the specific semiconductor element pattern 12A-A. Of the semiconductor element patterns 12 excluding the specific semiconductor element pattern 12A, when photolithography is performed using a reticle in which the semiconductor element pattern 12 that does not have the identification pattern 13-A exists, it corresponds to the pattern of the reticle. Thus, an exposure shot region including the semiconductor element pattern 12 having no identification pattern 13-A is obtained.
In each exposure shot region 11-A, a shot recognition pattern 17-A to which the shot recognition pattern 17 of the reticle 11 is transferred is formed.

  The identification pattern 13-A corresponds to the identification pattern 13 of the reticle 11, and the direction and distance from the semiconductor element pattern 12-A to the specific semiconductor element pattern 12A-A are set to 4 of the semiconductor element pattern 12-A. Starting from any one of the corners, there are two arrows along the peripheral edge. That is, the identification pattern 12-A is composed of a horizontal arrow 13a-A and a vertical arrow 13b-A corresponding to the arrows 13a and 13b in FIG. In FIG. 5, the semiconductor element patterns 12a-A, 12b-A, 12c-A, and 12d-A correspond to the semiconductor element patterns 12a to 12d in FIG.

The lengths of the arrows 13a-A and 13b-A of the identification pattern 13-A only have to indicate the distance to the specific semiconductor element pattern 12A-A in accordance with a predetermined rule.
Further, as the identification pattern 13-A, if the direction and distance from the semiconductor element pattern 12-A on which the identification pattern 13-A is formed to the specific semiconductor element pattern 12A-A can be recognized, an arrow Other than the shape may be used. For example, the tip of the arrow need not be formed.

  4 and 5, the semiconductor element pattern 12-A is indicated by a rectangle surrounded by a broken line, but actually, a photoresist pattern corresponding to the corresponding layer is formed in the rectangle. As a part of this photoresist pattern, an identification pattern 13-A is formed. For example, if the corresponding layer is a wiring layer, a wiring-shaped photo resist pattern is formed in the rectangle, and the identification pattern 13-A is formed as a part of the photo resist pattern. The same applies to FIGS. 14 and 17 described later.

Hereinafter, the case of inspecting the specific semiconductor element pattern 12A-A formed on the semiconductor substrate 100 will be described with reference to FIGS.
In this inspection, it is determined by observing and measuring whether or not the photoresist pattern constituting the semiconductor element pattern 12-A is formed in a desired size, shape, electrical characteristics, and the like. The specific semiconductor element pattern 12A-A defined in advance is an observation target. An optical microscope or SEM (hereinafter simply referred to as a microscope) is used for the inspection.

  First, as shown in FIG. 4, a portion where the four shot recognition patterns 17-A in the exposure shot region 11-A are adjacent to each other is caught in the inspection field of view of the microscope. Using these four shot recognition patterns 17-A as indices, an exposure shot area to be inspected is determined. For example, among the four shot recognition patterns 17-A, the lower right shot recognition pattern 17-A is used as an index, and among the four exposure shot areas, the lower right exposure shot area 11-Ab is determined as an inspection target. To do.

Next, in the determined exposure shot area, the specific semiconductor element pattern 12A-A to be inspected is searched for.
Identification patterns 13-A are respectively formed on the periphery of the semiconductor element pattern 12-A in the exposure shot region 11-A. When a certain semiconductor element pattern 12-A is captured in the inspection field of the microscope, the arrows 13a-A and 13b-A of the identification pattern 13-A arranged on the semiconductor element pattern 12-A in the inspection field are visually recognized. Thus, the position of the specific semiconductor element pattern 12A-A can be accurately estimated. The position of the specific semiconductor element pattern 12A-A is immediately and accurately recognized only by grasping one semiconductor element pattern 12-A within the inspection visual field and visually recognizing the arrows 13a-A and 13b-A of the identification pattern 13-A. It may not be possible. However, if the inspection visual field is appropriately moved based on the identification pattern 13-A, the identification pattern 13-A entering the inspection visual field changes, and traces to the specific semiconductor element pattern 12A-A in a short time. Can arrive.

  In the present embodiment, instead of performing a defect inspection visually by a user using a microscope, an inspection may be automatically performed. For example, as shown in FIG. 6, the automatic inspection apparatus of the present embodiment includes an SEM 1, a recognition unit 2, a calculation unit 3, a database 4, an inspection visual field adjustment unit 5, and a control unit 6.

  The recognition unit 2 recognizes a pattern of an inspection visual field image of a certain semiconductor element pattern 12-A obtained by the SEM 1. The calculation unit 3 performs calculation processing from the image pattern recognized by the recognition unit 2. For example, a plurality of templates are prepared in advance in the database 4. The template corresponds to the arrows 13a-A and 13b-A of the identification pattern 13-A. The calculation unit 3 compares the recognized image pattern with a template, and determines that the image corresponds to the template when it matches or resembles a predetermined template. The computing unit 3 calculates the direction and distance from the semiconductor element pattern 12-A to the specific semiconductor element pattern 12A-A based on the template.

  The inspection visual field adjustment unit 5 automatically moves and stops the inspection visual field of the SEM 1. The inspection visual field adjustment unit 5 automatically moves and stops the inspection visual field until the specific semiconductor element pattern 12A-A is captured based on the calculation result of the calculation unit 3. The inspection visual field adjustment unit 5 can be provided in the SEM 1 as one of the functions of the SEM 1.

  The control unit 6 performs overall control of the recognition unit 2, the calculation unit 3, and the inspection visual field adjustment unit 5. The functions of the recognition unit 2, the calculation unit 3, the control unit 6, and the like are realized by executing a program read from a storage medium such as a ROM or a hard disk by a CPU of the computer.

As described above, in order to form a semiconductor element such as a semiconductor integrated circuit element on a semiconductor substrate such as a silicon (Si) semiconductor substrate, a photo for realizing the element structure corresponding to the structure of the semiconductor element. -A plurality of reticles having a semiconductor element pattern corresponding to the lithography process are required.
In the present embodiment, when producing a plurality of reticles, it is possible to select in which process the pattern for identification is arranged for the reticle to be applied.

When manufacturing the reticle, first, for example, a chromium (Cr) layer is deposited so as to cover one main surface of a quartz glass substrate.
Next, a photo resist layer is applied and formed on the chromium layer, and latent images of the semiconductor element pattern 12 and the identification pattern 13 are formed on the photo resist layer in accordance with the graphic pattern data using, for example, an electron beam exposure apparatus. draw.
Then, the photo-resist layer is developed to form a resist pattern, and the chromium layer is selectively etched using the resist pattern as a mask, and the semiconductor element pattern 12 and the identification pattern 13 are formed on the quartz glass substrate. , And a shot recognition pattern 17 are formed.
As a result, a reticle in which a chromium layer including the semiconductor element pattern 12, the identification pattern 13, and the shot recognition pattern 17 is selectively provided as a mask layer is formed on one main surface of the quartz glass substrate. .

FIG. 7 shows a manufacturing process flow for producing a plurality of reticles including a reticle having an identification pattern in this embodiment.
Here, in a reticle set for manufacturing a semiconductor element on a semiconductor substrate, each reticle is manufactured after determining on which reticle the identification pattern according to the present invention is to be formed.

  In the reticle manufacturing flow of FIG. 7, first, the first reticle (N = 1) is selected from the reticles constituting a plurality of (for example, K) reticles (step S1). Hereinafter, description will be made assuming that the reticle to be manufactured is the Nth sheet (N = 1, 2,..., K).

Subsequently, it is determined whether or not the semiconductor element pattern formed by exposing the reticle to the photo resist requires inspection, that is, whether or not the specific semiconductor element pattern is inspected (step S2).
If it is determined to inspect the specific semiconductor element pattern, the process proceeds to step S3. On the other hand, when it is determined that the specific semiconductor element pattern is not inspected, the reticle is manufactured without forming the identification pattern (step S11), and the process proceeds to step S7.

  An example of a semiconductor element pattern that does not require inspection of a specific semiconductor element pattern is a photo resist mask for ion implantation that does not require relatively precise formation. In the case of forming a photo resist mask for ion implantation that requires relatively high precision in the formation state, an identification pattern is required for the reticle (a reticle having a first semiconductor element pattern corresponding to the mask). In many cases, the semiconductor element pattern is not inspected for measuring the width or the like.

  In step S <b> 3, it is determined whether or not an identification pattern is formed in any of the pattern formation steps before the semiconductor element pattern formation step using the reticle. That is, assuming that the pattern forming process using the reticle is S (M) (1 ≦ M ≦ K), S (M−1), S (M−2). It is determined whether or not the second identification pattern is formed in any one of (1).

If it is determined that the identification pattern has been formed in each previous pattern formation step, the process proceeds to step S4. On the other hand, if it is determined in the previous pattern formation process that the identification pattern is not formed, it is determined that the reticle needs an identification pattern (step S8), and the reticle is inserted so as to include the identification pattern. It is produced (step S9). Then, at the time of defect inspection of the semiconductor element pattern formed using the reticle, the recognition pattern is recognized to be used (step S10), and the process proceeds to step S7.
When N = 1, the previous reticle does not exist, so the process proceeds to step S7 through steps S8 to S10.

In step S4, when a specific semiconductor element pattern formed by exposure using the reticle is inspected, an identification pattern formed by exposure of the reticle used in an exposure process prior to exposure using the reticle It is determined whether or not can be recognized. For example, when a wiring layer is formed using the reticle (when the semiconductor element pattern of the reticle corresponds to the wiring layer), a wiring material is formed on the entire surface of the semiconductor substrate, and a photoresist is applied on the wiring material. . At this time, the identification pattern formed by exposure of the previous reticle may not be visible due to the presence of the wiring material covering the entire surface of the semiconductor substrate.
When it is determined that the identification pattern formed using the previous reticle can be recognized, the reticle is manufactured without forming the identification pattern (step S5). Then, when inspecting the specific semiconductor element pattern formed using the reticle, it recognizes that the existing identification pattern is used (step S6), and proceeds to step S7. On the other hand, if it is determined that the identification pattern formed using the previous reticle cannot be recognized, the process proceeds to step S7 via steps S8 to S10.

  In step S7, it is determined whether or not the reticle is the final reticle (N = K). If it is determined that it is the final reticle, the flow ends. On the other hand, when it is determined that the reticle is not the final reticle, N = N + 1 is added to, for example, a process counter (step S12), and steps S2 to S11 are repeated as appropriate.

The semiconductor device manufacturing method according to the present embodiment will be explained below.
Here, a case where a plurality of semiconductor elements including MOS transistors as functional elements are formed on a semiconductor substrate is illustrated.

A manufacturing flow of the semiconductor device according to the present embodiment is shown in FIG.
In this embodiment, photolithographic processing is performed using the reticles A1 to H1. Reticles A1 to H1 are manufactured according to the reticle manufacturing flow shown in FIG.
Here, description will be made assuming that the reticles A1 to H1 are formed with identification patterns together with semiconductor element patterns.

First, an element isolation region (isolation region) is formed on one main surface of a silicon (Si) semiconductor substrate.
Therefore, the reticle A1 corresponding to the element isolation region formation pattern is used.
The reticle A1 includes a semiconductor element pattern and an identification pattern corresponding to the element isolation region in the semiconductor element.

By a photolithography process using the reticle A1, a photo resist layer A2 that defines an element isolation region forming portion is formed on the semiconductor substrate.
The photo resist layer A2 includes a semiconductor element pattern having a resist pattern for forming an inter-element isolation region of the semiconductor element, and an identification pattern indicating a direction and a distance from the semiconductor element pattern to the specific semiconductor element pattern. Has been.
Then, a defect inspection is performed on the photoresist layer A2 using the identification pattern.

As a result of the inspection, when there is no defective portion, the photo resist layer A2 is used as a mask, and the semiconductor substrate is dry etched to form an element isolation groove.
Thereafter, the photoresist layer A2 is removed by an ashing process or a process using a predetermined chemical solution.

  If a defective portion is found as a result of the inspection, the photo resist layer A2 is removed by ashing or treatment using a predetermined chemical solution. Then, a photolithography process using the reticle A1 is performed again to form a photoresist layer A2.

The defects generated in the photo-resist layer A2 include those that are transferable due to the reticle A1, and non-responsibility caused by the resist material of the semiconductor element pattern in which the defect is found or the interface state between the resist pattern and the semiconductor substrate. Some are transferable.
When the found defect is a transferable one caused by the reticle A1, when the cause of the defect is a foreign matter adhering to the pellicle of the reticle A1, the foreign matter is removed using nitrogen blow or the like. Further, when the cause of the defect is a scratch on the pellicle of the reticle A1, the pellicle is replaced.
If the found defect is caused by the resist material of the semiconductor element pattern among the non-transferable ones, the defect is a foreign matter attached to the photo resist when applying the photo resist to the semiconductor substrate, This may be caused by photo-resist alteration, scratches or the like generated on the photo-resist itself.
If the found defect is caused by the state of the interface between the resist pattern and the semiconductor substrate among the non-transferable ones, the defect is caused by a protrusion, a step or the like on the surface of the semiconductor substrate. it is conceivable that.

  Next, an insulating film (for example, a silicon oxide film) for embedding the isolation trench is deposited by chemical vapor deposition (CVD) or the like, and is planarized by chemical mechanical polishing (CMP) or the like, A so-called STI (Shallow Trench Isolation) element isolation structure is formed in which the inside of the element isolation trench is filled with an insulator (step S21).

Next, after an insulating layer made of, for example, a silicon oxide film is formed on the surface of the semiconductor substrate by a thermal oxidation method or the like, a polycrystalline silicon layer is deposited on the insulating layer by a CVD method or the like.
The insulating layer forms the gate insulating layer of the MOS transistor, and the polycrystalline silicon layer forms the gate electrode of the MOS transistor.

Then, the polycrystalline silicon layer and the insulating layer are collectively patterned by applying the reticle B1 corresponding to the gate electrode formation pattern.
The reticle B1 includes a semiconductor element pattern and an identification pattern corresponding to the gate electrode of the semiconductor element.

That is, a photo resist layer B2 for the gate electrode is formed on the polycrystalline silicon layer by photolithography using the reticle B1.
In the photo resist layer B2, a semiconductor element pattern having a resist pattern for forming a gate electrode of the semiconductor element and an identification pattern indicating the direction and distance from the semiconductor element pattern to the specific semiconductor element pattern are formed. Yes.
Then, a defect inspection is performed on the photoresist layer B2 using an identification pattern.
If there is no defective portion as a result of the inspection, the polycrystalline silicon layer and the insulating layer are dry-etched using the photo resist layer B2 as a mask, and a gate electrode is formed on the semiconductor substrate via the gate insulating layer (step) S22).
Thereafter, the photoresist layer B2 is removed by an ashing process or a process using a predetermined chemical solution.

  If a defective portion is found as a result of the inspection, the photo resist layer B2 is removed by ashing or treatment using a predetermined chemical solution. Then, a photolithography process using the reticle B1 is performed again to form a photo resist layer B2.

Next, using the gate electrode as a mask, an impurity (boron (B ⁺ ), phosphorus (P ⁺ ), arsenic (As ⁺ ), or the like) is ion-implanted into the surface of the semiconductor substrate with a predetermined dose and acceleration energy. Extension regions are formed on both sides of the electrode (step S23).

Next, an insulating film (for example, a silicon oxide film) is deposited on the entire surface of the semiconductor substrate including the gate electrode by a CVD method or the like.
Then, an anisotropic dry etching (etchback) process is performed on the insulating film, and a so-called sidewall insulating film is formed leaving the insulating film only on both sides of the gate electrode and the gate insulating film (step S24). ).

Next, using the gate electrode and the sidewall insulating film as a mask, impurities (boron (B ⁺ ), phosphorus (P ⁺ ), arsenic (As ⁺ ), etc.) are applied in the vicinity of the surface of the semiconductor substrate with a predetermined dose and acceleration energy. Ion implantation.
By the ion implantation, source / drain regions partially overlapping with the extension regions are formed on both sides of the sidewall insulating film (step S25).

  The impurity implanted to form the extension region and the source region / drain region is selected in accordance with the channel conductivity type (N-channel type or P-channel type) of the MOS transistor to be formed. The

Therefore, when a semiconductor element is formed on the semiconductor substrate with a so-called CMOS transistor configuration, the P-channel MOS transistor region or the N-channel MOS transistor region is selectively covered in the steps S23 and S25. It is necessary to form a photoresist layer.
That is, when forming a P-channel MOS transistor, a photo resist layer is formed to cover the formation region of the N-channel MOS transistor and to expose the formation region of the P-channel MOS transistor. P-type impurities (boron (B ⁺ )) are ion-implanted into the semiconductor substrate using the resist layer as a mask.

  When forming the photoresist layer, a reticle C1 on which a semiconductor element pattern for forming a P-channel MOS transistor and an identification pattern are formed is used.

By a photolithographic process using the reticle C1, a photo resist layer C2 having a semiconductor element pattern and an identification pattern indicating a direction and a distance from the semiconductor element pattern to the specific semiconductor element pattern is formed on the semiconductor substrate. It is formed.
Then, a defect inspection is performed on the photoresist layer using the identification pattern.
As a result of the inspection, when there is no defective portion, ion implantation of P-type impurities is performed using the photo resist layer C2 as a mask.
Thereafter, the photoresist layer C2 is removed by an ashing process or a process using a predetermined chemical solution.

On the other hand, when forming an N-channel type MOS transistor, a photo resist layer D2 is formed which covers the formation region of the P-channel type MOS transistor and exposes the formation region of the N-channel type MOS transistor. N-type impurities are ion-implanted into the semiconductor substrate using the resist layer D2 as a mask.
When the resist mask layer D2 is formed, a reticle D1 on which a semiconductor element pattern for forming an N-channel MOS transistor and an identification pattern are formed is used.

By a photolithographic process using the reticle D1, a photo resist layer D2 having a semiconductor element pattern and an identification pattern indicating the direction and distance from the semiconductor element pattern to the specific semiconductor element pattern is formed on the semiconductor substrate. It is formed.
Then, a defect inspection is performed on the photoresist layer D2 using an identification pattern.
As a result of the inspection, when there is no defective portion, N-type impurity ions are implanted using the photo-resist layer D2 as a mask.
Thereafter, the photoresist layer D2 is removed by an ashing process or a process using a predetermined chemical solution.
In addition, in the stage of step S25 (source / drain formation process), the identification pattern formed in step S22 (gate electrode formation process) may be visible. In such a case, an identification pattern is not required in step S25.

Thereafter, an insulating film having a film thickness for embedding the gate electrode is deposited on the entire surface of the semiconductor substrate by a CVD method or the like to form a first interlayer insulating film (step S26).
Silicon oxide is applied as an insulator for forming the first interlayer insulating film.

Then, the first interlayer insulating film is selectively subjected to an opening process to form a so-called interlayer connection hole (contact hole).
The first interlayer insulating film is patterned by applying the reticle E1 corresponding to the interlayer connection hole formation pattern.
The reticle E1 includes a semiconductor element pattern and an identification pattern corresponding to the interlayer connection hole.

That is, a photo resist layer E2 for forming an interlayer connection hole is formed in the first interlayer insulating film by photolithography using the reticle E1.
In the photoresist layer E2, a semiconductor element pattern having an interlayer connection hole formation pattern and an identification pattern indicating the direction and distance from the semiconductor element pattern to the specific semiconductor element pattern are formed. However, if the identification pattern formed in step S22 (the formation process of the gate electrode) is easily visible after the formation of the first interlayer insulating film, the identification pattern is not necessarily required.
Then, a defect inspection is performed on the photo resist layer E2 using an identification pattern.
If there is no defective portion as a result of the inspection, an interlayer connection hole is formed in the first interlayer insulating film using the photo resist layer E2 as a mask (step S27).
Thereafter, the photoresist layer E2 is removed by an ashing process or a process using a predetermined chemical solution.

  If a defective portion is found as a result of the inspection, the photoresist layer E2 is removed by ashing or treatment using a predetermined chemical solution. Then, a photolithography process using the reticle E1 is performed again to form a photo resist layer E2.

Next, a conductive material made of tungsten (W), for example, is deposited on the first interlayer insulating film by a CVD method or the like so as to fill the interlayer connection hole via a predetermined glue film or the like.
Then, the conductive material is flattened by a CMP method or the like to form a so-called contact plug structure in which the interlayer connection hole is filled with the conductive material (step S28).

Subsequently, a wiring material layer made of, for example, an aluminum (Al) alloy is deposited on the first interlayer insulating film. When depositing the aluminum alloy, a sputtering method or the like can be applied.
Then, the wiring material layer is selectively removed to form an electrode wiring layer.

The wiring material layer is patterned by applying the reticle F1 corresponding to the electrode wiring layer formation pattern.
The reticle F1 includes a semiconductor element pattern and an identification pattern corresponding to the electrode wiring layer of the semiconductor element.

That is, a photo resist layer F2 for forming an electrode wiring layer is formed on the wiring material layer by photolithography using the reticle F1.
In the photoresist layer F2, a semiconductor element pattern having an electrode wiring layer forming pattern and an identification pattern indicating the direction and distance from the semiconductor element pattern to the specific semiconductor element pattern are formed.
Then, a defect inspection is performed on the photoresist layer F2 using an identification pattern.
If there is no defective portion as a result of the inspection, the wiring material layer is selectively etched using the photo resist layer F2 as a mask to form the first wiring layer on the first interlayer insulating film (step S29).
Thereafter, the photoresist layer F2 is removed by an ashing process or a process using a predetermined chemical solution.

  If a defective part is found as a result of the inspection, the photoresist layer F2 is removed by ashing or treatment using a predetermined chemical solution. Then, a photolithography process using the reticle F1 is performed again to form a photo resist layer F2.

Next, a second interlayer insulating film is formed to cover the exposed portion of the first wiring layer and the first interlayer insulating film (step S30).
For the second interlayer insulating film, silicon oxide can be applied as a material, and a CVD method can be applied as a deposition method.

Then, an opening process is selectively performed on the second interlayer insulating film to form a so-called interlayer connection hole (via hole).
The second interlayer insulating film is patterned by applying the reticle G1 corresponding to the interlayer connection hole formation pattern.
The reticle G1 includes a semiconductor element pattern and an identification pattern corresponding to the interlayer connection hole.

That is, a photo resist layer E2 for forming an interlayer connection hole is formed in the second interlayer insulating film by a photolithography process using the reticle G1.
In the photoresist layer G2, a semiconductor element pattern having an interlayer connection hole forming pattern and an identification pattern indicating the direction and distance from the semiconductor element pattern to the specific semiconductor element pattern are formed.
Then, a defect inspection is performed on the photoresist layer G2 using an identification pattern.
As a result of the inspection, when there is no defective portion, the second interlayer insulating film is etched using the photo resist layer G2 as a mask to form an interlayer connection hole (via hole) (step S31).
Thereafter, the photoresist layer E2 is removed by an ashing process or a process using a predetermined chemical solution.

  If a defective part is found as a result of the inspection, the photoresist layer G2 is removed by ashing or treatment using a predetermined chemical solution. Then, a photolithography process using the reticle G1 is performed again to form a photo resist layer G2.

Next, a conductive material made of tungsten (W), for example, is deposited on the second interlayer insulating film by a CVD method or the like so as to fill the interlayer connection hole via a predetermined glue film or the like.
Then, the conductive material is flattened by a CMP method or the like to form a so-called contact plug structure in which the interlayer connection hole is filled with the conductive material (step S32).

Subsequently, a wiring material layer made of, for example, an aluminum (Al) alloy is deposited on the second interlayer insulating film.
Then, the wiring material layer is selectively removed to form an electrode wiring layer.
The wiring material layer is patterned by applying the reticle H1 corresponding to the electrode wiring layer formation pattern.
The reticle H1 includes a semiconductor element pattern and an identification pattern corresponding to the electrode wiring layer.

That is, a photo resist layer H2 for forming an electrode wiring layer is formed on the wiring material layer by photolithography using the reticle H1.
In the photoresist layer H2, a semiconductor element pattern having an electrode wiring layer forming pattern and an identification pattern indicating the direction and distance from the semiconductor element pattern to the specific semiconductor element pattern are formed.
Then, a defect inspection is performed on the photoresist layer H2 using an identification pattern.
As a result of the inspection, if there is no defective portion, the wiring material layer is selectively etched using the photo resist layer H2 as a mask to form a second wiring layer on the second interlayer insulating film (step S33).
Thereafter, the photoresist layer H2 is removed by an ashing process or a process using a predetermined chemical solution.

  If a defective portion is found as a result of the inspection, the photo resist layer H2 is removed by ashing or treatment using a predetermined chemical solution. Then, a photolithography process using the reticle H1 is performed again to form a photo resist layer H2.

Next, a third interlayer insulating film is formed to cover the exposed portion of the second wiring layer and the second interlayer insulating film (step S34).
For the third interlayer insulating film, silicon oxide can be applied as a material, and a CVD method can be applied as a deposition method.

  Then, if necessary, an upper wiring layer is formed through an interlayer insulating film, and further, a stabilization layer (passivation layer) made of silicon nitride, an external connection terminal, and the like are formed. An electronic circuit including a MOS transistor is formed on the main surface.

  In addition, as a wiring layer material constituting the wiring layer, a wiring material mainly composed of copper (Cu) can be applied instead of an aluminum alloy or the like. In this case, the copper wiring can be formed by a so-called damascene method.

Here, of steps S21, S22, S25, S27, S29, S31, and S33 for performing a photolithographic process using a reticle, step S29 for forming the first wiring is taken as an example, and the photolithographic process is performed. Will be described in detail.
In addition, defect inspection is similarly performed in steps S21, S22, S27, S31, and S33.

9 and 10 show an example of a semiconductor substrate in which a plurality of semiconductor elements are formed on one main surface through the steps shown in FIG. 8 (steps S21 to S34).
As shown in FIG. 9, in the semiconductor substrate 100, a plurality of semiconductor element regions 11-B are arranged and defined in the horizontal direction and the vertical direction. Each semiconductor element region 11-B corresponds to one of the exposure shot regions 11A.

In FIG. 9, among the semiconductor element regions 11-B, the semiconductor element region 11-B1 is provided with a left-down hatching, and the semiconductor element region 11-B2 is provided with a right-down hatching, so that adjacent semiconductor element regions The positional relationship and the superposition relationship are shown.
In each semiconductor element region 11-B, for example, 121 semiconductor elements are arranged vertically and horizontally with a scribe region (not shown) interposed therebetween.
Note that in an actual semiconductor substrate on which a plurality of semiconductor elements are formed, the semiconductor element regions corresponding to the individual exposure shot regions cannot be distinguished. A state in which a plurality of semiconductor elements are arranged vertically and horizontally across a scribe region is shown.

FIG. 10 shows a state where 121 semiconductor element regions 11-B are arranged vertically and horizontally on the semiconductor substrate.
Here, the semiconductor element region 11-Ba is provided with a downward-sloping hatching, and the semiconductor element region 11Bb is provided with a downward-sloping hatching to indicate the positional relationship and the overlapping relationship of both semiconductor element regions.
As described above, in each semiconductor element region 11-B, 121 semiconductor element forming members are arranged vertically and horizontally with the scribe region 16-B interposed therebetween.
The scribe region 16-B and the scribe region 18-B have the same width.

One semiconductor element region 11-B of the semiconductor substrate 100 of FIG. 9 or FIG. 10 is shown in FIG.
In the semiconductor element region 11-B, for example, a specific semiconductor element 12A-B defined as an observation target at the time of inspection is formed in the central portion. In addition, shot recognition patterns 17-B are stacked at four corners of the semiconductor element region 11-B.

In the semiconductor element region 11-B, an index indicating the direction and distance from the semiconductor element 12-B to the specific semiconductor element 12A-B defined as the observation target at the time of inspection is provided on the peripheral edge of each semiconductor element 12-B. The identification pattern 13-B is formed.
The identification pattern 13-B is a pattern in which the direction and distance from the semiconductor element 12-B to the specific semiconductor element 12A-B is set to 2 along the peripheral edge starting from one of the four corners of the semiconductor element 12-B. It is said to be an arrow on the book. That is, the identification pattern 13-B includes horizontal arrows 13a-B and vertical arrows 13b-B corresponding to the arrows 13a-A and 13b-A in FIG. In FIG. 11, the semiconductor elements 12a-B, 12b-B, 12c-B, and 12d-B correspond to the semiconductor element patterns 12a-A to 12d-A in FIG.

The reference length of the identification pattern 13-B (the length corresponding to the case where the semiconductor element 12-B and the specific semiconductor element 12A-B are closest to each other), the width, and the shape are the chip size and inspection of the semiconductor element to be manufactured. It is appropriately selected according to the visual field range of the apparatus.
The identification pattern 13-B is obtained by appropriately stacking each identification pattern obtained by etching the material of the layer in the etching process using the semiconductor element pattern of each layer of the semiconductor element 12-B.

  A specific formation site of each identification pattern 13-B in the semiconductor element region 11-B will be described with reference to FIG. In FIG. 12, as the identification pattern 13-B, an L-shaped identification pattern 13-B consisting of a straight line formed corresponding to the L-shaped identification pattern 13 consisting of a straight line in FIG. .

FIG. 12A shows only a part including one specific semiconductor element 12A-B and 19 semiconductor elements 12-B around the specific semiconductor element 12A-B in the semiconductor element region 11-B. Show.
The scribe region 16B includes, for example, a first region 16B-1 at a central portion along the longitudinal direction of the scribe region 16B, as shown in FIG. It consists of a pair of 2nd area | region 16B-2 of the both-sides site | part of 1st area | region 16B-1.
In the first region 16B-1, for example, an in-scribe pattern 16Ba representing various information related to the semiconductor element 12-B is formed. In the second region 16B-2, for example, a bonding pad 16Bb that is an external connection terminal of the semiconductor element 12-B is formed.

As shown in FIG. 12B, the identification pattern 13-B has a boundary between the bonding pad 16Bb and the first region 16B-1 in the second region 16B-2 in the vicinity of the corner of the semiconductor element 12-B. Is provided in a free space 19a existing between the two. Further, instead of the empty area 19a, the empty area 19b existing between the bonding pad 16Bb and the boundary of the semiconductor element 12-B in the second area 16B-2, and the in-scribe pattern 16Ba in the first area 16B-1 The identification pattern 13-is formed in either the empty area 19 c existing between the boundary of the second area 16 B- 2 or the empty area 19 d existing between the boundary of the second area 16 B- 2 in the semiconductor element 12 -B. B may be provided. In FIG. 12B, different patterns for identification 13-B (four types in the above example) having different formation sites are marked with different patterns.
The scribe area 18B is also composed of a first and a pair of second areas similarly to the scribe area 16B, and the identification pattern 13-B can be formed in various empty areas.

Hereinafter, a case where the specific semiconductor element 12A-B formed on the semiconductor substrate 100 is inspected will be described with reference to FIGS.
This inspection is performed by observing and measuring whether or not the pattern constituting the semiconductor element 12-B is formed in a desired size, shape, electrical characteristics, and the like. The specific semiconductor element 12A-B defined in advance is an observation object. An optical microscope or SEM is used for the inspection.

  First, as shown in FIG. 10, a portion where the four shot recognition patterns 17-B of the semiconductor element region 11-B are adjacent to each other is caught in the inspection field of the microscope. A semiconductor element region to be inspected is determined using these four shot recognition patterns 17-B as indices. For example, among the four shot recognition patterns 17-B, the lower right shot recognition pattern 17-B is used as an index, and the semiconductor element region 11-Bb is determined as an inspection target.

Next, the specific semiconductor element pattern 12A-B to be inspected is searched for in the determined semiconductor element region.
Identification patterns 13-B are formed on the periphery of the semiconductor element 12-B in the semiconductor element region 11-B. When a certain semiconductor element 12-B is captured in the inspection field of the microscope, the arrows 13a-B and 13b-B of the identification pattern 13-B arranged on the semiconductor element 12-B in the inspection field are visually recognized. The position of the specific semiconductor element 12A-B can be accurately estimated. When the position of the specific semiconductor element 12A-B cannot be immediately recognized simply by grasping one semiconductor element 12-B in the inspection field of view and only visually recognizing the arrows 13a-B and 13b-B of the identification pattern 13-B There is also a possibility. However, if the inspection visual field is appropriately moved based on the identification pattern 13B-B, the identification pattern 13-B that falls within the inspection visual field changes and reaches the specific semiconductor element 12A-B in a short time. be able to.

  In the semiconductor substrate 100, each semiconductor element 12-B can be separated by cutting along the scribe regions 16-B and 18-B by dicing.

  As described above, according to the present embodiment, when inspecting the specific semiconductor element pattern 12A-A that is the transfer pattern on which the specific semiconductor element pattern 12A of the reticle 11 is exposed, a large number of semiconductor element patterns 12-A are present. Even if formed, the specific semiconductor element pattern 12A-A can be found easily and accurately in a short time, and the inspection can be performed very efficiently.

  In the present embodiment, the case where the identification pattern 13 is provided on the peripheral edge of all the semiconductor element patterns 12 of the reticle 11 is illustrated. And about the case where identification pattern 13-A (identification pattern 13-B) is formed in the peripheral part of all the semiconductor element patterns 12-A (semiconductor element 12-B) in each exposure shot area | region of the semiconductor substrate 100. Illustrated. However, in this embodiment, instead of providing the identification pattern 13 on all the semiconductor element patterns 12 in the reticle 11, it is conceivable to selectively provide the identification pattern 13 only on the predetermined semiconductor element pattern 12. For example, the identification pattern 13 may be provided every one or several semiconductor element patterns 12 (for example, in a staggered pattern).

  In the present embodiment, among the plurality of semiconductor element patterns 12 formed on the reticle 11, the semiconductor element pattern 12 positioned at the center portion is set as the specific semiconductor element pattern 12A to be inspected after exposure transfer. However, in the present embodiment, the specific semiconductor element pattern 12A may be arranged in addition to the central portion. For example, as shown in FIG. 13, the specific semiconductor element pattern 12 </ b> A is arranged in the lower left region among the plurality of semiconductor element patterns 12 of the reticle 11. In this case, for example, the semiconductor element pattern 12 (referred to as 12a in FIG. 13) shown in the circle C includes arrows 13a and 13b indicating the direction and distance from the semiconductor element pattern 12 to the specific semiconductor element pattern 12A. An identification pattern 13 is provided.

(Second Embodiment)
The present embodiment is different from the first embodiment in that a corner recognition pattern is provided on the reticle in addition to the identification pattern. Accordingly, a corner recognition pattern is formed on the semiconductor substrate together with the identification pattern, and a corner recognition pattern is finally formed on the semiconductor substrate together with the identification pattern.

FIG. 14 shows one reticle according to the second embodiment, and FIG. 15 shows one exposure shot region on a semiconductor substrate exposed using this reticle.
FIG. 15 shows the state of the exposure shot area transferred to the photo resist on the semiconductor substrate by this reticle.

As shown in FIG. 14, the reticle 30 according to the present embodiment includes, for example, 11 × 11 (121) semiconductor element patterns 12 (specific semiconductor element patterns) as in the reticle 11 of FIG. 1 of the first embodiment. 12A), and an identification pattern 13 is formed on the peripheral edge of each semiconductor element pattern 12.
Unlike the reticle 11, the reticle 30 does not have the shot recognition pattern 17, and a corner recognition pattern 31 is formed at a peripheral portion of each semiconductor element pattern 12 at a portion different from the identification pattern 13. .

The corner recognition pattern 31 is an index indicating the direction and distance to the corner closest to the identification pattern 13 among the four corners of the reticle 30.
The corner recognition pattern 31 includes, for example, two line segments 31a having a predetermined width along the peripheral edge from the corner that is a diagonal portion of the identification pattern 13 among the four corners of the semiconductor element pattern 12. 31b.

  For example, as in FIG. 1, attention is paid to the semiconductor element pattern 12a. The corner of the reticle 30 that is closest to the semiconductor element pattern 12a is the upper right corner. From the semiconductor element pattern 12a to the semiconductor element pattern 12 at the upper right corner, there are two semiconductor element patterns 12 on the right in the horizontal direction, and upward in the vertical direction. There are three semiconductor element patterns 12. A corner recognition pattern 31 corresponding to the positional relationship with the upper right corner of the reticle 30 is formed in the semiconductor element pattern 12 a together with the identification pattern 13. The corner recognizing pattern 31 starts from the lower left corner of the semiconductor element pattern 12a and corresponds to a line segment 31a having a length corresponding to “2” in the horizontal direction and “3” in the vertical direction. The line segment 31b has a proportion length.

  Further, as in FIG. 1, attention is paid to the semiconductor element pattern 12b. The semiconductor element pattern 12 b is the semiconductor element pattern 12 formed at the lower right corner of the reticle 30. In the semiconductor element pattern 12b, a corner recognition pattern 31 composed of small line segments 31a and 31b indicating that the semiconductor element pattern 12a is present in the lower right corner of the reticle 30 is formed in the upper left corner of the semiconductor element pattern 12a together with the identification pattern 13. ing.

  Further, as in FIG. 1, attention is paid to the first semiconductor element pattern 12c. The corner of the reticle 30 closest to the first semiconductor element pattern 12c is the upper left corner or the lower left corner. For example, from the first semiconductor element pattern 2c to the first semiconductor element pattern 2 at the upper left corner, three first semiconductor element patterns 12 on the left in the horizontal direction and five first semiconductor element patterns on the upper side in the vertical direction 2 exists. A corner recognition pattern 31 corresponding to the positional relationship with the upper left corner of the reticle 30 is formed in the semiconductor element pattern 12 c together with the identification pattern 13. The corner recognition pattern 31 starts from the lower right corner of the semiconductor element pattern 12c, and corresponds to a line segment 31a having a length corresponding to “3” to the left in the horizontal direction and “5” in the vertical direction. It consists of a line segment 31b having a proportion length.

  Further, as in FIG. 1, attention is paid to the semiconductor element pattern 12d. The corner of the reticle 30 closest to the semiconductor element pattern 12d is the lower left corner. From the semiconductor element pattern 12d to the semiconductor element pattern 12 at the lower left corner, there are two semiconductor element patterns 12 on the left in the horizontal direction and three semiconductor element patterns 12 on the lower side in the vertical direction. In the semiconductor element pattern 12 d, a corner recognition pattern 31 corresponding to the positional relationship with the lower left corner of the reticle 30 is formed together with the identification pattern 13. The corner recognition pattern 31 corresponds to a line segment 31a having a length corresponding to “2” to the left in the horizontal direction and “3” in the lower vertical direction starting from the upper right corner of the semiconductor element pattern 12d. It consists of a line segment 31b having a proportion length.

Similar to FIGS. 3 and 4 of the first embodiment, the reticle 30 is used to form a plurality of exposure shot areas by performing reduction projection exposure on the photoresist on the semiconductor substrate 100 a plurality of times and developing. To do. FIG. 15 shows a state of one exposure shot area 30-A corresponding to FIG. 5 of the first embodiment.
In the exposure shot region 30-A, 121 semiconductor element patterns 12-A to which 121 semiconductor element patterns 12 of the reticle 30 are transferred are formed. The semiconductor element pattern 12-A in the central portion of the exposure shot region 30-A is a specific semiconductor element pattern 12A-A to which the specific semiconductor element pattern 12-A is transferred.

In the exposure shot region 30-A, an identification pattern 13-A in which the identification pattern 13 is transferred is formed at the peripheral edge of each second semiconductor element pattern 12-A. Similarly, a corner recognition pattern 31-A in which the corner recognition pattern 31 is transferred to the diagonal portion of the identification pattern 13-A at the periphery of each semiconductor element pattern 12-A.
The corner recognition pattern 31-A is formed at the peripheral edge of each semiconductor element pattern 12-A in the exposure shot region 30-A, and the direction to the corner closest to the semiconductor element pattern 12-A and This is an index indicating distance.

The corner recognizing pattern 31-A corresponds to the corner recognizing pattern 31, and is a peripheral portion of the semiconductor element pattern 12-A starting from a corner that is a diagonal portion of the identifying pattern 12-A. Are formed of two line segments 31a-A and 31b-A having a predetermined width.
In FIG. 15, the semiconductor element patterns 12a-A, 12b-A, 12c-A, and 12d-A correspond to the semiconductor element patterns 12a to 12d in FIG.

Hereinafter, the case where the specific semiconductor element pattern 12A-A formed on the semiconductor substrate 100 is inspected will be described with reference to FIG.
An identification pattern 13-A and a corner recognition pattern 31-A are formed on the periphery of the semiconductor element pattern 12-A in the exposure shot region, respectively. When a certain semiconductor element pattern 12-A is captured within the inspection visual field of the microscope, first, arrows 31a-A, 31b- of the corner recognition pattern 31-A arranged on the semiconductor element pattern 12-A within the inspection visual field. By visually recognizing A, the position of the corner of the exposure shot region to which the semiconductor element pattern 12-A belongs can be accurately estimated. If the position of the corner is known, the exposure shot region to which the semiconductor element pattern 12-A belongs can be grasped.

  In the first embodiment, in order to grasp the exposure shot area, it is necessary to capture a portion where the four shot recognition patterns 17-A of the four exposure shot areas are adjacent to each other in the inspection field of view, and the inspection work is complicated. There is also a possibility of inducing. In the present embodiment, since each corner pattern recognition pattern 31-A is provided together with the identification pattern 13-A in each semiconductor element pattern 12-A, the exposure shot area can be grasped easily and accurately in a short time. it can.

  And in order to test | inspect the specific semiconductor element pattern 12A-A of the said exposure shot area | region 30-A, arrow 13a-A of the pattern 13-A for identification arranged on the semiconductor element pattern 12-A in a test | inspection visual field, Visually observe 13b-A. By this visual recognition, the position of the specific semiconductor element pattern 12A-A in the exposure shot region 30-A to which the semiconductor element pattern 12-A belongs can be accurately estimated. The inspection visual field can be moved according to the identification pattern 13-A, and the specific semiconductor element pattern 12A-A can be reached in a short time.

  In the present embodiment, as in the first embodiment, an automatic inspection apparatus similar to that in FIG. 6 is used to automatically inspect instead of performing a defect inspection by a user using a microscope. Anyway.

  Also in this embodiment, similarly to the first embodiment, a plurality of semiconductor elements are formed on one main surface of the semiconductor substrate through the steps (steps S21 to S34) shown in FIG. . In each semiconductor element, a corner recognition pattern corresponding to the reticle corner recognition pattern 31 is formed together with an identification pattern corresponding to the reticle identification pattern 13.

  As described above, according to the present embodiment, when inspecting the specific semiconductor element pattern 12A-A that is the transfer pattern on which the specific semiconductor element pattern 12A of the reticle 30 is exposed, the exposure shot region to be inspected is accurately determined. Can be selected. Even when a large number of semiconductor element patterns 12-A are formed, the specific semiconductor element pattern 12A-A can be found easily and accurately in a short time, and the inspection can be performed very efficiently.

  In the present embodiment, among the plurality of semiconductor element patterns 12 formed on the reticle 30, the semiconductor element pattern 12 positioned at the center portion is set as the specific semiconductor element pattern 12 </ b> A to be inspected after exposure transfer. However, in the present embodiment, the specific semiconductor element pattern 12A may be arranged in addition to the central portion.

  For example, as shown in FIG. 16, the specific semiconductor element pattern 12A is arranged in the upper right region among the plurality of semiconductor element patterns 12 of the reticle 30a. In this case, for example, the semiconductor element pattern 12 (referred to as 12a in FIG. 16) shown in a circle C is provided with an identification pattern 13 and a corner recognition pattern 32.

When the specific semiconductor element pattern is provided in the vicinity of the corner of the reticle, here, the case of FIG. 16 (the specific semiconductor element pattern 12A is provided in the vicinity of the upper right corner of the reticle 30a) will be described as an example. To do.
When viewed from the semiconductor element pattern 12a shown in the circle C, the specific semiconductor element pattern 12A and the upper right corner of the reticle 30a are both in the same direction (upper right direction). In this case, the corner recognition pattern 32 is integrally formed so as to extend from the identification pattern 13. By forming the corner recognition pattern 32 in this manner, the upper right corner corresponding to the corner recognition pattern 32 can be easily recognized in the exposure shot region formed by exposing the reticle 30a to the photo resist and developing. can do.

Specifically, the identification pattern 13 includes arrows 13a and 13b indicating the direction and distance from the semiconductor element pattern 12a to the specific semiconductor element pattern 12A.
The corner recognition pattern 32 is an index indicating the direction and distance to the corner closest to the identification pattern 13 among the four corners of the reticle 30, here the right corner. The corner recognition pattern 32 includes two line segments 32a and 32b having a predetermined width. A line segment 32a is formed in the same direction as the arrow 13a starting from the tip of the arrow 13a of the identification pattern 13, and a line segment 32b is formed in the same direction as the arrow 13a starting from the tip of the arrow 13b of the identifying pattern 13. Yes.

(Third embodiment)
In the present embodiment, similarly to the second embodiment, a corner recognition pattern is provided on the reticle in addition to the first identification pattern. Furthermore, in the present embodiment, the reticle is provided with a plurality of specific semiconductor element patterns to be observed when the transfer pattern is inspected.
FIG. 17 shows one reticle according to the third embodiment. FIG. 18 shows one exposure shot area in the semiconductor substrate exposed using this reticle.
FIG. 17 shows the state of the exposure shot area transferred to the photo resist on the semiconductor substrate by this reticle.

  As shown in FIG. 17, the reticle 40 according to the present embodiment includes, for example, 11 × 11 (121) semiconductor element patterns 12 (specific semiconductor element patterns) as in the reticle 11 of FIG. 1 of the first embodiment. 12A.) Is formed. In the reticle 40, the semiconductor element patterns 12 to be observed at the time of inspection of the transfer pattern are provided at, for example, three locations, and are designated as specific semiconductor element patterns 12A, 12B, and 12C.

Each semiconductor element pattern 12 is formed with corner recognition patterns 31 and identification patterns 41 to 43 similar to those of the second embodiment at the periphery thereof.
The identification pattern 41 is an index indicating the direction and distance from the semiconductor element pattern 12 to the specific semiconductor element pattern 12A. The identification pattern 42 is an index indicating the direction and distance from the semiconductor element pattern 12 to the specific semiconductor element pattern 12B. The identification pattern 43 is an index indicating the direction and distance from the semiconductor element pattern 12 to the specific semiconductor element pattern 12C.

For example, attention is focused on the semiconductor element pattern 12 (referred to as 12a in FIG. 17) shown in a circle C in FIG.
In the semiconductor element pattern 12a, an identification pattern 41 corresponding to the positional relationship with the specific semiconductor element pattern 12A is formed. From the semiconductor element pattern 12a to the specific semiconductor element pattern 12A, there are five semiconductor element patterns 12 on the left in the horizontal direction and three semiconductor element patterns 12 on the lower side in the vertical direction. The identification pattern 41 starts from the upper right corner of the semiconductor element pattern 12 and has an arrow 41a with a length corresponding to “5” on the left in the horizontal direction and a length corresponding to “3” on the lower side in the vertical direction. And an arrow 41b.

  Furthermore, an identification pattern 42 corresponding to the positional relationship with the specific semiconductor element pattern 12B is formed in the semiconductor element pattern 12a. From the semiconductor element pattern 12a to the specific semiconductor element pattern 12B, there are three semiconductor element patterns 12 on the left side in the horizontal direction and two semiconductor element patterns 12 on the upper side in the vertical direction. The identification pattern 42 starts from the lower right corner of the semiconductor element pattern 12 and has an arrow 42a having a length corresponding to “3” to the left in the horizontal direction and a length corresponding to “2” in the vertical direction. And an arrow 42b.

  Further, an identification pattern 43 corresponding to the positional relationship with the specific semiconductor element pattern 12C is formed in the semiconductor element pattern 12a. From the semiconductor element pattern 12a to the specific semiconductor element pattern 12C, there is one semiconductor element pattern 12 on the right side in the horizontal direction and two semiconductor element patterns 12 on the lower side in the vertical direction. The identification pattern 43 starts from the upper left corner of the semiconductor element pattern 12 and has an arrow 43a having a length corresponding to “1” in the horizontal direction and a length corresponding to “2” in the vertical direction. And an arrow 43b.

  Furthermore, corner recognition patterns 31 are formed in the semiconductor element pattern 12a. The corner of the reticle 40 that is closest to the semiconductor element pattern 12a is the upper right corner. The two semiconductor element patterns 12 are formed laterally rightward from the semiconductor element pattern 12a to the semiconductor element pattern 12 at the upper right corner. There are four semiconductor element patterns 12. The corner recognition pattern 31 starts from the lower left corner of the semiconductor element pattern 12 and corresponds to a line segment 31a having a length corresponding to “2” to the right in the horizontal direction and “4” in the vertical direction. The line segment 31b has a proportion length.

Similar to FIGS. 3 and 4 of the first embodiment, a plurality of exposure shot regions are formed by performing reduction projection exposure on the photoresist on the semiconductor substrate 100 a plurality of times and developing using the reticle 40. To do. FIG. 18 shows a state of one exposure shot area corresponding to FIG. 15 of the second embodiment.
In the exposure shot area 40-A, 121 semiconductor element patterns 12-A to which 121 semiconductor element patterns 12 of the reticle 40 are transferred are formed. In the exposure shot area 40-A, specific semiconductor element patterns 12A-A, 12B-A, and 12C-A to which the specific semiconductor element patterns 12A, 12B, and 12C are transferred.

  In the exposure shot area 40-A, identification patterns 41-A, 42-A, and 43-A, in which the identification patterns 41, 42, and 43 are transferred, are formed on the periphery of each semiconductor element pattern 12-A. The Similarly, a corner recognition pattern 31-A, in which the corner recognition pattern 31 is transferred, is formed in the peripheral portion of each semiconductor element pattern 12-A and on the diagonal portion of the identification pattern 41-A.

The identification pattern 41-A corresponds to the identification pattern 41, and has two arrows 41a having a predetermined width starting from the upper right corner of the semiconductor element pattern 12-A and extending along the peripheral edge of the semiconductor element pattern 12-A. -A, 41b-A.
The identification pattern 42-A corresponds to the identification pattern 42, and has two arrows 42a having a predetermined width starting from the lower right corner of the semiconductor element pattern 12-A and extending along the peripheral edge of the semiconductor element pattern 12-A. -A, 42b-A.
The identification pattern 43-A corresponds to the identification pattern 43, and has two arrows 43a having a predetermined width starting from the upper left corner of the semiconductor element pattern 12-A and extending along the peripheral edge of the semiconductor element pattern 12-A. -A, 43b-A.

A case where the specific semiconductor element patterns 12A-A, 12B-A, and 12C-A formed on the semiconductor substrate 100 are inspected will be described.
When a certain semiconductor element pattern 12-A is captured within the inspection visual field of the microscope, first, arrows 31a-A, 31b- of the corner recognition pattern 31-A arranged on the semiconductor element pattern 12-A within the inspection visual field. By visually recognizing A, the position of the corner of the exposure shot region 40-A to which the semiconductor element pattern 12-A belongs can be accurately estimated. If the position of the corner is known, the exposure shot area 40-A to which the semiconductor element pattern 12-A belongs can be grasped.

  In order to inspect the specific semiconductor element pattern 12A-A in the exposure shot area 40-A, the arrows 41a-A and 41b of the identification pattern 41-A arranged on the semiconductor element pattern 12-A in the inspection field of view. -A is visually recognized. By this visual recognition, the position of the specific semiconductor element pattern 12A-A in the exposure shot region 40-A can be accurately estimated. The inspection visual field can be moved according to the identification pattern 41-A, and the specific semiconductor element pattern 12A-A can be reached in a short time.

  Further, in order to inspect the specific semiconductor element pattern 12B-A in the exposure shot area 40-A, the arrows 42a-A of the identification pattern 42-A arranged on the semiconductor element pattern 12-A in the inspection field of view, 42b-A is visually recognized. With this visual recognition, the position of the specific semiconductor element pattern 12B-A in the exposure shot area 40-A can be accurately estimated. The inspection visual field can be moved according to the identification pattern 42-A, and the specific semiconductor element pattern 12B-A can be reached in a short time.

  Further, in order to inspect the specific semiconductor element pattern 12C-A in the exposure shot region 40-A, the arrows 43a-A, 43b of the identification pattern 43-A arranged on the semiconductor element pattern 12-A in the inspection field of view. -A is visually recognized. With this visual recognition, the position of the specific semiconductor element pattern 12C-A in the exposure shot region 40-A can be accurately estimated. The inspection visual field is moved according to the identification pattern 43-A, and the specific semiconductor element pattern 12C-A can be reached in a short time.

  In the present embodiment, as in the first embodiment, an automatic inspection apparatus similar to that in FIG. 6 is used to automatically inspect instead of performing a defect inspection by a user using a microscope. Anyway.

  Also in this embodiment, similarly to the first embodiment, a plurality of semiconductor elements are formed on one main surface of the semiconductor substrate through the steps (steps S21 to S34) shown in FIG. . Each semiconductor element is formed with an identification pattern corresponding to the reticle identification pattern 41, 42, 43 and a corner recognition pattern corresponding to the corner recognition pattern 31 of the reticle.

  As described above, according to the present embodiment, the specific semiconductor element patterns 12A-A, 12B-A, and 12C-A, which are transfer patterns on which the specific semiconductor element patterns 12A, 12B, and 12C of the reticle 40 are exposed, are inspected. In this case, it is possible to accurately select an exposure shot area to be inspected. Even when a large number of semiconductor element patterns 12-A are formed, the specific semiconductor element patterns 12A-A, 12B-A, and 12C-A can be found easily and accurately in a short time, and inspection can be performed very efficiently. It can be carried out.

(Fourth embodiment)
In this embodiment, similar to the third embodiment, a plurality of specific semiconductor element patterns to be observed at the time of inspection of a transfer pattern are provided on a reticle.
FIG. 19 shows one reticle according to the fourth embodiment. FIG. 20 shows one exposure shot area transferred to the photo resist on the semiconductor substrate by this reticle.
In FIG. 19, as the identification pattern 13, an L-shaped identification pattern 13 composed of straight lines shown in FIG. 2 is illustrated. Similarly, in FIG. 20, as the identification pattern 13 -A, an L-shaped identification pattern 13 -A composed of straight lines corresponding to the L-shaped identification pattern 13 composed of straight lines shown in FIG. 2 is illustrated. .

  As shown in FIG. 19, the reticle 50 according to the present embodiment includes, for example, 11 × 11 (121) semiconductor element patterns 12 (specific semiconductor element patterns) as in the reticle 11 of FIG. 1 of the first embodiment. 12A.) Is formed. In the reticle 50, the semiconductor element patterns 12 to be observed at the time of inspection of the transfer pattern are provided at a plurality of places, for example, three places, and are designated as specific semiconductor element patterns 12A, 12B, and 12C. In this embodiment, the observation order when transferred to the photo resist on the semiconductor substrate is defined in advance in the order of the specific semiconductor element patterns 12A, 12B, and 12C. That is, after first inspecting the specific semiconductor element pattern 12A, the specific semiconductor element pattern 12B is inspected, and then the specific semiconductor element pattern 12C is inspected sequentially.

Each semiconductor element pattern 12 is formed with an identification pattern 13 similar to that of the first embodiment at the periphery thereof. The identification pattern 13 is an index indicating the direction and distance from the semiconductor element pattern 12 to the specific semiconductor element pattern 12A.
Further, in the present embodiment, among the 121 semiconductor element patterns 12 of the reticle 50, the specific semiconductor element patterns 12A and 12B, the predetermined semiconductor element patterns 12A and 12B, and the predetermined semiconductor element patterns 12B and 12C existing between the specific semiconductor element patterns 12B and 12C. In addition to the identification pattern 13, path display patterns 51 </ b> A and 51 </ b> B are formed on the semiconductor element pattern 12.

Attention is paid to a predetermined semiconductor element pattern 12 (referred to as a semiconductor element pattern 12a in FIG. 19) shown in a circle C1 in FIG.
In a region R1 surrounded by a one-dot chain line in FIG. 19, a predetermined number (not shown) that forms a path connecting the specific semiconductor element pattern 12A and the specific semiconductor element pattern 12B among the 121 semiconductor element patterns 12 of the reticle 50. In the example, eight semiconductor element patterns 12 are included. The semiconductor element pattern 12a is one of the semiconductor element patterns 12 in the region R1. In each semiconductor element pattern 12 forming the path, a path display pattern 51A is formed in addition to the identification pattern 13 for finding the specific semiconductor element pattern 12A. The path display pattern 51A clearly shows the path from the semiconductor element pattern 12A to the specific semiconductor element pattern 12B.

Attention is paid to a predetermined semiconductor element pattern 12 (referred to as a semiconductor element pattern 12b in FIG. 19) shown in a circle C2 in FIG.
In a region R2 surrounded by a one-dot chain line in FIG. 19, a predetermined number (not shown) that forms a path connecting the specific semiconductor element pattern 12B and the specific semiconductor element pattern 12C among the 121 semiconductor element patterns 12 of the reticle 50. In the example, two semiconductor element patterns 12 are included. The semiconductor element pattern 12b is one of the semiconductor element patterns 12 in the region R2. In each semiconductor element pattern 12 forming the path, a path display pattern 51B is formed in addition to the identification pattern 13 for finding the specific semiconductor element pattern 12A. The path display pattern 51B clearly shows the path from the semiconductor element pattern 12B to the specific semiconductor element pattern 12C.

Here, the path display pattern 51 </ b> A is configured by, for example, a plurality (four in the illustrated example) of rectangular dots 52 a arranged in parallel at two opposite sides of the peripheral portion of the semiconductor element pattern 12. The path display pattern 51B has a shape different from the rectangular dots 52a, for example, a plurality of (four in the illustrated example) diagonal dots 52b arranged in parallel at two opposite sides of the periphery of the semiconductor element pattern 12. Composed.
The route display patterns 51A and 51B may be preferably formed in, for example, a single arrow shape other than the shape in which the plurality of dots are arranged in parallel.

Similar to FIGS. 3 and 4 of the first embodiment, a plurality of exposure shot areas are formed by performing reduction projection exposure on the photoresist on the semiconductor substrate a plurality of times and developing using the reticle 50. To do. FIG. 20 shows the state of one exposure shot area as in FIG. 15 of the second embodiment.
In the exposure shot region 50-A, 121 semiconductor element patterns 12-A to which 121 semiconductor element patterns 12 of the reticle 50 are transferred are formed. In the exposure shot region 50-A, specific semiconductor element patterns 12A-A, 12B-A, and 12C-A to which the specific semiconductor element patterns 12A, 12B, and 12C are transferred are formed.

  In the exposure shot region 50-A, an identification pattern 13-A in which the identification pattern 13 of the reticle 50 is transferred is formed at the peripheral edge of each semiconductor element pattern 12-A. Furthermore, among the 121 semiconductor element patterns 12-A, the specific semiconductor element patterns 12A-A and 12B-A, the specific semiconductor element patterns 12A-A and 12B-A, and the specific semiconductor element patterns 12B-A and 12C. In addition to the identification pattern 13-A, path display patterns 51-A and 51-B are formed in the predetermined semiconductor element pattern 12-A existing between −A.

Attention is focused on a predetermined semiconductor element pattern 12-A (referred to as semiconductor element pattern 12a-A in FIG. 20) shown in a circle C1 in FIG.
In the region R1 surrounded by the alternate long and short dash line in FIG. 20, a predetermined number of paths that connect the specific semiconductor element pattern 12A-A and the specific semiconductor element pattern 12B-A among the 121 semiconductor element patterns 12-A are formed. The semiconductor element pattern 12-A (eight in the illustrated example) is included. The semiconductor element pattern 12a-A is one of the semiconductor element patterns 12-A in the region R1. In each semiconductor element pattern 12-A that forms the path, a path display pattern 51A-A in which the path display pattern 51A of the reticle 50 is transferred is formed on the periphery thereof. The route display pattern 51A-A includes a plurality of rectangular dots 52a-A arranged in parallel.

Similarly, attention is focused on a predetermined semiconductor element pattern 12-A (referred to as semiconductor element pattern 12b-A in FIG. 20) shown in a circle C2 in FIG.
In the region R2 surrounded by the alternate long and short dash line in FIG. 20, among the 121 semiconductor element patterns 12-A, a predetermined number forming a path connecting the specific semiconductor element pattern 12B-A and the specific semiconductor element pattern 12C-A. The semiconductor element pattern 12-A (two in the illustrated example) is included. The semiconductor element pattern 12b-A is one of the semiconductor element patterns 12-A in the region R2. In each semiconductor element pattern 12-A that forms the path, a path display pattern 51B-A in which the path display pattern 51B of the reticle 50 is transferred is formed on the periphery thereof. The route display pattern 51B-A includes a plurality of diagonal dots 52b-A arranged in parallel.

  In the present embodiment, the case where three specific semiconductor element patterns 12A-A, 12B-A, and 12C-A are provided is exemplified, but a larger number, for example, N (N is an integer satisfying N ≧ 4). The same applies to the case where the specific semiconductor element pattern is provided. That is, in this case, the observation order of N specific semiconductor element patterns is defined in advance, and the identification pattern is for detecting the first specific semiconductor element pattern in the observation order. The reticle has a path display pattern indicating a path from the Mth specific semiconductor element pattern (M is an integer satisfying 1 ≦ M ≦ N−1) to the M + 1th specific semiconductor element pattern.

A case where the specific semiconductor element patterns 12A-A, 12B-A, and 12C-A formed on the semiconductor substrate are inspected will be described. In this embodiment, inspection is performed in the order of 12A-A, 12B-A, and 12C-A.
First, when inspecting the specific semiconductor element pattern 12A-A in the exposure shot region 50-A, the identification pattern 13-A arranged on the semiconductor element pattern 12-A in the inspection field of the microscope is visually recognized. The position of the specific semiconductor element pattern 12A-A in the exposure shot area 50-A can be accurately estimated by the visually recognized identification pattern 13-A. The inspection visual field can be moved according to the identification pattern 13-A, and the specific semiconductor element pattern 12A-A can be reached in a short time.

  After inspecting the specific semiconductor element pattern 12A-A, the specific semiconductor element pattern 12B-A is subsequently inspected. In this case, the path display pattern 51A-A formed at the peripheral edge of the specific semiconductor element pattern 12A-A is used as a starting point to trace the adjacent semiconductor element pattern 12-A indicated by the path display pattern 51A-A. Further, the adjacent semiconductor element pattern 12-A indicated by the path display pattern 51A-A formed in the adjacent semiconductor element pattern 12-A is traced. In the example of FIG. 20, following the path display pattern 51A-A, the semiconductor device pattern 12-A advances downward from the specific semiconductor device pattern 12A-A by three semiconductor device patterns 12-A, and further advances to the right by six semiconductor device patterns 12-A. The specific semiconductor element pattern 12B-A is reached by only proceeding. As described above, by tracing the semiconductor element pattern 12-A according to the path display pattern 51A-A and moving the inspection visual field of the microscope, the specific semiconductor element pattern 12B-A can be easily reached in a short time. .

  After the specific semiconductor element pattern 12B-A is inspected, the specific semiconductor element pattern 12C-A is subsequently inspected. In this case, starting from the path display pattern 51B-A formed at the peripheral edge of the specific semiconductor element pattern 12B-A, the semiconductor element pattern 12-A indicated by the path display pattern 51B-A is traced. Further, the adjacent semiconductor element pattern 12-A indicated by the path display pattern 51B-A formed in the adjacent semiconductor element pattern 12-A is traced. In the example of FIG. 20, the specific semiconductor element pattern 12C-A is reached by following the path display pattern 51B-A and proceeding downward from the specific semiconductor element pattern 12B-A by two semiconductor element patterns 12-A. As described above, the specific semiconductor element pattern 12C-A can be easily reached in a short time by tracing the semiconductor element pattern 12-A according to the path display pattern 51B-A and moving the inspection visual field of the microscope. .

  Also in the present embodiment, similarly to the first embodiment, the steps (steps S21 to S34) shown in FIG. 8 are performed. Thus, for example, as shown in FIG. 21, in the semiconductor element region 50-B corresponding to the exposure shot region 50-A in FIG. 20, a plurality of the main surfaces corresponding to the semiconductor element pattern 12 of the reticle 50 are formed on one main surface. Individual semiconductor elements 12-B are formed. Here, the specific semiconductor elements 12A-B, 12B-B, and 12C-B are formed corresponding to the specific semiconductor element patterns 12A, 12B, and 12C of the reticle 50. In each semiconductor element 12-B, each identification pattern 13B corresponding to the identification pattern 13 of the reticle 50 is formed.

FIG. 22 shows only the specific semiconductor elements 12A-B, 12B-B, and 12C-B and the semiconductor element 12-B on which the path display patterns 51A-B and 51B-B described later are formed, extracted from FIG. .
Each semiconductor element 12-B that forms a path connecting the specific semiconductor element 12A-B and the specific semiconductor element 12B-B has a path display pattern 51A- in which the path display pattern 51A of the reticle 50 is transferred to the peripheral edge thereof. B is formed. The route display patterns 51A-B are configured by a plurality of rectangular dots 52a-B arranged in parallel.
Each semiconductor element 12-B that forms a path connecting the specific semiconductor element 12B-B and the specific semiconductor element 12C-B has a path display pattern 51B- in which the path display pattern 51B of the reticle 50 is transferred to the periphery. B is formed. The route display pattern 51B-B includes a plurality of diagonal dots 52b-B arranged in parallel.

FIG. 23A shows an enlarged view of the area shown in the circle C1 in FIG. 21, and FIG. 23B shows an enlarged view of the area shown in the circle C2 in FIG.
In FIG. 23A, the identification pattern 13-B is formed between the bonding pad 16Bb and the first region 16B-1 in the second region 16B-2, for example, in the scribe region 16B near the corner of the semiconductor element 12-B. It is provided in an empty area 19a existing between the boundary. In the scribe region 16B near the two opposing sides of the semiconductor element 12-B, the path display pattern 51A-B is, for example, between the in-scribe pattern 16Ba and the boundary between the second region 16B-2 in the first region 16B-1. Is formed in a free space 19c existing in

  In FIG. 23B, the identification pattern 13-B is formed between the bonding pad 16Bb and the first region 16B-1 in the second region 16B-2, for example, in the scribe region 16B near the corner of the semiconductor element 12-B. It is provided in an empty area 19a existing between the boundary. The route display pattern 51B-B is, for example, between the in-scribe pattern 16Ba and the boundary of the second region 16B-2 in the first region 16B-1 in the scribe region 16B near the two opposite sides of the semiconductor element 12-B. Is formed in a free space 19c existing in

A case where the specific semiconductor elements 12A-B, 12B-B, and 12C-B formed on the semiconductor substrate are inspected will be described. In this embodiment, inspection is performed in the order of 12A-B, 12B-B, and 12C-B.
First, when the specific semiconductor element 12A-B in the semiconductor element region 50-B is inspected, the identification pattern 13-B arranged on the semiconductor element 12-B in the inspection field of the microscope is visually recognized. The position of the specific semiconductor element 12A-B in the semiconductor element region 50-B can be accurately estimated by the visually recognized identification pattern 13-B. The inspection visual field can be moved according to the identification pattern 13-B, and the specific semiconductor element 12A-B can be reached in a short time.

  After the specific semiconductor element 12A-B is inspected, the specific semiconductor element 12B-B is subsequently inspected. In this case, the path display pattern 51A-B formed at the peripheral edge of the specific semiconductor element 12A-B is used as a starting point to trace the adjacent semiconductor element 12-A indicated by the path display pattern 51A-B. Further, the adjacent semiconductor element 12-B indicated by the path display pattern 51A-B formed in the adjacent semiconductor element 12-B is traced. In the example of FIG. 21, following the path display pattern 51A-B, the semiconductor device 12A-B progresses downward from the specific semiconductor device 12A-B by three semiconductor devices 12-B, and further advances to the right by six semiconductor devices 12-B. To the specific semiconductor element 12B-B. As described above, the specific semiconductor element 12B-B can be easily reached in a short time by tracing the semiconductor element 12-B according to the path display pattern 51A-B and moving the inspection visual field of the microscope.

  After inspecting the specific semiconductor element 12B-B, the specific semiconductor element 12C-B is subsequently inspected. In this case, starting from the path display pattern 51B-B formed at the peripheral edge of the specific semiconductor element 12B-B, the adjacent semiconductor element 12-B indicated by the path display pattern 51B-B is traced. Further, the adjacent semiconductor element 12-B indicated by the path display pattern 51B-B formed in the adjacent semiconductor element 12-B is traced. In the example of FIG. 21, the specific semiconductor element 12C-B is reached by following the path display pattern 51B-B and proceeding downward from the specific semiconductor element 12B-B by two semiconductor elements 12-B. As described above, the specific semiconductor element 12C-B can be easily reached in a short time by tracing the semiconductor element 12-B according to the path display pattern 51B-B and moving the inspection visual field of the microscope.

  In the present embodiment, the case where three specific semiconductor elements 12A-B, 12B-B, and 12C-B are provided is illustrated, but a larger number, for example, N (N is an integer satisfying N ≧ 4). The same applies when a specific semiconductor element is provided. That is, in this case, the observation order of the N specific semiconductor elements is defined in advance, and the identification pattern is for detecting the first specific semiconductor element having the first observation order. On the semiconductor substrate, a path display pattern indicating a path from the Mth specific semiconductor element (M is an integer satisfying 1 ≦ M ≦ N−1) to the M + 1th specific semiconductor element is formed.

  Also, in this embodiment, as in the first embodiment, an automatic inspection apparatus similar to that in FIG. 6 is used to automatically perform inspection instead of performing visual defect inspection using a microscope. Anyway.

  As described above, according to the present embodiment, the specific semiconductor element patterns 12A-A, 12B-A, and 12C-A, which are transfer patterns on which the specific semiconductor element patterns 12A, 12B, and 12C of the reticle 50 are exposed, are obtained. The inspection efficiency is improved when sequentially inspecting in order. That is, even when a large number of semiconductor element patterns 12-A are formed, the specific semiconductor element patterns 12A-A, 12B-A, and 12C-A can be found easily and accurately in a short time, and inspection can be performed very efficiently. It can be carried out. Further, in the present embodiment, by providing a path display pattern only in a predetermined semiconductor element pattern 12-A between specific semiconductor element patterns, a more efficient semiconductor device can be designed, and pattern misidentification at the inspection stage is possible. Is reduced.

  Hereinafter, various aspects will be collectively described as additional notes.

(Appendix 1) A step of forming a photoresist layer on one main surface of a semiconductor substrate;
A plurality of semiconductor element patterns, and an identification pattern indicating a direction and a distance from the semiconductor element pattern to at least one of the plurality of semiconductor element patterns and a specific semiconductor element pattern to be observed. A step of performing an exposure process on the photoresist layer using a reticle having
Developing the photoresist layer;
And a step of detecting the specific semiconductor element pattern using the identification pattern as an index.

  (Additional remark 2) The said reticle has the said pattern for identification in the peripheral part of the said semiconductor element pattern, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.

  (Supplementary Note 3) The reticle further includes a corner recognition pattern indicating a direction and a distance from the semiconductor element pattern to a corner closest to the semiconductor element pattern among the four corners of the reticle. The manufacturing method of a semiconductor device according to the supplementary note 1 or 2, which is characterized by the following.

  (Additional remark 4) The said reticle has the said pattern for corner recognition in the peripheral part of the said semiconductor element pattern, The manufacturing method of the semiconductor device of Additional remark 3 characterized by the above-mentioned.

(Supplementary Note 5) N specific semiconductor element patterns (N is an integer satisfying N ≧ 2) are provided, and an observation order of each specific semiconductor element pattern is defined in advance,
The identification pattern is for detecting the specific semiconductor element pattern whose observation order is first,
The reticle has a path display pattern indicating a path from the specific semiconductor element pattern whose observation order is Mth (M is an integer satisfying 1 ≦ M ≦ N−1) to the M + 1th specific semiconductor element pattern. And
A step of sequentially detecting N-1 specific semiconductor element patterns using the path display pattern after detecting the first specific semiconductor element pattern having the first observation order using the identification pattern as an index; The method for manufacturing a semiconductor device according to any one of appendices 1 to 4, further comprising:

(Appendix 6) A plurality of semiconductor element patterns;
An identification pattern indicating a direction and a distance from the semiconductor element pattern to at least one of the plurality of semiconductor element patterns and a specific semiconductor element pattern to be observed. Reticle.

  (Appendix 7) On one main surface, a plurality of semiconductor elements, and directions and distances from the semiconductor elements to at least one of the plurality of semiconductor elements and a specific semiconductor element to be observed A semiconductor substrate comprising an identification pattern shown.

  (Additional remark 8) The semiconductor pattern of Additional remark 7 characterized by the said pattern for identification being formed in the peripheral part of the said semiconductor element.

  (Supplementary note 9) The semiconductor substrate according to Supplementary note 7 or 8, wherein a semiconductor element group is configured by a plurality of the semiconductor elements, and a plurality of the semiconductor element groups are arranged adjacent to each other.

  (Supplementary Note 10) A corner recognition pattern further indicating a direction and a distance from the semiconductor element in the semiconductor element group to a corner closest to the semiconductor element among the four corners of the semiconductor element group. The semiconductor substrate according to appendix 9, wherein:

  (Additional remark 11) The semiconductor substrate of Additional remark 10 characterized by the said corner part recognition pattern being formed in the peripheral part of the said semiconductor element.

(Supplementary Note 12) N specific semiconductor elements are provided (N is an integer satisfying N ≧ 2), and the observation order of the specific semiconductor elements is defined in advance.
The identification pattern is for detecting the specific semiconductor element whose observation order is first,
It has a path display pattern indicating a path from the specific semiconductor element whose observation order is Mth (M is an integer satisfying 1 ≦ M ≦ N−1) to the M + 1th specific semiconductor element. The semiconductor substrate according to any one of appendices 7 to 11.

1 SEM
2 Recording unit 3 Recognition unit 4 Calculation unit 5 Database 6 Inspection visual field adjustment unit 7 Control unit 11, 30, 30a, 40 Reticle 11-A, 30-A, 40-A Exposure shot region 11-B, 50-B Semiconductor element Regions 12, 12a, 12b, 12c, 12d, 12-A, 12a-A, 12b-A, 12c-A, 12d-A, 12-B, 12a-B, 12b-B, 12c-B, 12d-B Semiconductor element patterns 12A, 12B, 12C, 12A-A, 12B-A, 12C-A, 12A-B Specific semiconductor element patterns 13, 41 to 43, 13-A, 41-A to 43-A Identification patterns 13a, 13b, 13a-A, 13b-A, 13a-B, 13b-B, 41a, 41b, 42a, 42b, 43a, 43b, 41a-A, 41b-A, 42a-A, 42b-A, 43a A, 43b-A
16 areas 16-A, 18, 18-A scribe areas 17, 17-A shot recognition patterns 19a, 19b, 19c, 19d empty areas 31, 31-A, 32 corner recognition patterns 31a, 31a-A, 31b , 31b-A, 32a, 32b Line segments 51A, 51B, 51A-A, 51B-A, 51A-B, 51B-B Route display patterns 52a, 52a-A, 52a-B Sectional dots 52b, 52b-A, 52b-B Diagonal dots

Claims (6)

Forming a photoresist layer on one main surface of the semiconductor substrate;
A plurality of semiconductor element patterns, and an identification pattern indicating a direction and a distance from the semiconductor element pattern to at least one of the plurality of semiconductor element patterns and a specific semiconductor element pattern to be observed. A step of performing an exposure process on the photoresist layer using a reticle having
Developing the photoresist layer;
And a step of detecting the specific semiconductor element pattern using the identification pattern as an index.   The reticle further includes a corner recognition pattern indicating a direction and a distance from the semiconductor element pattern to a corner closest to the semiconductor element pattern among the four corners of the reticle. Item 14. A method for manufacturing a semiconductor device according to Item 1. N specific semiconductor element patterns (N is an integer satisfying N ≧ 2) are provided, and an observation order of the specific semiconductor element patterns is defined in advance.
The identification pattern is for detecting the specific semiconductor element pattern whose observation order is first,
The reticle has a path display pattern indicating a path from the specific semiconductor element pattern whose observation order is Mth (M is an integer satisfying 1 ≦ M ≦ N−1) to the M + 1th specific semiconductor element pattern. And
A step of sequentially detecting N-1 specific semiconductor element patterns using the path display pattern after detecting the first specific semiconductor element pattern having the first observation order using the identification pattern as an index; The method for manufacturing a semiconductor device according to claim 1, further comprising: A plurality of semiconductor element patterns;
An identification pattern indicating a direction and a distance from the semiconductor element pattern to at least one of the plurality of semiconductor element patterns and a specific semiconductor element pattern to be observed. Reticle. On one main surface, a plurality of semiconductor elements,
A semiconductor substrate comprising: an identification pattern indicating a direction and a distance from the semiconductor element to at least one of the plurality of semiconductor elements and a specific semiconductor element to be observed .   6. The semiconductor substrate according to claim 5, wherein the identification pattern is formed on a peripheral portion of the semiconductor element.

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