JP2011135278A - Operational amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an operational amplifier superior in jitter characteristics. <P>SOLUTION: The operational amplifier includes a first differential amplifier PA which contains a first PMOS transistor pair of PM6 and PM7 in which each gate is input with a differential input signal, a second differential amplifier NA which contains a first NMOS transistor pair of NM13 and NM14 in which each gate is input with a differential input signal, an in-phase component detection unit 1 which detects an in-phase component of the differential input signal, a high frequency component removing part 2 which removes a high frequency component from the in-phase component, and a control signal generation unit 3 which generates a control signal that stops operation of the first differential amplifier PA if a common mode voltage of the differential input signal is higher than a first reference voltage, but stops operation of the second differential amplifier NA if the common mode voltage is lower than a second reference voltage (where, the second reference voltage is lower than the first reference voltage). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an operational amplifier, and more particularly to a rail-to-rail operational amplifier.

  A rail-to-rail operational amplifier that can be used as an input common mode voltage (input common-mode voltage) from the vicinity of the low potential power supply voltage VSS to the vicinity of the high potential power supply voltage VDD is known. For example, Patent Document 1 discloses a rail-to-rail operational amplifier including a differential amplifier circuit having a PMOS input pair and a differential amplifier circuit having an NMOS input pair.

  In such a rail-to-rail operational amplifier, when the input common mode voltage is on the low potential power supply voltage VSS side, a differential amplifier circuit mainly having a PMOS input pair operates, and the input common mode voltage is In the case of the high potential power supply voltage VDD side, a differential amplifier circuit mainly having an NMOS input pair operates. That is, a differential amplifier circuit having a PMOS input pair and a differential amplifier circuit having an NMOS input pair operate in a complementary manner according to the input common mode voltage.

JP-A-6-85570

  However, when the input common mode voltage is close to the low potential power supply voltage VSS, the operation of the differential amplifier circuit having the NMOS input pair becomes unstable. On the other hand, when the input common mode voltage is near the high potential power supply voltage VDD, the operation of the differential amplifier circuit having the PMOS input pair becomes unstable. Therefore, when the input common mode voltage is in the vicinity of the low potential power supply voltage VSS or the high potential power supply voltage VDD, there is a problem that noise of the output signal, that is, jitter increases.

An operational amplifier according to the present invention includes:
A first differential amplifier having a first PMOS transistor pair with a differential input signal input to each gate;
A second differential amplifier having a first NMOS transistor pair to which the differential input signal is input to each gate;
An in-phase component detector for detecting an in-phase component of the differential input signal;
A high-frequency component removing unit that removes a high-frequency component from the in-phase component;
When the common mode voltage of the differential input signal is higher than the first reference voltage based on the common-mode component from which the high frequency component has been removed, the operation of the first differential amplifier is stopped, and the common mode voltage is A control signal generator for generating a control signal for stopping the operation of the second differential amplifier when the voltage is lower than a reference voltage (however, the second reference voltage is lower than the first reference voltage). Is.

  In the present invention, when the common mode voltage of the differential input signal is higher than the first reference voltage based on the in-phase component from which the high frequency component has been removed, the operation of the first differential amplifier is stopped, and the common mode voltage is When lower than the reference voltage, the operation of the second differential amplifier is stopped. Therefore, an operational amplifier having excellent jitter characteristics can be provided.

  According to the present invention, an operational amplifier having excellent jitter characteristics can be provided.

2 is a block diagram of an operational amplifier according to the first embodiment. FIG. 3 is a circuit diagram of an operational amplifier according to an example of the first embodiment. FIG. It is a circuit diagram of the operational amplifier which concerns on a comparative example. It is a graph which compares and shows the jitter characteristic of the operational amplifier which concerns on an Example and a comparative example.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. However, the present invention is not limited to the following embodiment. In addition, for clarity of explanation, the following description and drawings are simplified as appropriate.

(Embodiment 1)
An operational amplifier according to a first embodiment of the present invention will be described with reference to FIG. 2 is a block diagram of an operational amplifier according to the first embodiment. FIG. As shown in FIG. 1, the operational amplifier according to the first embodiment is a rail-to-rail operational amplifier including a PMOS input differential amplifier circuit PA and an NMOS input differential amplifier circuit NA. Furthermore, the operational amplifier according to the first embodiment includes an in-phase component detection unit 1, a high frequency component removal unit 2, and a control signal generation unit 3.

  Differential input signals INP and INN are input to the PMOS input differential amplifier circuit PA and the NMOS input differential amplifier circuit NA, respectively. Further, the differential input signals INP and INN are also input to the in-phase component detector 1, and the in-phase component detector of the differential input signal is detected. The high frequency component of the input common mode voltage is removed by the high frequency component removing unit 2.

  A control signal for controlling operations of the PMOS input differential amplifier circuit PA and the NMOS input differential amplifier circuit NA is generated by the control signal generator 3 based on the in-phase component from which the high frequency component has been removed. Specifically, when the input common mode voltage approaches the high potential power supply voltage VDD and becomes larger than the predetermined first reference signal by this control signal, the operation of the PMOS input differential amplifier circuit PA is stopped. In addition, when the input common mode voltage approaches the low potential power supply voltage VSS and becomes smaller than the predetermined second reference signal by this control signal, the operation of the NMOS input differential amplifier circuit NA is stopped. Note that both the PMOS input differential amplifier circuit PA and the NMOS input differential amplifier circuit NA operate between the first and second reference signals.

  FIG. 2 is a circuit diagram of an operational amplifier according to an example of the first embodiment. The operational amplifier includes a constant current source CS, NMOS transistors NM1 to NM18, PMOS transistors PM1 to PM17, switches SW1 to SW4, resistors R1 to R4, capacitors C1 and C2, hysteresis comparators X1 and X4, inverters X2, X3, and X5. X8 is provided. For example, the operational amplifier generates a single phase clock signal from the differential clock signal. First, the connection relationship of each component will be described.

  The drain of the NMOS transistor NM1 is connected to the constant current source CS, and the source is connected to the low potential power supply (voltage VSS). The gate of the NMOS transistor NM1 is connected to the gate of the NMOS transistor NM2 and to the drain of the NMOS transistor NM1. That is, the NMOS transistor NM1 and the NMOS transistor NM2 form a current mirror. The source of the NMOS transistor NM2 is connected to the low potential power supply (voltage VSS), and the drain is connected to the drain of the PMOS transistor PM1.

  The source of the PMOS transistor PM1 is connected to a high potential power supply (voltage VDD). The gate of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2 and to the drain of the PMOS transistor PM1. That is, the PMOS transistor PM1 and the PMOS transistor PM2 form a current mirror. The source of the PMOS transistor PM2 is connected to a high potential power supply (voltage VDD). The drain of the PMOS transistor PM2 is connected to the sources of the PMOS transistors PM3 and PM4 connected in parallel with each other. This connection node is the node N1.

  The drains of the PMOS transistors PM3 and PM4 are connected to one end of the resistor R1. This connection node is the node N2. Differential input signals INP and INN are input to the gates of the PMOS transistors PM3 and PM4, respectively. The other end of the resistor R1 is connected to a low potential power supply (voltage VSS). As shown in FIG. 2, the PMOS transistors PM3 and PM4 and the resistor R1 constitute an in-phase component detection unit 1a corresponding to the in-phase component detection unit 1 of FIG.

  Further, one end of a resistor R2 is connected to the node N2. The other end of the resistor R2 is connected to one end of the capacitor C1. This connection node is the node N3. The other end of the capacitor C1 is connected to a low potential power supply (voltage VSS). As shown in FIG. 2, the resistor R2 and the capacitor C1 constitute a high frequency component removal unit 2a corresponding to the high frequency component removal unit 2 of FIG.

  The input of the hysteresis comparator X1 is connected to the node N3. The output signal from the hysteresis comparator X1 is output as the enable signal ENP via the inverter X2. Further, an enable signal ENBP whose polarity is inverted from that of the enable signal ENP is output via the inverter X3. As shown in FIG. 2, the hysteresis comparator X1 and the inverters X2 and X3 constitute a control signal generator 3a corresponding to the control signal generator 3 of FIG.

  The source of the PMOS transistor PM5 is connected to the high potential power supply (voltage VDD), and the drain is connected to the sources of the PMOS transistors PM6 and PM7 constituting the PMOS input pair. This connection node is the node N4. The gate of the PMOS transistor PM5 is connected to the gate of the PMOS transistor PM1 via the switch SW2. That is, the PMOS transistor PM5 is a constant current source transistor that forms a current mirror with the PMOS transistor PM1 when the switch SW2 is on. The gate of the PMOS transistor PM5 is connected to a high potential power supply (voltage VDD) via the switch SW1. Therefore, when the switch SW1 is on, the source-gate voltage of the PMOS transistor PM5 becomes equal, and the PMOS transistor PM5 is turned off.

  More specifically, the switches SW1 and SW2 are PMOS transistors connected in series. The source of the switch SW1 is connected to the high potential power supply (voltage VDD), and the drain is connected to the source of the switch SW2. The gate of the PMOS transistor PM5 is connected between the drain of the switch SW1 and the source of the switch SW2. The drain of the switch SW2 is connected to the gate of the PMOS transistor PM1. An enable signal ENP and an enable signal ENBP are input to the gates of the switches SW1 and SW2, respectively. Therefore, the switches SW1 and SW2 are turned on and off in a complementary manner.

  The drain of the PMOS transistor PM6 constituting the PMOS input pair is connected to the drain of the NMOS transistor NM3. The source of the NMOS transistor NM3 is connected to a low potential power supply (voltage VSS). On the other hand, the drain of the PMOS transistor PM7 constituting the PMOS input pair is connected to the drain of the NMOS transistor NM4. The source of the NMOS transistor NM4 is connected to a low potential power supply (voltage VSS).

  The gate of the NMOS transistor NM3 is connected to the gate of the NMOS transistor NM6 and to the drain of the NMOS transistor NM3. That is, the NMOS transistor NM3 and the NMOS transistor NM6 form a current mirror. The source of the NMOS transistor NM6 is connected to the low potential power supply (voltage VSS), and the drain is connected to the drain of the PMOS transistor PM9.

  The gate of the NMOS transistor NM4 is connected to the gate of the NMOS transistor NM5 and to the drain of the NMOS transistor NM4. That is, the NMOS transistors NM4 and NM5 form a current mirror. The source of the NMOS transistor NM5 is connected to the low potential power supply (voltage VSS), and the drain is connected to the drain of the PMOS transistor PM8.

  The sources of the PMOS transistors PM8 and PM9 are both connected to a high potential power supply (voltage VDD). The gate of the PMOS transistor PM8 is connected to the gate of the PMOS transistor PM8 and to the drain of the PMOS transistor PM8. That is, the PMOS transistors PM8 and PM9 constitute a current mirror. The source of the PMOS transistor PM9 is connected to a high potential power supply (voltage VDD). An output signal of the PMOS input differential amplifier circuit PA is output from a connection node N5 between the drain of the PMOS transistor PM9 and the drain of the NMOS transistor NM6.

  On the other hand, the gate of the NMOS transistor NM1 is also connected to the gate of the NMOS transistor NM7. That is, the NMOS transistors NM1 and NM7 form a current mirror. The source of the NMOS transistor NM7 is connected to the low potential power supply (voltage VSS), and the drain is connected to the drain of the PMOS transistor PM10.

  The source of the PMOS transistor PM10 is connected to a high potential power supply (voltage VDD). The gate of the PMOS transistor PM10 is connected to the gate of the PMOS transistor PM11 and is connected to the drain of the PMOS transistor PM10. That is, the PMOS transistors PM10 and PM11 constitute a current mirror. The source of the PMOS transistor PM11 is connected to a high potential power supply (voltage VDD). The drain of the PMOS transistor PM11 is connected to the drain of the NMOS transistor NM8.

  The source of the NMOS transistor NM8 is connected to a low potential power supply (voltage VSS). The gate of the NMOS transistor NM8 is connected to the gate of the NMOS transistor NM9 and to the drain of the NMOS transistor NM8. That is, the NMOS transistors NM8 and NM9 form a current mirror. The source of the NMOS transistor NM9 is connected to a low potential power supply (voltage VSS). The drain of the NMOS transistor NM9 is connected to the sources of the NMOS transistors NM10 and NM11 connected in parallel with each other. This connection node is the node N6.

  The drains of the NMOS transistors NM10 and NM11 are connected to one end of the resistor R3. This connection node is the node N7. Differential input signals INP and INN are input to the gates of the NMOS transistors NM10 and NM11, respectively. The other end of the resistor R3 is connected to a high potential power supply (voltage VDD). As shown in FIG. 2, the NMOS transistors NM10 and NM11 and the resistor R3 constitute an in-phase component detector 1b corresponding to the in-phase component detector 1 of FIG.

  Further, one end of a resistor R4 is connected to the node N7. The other end of the resistor R4 is connected to one end of the capacitor C2. This connection node is the node N8. The other end of the capacitor C2 is connected to a high potential power supply (voltage VDD). As shown in FIG. 2, the resistor R4 and the capacitor C2 constitute a high frequency component removing unit 2b corresponding to the high frequency component removing unit 2 in FIG.

  The input of the hysteresis comparator X4 is connected to the node N8. The output signal from the hysteresis comparator X4 is output as an enable signal ENBN via the inverter X5. Further, the signal is output as an enable signal ENN whose polarity is inverted from that of the enable signal ENBN via the inverter X6. As shown in FIG. 2, the hysteresis comparator X4 and the inverters X5 and X6 constitute a control signal generator 3b corresponding to the control signal generator 3 of FIG.

  The source of the NMOS transistor NM12 is connected to the low potential power supply (voltage VSS), and the drain is connected to the sources of the NMOS transistors NM13 and NM14 constituting the NMOS input pair. This connection node is the node N9. The gate of the NMOS transistor NM12 is connected to the gate of the NMOS transistor NM8 via the switch SW4. That is, the NMOS transistor NM12 is a constant current source transistor that forms a current mirror with the NMOS transistor NM8 when the switch SW4 is on. The gate of the NMOS transistor NM12 is connected to the low potential power supply (voltage VSS) via the switch SW3. Therefore, when the switch SW3 is on, the source / gate voltages of the NMOS transistor NM12 are equal, and the NMOS transistor NM12 is off.

  More specifically, the switches SW3 and SW4 are NMOS transistors connected in series. The source of the switch SW3 is connected to the low potential power supply (voltage VSS), and the drain is connected to the source of the switch SW4. The gate of the NMOS transistor NM12 is connected between the drain of the switch SW3 and the source of the switch SW4. The drain of the switch SW4 is connected to the gate of the NMOS transistor NM8. An enable signal ENBN and an enable signal ENN are input to the gates of the switches SW3 and SW4, respectively. Therefore, the switches SW3 and SW4 are turned on and off in a complementary manner.

  The drain of the NMOS transistor NM13 constituting the NMOS input pair is connected to the drain of the PMOS transistor PM12. The source of the PMOS transistor PM12 is connected to a high potential power supply (voltage VDD). On the other hand, the drain of the NMOS transistor NM14 constituting the NMOS input pair is connected to the drain of the PMOS transistor PM13. The source of the PMOS transistor PM13 is connected to a high potential power supply (voltage VDD).

  The gate of the PMOS transistor PM12 is connected to the gate of the PMOS transistor PM14 and is connected to the drain of the PMOS transistor PM12. That is, the PMOS transistors PM12 and PM14 form a current mirror. The source of the PMOS transistor PM14 is connected to the high potential power supply (voltage VDD), and the drain is connected to the drain of the NMOS transistor NM15. The source of the NMOS transistor NM15 is connected to a low potential power supply (voltage VSS).

  The gate of the PMOS transistor PM13 is connected to the gate of the PMOS transistor PM15 and to the drain of the PMOS transistor PM13. That is, the PMOS transistors PM13 and PM15 form a current mirror. The source of the PMOS transistor PM15 is connected to the high potential power supply (voltage VDD), and the drain is connected to the drain of the NMOS transistor NM16. The source of the NMOS transistor NM16 is connected to a low potential power supply (voltage VSS).

  The gate of the NMOS transistor NM15 is connected to the gate of the NMOS transistor NM18 and to the drain of the NMOS transistor NM15. That is, the NMOS transistors NM15 and NM18 constitute a current mirror. The source of the NMOS transistor NM18 is connected to the low potential power supply (voltage VSS), and the drain is connected to the drain of the PMOS transistor PM17.

  The gate of the NMOS transistor NM16 is connected to the gate of the NMOS transistor NM17 and to the drain of the NMOS transistor NM16. That is, the NMOS transistors NM16 and NM17 form a current mirror. The source of the NMOS transistor NM17 is connected to the low potential power supply (voltage VSS), and the drain is connected to the drain of the PMOS transistor PM16.

  The sources of the PMOS transistors PM16 and PM17 are both connected to a high potential power supply (voltage VDD). The gate of the PMOS transistor PM16 is connected to the gate of the PMOS transistor PM17 and to the drain of the PMOS transistor PM16. That is, the PMOS transistors PM16 and PM17 constitute a current mirror. The source of the PMOS transistor PM17 is connected to a high potential power supply (voltage VDD). An output signal of the NMOS input differential amplifier circuit NA is output from a connection node N10 between the drain of the PMOS transistor PM17 and the drain of the NMOS transistor NM18.

  The output signal of the PMOS input differential amplifier circuit PA output from the node N5 and the output signal of the NMOS input differential amplifier circuit NA output from the node N10 are combined at the node N11. Then, an output signal OUT of the rail-to-rail operational amplifier is output via inverters X7 and X8 which are waveform shaping buffers.

  Next, the operation of the operational amplifier of FIG. 2 will be described. As described above, the differential input signals INP and INN are input to the gates of the PMOS transistors PM3 and PM4, respectively. As a result, the in-phase component (voltage corresponding to the input common mode voltage) of the differential input signals INP and INN is detected at the node N2. The voltage at the node N2 is determined by the product of the resistor R1 and the current flowing through the resistor R1. Here, the current flowing through the resistor R1 is equal to the current generated by the PMOS transistor PM2 functioning as a constant current source.

  The PMOS transistor PM2 normally operates in the saturation region. However, when the input common mode voltage of the differential input signals INP and INN approaches the high potential power supply voltage VDD, the voltage at the node N1 also approaches the high potential power supply voltage VDD, and the drain-source voltage of the PMOS transistor PM2 decreases. Therefore, the PMOS transistor PM2 operates in the linear region. In the linear region, the drain-source voltage dependency of the drain current of the PMOS transistor PM2 increases. Therefore, as the input common mode voltage approaches the high potential power supply voltage VDD, the drain current of the PMOS transistor PM2 rapidly decreases. Along with this, the voltage at the node N2 also drops rapidly.

  Here, since the voltage of the node N2 has a high frequency component generated by, for example, switching between the differential input signals INP and INN, the low pass filter composed of the resistor R2 and the capacitor C1, that is, the high frequency component removing unit 2a, It is necessary to remove high frequency components. The voltage at the node N3 from which this high frequency component has been removed becomes the input signal of the hysteresis comparator X1. When the voltage at the node N2 decreases, the voltage at the node N3 also decreases. When the voltage at the node N3 becomes lower than the first reference voltage of the hysteresis comparator X1, the enable signal ENP becomes L and the enable signal ENBP becomes H. Therefore, the switch SW1 is turned on, the switch SW2 is turned off, and the PMOS transistor PM5 that is a constant current source is turned off. That is, the operation of the PMOS input differential amplifier circuit PA is stopped. In FIG. 2, the operation of the PMOS input differential amplifier circuit PA is stopped by turning off the PMOS transistor PM5, which is a constant current source. However, the present invention is not limited to this.

  Here, by designing the potential of the node N1 to be higher than the potential of the node N4, when the input common mode voltage approaches the high potential power supply voltage VDD, the operation of the PMOS transistor PM5, which is a constant current source, is linear. The operation of the PMOS input differential amplifier circuit PA can be stopped before the operation in the region. Specifically, the W / L ratio (W: channel width, L: channel length) of the PMOS transistors PM3 and PM4 constituting the in-phase component detection unit 1a is set as the W / L ratio of the PMOS transistors PM6 and PM7 constituting the PMOS input pair. By making it smaller than the L ratio, the potential of the node N1 can be made higher than the potential of the node N4. Further, the potential of the node N1 can be made higher than the potential of the node N4 by making the size of the PMOS transistor PM2 larger than that of the PMOS transistor PM5 which is a constant current source.

  As described above, since the operation of the PMOS input differential amplifier circuit PA can be stopped before the operation of the PMOS transistor PM5, which is a constant current source, becomes the operation in the linear region, as seen in a comparative example described later. There is no increase in jitter. That is, jitter can be reduced.

  Similarly, differential input signals INP and INN are input to the gates of the NMOS transistors NM10 and NM11, respectively. As a result, the in-phase components of the differential input signals INP and INN are detected at the node N7. The voltage at the node N7 is determined by the product of the resistor R3 and the current flowing through the resistor R3. Here, the current flowing through the resistor R3 is equal to the current generated by the NMOS transistor NM9 functioning as a constant current source.

  The NMOS transistor NM9 normally operates in the saturation region. However, when the input common mode voltage of the differential input signals INP and INN approaches the low potential power supply voltage VSS, the voltage at the node N6 also approaches the low potential power supply voltage VSS, and the drain-source voltage of the NMOS transistor NM9 decreases. Therefore, the NMOS transistor NM9 operates in the linear region. In the linear region, the drain-source voltage dependency of the drain current of the NMOS transistor NM9 increases. Therefore, as the input common mode voltage approaches the low potential power supply voltage VSS, the drain current of the NMOS transistor NM9 rapidly decreases. Along with this, the voltage at the node N7 also rises rapidly.

  Here, since the voltage at the node N7 has a high-frequency component, it is necessary to remove the high-frequency component by a low-pass filter composed of the resistor R4 and the capacitor C2, that is, the high-frequency component removing unit 2b. The voltage at the node N8 from which this high frequency component has been removed becomes the input signal to the hysteresis comparator X4. When the voltage at the node N8 increases, the voltage at the node N3 also increases. When the voltage at the node N3 becomes higher than the second reference voltage of the hysteresis comparator X4, the enable signal ENBN becomes H and the enable signal ENN becomes L. Therefore, the switch SW3 is turned on, the switch SW4 is turned off, and the NMOS transistor NM12 that is a constant current source is turned off. That is, the operation of the NMOS input differential amplifier circuit NA is stopped. In FIG. 2, the operation of the NMOS input differential amplifier circuit NA is stopped by turning off the NMOS transistor NM12, which is a constant current source. However, the present invention is not limited to this.

  Here, by designing the potential of the node N6 to be lower than the potential of the node N9, when the input common mode voltage approaches the low potential power supply voltage VSS, the operation of the NMOS transistor NM12 that is a constant current source is linear. The operation of the NMOS input differential amplifier circuit NA can be stopped before the operation in the region is started. Specifically, by making the W / L ratio of the NMOS transistors NM10 and NM11 constituting the in-phase component detector 1b smaller than the W / L ratio of the NMOS transistors NM13 and NM14 constituting the NMOS input pair, the node N6 Can be made lower than the potential of the node N9. Further, the potential of the node N6 can be made lower than the potential of the node N9 by making the size of the NMOS transistor NM9 larger than the NMOS transistor NM12 which is a constant current source.

  As described above, the operation of the NMOS input differential amplifier circuit NA can be stopped before the operation of the NMOS transistor NM12, which is a constant current source, becomes the operation in the linear region. There is no increase in jitter. That is, jitter can be reduced.

  FIG. 3 is a circuit diagram of an operational amplifier according to a comparative example of the first embodiment. Compared with the operational amplifier of FIG. 2, in-phase component detectors 1a and 1b, high-frequency component removers 2a and 2b, control signal generators 3a and 3b, switches SW1 to SW4, PMOS transistors PM1 and PM2, NMOS transistors NM2 and NM9 Is a configuration that has been deleted. The gate of the PMOS transistor PM5, which is a constant current source of the PMOS input differential amplifier circuit PA, is connected to the gate of the PMOS transistor PM10. The gate of the NMOS transistor NM12, which is a constant current source of the NMOS input differential amplifier circuit NA, is connected to the gate of the NMOS transistor NM8. Since other configurations are the same as those of the first embodiment, description thereof is omitted.

  The PMOS transistor PM5 normally operates in the saturation region. However, when the input common mode voltage of the differential input signals INP and INN approaches the high potential power supply voltage VDD, the voltage at the node N4 also approaches the high potential power supply voltage VDD, and the drain-source voltage of the PMOS transistor PM5 decreases. Therefore, the operation of the PMOS transistor PM5 is an operation in the linear region. In the linear region, the drain-source voltage dependency of the drain current of the PMOS transistor PM5 increases. Therefore, when noise is superimposed on the high potential power supply voltage VDD, the drain current of the PMOS transistor PM5 changes. As a result, the delay time of the PMOS input differential amplifier circuit PA changes and the jitter increases. If the input common mode voltage further rises, the PMOS transistor PM5 is turned off, so that the jitter is reduced.

  On the other hand, the NMOS transistor NM12 normally operates in the saturation region. However, when the input common mode voltage of the differential input signals INP and INN approaches the low potential power supply voltage VSS, the voltage at the node N9 also approaches the low potential power supply voltage VSS, and the drain-source voltage of the NMOS transistor NM12 decreases. Therefore, the operation of the NMOS transistor NM12 is an operation in the linear region. In the linear region, the drain-source voltage dependency of the drain current of the NMOS transistor NM12 increases. Therefore, when noise is superimposed on the low-potential power supply voltage VSS, the drain current of the NMOS transistor NM12 changes. As a result, the delay time of the NMOS input differential amplifier NA changes and the jitter increases. When the input common mode voltage further decreases, the NMOS transistor NM12 is turned off, and the jitter decreases conversely.

  FIG. 4 is a graph showing a comparison of jitter characteristics of the operational amplifiers according to the example and the comparative example. The horizontal axis represents the input common mode voltage Vcm [V], and the vertical axis represents the jitter [ps] of the output signal OUT. It is a simulation result when 100 mV, 250 MHz sine wave noise is superimposed on the high potential power supply voltage VDD, and 100 mV, 100 MHz sine wave noise is superimposed on the low potential power supply voltage VSS. In both the example and the comparative example, the low potential power supply voltage VSS = 0V and the high potential power supply voltage VDD = 1.8V. As shown in FIG. 4, in the comparative example, the NMOS input differential amplifier circuit NA operates in the linear region near 0.5V, and the PMOS input differential amplifier circuit PA operates in the linear region near 1.3V. Jitter characteristics are extremely deteriorated.

  On the other hand, as described above, in the embodiment, the operations of the differential amplifier circuits NA and PA can be stopped before the operations of the NMOS transistor NM12 and the PMOS transistor PM5, which are constant current sources, become operations in the linear region. Therefore, there is no input common mode voltage Vcm whose jitter characteristics are extremely deteriorated. Therefore, it has good jitter characteristics with respect to the input common mode voltage Vcm in the entire range from the low potential power supply voltage VSS to the high potential power supply voltage VDD. As shown in FIG. 4, the jitter characteristics are particularly good in the input common mode voltage Vcm range where the differential amplifier circuits NA and PA operate together, regardless of the embodiment or the comparative example.

1, 1a, 1b In-phase component detector 2, 2a, 2b High frequency component remover 3, 3a, 3b Control signal generator C1, C2 Capacitance CS Constant current source N1-N11 Node NA NMOS input differential amplifier circuit NM1-NM18 NMOS Transistor PA PMOS input differential amplifier circuit PM1-PM17 PMOS transistor R1-R4 Resistor SW1-SW4 Switch X1, X4 Hysteresis comparator X2, X3, X5-X8 Inverter

Claims (7)

A first differential amplifier having a first PMOS transistor pair with a differential input signal input to each gate;
A second differential amplifier having a first NMOS transistor pair to which the differential input signal is input to each gate;
An in-phase component detector for detecting an in-phase component of the differential input signal;
A high-frequency component removing unit that removes a high-frequency component from the in-phase component;
When the common mode voltage of the differential input signal is higher than the first reference voltage based on the common-mode component from which the high frequency component has been removed, the operation of the first differential amplifier is stopped, and the common mode voltage is A control signal generator for generating a control signal for stopping the operation of the second differential amplifier when the voltage is lower than a reference voltage (however, the second reference voltage is lower than the first reference voltage). Operational amplifier. The in-phase component detection unit
A first common-mode component detection unit having a second PMOS transistor pair in which the differential input signal is input to each gate and the sources and drains are connected to each other;
2. The calculation according to claim 1, further comprising: a second in-phase component detection unit having a second NMOS transistor pair in which the differential input signal is input to each gate and the sources and drains are connected to each other. amplifier. A current source PMOS transistor provided between the first PMOS transistor pair and a high potential power source;
A PMOS transistor provided between the second PMOS transistor pair and a high potential power source,
The drain voltage of the PMOS transistor is higher than the drain voltage of the current source PMOS transistor;
A current source NMOS transistor provided between the first NMOS transistor pair and a high potential power source;
An NMOS transistor provided between the second NMOS transistor pair and a high potential power source,
3. The operational amplifier according to claim 2, wherein a drain voltage of the NMOS transistor is lower than a drain voltage of the current source NPMOS transistor. The high-frequency component removing unit is
A first low-pass filter connected to the first in-phase component detector;
The operational amplifier according to claim 2, further comprising: a second low-pass filter connected to the second in-phase component detection unit. The control signal generator
A first comparator connected to the first low pass filter;
The operational amplifier according to claim 4, further comprising a second comparator connected to the second low-pass filter.   6. The operational amplifier according to claim 5, wherein the first and second comparators are hysteresis comparators. Based on the control signal output from the first comparator, the voltage applied to the gate of the current source PMOS transistor is switched,
7. The operational amplifier according to claim 5, wherein a voltage applied to a gate of the current source NMOS transistor is switched based on the control signal output from the second comparator.

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