JP2011135157A - Differential amplifier circuit and liquid crystal display driver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential amplifier circuit which highly accurately operates in a linear region, and also to provide a liquid crystal display driver using the differential amplifier circuit. <P>SOLUTION: The differential amplifier circuit is equipped with: transistors M1 and M2 each having a gate terminal applied with an input voltage V1; a plurality of differential pairs D1-D4 each having a transistor M3 having a drain terminal connected to a source terminal of the transistor M1, a switch S1 switching as to whether an input voltage V1 should be applied to a gate terminal of the transistor M3, a switch S2 switching as to whether an input voltage V2 should be applied to a gate terminal of the transistor M3, and a transistor M4 having a drain terminal connected to a source terminal of the transistor M2, a gate terminal given an input voltage V3, and a source terminal connected to the source terminal of the transistor M3; and a current source I1 for supplying current to the source terminals of the transistors M3 and M4 of the differential pairs D1-D4. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a differential amplifier circuit and a liquid crystal display driver.

  A DAC (digital) that has a plurality of differential pairs and switches the input terminals of each differential pair to be connected to one of the two input voltages, thereby providing a voltage value between the two input voltages to the amplifier circuit. An amplifier circuit with an analog converter has been proposed (see, for example, Patent Document 1). For example, when two input voltages V1 and V2 (V1 <V2) are given and a voltage value V1 + (V2−V1) / 2 is input to the amplifier circuit, the influence of V1 and V2 is halved. That is, the differential pair to which the voltage V1 is input and the differential pair to which the voltage V2 is input are controlled to be 1: 1. By performing such control, the value between the two input voltages can be complemented.

  However, since the differential pair operates in the saturation region, the distortion between the differential pair cannot compensate for the value between the two input voltages as the differential pair ratio, and the DAC characteristics deteriorate. There was a problem. In particular, the greater the difference between the two input voltages, the greater the influence of the non-linearity of the differential pair, and the operation accuracy decreased.

  Further, if a circuit for correcting the nonlinearity is added to reduce the influence of the nonlinearity of the differential pair, there is a problem that the circuit area and the current consumption increase.

JP 2006-197532 A

  An object of the present invention is to provide a differential amplifier circuit that operates with high accuracy in a linear region, and a liquid crystal display driver using the differential amplifier circuit.

  In a differential amplifier circuit according to one embodiment of the present invention, a first input voltage is applied to a gate terminal, and the first transistor and the second transistor having the same conductivity type are connected to the source terminal of the first transistor. A third switch having a drain terminal connected and having the same conductivity type as the first and second transistors, and a first switch for switching whether or not to apply the first input voltage to the gate terminal of the third transistor A second switch for switching whether to apply a second input voltage to the gate terminal of the third transistor; a drain terminal connected to the source terminal of the second transistor; and a third input to the gate terminal. A voltage is applied, a source terminal is connected to a source terminal of the third transistor, and a fourth conductivity type is the same as that of the first to third transistors. A plurality of differential pairs each having a transistor, in which and a current source for supplying a current to the source terminal of the source terminal and the fourth transistor of the third transistor of the plurality of differential pairs.

  A liquid crystal display driver according to an aspect of the present invention includes a digital-to-analog converter that outputs a plurality of voltages, a selection switch circuit that selects any two of the plurality of voltages, and the differential amplifier circuit, A buffer amplifier which is supplied with the selected two voltages, generates a voltage having a voltage value between the two voltages, and applies the generated voltage to a plurality of liquid crystal cells provided in a liquid crystal display panel; It is to be prepared.

  According to the present invention, it is possible to operate with high accuracy in a linear region.

1 is a schematic configuration diagram of a differential amplifier circuit according to a first embodiment of the present invention. It is a schematic block diagram of the amplifier circuit which concerns on the 2nd Embodiment of this invention. It is a schematic block diagram of the amplifier circuit which concerns on the 3rd Embodiment of this invention. It is a schematic block diagram of the liquid crystal display device which concerns on the 4th Embodiment of this invention. It is a schematic block diagram of the column driver which concerns on the 4th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  (First Embodiment) FIG. 1 shows a schematic configuration of a differential amplifier circuit according to a first embodiment of the present invention. The differential amplifier circuit includes transistors M1 and M2, differential pairs D1 to D4, and a current source I1. The differential pair D1 includes transistors M3 and M4 and switches S1 and S2. The differential pairs D2 to D4 have the same configuration as the differential pair D1. The differential pairs D1 to D4 are provided in parallel. The transistors M1 to M4 are of the same conductivity type, and are assumed here to be NMOS transistors.

  The drain terminal of the transistor M1 is connected to the output terminal T1, and the source terminal is connected to the drain terminal of the transistor M3 in the differential pair D1 to D4. The drain terminal of the transistor M2 is connected to the output terminal T2, and the source terminal is connected to the drain terminal of the transistor M4 in the differential pairs D1 to D4. An input voltage V1 is applied to the gate terminals of the transistors M1 and M2.

  The source terminal of the transistor M3 and the source terminal of the transistor M4 in the differential pair D1 to D4 are both connected to the current source I1. The current source I1 supplies a current to the common source terminal of the transistors M3 and M4. The gate terminal of the transistor M3 can be switched between applying the input voltage V1 via the switch S1 or applying the input voltage V2 via the switch S2. A voltage V3 is applied to the gate terminal of the transistor M4. On / off control of the switches S1 and S2 in the differential pairs D1 to D4 is performed by a control unit (not shown).

  When the voltages V1, V2, and V3 are close to each other, the source voltages of the transistors M3 and M4 in the differential pair D1 to D4 are the source voltage determined from the transistor M3 (the voltage V1 (or V2) to the gate of the transistor M3). Of the source voltage determined by the transistor M4 (the value decreased by the gate-source voltage of the transistor M4 from the voltage V3) and the higher voltage is determined to be dominant. The

  The drain voltages of the transistors M3 and M4 are determined by the source voltages of the transistors M1 and M2. The source voltages of the transistors M1 and M2 are values obtained by dropping the gate-source voltage of the transistors M1 and M2 from the input voltage V1, which is the gate voltage of the transistors M1 and M2.

  Under such conditions, the transistors M3 and M4 of the differential pairs D1 to D4 operate in the linear region because the drain-source voltage is very small.

When the transistors M3 and M4 in the differential pair D1 to D4 are operating in the linear region, the voltage applied to the gate terminal of the transistor M3 in the differential pair D1 to D4 is input to the input voltage V1 using the switches S1 and S2. , V2 can be switched to change the values of the output currents I ₀₊ and I ₀₋ from the output terminals T1 and T2. Specifically, depending on the ratio of the number of differential pairs in which the voltage V1 is applied to the gate terminal of the transistor M3 and the number of differential pairs in which the voltage V2 is applied to the gate terminal of the transistor M3, The output currents I ₀₊ and I ₀₋ change.

Since the influence of the input voltages V1 and V2 on the output currents I ₀₊ and I ₀₋ can be changed, this circuit discretely changes the value between the input voltages V1 and V2 according to the control of the switches S1 and S2. It operates as a differential amplifier circuit that compares the voltage value taken by (1) and the voltage V3. Since the transistors M3 and M4 operate in the linear region and the input voltage range in which the transistors operate linearly can be made larger than in the case of using transistors operating in the saturation region, the voltage difference between the input voltages V1 and V2 Even when is large, it can operate with high accuracy. In addition, since it is not necessary to add a circuit for correcting the nonlinearity of the differential pair, an increase in circuit area and current consumption can be prevented.

  When the input voltage V1 is higher than the input voltage V2 and the voltage V2 is applied to the gate terminals of some transistors M3 of the differential pairs D1 to D4, the source voltages of the transistors M3 and M4 are changed from the voltage V2 to the transistors M3, The voltage drops by the gate-source voltage of M4, and the drain voltages of the transistors M3 and M4 become the voltage dropped by the gate-source voltage of the transistors M1 and M2 from the voltage V1.

  Therefore, the drain-source voltage of the transistors M3 and M4 is V1-V2, and when this voltage value exceeds the drain-source saturation voltage of the transistors M3 and M4, the transistors M3 and M4 operate in the saturation region. Therefore, the input voltage range that operates linearly decreases, and the voltage difference between the voltages V1 and V2 cannot be increased.

  On the other hand, when the input voltage V1 is lower than the input voltage V2, the situation where the drain-source voltage of the transistors M3 and M4 described above exceeds the drain-source saturation voltage does not occur. Since the input voltage range which operates linearly can be expanded, even when the voltage difference between the voltages V1 and V2 is large, the operation can be performed with high accuracy. Therefore, the transistors M3 and M4 in the differential pair D1 to D4 can be more reliably operated in the linear region. Therefore, it is preferable that the input voltage V1 is lower than the input voltage V2.

  In the above embodiment, the case where the transistors M1 to M4 are NMOS transistors has been described as an example. However, the transistors M1 to M4 may be PMOS transistors. In that case, the higher voltage of the input voltages V1 and V2 is applied to the gate terminals of the transistors M1 and M2.

  In the above embodiment, a configuration in which four differential pairs are provided has been described. However, a plurality of differential pairs may be used, and the number of differential pairs is determined based on the input voltages V1 and V2 and the voltage value to be generated. The

  (Second Embodiment) FIG. 2 shows a schematic configuration of an amplifier circuit according to a second embodiment of the present invention. The amplifier circuit uses the differential amplifier circuit according to the first embodiment shown in FIG. 1 as an input stage, and includes an active load (active load) including transistors M5 and M6, a transistor M7, and a current source I2. The output stage has a class A output stage.

  The differential amplifier circuit used as the input stage has two differential pairs D1 and D2. The transistors M31 and M32 in FIG. 2 correspond to the transistor M3 in FIG. Similarly, the transistors M41 and M42 in FIG. 2 correspond to the transistor M4 in FIG. 1, the switches S11 and S21 in FIG. 2 correspond to the switch S1 in FIG. 1, and the switches S21 and S22 in FIG. Corresponds to S2.

  The drain terminal of the transistor M5 is connected to the drain terminal of the transistor M1 and the gate terminal of the transistor M7. The drain terminal of the transistor M6 is connected to the drain terminal of the transistor M2 and the gate terminals of the transistors M5 and M6. The source terminal of the transistor M7 is connected to the source terminals of the transistors M5 and M6, and the drain terminal is connected to the output terminal T0 of the amplifier circuit, the current source I2, and the gate terminals of the transistors M41 and M42.

  With such a configuration, the amplifier circuit illustrated in FIG. 2 has a voltage follower configuration having two input terminals. In a voltage follower configuration having an amplifier circuit using a normal class A output stage, the output voltage is substantially equal to the input voltage. The amplifier circuit according to the present embodiment can obtain the following output voltage V0 according to the connection conditions of the switches S11, S21, S12, and S22 in the differential pair D1 and D2.

  First, a case where one of the voltages V1 and V2 is applied to both of the gate terminals of the transistors M31 and M32 in the differential pair D1 and D2 (when the switches S11 and S12 are on or the switches S21 and S22 are on). Think.

  In this case, since the connection conditions of the input terminals of the differential pair D1 and the differential pair D2 are equal, the configuration is close to that of a normal voltage follower having one input terminal. Therefore, when the switches S11 and S12 are on, the output voltage V0 is substantially equal to the voltage V1, and when the switches S21 and S22 are on, the output voltage V0 is substantially equal to the voltage V2.

  Next, consider the case where the voltage V1 is applied to one of the gate terminals of the transistors M31 and M32 and the voltage V2 is applied to the other (when the switches S11 and S22 are on or the switches S12 and S21 are on).

In this case, when the amplifier circuit operates as an ideal voltage follower, the output current V 0 of the differential pair D1 and D2 becomes equal to the output current I ₀₊ and I ₀₋ (I ₀₊ = I ₀₋ ). It stabilizes at. The influence of the input voltages V1 and V2 on the output voltage V0 at this time is obtained. The transistors M1 and M2 have the same gate voltage (V1) and the same drain current (I ₀₊ , I ₀₋ ). Accordingly, the source voltages V _{d +} and V _{d− of} the transistors M1 and M2 are also equal.

When the currents flowing through the transistors M31, M41, M32, and M42 are I ₃₁ , I ₄₁ , I ₃₂ , and I ₄₂ , respectively, the following formulas 1 and 2 are obtained.

I ₃₁ , I ₄₁ , I ₃₂ , and I ₄₂ are drain currents of the transistors M31, M41, M32, and M42 operating in the linear region. When the source voltage of the transistors M31, M41, M32, and M42 is Vs, the threshold voltage is V _thn , and the voltage-current conversion gain is β, the following Equation 3 is obtained.

When Equation 3 is obtained for V0, the following Equation 4 is obtained.

  That is, the amplifier circuit can output a voltage having an intermediate value between the voltages V1 and V2.

  As described above, when the amplifier circuit using the differential amplifier circuit according to the first embodiment as an input stage has a voltage follower configuration, the two input voltages V1 are set according to the state of the switches in the plurality of differential pairs. , V2 can be switched between a state in which an output voltage equal to one of the voltages is output and a state in which an intermediate voltage between the two input voltages V1 and V2 is output.

  Since the transistors M31, M41, M32, and M42 operate in the linear region, and an input voltage range that operates linearly can be made larger than when a transistor that operates in the saturation region is used, the input voltage V1, Even when the voltage difference of V2 is large, it can operate with high accuracy. In addition, since it is not necessary to add a circuit for correcting the nonlinearity of the differential pair, an increase in circuit area and current consumption can be prevented.

  In the second embodiment, the configuration in which two differential pairs are provided has been described, but three or more differential pairs may be provided. For example, when three differential pairs are provided, the voltage of 1/3 and 2/3 between the two input voltages (V1 + (V2−V1) / 3, V1 + 2 (V2−V1) / 3) is output. Is also possible. Depending on the number of differential pairs, the level of the output voltage between the two input voltages can be changed.

  (Third Embodiment) FIG. 3 shows a schematic configuration of an amplifier circuit according to a third embodiment of the present invention. This amplifier circuit has a configuration in which a phase compensation capacitor Cc is further provided in the amplifier circuit according to the second embodiment shown in FIG. The capacitor Cc is provided between the output terminal T0 and the source terminal of the transistor M1.

  Since the input voltage V1 is applied to the gate terminal of the transistor M1, the source voltage of the transistor M1 changes following the change of the voltage V1. Further, since the amplifier circuit has a voltage follower configuration, the output voltage V0 changes following the two input voltages V1 and V2.

  When the input voltages V1 and V2 change due to a large signal, the voltage at the terminals at both ends of the phase compensation capacitor Cc changes in the same phase. Therefore, the phase compensation capacitor Cc is more effective than the phase compensation method using a normal mirror capacitor. The current required for driving can be reduced.

  (Fourth Embodiment) FIG. 4 shows a schematic configuration of a liquid crystal display device according to a fourth embodiment of the present invention. The liquid crystal display device includes a liquid crystal display panel 100, a row driver 200 that drives the liquid crystal display panel 100, and a column driver 300. In the liquid crystal display panel 100, cells 110 corresponding to red, green, and blue colors are provided in a matrix for each pixel.

  The column driver 300 includes a resistor string D / A converter 310, a selection switch circuit 320, and a buffer amplifier 330. A plurality of buffer amplifiers 330 are provided so as to correspond to each column of cells 110 in the liquid crystal display panel 100. The output of the resistor string D / A converter 310 is buffered by the buffer amplifier 330 via the selection switch circuit 320 and supplied to the cell 110.

  The row driver 200 controls whether the output voltage from the buffer amplifier 330 is applied to the electrode of the cell 110 by turning on / off the switch SW.

  FIG. 5 shows an enlarged view of a part of the column driver 300. As the buffer amplifier 330, the amplifier circuit according to the second embodiment shown in FIG. 2 or the amplifier circuit according to the third embodiment shown in FIG. 3 is applied.

  The lower B bits of the A + 1 bit data (DATA [A: 0]) for controlling on / off of the switch are given to the buffer amplifier 330, and the upper A-B bits are given to the selection switch circuit 320 (both A and B are positive). Integer). The selection switch circuit 320 applies any two voltages among the plurality of voltages output from the resistor string D / A converter 310 to the buffer amplifier 330 based on the value of the upper A-B bit. The buffer amplifier 330 adjusts the output voltage according to the value of the lower B bits. For example, on / off of the switches S11, S21, S12, and S22 in FIGS. 2 and 3 is controlled based on the value of the lower B bits.

  When two input voltages are supplied from the resistor string D / A converter 310 to the buffer amplifier 330 via the selection switch circuit 320, the buffer amplifier 330 has 2 as described in the first and second embodiments. A value between two input voltages can be output. The amplifier circuit (buffer amplifier 330) operating as a buffer can have a part of the digital-analog conversion function. Therefore, the number of bits of the original D / A converter 310 can be reduced, and the area of the column driver 300 can be reduced.

  In addition, since the transistors (see FIGS. 1 to 3) constituting the differential pair in the buffer amplifier 330 operate in a linear region, they operate with high accuracy even when the voltage difference between the two input voltages of the buffer amplifier is large. be able to. In addition, since it is not necessary to add a circuit for correcting the nonlinearity of the differential pair, an increase in circuit area and current consumption can be prevented.

  In this way, by applying the differential amplifier circuit according to the above embodiment to the column driver 300 that drives the liquid crystal display panel 100, an increase in the circuit area and current consumption of the column driver 300 is suppressed, and the DAC characteristics are deteriorated. Can be prevented.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

D1 to D4 Differential pair M1 to M7 Transistors S1, S2 Switches I1, I2 Current source 100 Liquid crystal display panel 200 Row driver 300 Column driver

Claims (5)

A first transistor and a second transistor having a first input voltage applied to a gate terminal and having the same conductivity type;
A drain terminal is connected to a source terminal of the first transistor, a third transistor having the same conductivity type as the first and second transistors, and a first input voltage applied to a gate terminal of the third transistor. A drain switch connected to a first switch for switching whether to apply, a second switch for switching whether to apply a second input voltage to the gate terminal of the third transistor, and a source terminal of the second transistor And a third input voltage is applied to the gate terminal, a source terminal is connected to a source terminal of the third transistor, and a fourth transistor having the same conductivity type as the first to third transistors is provided. Multiple differential pairs;
A current source for supplying current to a source terminal of the third transistor and a source terminal of the fourth transistor of the plurality of differential pairs;
A differential amplifier circuit comprising:   When the first and second transistors are NMOS transistors, the first input voltage is lower than the second input voltage, and when the first and second transistors are PMOS transistors, The differential amplifier circuit according to claim 1, wherein an input voltage is higher than the second input voltage. An active load transistor connected to the drain terminals of the first and second transistors;
An output stage connected to the drain terminal of the first transistor and having an output terminal;
Further comprising
3. The differential amplifier circuit according to claim 1, wherein the fourth transistor has a voltage follower configuration in which the gate terminal of the fourth transistor is connected to the output terminal.   The differential amplifier circuit according to claim 3, further comprising a phase compensation capacitor provided between the output terminal and the source terminal of the first transistor. A digital-to-analog converter that outputs multiple voltages;
A selection switch circuit for selecting any two of the plurality of voltages;
5. The differential amplifier circuit according to claim 1, wherein the selected two voltages are supplied, a voltage having a voltage value between the two voltages is generated, and the liquid crystal display panel is provided. A buffer amplifier for applying the generated voltage to a plurality of liquid crystal cells provided;
LCD driver with

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