JP2011134393A - Nonvolatile semiconductor memory device, nonvolatile semiconductor memory system, and data rewriting method for nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a period for rewriting data of a nonvolatile semiconductor memory device. <P>SOLUTION: The nonvolatile semiconductor memory device 1 has a storage area in which data can be rewritten for each block, a RAM 4 for evacuating data, and a controller 3. The device 1 includes: a preprogram step for applying a program voltage when a state of each cell in a block 2 is an erasing state; an erasing step for erasing all cells in the block; and a post program step for equalizing a threshold voltage. In the preprogram step, copying to the RAM is performed while determining the state of each cell in the block, and in the post program step, when data after the cells are rewritten is data corresponding to the erasing state, the post program voltage is applied to the cell to equalize the threshold voltage after erasing the cells, and when data after the cells are rewritten is data corresponding to a program state, the program voltage is applied to the cell to put the cell into the program state. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device, a nonvolatile semiconductor memory system, and a data rewriting method for a nonvolatile semiconductor memory device.

  A flash memory is a non-volatile semiconductor memory device capable of rewriting data, but can be changed from an erased state (for example, “1” state) to a programmed state (for example, “0” state) in units of 1 byte. However, it is necessary to erase the data in units of blocks before writing the update data.

  Patent Document 1 describes that a register for temporarily saving information of an area that does not require rewriting is provided before the flash memory is completely erased. Further, Patent Document 2 describes that after an execution program transferred from the outside is loaded into the first RAM, it is transferred to the flash memory using the CPU idle time, and is controlled by the flash memory. Yes. Further, Patent Document 3 describes that a changed portion of old data is copied from a flash memory to a RAM, and a program rewritten on the RAM is returned to the flash memory.

  In a system including a conventional flash memory, all the RAMs are external to the flash memory and are connected to the flash memory via an external bus. For this reason, rewriting the data in the flash memory requires a copy process from the flash memory to the RAM, an erase process from the flash memory, and a write back process from the RAM to the flash memory. It was necessary to issue a command. Accordingly, rewriting of data in the flash memory requires time for executing all these processes.

  FIG. 3 is a block diagram showing a hardware configuration of a conventional nonvolatile semiconductor memory system. The nonvolatile semiconductor memory device 101 includes a storage area and a controller 103. The storage area is an area for storing data, and is divided into blocks, and the stored data is updated (rewritten) for each block. The controller 103 controls the operation of the nonvolatile semiconductor memory device 101. For example, the controller 103 has a function of determining whether the state of each cell in the block 102 of the storage area is a program state (for example, “0” state) or an erase state (for example, “1” state). is doing.

  An MPU 105 is connected to the nonvolatile semiconductor memory device 101. The MPU 105 includes a processor 106 and a RAM 107. However, the RAM 107 does not necessarily have to be built in the MPU 105 and may be outside the MPU 105 and the nonvolatile semiconductor memory device 101. The processor 106 communicates with the controller 103 in the nonvolatile semiconductor memory device 101 to control the data update operation. For example, the processor 106 sends an erase start command to the controller 103. The data of the block 102 including the data to be updated in the nonvolatile semiconductor memory device 101 is copied to the RAM 107, and the data is updated here.

  FIG. 4 is a flowchart showing a processing procedure when data stored in the conventional nonvolatile semiconductor memory device 101 is updated. First, in step S101, all the data in the block 102 including the data to be updated in the storage area of the nonvolatile semiconductor memory device 101 is copied to the RAM 107 in the MPU 105 outside the nonvolatile semiconductor memory device 101 ( evacuate. Next, in step S102, a necessary portion of the data copied to the RAM 107 is updated. Next, in step S103, all data in the corresponding block 102 of the storage area of the nonvolatile semiconductor memory device 101 is erased. Finally, in step S104, the data of the entire block including the updated data in the RAM 107 of the MPU 105 is written back to the corresponding block 102 in the storage area of the nonvolatile semiconductor memory device 101.

  FIG. 5 is a flowchart showing a detailed process of the erase process in step S103 in FIG. The erase process is divided into a pre-program process, an erase process, and a post-program process.

  In the pre-programming process, all cells in the erased state (for example, “1” state) in the corresponding block 102 are set to the programmed state (for example, “0” state). Therefore, first, in step S301, it is checked (verified) whether the state of each cell is the program state or the erase state in order from the top address of the corresponding block 102. Next, in step S302, branching is performed according to the state of the checked cell. That is, if the cell state is the programmed state (NO), the process proceeds to step S304. If the cell state is the erase state (YES), the process proceeds to step S303. In step S303, program stress is applied to the erased cell to bring it into the programmed state. In step S304, it is determined whether or not the preprogram processing has been completed up to the final address of the block 102. If not completed (NO), the process returns to step S301, and the preprogram processing of the cell at the next address is performed. If the final address has been completed (YES), the process proceeds to step S305 of the next erase process.

  In step S305 of the erase process, all cells in the block 102 are erased and it is checked (verified) whether or not a normal erase state has been achieved. When the erase process ends, the process proceeds to step S306 of the next post program process.

  In the post program process, the threshold voltage Vt is equalized for all erased cells in the block 102. For this reason, first, in step S306, in order from the head address of the block 102, post-program stress (post-program voltage) is applied to each cell to equalize the threshold voltage Vt of each cell. Further, it is checked (verified) whether or not the normal threshold voltage Vt has been reached. Next, in step S307, it is determined whether or not the post program processing (threshold voltage Vt equalization) has been completed up to the final address in the block 102. If not completed (NO), the process returns to step S306 to execute the post program process for the cell at the next address. If the final address has been completed (YES), the post program process is terminated and the entire erase process (step S103 in FIG. 4) is terminated.

Japanese Patent Laid-Open No. 5-233478 Japanese Unexamined Patent Publication No. 9-146767 Japanese Patent Laid-Open No. 2002-14833

  In the conventional flash memory rewriting process, first the data of the corresponding block is copied from the flash memory to the external RAM, then the data of the RAM is updated, then the corresponding block of the flash memory is erased, and finally the flash memory is flashed. The update data was written back to the memory. For this reason, there is a problem that the rewriting process takes time.

  In order to solve the above problems, the present invention provides a storage area in which cell data can be rewritten for each block including a plurality of cells, and a RAM for saving cell data in the block to be rewritten. In the non-volatile semiconductor memory device having a controller for controlling reading and writing of the storage area and the RAM, the rewriting process of the data stored in the cell in the block is the state of each cell in the block to be rewritten Is in a program state or an erase state, and if it is in an erase state, in order to enter the program state, a preprogramming process in which a program voltage is applied to the cell and all the blocks in the block to be rewritten Erase process for erasing cells and post-program process for equalizing threshold voltage of erased cells In the pre-programming process, it is determined whether the state of each cell in the block to be rewritten is a programmed state or an erased state, and at the same time, the state of each cell is transferred to the RAM. Copy and rewrite data in the RAM during the erase process, and in the post-program process, based on the rewritten data in the RAM, if the data after cell rewrite is data corresponding to the erase state, In order to equalize the threshold voltage after erasing the cell, a post-program voltage is applied to the cell. If the data after rewriting the cell is data corresponding to the programmed state, the program voltage is applied to the cell to bring the cell into the programmed state. It is characterized by applying.

  According to another aspect of the present invention, there is provided a nonvolatile semiconductor memory system including the nonvolatile semiconductor memory device described above and an MPU that communicates with the nonvolatile semiconductor memory device.

  The present invention also provides a storage area in which cell data can be rewritten for each block including a plurality of cells, a RAM for saving cell data in the block to be rewritten, the storage area and the RAM. In a data rewriting method for a nonvolatile semiconductor memory device comprising a controller for controlling reading and writing, the data rewriting process for the data stored in the cells in the block is performed when the state of each cell in the block to be rewritten is programmed. It is determined whether it is in the erased state or not, and if it is in the erased state, in order to enter the programmed state, the preprogramming process in which the program voltage is applied to the cell and all the cells in the block to be rewritten are erased. Erase process, and a post-program process to equalize the threshold voltage of the erased cell In the pre-programming process, it is determined whether the state of each cell in the block to be rewritten is a programmed state or an erased state, and at the same time, the state of each cell is copied to the RAM. If the data in the RAM is rewritten during the erase process, and the data after rewriting the cell is data corresponding to the erase state based on the rewritten data in the RAM in the post program process, the cell In order to equalize the threshold voltage after erasing, a post-program voltage is applied to the cell, and if the data after rewriting the cell is data corresponding to the programmed state, the program voltage is applied to the cell to bring the cell into the programmed state. It is characterized by pouring.

  The nonvolatile semiconductor memory device according to the present invention has a built-in RAM, and performs a copy process to the RAM simultaneously with the verify step in the pre-program process of the conventional erase process, and further in the post-program process of the erase process. Simultaneously with the step of applying the post program stress, the write back processing from the RAM is performed.

  The present invention can reduce the time required for external processing when updating data in the nonvolatile semiconductor memory device, and can drastically shorten the data update time of the nonvolatile semiconductor memory device. Therefore, the performance of the nonvolatile semiconductor memory system including the nonvolatile semiconductor memory device can be dramatically improved.

1 is a block diagram showing a hardware configuration of a nonvolatile semiconductor memory system according to an embodiment of the present invention. It is a flowchart which shows the process sequence at the time of updating the data memorize | stored in the non-volatile semiconductor memory device of this invention. It is a block diagram which shows the hardware constitutions of the conventional non-volatile semiconductor memory system. It is a flowchart which shows the process sequence at the time of updating the data memorize | stored in the conventional non-volatile semiconductor memory device. It is a flowchart which shows the detailed process of the erase process in step S103 in FIG.

  FIG. 1 is a block diagram showing a hardware configuration of a nonvolatile semiconductor memory system according to an embodiment of the present invention. The nonvolatile semiconductor memory device 1 includes a storage area, a controller 3, and a RAM 4. The storage area is an area for storing data, and is divided into blocks, and updating (rewriting) of stored data is performed for each block. The controller 3 controls the operation of the nonvolatile semiconductor memory device 1. For example, the controller 3 has a function of determining whether the state of each cell in the block 2 of the storage area is a program state (for example, “0” state) or an erase state (for example, “1” state). is doing. The data of the block 2 including the data to be updated is copied (saved) to the RAM 4, and the data is updated here.

  Although not shown in FIG. 1, the nonvolatile semiconductor memory device 1 generates a program voltage for setting a cell in a program state and a post program voltage for equalizing the threshold voltage Vt of the erased cell. Has a regulator. Furthermore, it has a voltage changeover switch for switching the voltage applied to the cell.

  An MPU 5 is connected to the nonvolatile semiconductor memory device 1. The MPU 5 includes a processor 6. The processor 6 communicates with the controller 3 in the nonvolatile semiconductor memory device 1 to control the data update operation. For example, the processor 6 sends an update operation start command to the controller 3. Further, the processor 6 sends data update information (information indicating which bit of the data is rewritten to what value) to the RAM 4 in the nonvolatile semiconductor memory device 1.

  FIG. 2 is a flowchart showing a processing procedure when data stored in the nonvolatile semiconductor memory device 1 is updated. The data update process is divided into a preprogram process, an erase process, and a post program process.

  In the pre-programming process, all data in the block 2 including data to be updated is copied (saved) to the RAM 4, and all erased cells are set to the programmed state. For this reason, first, in step S1, it is checked (verified) whether the state of each cell is the program state or the erase state in order from the top address of the block 2. At the same time, the state of the checked cell, that is, the stored data is copied to the RAM 4. Next, in step S2, branching is performed according to the state of the checked cell. That is, if the state of the cell is the programmed state (NO), the process proceeds to step S4. If the cell state is the erase state (YES), the process proceeds to step S3. In step S3, program stress (program voltage) is applied to the erased cell to bring it into the programmed state. In step S4, it is determined whether or not the preprogram processing has been completed up to the final address of block 2. If not completed (NO), the process returns to step S1, and the preprogram processing of the cell at the next address is performed. If the final address has been completed (YES), the process proceeds to step S5 of the next erase process.

  In step S5 of the erase process, all the cells in the block 2 are erased, and it is checked (verified) whether or not a normal erase state has been achieved. In parallel, the data copied to the RAM 4 is updated. When the erase process ends, the process proceeds to step S6 of the next post program process.

  In the post program process, the threshold voltage Vt of the erased cells in the block 2 is equalized. At the same time, data is written to the cells to be programmed by updating the data by applying a program voltage. Although the post-program voltage for equalizing the threshold voltage Vt after erasure and the program voltage for bringing the cell into the program state are different, these voltages are generated by the regulator. Further, the voltage applied to the cells is switched by referring to the data in the RAM 4 and using the voltage switch according to the state of each cell after the update.

  First, in step S6, stress is applied to each cell in order from the top address of block 2. At this time, the updated data stored in the RAM 4 is referred to. If the updated data of the cell is data corresponding to the erased state, the threshold voltage Vt after the erase of the cell is equalized. A post program voltage is applied, and it is checked (verified) whether or not a normal threshold voltage Vt has been reached. If the updated data of the cell is data corresponding to the programmed state, a program voltage is applied to the cell to bring the cell into the programmed state. Next, in step S7, it is determined whether or not the post program processing (post program voltage or program voltage application) has been completed up to the cell at the final address in the block 2. If not completed (NO), the process returns to step S6 to perform the post program process for the cell at the next address. If the cell at the final address has been completed (YES), the post program process is terminated and the entire data update process is terminated.

  In the present invention, the copy process to the RAM is performed simultaneously with the verify in the preprogram process. Further, the write back processing from the RAM is performed simultaneously with the application of post program stress (post program voltage) in the post program process. Thereby, the data update time can be dramatically shortened. That is, conventionally, data update = copy process to RAM + erase process + write-back process from RAM is the only data update = erase process in the present invention. Furthermore, since the RAM is built in the nonvolatile semiconductor memory device, command issuance between the nonvolatile semiconductor memory device 1 and the MPU 5 is also reduced.

For example, if the block is 512 words, the time required for conventional copy processing is 65 ns per word, the time required for issuing commands is 65 ns per word, and the time required for write-back processing is 500 ns per word. The data update time reduced by the present invention is:
Copy processing: 65 ns × 512 = 33 μs
Command issuance: 65ns × 512 = 33μs
Write back processing: 500 ns × 512 = 256 μs
Therefore, the total is 322 μs. If the block is 32K words, it can be shortened by 322 μs × (32K / 512) = about 20 ms.

DESCRIPTION OF SYMBOLS 1 Nonvolatile semiconductor memory device 2 Block 3 Controller 4 RAM
5 MPU
6 processor

Claims (3)

A storage area in which cell data can be rewritten for each block including a plurality of cells,
RAM for saving cell data in the block to be rewritten;
In a nonvolatile semiconductor memory device comprising a controller for controlling reading and writing of the storage area and RAM,
The rewriting process of data stored in the cells in the block is as follows:
A preprogramming process in which the state of each cell in the block to be rewritten is determined to be in a programmed state or an erased state. When,
An erasing process for erasing all cells in the block to be rewritten,
A post-programming process for equalizing the threshold voltage of the erased cell,
In the preprogramming process, it is determined whether the state of each cell in the block to be rewritten is a programmed state or an erased state, and at the same time, the state of each cell is copied to the RAM,
During the erase process, the RAM data is rewritten,
If the data after rewriting the cell is data corresponding to the erase state based on the rewritten data in the RAM in the post-programming process, the data is posted to the cell in order to equalize the threshold voltage after erasing the cell. A nonvolatile semiconductor memory device, wherein a program voltage is applied, and if the data after rewriting of the cell is data corresponding to a programmed state, the program voltage is applied to the cell to bring the cell into the programmed state. The nonvolatile semiconductor memory device according to claim 1;
A nonvolatile semiconductor memory system comprising an MPU that communicates with the nonvolatile semiconductor memory device. A storage area in which cell data can be rewritten for each block including a plurality of cells,
RAM for saving cell data in the block to be rewritten;
In a data rewriting method for a nonvolatile semiconductor memory device comprising a controller for controlling reading and writing of the storage area and RAM,
The rewriting process of data stored in the cells in the block is as follows:
A preprogramming process in which the state of each cell in the block to be rewritten is determined to be in a programmed state or an erased state. When,
An erasing process for erasing all cells in the block to be rewritten,
A post-programming process for equalizing the threshold voltage of the erased cell,
In the preprogramming process, it is determined whether the state of each cell in the block to be rewritten is a programmed state or an erased state, and at the same time, the state of each cell is copied to the RAM,
During the erase process, the RAM data is rewritten,
If the data after rewriting the cell is data corresponding to the erase state based on the rewritten data in the RAM in the post-programming process, the data is posted to the cell in order to equalize the threshold voltage after erasing the cell. A data rewriting method for a nonvolatile semiconductor memory device, wherein a program voltage is applied to a cell in order to bring the cell into a program state if the program voltage is applied and the data after the cell is rewritten corresponds to the program state. .

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