JP2011129182A - Clock data recovery circuit and operating method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock data recovery circuit in which circuit scale and power consumption can be reduced. <P>SOLUTION: The clock data recovery circuit 3 is configured such that A/D conversion is carried out by an A/D converter 301 responding to a sampling clock of a clock generator 300, a plurality of digital output signals generated sequentially are supplied to a data correction unit 303, and correction digital signals generated sequentially are supplied to a phase comparator 305. The output of the phase comparator 305 is supplied to a timing generation unit 304 through a loop filter 306, the information Pvco on the plurality of re-sampling timings is supplied to the data correction unit 303. A detection circuit 302 generates error information nvco of a ratio T/t of a period T of an analog input signal and a period t of a sampling clock, a timing generation unit 304 generates the plurality of re-sampling timings by the plurality of delay times, and the data correction unit 303 generates the plurality of correction digital signals with the plurality of correction factors. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a clock data recovery circuit that regenerates a clock and data included in an input signal, and more particularly to a technique effective for reducing the circuit scale and power consumption.

  In an apparatus for reproducing a recording signal of an optical disk such as a CD (Compact Disk), a DVD (Digital Versatile Disk), or a BD (Blu-Ray Disk), the recording surface of the optical disk is irradiated with laser light emitted from an optical pickup, The reflected light is detected by an optical pickup, and an analog reproduction signal (hereinafter referred to as an RF signal) is generated. Digital signal processing determined by the specifications of each disc is executed on the RF signal, and reproduction data can be generated.

  On the other hand, with BD or the like, high-density recording is realized, and the RF signal is weak. For this reason, in order to accurately detect the RF signal, a clock and data recovery circuit (Clock and Data Recovery Circuit) for reproducing the clock and data included in the RF analog input signal is required. A general clock data recovery circuit includes an A / D converter, a digital phase comparator, a digital loop filter, a D / A converter, and a voltage controlled oscillator (VCO).

  The RF signal detected by the optical pickup is supplied to the input terminal of the A / D converter via the analog front end (AFE), and a digital signal is generated from the output terminal of the A / D converter. The digital signal is transmitted to the control input terminal of the voltage controlled oscillator (VCO) through the digital phase comparator, the digital loop filter, and the D / A converter, so that the A / O is output from the output terminal of the voltage controlled oscillator (VCO). It becomes possible to generate a clock signal with accurate timing supplied to the sampling control terminal of the D converter. Therefore, an accurate data signal is generated from the output terminal of the A / D converter, and this data signal can be decoded by a Viterbi decoder.

  However, in such a clock data recovery circuit, an A / D converter, a digital phase comparator, a digital loop filter, a D / A converter, and a voltage controlled oscillator (VCO) constitute a PLL (Phase Locked Loop) circuit. ing. In this PLL circuit, the D / A converter and the voltage controlled oscillator (VCO) are analog circuits. On the other hand, in order to increase the reproduction speed of the optical disc, it is necessary to ensure the stability of the PLL characteristic, but the characteristic variation of the analog circuit is an obstacle.

  The analog circuit of the PLL circuit is built in the analog / digital mixed LSI, but with the progress of miniaturization (high integration) of the LSI manufacturing process, the integration density of the digital circuit can be expected to increase. Density improvement cannot be expected. In order to solve this problem, Non-Patent Document 1 described below uses an asynchronous clock that is asynchronous with the frequency and phase of the RF signal as the clock signal supplied to the sampling terminal of the A / D converter. . The asynchronous clock is supplied to the sampling terminal of the A / D converter, the timing decoder, the reference level generator, and the Viterbi detector, and the asynchronous sampling data signal generated from the output of the A / D converter is supplied to the timing decoder and Viterbi. The pseudo-synchronized clock and the phase signal supplied to the detector and generated from the timing decoder are supplied to the Viterbi detector and the reference level generator, respectively.

  The asynchronous clock is an oversampling clock having a fixed frequency generated from a frequency synthesizer. The timing decoder consists of a period rate calculator, phase controller, synchronous pattern interval checker, NCO controller, and numerically controlled oscillator (NCO), and the Viterbi detector adds, compares, and selects multiple branch metrics. It is composed of a block and a survivor path management unit.

Akira Yamamoto et al, “Robust Read Channel System Processing Processing Asynchronous Sampling Data”, Japan Journal of Applied Phys. 45, no. 2B, 2006, PP. 1054-1057

  Prior to the present invention, the present inventors engaged in the development of an optical / disk / drive LSI capable of reducing the cost by using a miniaturized semiconductor process.

  In the development of this LSI, the reduction of analog circuits that hinders the increase in integration density has been an issue. In order to solve this problem, a technique for generating a pseudo-synchronous clock from an asynchronous clock described in Non-Patent Document 1 has been studied by the present inventors prior to the present invention.

  As a result of the examination by the present inventors prior to the present invention, the method described in Non-Patent Document 1 increases the circuit scale of the timing decoder and the reference level generator in order to reduce the error and improve the calculation accuracy. It has been clarified that the power consumption also increases. Furthermore, in the optical disk recording / reproducing apparatus, it is necessary to adjust the recording strategy (Write Strategy) to the disk by detecting the time fluctuation (jitter) between the reproduction clock and the zero crossing point of the rise and fall of the RF signal. is there. However, the problem that the method described in Non-Patent Document 1 does not consider the correspondence of the jitter has also been clarified by the examination by the present inventors prior to the present invention. The recording strategy is a technique for optimizing the pulse signal waveform supplied to the semiconductor laser when data is recorded on the recording surface of an optical disc, for example.

  The present invention has been made as a result of the examination by the present inventors prior to the present invention as described above.

  Accordingly, an object of the present invention is to provide a clock data recovery circuit capable of reducing the circuit scale and power consumption.

  Another object of the present invention is to provide a clock data recovery circuit that can easily cope with jitter in a disk recording / reproducing apparatus.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  A typical one of the inventions disclosed in the present application will be briefly described as follows.

  That is, in a typical embodiment of the present invention, the clock data recovery circuit (3) includes a clock generator (300), an A / D converter (301), a detection circuit (302), and a data correction unit (303). , A timing generator (304), a phase comparator (305), and a loop filter (306).

  In response to the sampling clock from the clock generator (300), the A / D converter (301) performs A / D conversion of an analog input signal to a digital output signal.

  A plurality of digital output signals sequentially generated from the A / D converter (301) are supplied to the data correction unit (303), and a plurality of correction digital signals sequentially generated from the data correction unit (303) are This is supplied to the phase comparator (305).

  The output signal of the phase comparator (305) is supplied to the timing generator (304) via the loop filter (306), and information on a plurality of re-sampling timings (Pvco) generated from the timing generator is The data correction unit (303) is supplied.

  The detection circuit (302) generates sampling error information (nvco) of a ratio (T / t) between a channel period (T) of the analog input signal and a sampling period (t) of the sampling clock.

  In response to the sampling period (t) and the sampling error information (nvco), the timing generation unit (304) generates the sampling error information from a plurality of A / D conversion timings by the A / D converter (301). The plurality of resampling timings delayed by a plurality of delay times adjusted by (nvco) are generated.

  The data correction unit (303) includes a plurality of corrections adjusted according to the plurality of delay times from the plurality of digital output signals sequentially generated from the output terminal of the A / D converter (301). The plurality of corrected digital signals respectively corrected at a rate can be sequentially generated at the plurality of re-sampling timings (see FIG. 1).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to provide a clock data recovery circuit capable of reducing the circuit scale and power consumption.

FIG. 1 is a diagram showing a configuration of an optical disc recording / reproducing apparatus that can be integrated in a semiconductor integrated circuit studied by the present inventors prior to the present invention. FIG. 2 is a waveform diagram for explaining the initialization operation when the optical disc recording / reproducing apparatus according to Embodiment 1 of the present invention shown in FIG. 1 is turned on. FIG. 3 is a waveform diagram for explaining the virtual lock operation of the virtual PLL in the normal operation after the initialization operation at the time of power-on of the optical disc recording / reproducing apparatus according to Embodiment 1 of the present invention shown in FIG. FIG. 4 is a waveform diagram for explaining the actual operation of the virtual PLL in the normal operation after the initialization operation at the time of power-on of the optical disc recording / reproducing apparatus according to Embodiment 1 of the present invention shown in FIG. FIG. 5 is a diagram showing a configuration of an optical disc recording / reproducing apparatus incorporating a clock data recovery circuit according to the second embodiment of the present invention. FIG. 6 is a diagram showing a configuration of an optical disc recording / reproducing apparatus incorporating a clock data recovery circuit according to the third embodiment of the present invention. FIG. 7 is a diagram showing a configuration of a semiconductor memory device 700 incorporating the clock data recovery circuit 3 according to the fourth embodiment of the present invention. FIG. 8 is a diagram showing a configuration of a transceiver 800 incorporating the clock data recovery circuit 3 according to the fifth embodiment of the present invention. FIG. 9 is a diagram showing a configuration of an optical disc recording / reproducing apparatus having a built-in clock data recovery circuit according to the sixth embodiment of the present invention and added with a circuit for detecting jitter as a recording quality index.

1. First, an outline of a typical embodiment of the invention disclosed in the present application will be described. The reference numerals of the drawings referred to with parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A clock data recovery circuit (3) according to a typical embodiment of the present invention includes a clock generator (300), an analog / digital converter (301), a detection circuit (302), and a data correction unit. (303), a timing generator (304), a phase comparator (305), and a loop filter (306).

  In response to the sampling clock generated from the clock generator (300), the analog / digital converter (301) can perform A / D conversion of an analog input signal to a digital output signal.

  A plurality of digital output signals (D (1), D (2), D (3), D (4)...) Sequentially generated from the output terminal of the analog / digital converter (301) are supplied to the data correction unit ( 303) and a plurality of correction digital signals (V (1), V (2), V (3), V (4),...) Sequentially generated at the output terminal of the data correction unit (303). ) Is supplied to the input terminal of the phase comparator (305).

  The output signal of the phase comparator (305) is supplied to the timing generator (304) through the loop filter (306), and a plurality of re-sampling timings (P1, Information (Pvco) of P2, P3, P4... Is supplied to the data correction unit (303).

  The detection circuit 302 can generate sampling error information (nvco) of a ratio (T / t) between a channel period (T) of the analog input signal and a sampling period (t) of the sampling clock.

  In response to the sampling period (t) and the sampling error information (nvco), the timing generation unit (304) generates a plurality of A / D conversion timings (p1, p2,...) By the analog / digital converter (301). The plurality of re-sampling timings (P1, P2, P3,...) delayed by a plurality of delay times (Δt, 2Δt, 3Δt, 4Δt...) adjusted by the sampling error information (nvco) from p3, p4,. P4 ...) can be generated.

  The data correction unit (303) is configured to output the plurality of digital output signals (D (1), D (2), D (3), D) sequentially generated from the output terminal of the analog / digital converter (301). (4)...) To the plurality of correction digitals respectively corrected with a plurality of correction factors (1 * nvco, 2 * nvco, 3 * nvco, 4 * nvco...) Adjusted corresponding to the plurality of delay times. The signals (V (1), V (2), V (3), V (4)...) Can be sequentially generated at the plurality of re-sampling timings (P1, P2, P3, P4...). (See FIG. 1).

  According to the embodiment, it is possible to provide a clock data recovery circuit capable of reducing the circuit scale and power consumption.

  In a preferred embodiment, the analog input signal includes a positive amplitude, a negative amplitude, and a cross point (Zc) between the positive amplitude and the negative amplitude.

  A first resampling timing (P3) and a second resampling timing respectively positioned immediately before and immediately after the cross point (Zc) between the plurality of resampling timings (P1, P2, P3, P4...). The phase comparator (305) and the loop filter (306) control the timing generator (304) so that the cross point (Zc) is positioned approximately in the middle of (P4). To do.

  According to the preferred embodiment, it is possible to realize a peak detection method for accurately detecting the positive amplitude peak value and the negative amplitude peak value of the analog input signal used in the partial response maximum likelihood decoding technique. It becomes.

  In another preferred embodiment, the analog input signal in which a time from one rising to the next rising is set to a predetermined value is supplied to the detection circuit (302) during an initialization operation, thereby The detection circuit (302) measures the time a plurality of times at the sampling period (t) of the sampling clock, and generates the sampling error information (nvco) from an average value of the measurement results of the plurality of times. It is what.

  In a more preferred embodiment, the plurality of delay times adjusted by the timing generation unit (304) are sequentially set to large delay times (Δt, 2Δt, 3Δt, 4Δt...) As time elapses.

  The plurality of correction factors used to generate the plurality of correction digital signals (V (1), V (2), V (3), V (4)...) In the data correction unit (303) are: As the time elapses, the correction rate is set to a large correction rate (1 * nvco, 2 * nvco, 3 * nvco, 4 * nvco...) Sequentially.

  In another more preferred embodiment, the input terminal of the Viterbi decoder (5) is connected to the output terminal of the data correction unit (303).

  The input terminal of the Viterbi decoder (5) has a plurality of correction digital signals (V (1), V (2), V (3) sequentially generated from the output terminal of the data correction unit (303). ), V (4)...) Are supplied.

  In still another more preferred embodiment, a waveform equalization circuit (4) is connected between the output terminal of the data correction unit (303) and the input terminal of the Viterbi decoder (5), and The output terminal of the Viterbi decoder (5) is connected to the input terminal of the demodulation circuit (6), and the output terminal of the demodulation circuit (6) is connected to the input terminal of the error correction circuit (7). To do.

  In a specific embodiment, the clock data recovery circuit (3) is built in a disk recording / reproducing apparatus.

  The clock data recovery circuit (3) reproduces a data component and a clock component included in the analog input signal reproduced from the recording disk driven by the disk recording / reproducing apparatus. (See FIGS. 1, 5, 6, and 9).

  In another specific embodiment, the clock data recovery circuit (3) is built in a semiconductor integrated circuit (700) containing a semiconductor memory (74).

  The clock data recovery circuit (3) reproduces a clock component, a command, an address, and data included in serial data supplied from the outside to the semiconductor memory (74) of the semiconductor integrated circuit (700). It is a characteristic (see FIG. 7).

  In still another specific embodiment, the clock data recovery circuit (3) is incorporated in a semiconductor integrated circuit (700) incorporating a data processing function block.

  The clock data recovery circuit (3) reproduces a clock component, a command, and data included in serial data supplied from the outside to the data processing function block of the semiconductor integrated circuit (700). (See FIG. 7).

  In still another specific embodiment, the clock data recovery circuit (3) is incorporated in a semiconductor integrated circuit including a transceiver (800) including a receiver (81) and a transmitter (82). It is a thing.

  The clock data recovery circuit (3) reproduces a clock component and data included in a reception signal (RX) supplied from the outside to the receiver (81) of the semiconductor integrated circuit. (See FIG. 8).

  [2] A typical embodiment of another aspect of the present invention includes a clock generator (300), an analog / digital converter (301), a detection circuit (302), a data correction unit (303), The operation method of the clock data recovery circuit (3) including the timing generation unit (304), the phase comparator (305), and the loop filter (306).

  In response to the sampling clock generated from the clock generator (300), the analog / digital converter (301) can perform A / D conversion of an analog input signal to a digital output signal.

  A plurality of digital output signals (D (1), D (2), D (3), D (4)...) Sequentially generated from the output terminal of the analog / digital converter (301) are supplied to the data correction unit ( 303) and a plurality of correction digital signals (V (1), V (2), V (3), V (4),...) Sequentially generated at the output terminal of the data correction unit (303). ) Is supplied to the input terminal of the phase comparator (305).

  The output signal of the phase comparator (305) is supplied to the timing generator (304) through the loop filter (306), and a plurality of re-sampling timings (P1, Information (Pvco) of P2, P3, P4... Is supplied to the data correction unit (303).

The operation method is as follows:
Generating, by the detection circuit (302), sampling error information (nvco) of a ratio (T / t) between a channel period (T) of the analog input signal and a sampling period (t) of the sampling clock;
In response to the sampling period (t) and the sampling error information (nvco), a plurality of A / D conversion timings (p1, p2,...) By the analog / digital converter (301) are generated by the timing generation unit (304). The plurality of re-sampling timings (P1, P2, P3,...) delayed by a plurality of delay times (Δt, 2Δt, 3Δt, 4Δt...) adjusted by the sampling error information (nvco) from p3, p4,. Generating P4 ...),
The plurality of digital output signals (D (1), D (2), D (3), D) sequentially generated from the output terminal of the analog / digital converter (301) by the data correction unit (303). (4)...) To the plurality of correction digitals respectively corrected with a plurality of correction factors (1 * nvco, 2 * nvco, 3 * nvco, 4 * nvco...) Adjusted corresponding to the plurality of delay times. Sequentially generating signals (V (1), V (2), V (3), V (4)...) At the plurality of re-sampling timings (P1, P2, P3, P4...). (See FIG. 1).

  According to the embodiment, it is possible to provide a clock data recovery circuit capable of reducing the circuit scale and power consumption.

2. Details of Embodiment Next, the embodiment will be described in more detail. In all the drawings for explaining the best mode for carrying out the invention, components having the same functions as those in the above-mentioned drawings are denoted by the same reference numerals, and repeated description thereof is omitted.

[Embodiment 1]
<< Configuration of optical disc recording / reproducing apparatus >>
FIG. 1 is a diagram showing a configuration of an optical disc recording / reproducing apparatus incorporating a clock data recovery circuit according to Embodiment 1 of the present invention.

  An optical disk recording / reproducing apparatus according to Embodiment 1 of the present invention shown in FIG. 1 includes an optical disk 100, a motor 101, an optical pickup 102, a pickup interface circuit 201, a clock data recovery circuit (CDR) 3, a waveform equalization circuit 4, and a Viterbi decoding. 5, a demodulator circuit 6, and an error correction circuit 7. In the optical disk recording / reproducing apparatus shown in FIG. 1, the pickup interface circuit 201, the clock data recovery circuit 3, the waveform equalization circuit 4, the Viterbi decoder 5, the demodulation circuit 6, and the error correction circuit 7 are optical, disk, and drive LSIs. The semiconductor chip is integrated.

  Information is recorded by irradiating the recording surface of the optical disc 100 with laser light emitted from the optical pickup 102. When reproducing information, reflected light is detected by the optical pickup 102 to generate an RF signal. The motor 101 rotates the optical disc 100 during information recording and information reproduction. The optical disk 100 is a removable disk that can be attached to and detached from the recording / reproducing apparatus.

  An RF signal generated from the optical pickup 102 is amplified by a variable gain amplifier with automatic gain control (AGC) of an analog front end (AFE) included in the pickup interface circuit 201, and is amplified by a clock data recovery circuit (CDR). 3 is supplied. In the clock data recovery circuit 3, the clock and data included in the RF analog input signal are reproduced, and the reproduced data is supplied to the waveform equalization circuit 4, Viterbi decoder 5, demodulation circuit 6, and error correction circuit 7. .

  The waveform equalization circuit 4 is composed of a low-pass filter having a high-frequency component boost function, and can reduce intersymbol interference (ISI: Inter Symbol Interference). The Viterbi decoder 5 is used not only in a disk recording / reproducing apparatus but also in a hard disk recording / reproducing apparatus, and generates a reproduction signal based on a Viterbi algorithm which is a kind of dynamic programming algorithm for searching for a maximum likelihood path. The demodulating circuit 6 demodulates the reproduction signal generated by the Viterbi decoder 5 based on standards such as CD, DVD, BD and the like. The error correction circuit 7 corrects an error in the signal demodulated by the demodulation circuit 6 using an error correction code (ECC).

<< Configuration of clock data recovery circuit >>
The clock data recovery circuit (CDR) 3 according to the first embodiment of the present invention shown in FIG. 1 includes a clock generator (CLK_Gen) 300, an analog / digital converter (A / D_Conv) 301, a rate detection circuit (Rate_Det) 302, a virtual Re-sampling circuit (Re-Sampling) 303, virtual voltage controlled oscillator (Virtual_VCO) 304, phase comparator (PD) 305, virtual loop filter (Virtual_LF) 306, subtractor (Sub) 307, first switch SW1, second switch Includes SW2.

  The clock generator (CLK_Gen) 300 generates an oversampling clock having a fixed frequency and supplies the oversampling clock to the sampling control terminal of the analog / digital converter (A / D_Conv) 301. An analog / digital converter (A / D_Conv) 301 converts an RF analog input signal supplied from the output of the pickup interface circuit 201 into a digital signal in response to an oversampling clock. A rate detection circuit (Rate_Det) 302 detects a ratio T / t between the channel period T of the RF analog input signal and the period t of the oversampling clock from the digital signal of the analog / digital converter 301 and the oversampling clock.

<< Virtual PLL >>
The virtual resampling circuit 303, the phase comparator 305, the second switch SW2, the virtual loop filter 306, the first switch SW1, and the virtual voltage controlled oscillator 304 of the clock data recovery circuit (CDR) 3 constitute a virtual PLL. In the virtual operation by the virtual PLL, the virtual resampling circuit 303 resamples the digital signal output from the analog / digital converter 301 in response to the output signal Pvco of the virtual voltage controlled oscillator 304.

<< Initialization at power-on >>
Even if the oversampling clock period t is shorter than the channel period T of the RF analog input signal due to the setting of the clock generator 300, the optical disk recording / reproducing apparatus according to the first embodiment of the present invention shown in FIG. The timing of resampling of the virtual resampling circuit 303 by the output signal Pvco of the virtual voltage controlled oscillator 304 in the normal operation can be matched with the channel period T of the RF analog input signal by the initialization operation at power-on. . In the case of a CD, the channel period T of the RF analog input signal is the rising edge of the RF analog input signal that can be processed by a clock data recovery circuit that operates in a zero cross / peak detect system, as will be described below. Is defined as approximately 1/6 of the shortest time between the timing of the first and the next rising timing.

  That is, in the initialization operation when the power is turned on, the initial value of the virtual loop filter 306 of the virtual PLL is zero. The subtractor 307 compares the information of the ratio T / t of the channel period T of the RF analog input signal detected by the rate detection circuit 302 and the period t of the oversampling clock with the initial value zero of the virtual loop filter 306, The comparison output signal of the subtractor 307 connects the first switch SW1 and the second switch SW2 to the B side terminal. Therefore, the information on the period t of the oversampling clock is stored in the virtual voltage controlled oscillator 304 via the rate detection circuit 302 and the first switch SW1, and further, the RF analog input signal detected by the rate detection circuit 302 is also stored. Information on the ratio T / t between the channel period T and the oversampling clock period t is stored in the virtual loop filter 306 via the subtractor 307 and the second switch SW2.

<Rate detection circuit>
In order to improve the accuracy of the ratio T / t information detected by the rate detection circuit 302, an average value of a plurality of measurement results is calculated. The rate detection circuit 302 detects the channel rate by measuring the time from the rising time of the output digital data of the analog / digital converter 301 to the next rising time with the period t of the oversampling clock. For example, in the case of a CD, the time from the rising edge of the RF analog input signal to the next rising edge is 6T at the shortest and 22T at the longest. The time width of 22T is counted with the resolution of the period t of the oversampling clock, and the occurrence frequency of the count value is measured. When the count value 35 is counted 6 times and the count value 36 is counted 4 times in 10 measurements, the following equation is established.

  22T = 0.6 * 35t + 0.4 * 36t (1) formula

  From the above equation (1), the average value ratio T / t = 35.4 / 22 = 1.61 can be calculated.

<Initialization waveform>
FIG. 2 is a waveform diagram for explaining the initialization operation when the optical disc recording / reproducing apparatus according to Embodiment 1 of the present invention shown in FIG. 1 is turned on. The horizontal axis and the vertical axis in FIG. 2 indicate time and amplitude of the RF analog input signal supplied from the pickup interface circuit 201 to the clock data recovery circuit (CDR) 3, respectively.

  As shown in FIG. 2, the RF analog input signal has a channel period T, while the oversampling clock generated from the clock generator 300 has a period t shorter than the channel period T. The time from the rise of the RF analog input signal shown in FIG. 2 to the next rise is the shortest 6T time. The longest time is 22T, and when calculating the ratio T / t between the channel period T of the RF analog input signal and the period t of the oversampling clock, counting with the resolution of the period t is performed during the period of the longest time 22T. Executed.

  On the other hand, as an ideal operation of the clock data recovery circuit 3, the period t of the oversampling clock generated from the clock generator 300 and supplied to the sampling control terminal of the A / D converter 301 is the RF analog input signal. It is equal to the channel period T. However, since the oversampling clock has a period t shorter than the channel period T, the sampling timing of the A / D converter 301 is a shorter period t earlier than the ideal channel period T timings P0, P1,. The timings p0, p1,.

  During normal operation of the virtual PLL, the phase comparator 305 immediately follows the absolute value of the positive or negative amplitude of the RF analog input signal at the sampling timings P0, P3, P6... Immediately before the zero cross Zc in FIG. The virtual PLL performs a closed loop operation so that the absolute value of the positive amplitude or the negative amplitude of the RF analog input signal at the sampling timings P1, P4, P7. That is, by the normal operation of the virtual PLL, the lock operation by the closed loop is executed so that the zero cross Zc is positioned at a substantially intermediate point between the immediately preceding sampling timings P0, P3, P6... And the immediately following sampling timings P1, P4, P7. Is done.

  Therefore, the positive peak level and the negative peak level of the RF analog input signal can be detected at the sampling timing P2 and the sampling timing P5, respectively, and the partial response maximum likelihood (PRML: Partial Response) enabling high density storage. Peak Detect used for Maximum Likelihood decoding technology can be realized. However, at the sampling timings p0, p1,..., P7 of an early short cycle t, it becomes impossible to detect the positive peak level and the negative peak level of the RF analog input signal, and peak detection cannot be realized. Therefore, the sampling timing during normal operation needs to match the channel period T of the RF analog input signal.

  On the other hand, the subtracter 307 responds to the fact that the information on the ratio T / t stored in the virtual loop filter 306 and the information on the ratio T / t of the output of the rate detection circuit 302 are equal to each other. The first switch SW1 and the second switch SW2 are connected to the A-side terminal, so that the operation of the optical disc recording / reproducing apparatus shown in FIG. 1 is switched from the initialization operation when the power is turned on to the normal operation.

<Normal operation>
In the normal operation of the optical disk recording / reproducing apparatus shown in FIG. 1, the virtual resampling circuit 303 of the virtual PLL constituting the clock data recovery circuit (CDR) 3, the phase comparator 305, the second switch SW2, the virtual loop filter 306, and the first The 1 switch SW1 and the virtual voltage controlled oscillator 304 execute a closed loop operation. The output of the virtual voltage controlled oscillator 304 in the normal operation according to the period t information stored in the virtual voltage controlled oscillator 304 and the ratio T / t information stored in the virtual loop filter 306 in the initialization operation at the time of power-on. The timing of resampling of the virtual resampling circuit 303 by the signal Pvco can be matched with the channel period T of the RF analog input signal.

  That is, the delay information of the ratio T / t stored in the virtual loop filter 306 is supplied to the virtual voltage controlled oscillator 304 as the control signal nvco through the first switch SW1. As a result, the output signal Pvco of the virtual voltage controlled oscillator 304 responding to the control signal nvco is given by the following equation.

  Pvco = 1 / nvco = t / T (2) equation

  This output signal Pvco serves as a control signal that delays the resampling timing of the virtual resampling circuit 303. The virtual voltage controlled oscillator 304 and the virtual resampling circuit 303 respond to the period t information stored in the virtual voltage controlled oscillator 304 in the initialization operation at power-on and the delay control signal Pvco given by the above equation (2). The virtual oscillation frequency fvco is given by the following equation.

  fvco = 1 / nvco * t = 1 / T (3)

  In this way, the virtual oscillation frequency fvco that determines the timing of re-sampling of the virtual re-sampling circuit 303 by the output signal Pvco of the virtual voltage-controlled oscillator 304 during normal operation is determined by the channel period T of the RF analog input signal. be able to.

<< Virtual lock operation of virtual PLL >>
FIG. 3 is a waveform diagram for explaining the virtual lock operation of the virtual PLL in the normal operation after the initialization operation at the time of power-on of the optical disc recording / reproducing apparatus according to Embodiment 1 of the present invention shown in FIG. The horizontal axis and the vertical axis in FIG. 3 indicate time and the amplitude of the RF analog input signal supplied from the pickup interface circuit 201 to the clock data recovery circuit (CDR) 3, respectively.

  As shown in FIG. 3, the timing p0, p1, p2, P3, and p4 of the initial short cycle t are delayed by zero delay time, Δt, 2Δt, 3Δt, and 4Δt, respectively, so that an ideal channel cycle is obtained. The timings T0, P1, P2, P3, and P4 can be matched. This unit delay time Δt can be set by the delay control signal Pvco given by the above equation (2).

  The timings p5, p6, p7... Of the early short period t thereafter are delayed by the delay times Δt, 2Δt, 3Δt. Can. By controlling in this way, the relationship between the length of the delay time nΔt (n = 1...) And the length of the period t of the oversampling clock is maintained in a relationship of nΔt ≦ t. Can be improved.

  On the other hand, the following equation is obtained from the above equation (2).

  t = T / nvco (4)

  The unit delay time Δt is given by the following equation.

  Δt = T−t (5)

  Substituting the above equation (4) into the above equation (5) yields the following equation.

Δt = T−t
= (Nvco-1) * T / nvco
= (Nvco-1) * t (6)

  Accordingly, the virtual voltage controlled oscillator 304 has an ideal channel period in which the timings p0, p1, p2, p3, and p4 of the initial early short period t are delayed by zero delay time, Δt, 2Δt, 3Δt, and 4Δt, respectively. T timings P0, P1, P2, P3, and P4 are generated. With this ideal channel period T, the resampling operation of the virtual resampling circuit 303 can be executed.

  For example, by using a crystal oscillator or the like for the clock generator 300, the period t of the oversampling clock generated from the clock generator 300 can be set stably against temperature fluctuations, power supply voltage fluctuations, and the like. . While this period t is grasped in advance by a high-precision measuring device, the rate detection circuit 301 detects the information nvco (= T / t) of the ratio T / t with high accuracy, thereby making it The voltage controlled oscillator 304 can control the unit delay time Δt with high accuracy.

<< Real operation of virtual PLL >>
The above describes the virtual lock operation of the virtual PLL during the normal operation of the optical disc recording / reproducing apparatus according to Embodiment 1 of the present invention shown in FIG. However, the actual operation of the virtual PLL during this normal operation is as follows.

  In other words, the virtual voltage controlled oscillator 304 and the virtual resampling circuit 303 are the first digital signal D (0) output first from the output terminal of the A / D converter 301 and the second digital output second. Using the signal D (1) and the control signal Pvco of the above equation (2), a first compensated digital output signal V (1) given by the following equation is generated.

V (1) = D (0) + 1 * (D (1) -D (0)) / Pvco
= D (0) + 1 * (D (1) -D (0)) * nvco (7)

  Next, the virtual voltage controlled oscillator 304 and the virtual resampling circuit 303 have the first compensation digital output signal V (1) and the third digital signal D output third from the output terminal of the A / D converter 301. The second compensated digital output signal V (2) given by the following equation is generated using (2) and the control signal Pvco of the above equation (2).

V (2) = V (1) + 2 * (D (2) -V (1)) / Pvco
= V (1) + 2 * (D (2) -V (1)) * nvco (8) equation

  Further, the virtual voltage controlled oscillator 304 and the virtual resampling circuit 303 are connected to the second compensated digital output signal V (2) and the fourth digital signal D (3) output from the output terminal of the A / D converter 301 for the fourth time. ) And the control signal Pvco of the above equation (2) are used to generate a third compensated digital output signal V (3) given by the following equation.

V (3) = V (2) + 3 * (D (3) -V (2)) / Pvco
= V (2) + 3 * (D (3) -V (2)) * nvco (9) equation

  Further, the virtual voltage controlled oscillator 304 and the virtual resampling circuit 303 have the third compensated digital output signal V (3) and the fifth digital signal D (4) output fifth from the output terminal of the A / D converter 301. ) And the control signal Pvco of the above equation (2) are used to generate a fourth compensated digital output signal V (4) given by the following equation.

V (4) = V (3) + 4 * (D (4) -V (3)) / Pvco
= V (3) + 4 * (D (4) -V (3)) * nvco (10)

  At timing P5 thereafter, the virtual voltage controlled oscillator 304 and the virtual resampling circuit 303 are the sixth output from the fourth compensation digital output signal V (4) and the output terminal of the A / D converter 301 for the sixth time. Using the digital signal D (5) and the control signal Pvco of the above equation (2), a fifth compensated digital output signal V (5) given by the following equation is generated.

V (5) = V (4) + 1 * (D (5) -V (4)) / Pvco
= V (4) + 1 * (D (5) -V (4)) * nvco (11) equation

  At the next timing P6, the virtual voltage controlled oscillator 304 and the virtual resampling circuit 303 are the seventh digital output seventh from the fifth compensated digital output signal V (5) and the output terminal of the A / D converter 301. Using the signal D (6) and the control signal Pvco of the above equation (2), a sixth compensated digital output signal V (6) given by the following equation is generated.

V (6) = V (5) + 2 * (D (6) −V (5)) / Pvco
= V (5) + 2 * (D (6) -V (5)) * nvco (12) formula

  Similarly, at the next timing P7, the virtual voltage controlled oscillator 304 and the virtual resampling circuit 303 output the sixth compensated digital output signal V (6) and the eighth output from the output terminal of the A / D converter 301. The seventh compensated digital output signal V (7) given by the following equation is generated using the eighth digital signal D (7) and the control signal Pvco of the above equation (2).

V (7) = V (6) + 3 * (D (7) -V (6)) / Pvco
= V (6) + 3 * (D (7) -V (6)) * nvco (13)

  FIG. 4 is a waveform diagram for explaining the actual operation of the virtual PLL in the normal operation after the initialization operation at the time of power-on of the optical disc recording / reproducing apparatus according to Embodiment 1 of the present invention shown in FIG. In FIG. 4, the horizontal axis and the vertical axis represent time, first digital signal D (0), second digital signal D (1), first compensation digital output signal V (1), and second compensation digital output signal, respectively. V (2)...

  As shown in FIG. 4, at the timings P1, P2, P3, P4... Of the ideal channel period T, accurate first compensation digital output signal V (1) and second compensation digital output signal V (2 ), The third compensated digital output signal V (3)... Is obtained. That is, in FIG. 4, the timing P1 of the ideal channel period T delayed by the delay times Δt, 2Δt, 3Δt, 4Δt,..., Respectively, from the timing p1, p2, p3, p4. , P2, P3, P4,..., Accurate first compensation digital output signal V (1), second compensation digital output signal V (2), third compensation digital output signal V (3), fourth compensation digital output. Signals V (4)... Can be generated sequentially.

  As described above, in the actual operation of the virtual PLL of FIG. 4, the virtual voltage controlled oscillator 304 first responds to the control signal nvco (= ratio T / t) stored in the virtual loop filter 306 in the initial early cycle t Timings P1, P2, P3, P4,..., Which are delayed by the delay times Δt, 2Δt, 3Δt, 4Δt,. The unit delay time Δt can be controlled by a control signal nvco (= ratio T / t). Next, the virtual resampling circuit 303 generates compensation data by interpolation of two data as understood from the above equations (7) to (13).

  A general interpolation operation (Interpolation) generates data located between two data by an arithmetic processing of two data, whereas an interpolation operation of the virtual resampling circuit 303 is performed by an arithmetic processing of two data. Data that is located outside one data is generated. Further, in the interpolation operation of the virtual resampling circuit 303, the interpolation rate is set to 1 * nvco, 2 * nvco, 3 * nvco, 4 * nvco... Corresponding to each delay time Δt, 2Δt, 3Δt, 4Δt. Yes. When the relationship between the length of the delay time nΔt and the length of the oversampling clock period t is not maintained in the relationship of nΔt ≦ t, the interpolation operation of the virtual resampling circuit 303 is the first delay time Δt and the interpolation rate is 1 *. After returning to the nvco state, the delay time is changed to 2Δt, 3Δt, 4Δt..., and the interpolation rate is changed to 2 * nvco, 3 * nvco, 4 * nvco.

  Therefore, in the actual operation of the virtual PLL of FIG. 4, the error information nvco of the ratio T / t of the channel period T of the RF analog input signal detected by the rate detection circuit 302 and the period t of the oversampling clock is constituted by a digital filter. Stored as an initial value in the virtual loop filter 306. Next, the virtual voltage controlled oscillator 304 determines the unit delay time Δt using the initial value nvco of the virtual loop filter 306 as a correction value, and delays the timings p1, p2, p3, p4. The timings P1, P2, P3, P4... Of the ideal channel period T delayed by the time Δt, 2Δt, 3Δt, 4Δt. This ideal timing reproduction makes it possible to effectively reproduce the clock included in the RF input signal.

  Further, the virtual voltage controlled oscillator 304 generates an interpolation coefficient Pvco (= 1 / nvco) that is the reciprocal of the initial value nvco of the virtual loop filter 306, and supplies the interpolation coefficient Pvco to the virtual resampling circuit 303. The virtual resampling circuit 303 uses the interpolation coefficient Pvco and digital signals D (0), D (1), D (2), D (3),... Sequentially output from the output terminal of the A / D converter 301. Is used to change the interpolation rate described in the equation (7) to the equation (13) to 1 * nvco, 2 * nvco, 3 * nvco, 4 * nvco. By this data interpolation operation, the compensated digital output signals V (1), V (2), V (3), V (4) with accurate values at the timings P1, P2, P3, P4. ) ... can be generated sequentially.

  Therefore, the virtual loop filter 306 can be configured by a digital filter that can store the initial value nvco. The virtual voltage controlled oscillator 304 has a timing adjustment function for reproducing the ideal channel period T by delaying the delay time Δt, 2Δt, 3Δt, 4Δt... Can be constituted by a digital circuit having a calculation function for generating an interpolation coefficient Pvco having a reciprocal of the initial value nvco. Further, the virtual resampling circuit 303 is configured by a digital circuit having a function of executing a data interpolation operation while sequentially changing the interpolation rate to 1 * nvco, 2 * nvco, 3 * nvco, 4 * nvco. Can do.

  Therefore, the digital circuit constituting the virtual loop filter 306, the virtual voltage controlled oscillator 304, and the virtual resampling circuit 303 has a circuit size and consumption that are higher than those of the timing decoder and the reference level generator described in Non-Patent Document 1. Electric power can be reduced.

[Embodiment 2]
FIG. 5 is a diagram showing a configuration of an optical disc recording / reproducing apparatus incorporating a clock data recovery circuit according to the second embodiment of the present invention.

  The difference between the optical disk recording / reproducing apparatus according to the second embodiment of the present invention shown in FIG. 5 and the first embodiment of the present invention shown in FIG. 1 is that the first switch SW1 of the clock data recovery circuit 3 in FIG. 5 is omitted in the clock data recovery circuit (CDR) 3 and the demodulating state signal in the demodulating circuit 6 is used to switch the second switch SW2. In the second embodiment of the present invention shown in FIG. 5, in the activated state, the output of the rate detection circuit 302 is added to the virtual loop filter 306 via the subtractor 307 and is integrated. As a control signal for controlling the second switch SW2 from the demodulating circuit 6, for example, a signal indicating that a synchronization signal pattern periodically generated in the reproduction data can be detected periodically can be used. In other words, the initialization operation can be switched to the normal operation using a signal detected when the frequency of the virtual voltage controlled oscillator 304 substantially matches the frequency of the RF signal, and the phase pull-in operation can be performed by the PLL. If the synchronization signal pattern cannot be detected by the demodulation circuit 6 due to the influence of jitter or the like, the second switch SW2 is changed from the connection of the A side terminal to the connection of the B side terminal again, and is initialized again. The operation is started.

[Embodiment 3]
FIG. 6 is a diagram showing a configuration of an optical disc recording / reproducing apparatus incorporating a clock data recovery circuit according to the third embodiment of the present invention.

  The optical disc recording / reproducing apparatus according to the third embodiment of the present invention shown in FIG. 6 differs from the first embodiment of the present invention shown in FIG. 1 and the second embodiment of the present invention shown in FIG. The configuration of the device 300.

  A clock generator 300 shown in FIG. 6 includes a clock oscillator 3001, a frequency divider 3002, and a frequency division control circuit 3003. The clock signal generated from the clock oscillator 3001 can be divided by the divider 3002, and the divided output signal of the divider 3002 can be output as an oversampling clock with a period t. The frequency ratio can be controlled by the frequency division control circuit 3003.

  An optical disk recording / reproducing apparatus needs to reproduce a disk such as a BD (Blu-Ray Disk), a CD (Compact Disk), and a DVD (Digital Versatile Disk). In a disc such as a CD or DVD, a signal recorded on the disc with a constant linear velocity (CLV) recording method is generally played back with a constant angular velocity (CAV) reproduction method. ing. In the case of this CAV reproduction, for example, the transfer rate and frequency of the reproduction RF analog signal differ by two times between the inner radius of the disc 25 mm and the outer radius 50 mm. That is, the transfer rate and frequency of the reproduction RF analog signal on the inner circumference of the disc are approximately twice as low as the transfer rate and frequency of the reproduction RF analog signal on the outer circumference of the disc, and the channel period T Is approximately twice as long as the channel period T of the reproduced RF analog signal on the outer periphery of the disk.

  Therefore, the power consumption of the clock data recovery circuit 3 can be reduced by lengthening the period t of the oversampling clock in response to the lengthening of the channel period T of the reproduction RF analog signal on the inner periphery of the disk. In order to realize this operation, when the rate detection circuit 302 detects that the ratio T / t is larger than 2, the frequency division control circuit 3003 responds to the detection output signal of the rate detection circuit 302 to divide the frequency. The operation of the device 3002 is increased from the division ratio 1 to the division ratio 2. Accordingly, the period t of the oversampling clock generated from the clock generator 300 shown in FIG. 6 is lengthened due to the increase of the frequency dividing ratio of the frequency divider 3002, so that the power consumption of the clock data recovery circuit 3 can be reduced. It becomes.

  On the other hand, when the rate detection circuit 302 detects that the ratio T / t becomes a value smaller than 2 by reproducing the disk outer periphery, the frequency division control circuit 3003 responds to the detection output signal of the rate detection circuit 302 and the frequency divider 3002 This operation is reduced from the division ratio 2 to the division ratio 1, and the period t of the oversampling clock generated from the clock generator 300 is shortened. Therefore, it is possible to increase the accuracy of signal processing by the clock data recovery circuit 3 in response to the shortening of the channel period T of the reproduced RF analog signal on the outer periphery of the disk.

  Further, when the rate detection circuit 302 detects that the ratio T / t is larger than 2, the frequency division control circuit 3003 sets the delay time of the digital filter constituting the virtual loop filter 306 to a large value, while the rate detection circuit 302 When the circuit 302 detects that the ratio T / t is smaller than 2, the frequency division control circuit 3003 sets the delay time of the digital filter constituting the virtual loop filter 306 to a small value. As a result, by adjusting the delay time of the digital filter constituting the virtual loop filter 306, the signal processing by the clock data recovery circuit 3 can be further improved in accuracy.

[Embodiment 4]
FIG. 7 is a diagram showing a configuration of a semiconductor memory device 700 incorporating the clock data recovery circuit 3 according to the fourth embodiment of the present invention.

  The semiconductor memory device 700 according to the fourth embodiment of the present invention shown in FIG. 7 includes a clock data recovery (CDR) circuit 3, a waveform equalization circuit 4, a Viterbi decoder 5, a demodulation circuit 6, an error correction circuit 7, a demultiplexer. A DEMUX 70, an X address circuit 71, a Y address circuit 72, a write circuit 73, a memory cell array 74, a read circuit 75, a PLL circuit 76, and a serializer (SER) 77 are provided.

  The clock data recovery circuit 3, the waveform equalization circuit 4, and the Viterbi decoder 5 included in the semiconductor memory device 700 of FIG. 7 are the above-described first embodiment of the present invention of FIG. 1 and the implementation of the present invention of FIG. Form 2 and Embodiment 3 of the present invention shown in FIG. 6 have the same configuration as those, have the same functions as those, and execute operations similar to those.

  The input terminal T1 of the semiconductor memory device 700 can be accessed by a host computer via a high-speed serial transmission line.

  At the time of write access, serial data including a write command, a write address, and write data is supplied from the host computer to the input terminal T1 via the high-speed serial transmission line. A write command is decoded by an instruction decoder (not shown), and an X address circuit 71, a Y address circuit 72, a write circuit 73, and a memory cell array 74 are activated by the decoding result, and a memory cell designated by the write address Write data is written to.

  At the time of read access, serial data including a read command and a read address is supplied from the host computer to the input terminal T1 via the high-speed serial transmission line. A read command is decoded by an instruction decoder (not shown), and an X address circuit 71, a Y address circuit 72, a memory cell array 74, a read circuit 75, a PLL circuit 76, and a serializer (SER) 77 are activated by the decoding result. Is done. Read data is read from the memory cell specified by the read address, the read parallel data is converted into serial data by the serializer (SER) 77, and the read serial data is sent via the output terminal T2 and the high-speed serial transmission line. Supplied to the host computer. The conversion operation from the parallel data to the serial data by the serializer 77 is executed in response to the clock signal CLK supplied from the PLL circuit 76.

  By the way, in the semiconductor memory device 700 of FIG. 7, the command, address, and data serial supplied to the input terminal T1 via the high-speed serial transmission line at the time of write or read access due to reasons such as delay in the high-speed serial transmission line. Waveform degradation occurs in the data. The clock data recovery circuit 3, the waveform equalization circuit 4, the Viterbi decoder 5, the demodulation circuit 6, and the error correction circuit 7 included in the semiconductor memory device 700 of FIG. The commands, addresses, data, etc. included in the are reproduced accurately. The correctly reproduced command is supplied to the instruction decoder, the correctly reproduced address is supplied to the X address circuit 71 and the Y address circuit 72, and the correctly reproduced write data is supplied to the writing circuit 73. Is possible. A demultiplexer (DEMUX) 70 separates write data and write addresses or read addresses, and supplies the separated write data and addresses to the write circuit 73, X address circuit 71, and Y address circuit 72, respectively. It is. Further, the recovered clock signal Re-CLK accurately reproduced by the clock data recovery circuit (CDR) 3 from the serial data whose waveform has deteriorated is supplied to the writing circuit 73, the X address circuit 71, the Y address circuit 72, etc. for timing adjustment. Is done.

In another embodiment, the output terminal T2 can be omitted, and the terminal T1 is an input / output terminal. The input / output terminal T1 and the input of the clock data recovery circuit (CDR) 3 and the serializer ( It is also possible to connect an input / output switching circuit to the output of (SER) 77.
Written.

  Furthermore, as another embodiment, the nonvolatile write operation to the nonvolatile memory cell array 74 can be executed by configuring the memory cell array 74 with nonvolatile memory cells. In this case, at the time of erase access, serial data including an erase command and an erase address is supplied from the host computer to the input terminal T1 via the high-speed serial transmission line. An erase command is decoded by an instruction decoder (not shown), and the nonvolatile memory cell array 74 and the erasing high voltage generation circuit are activated by the decoding result. A high voltage for erasing is applied to the nonvolatile memory cell designated by the erasing address, and the erasing operation of the nonvolatile memory cell array 74 is executed.

  As still another embodiment, a central processing unit (CPU), a digital signal processor (DSP), and a video display processor (VDP) are further provided inside the semiconductor chip of the semiconductor memory device 700 of FIG. It is also possible to incorporate a data processing function block such as Therefore, the clock data recovery circuit 3, the waveform equalization circuit 4, the Viterbi decoder 5, the demodulation circuit 6 and the error correction circuit 7 are connected to a command or address included in the serial data supplied via the high-speed serial transmission line. Data and the like are accurately reproduced and supplied to the data processing function block. When the data processing function block processes the data stored in the memory cell array 74, the data processing command supplied from the high-speed serial transmission line to the input terminal T1 is sent via the demultiplexer (DEMUX) 70 to the data processing function block. It is also possible to be supplied to the instruction decoder. The data processing result by the data processing function block can be stored in the memory cell array 74, and can be supplied from the output terminal T2 to the host computer via the high-speed serial transmission line.

[Embodiment 5]
FIG. 8 is a diagram showing a configuration of a transceiver (transceiver) 800 incorporating the clock data recovery circuit 3 according to the fifth embodiment of the present invention.

  The transceiver 800 according to the fifth embodiment of the present invention shown in FIG. 8 includes a clock data recovery (CDR) circuit 3, a waveform equalization circuit 4, a Viterbi decoder 5, a demodulation circuit 6, an error correction circuit 7, a duplexer 80, A receiver 81, a transmitter 82, a deserializer (DES) 83, a processor 84, a serializer (SER) 85, and a PLL circuit 86 are provided. 8 includes a clock data recovery circuit 3, a waveform equalization circuit 4, a Viterbi decoder 5, an error correction circuit 7, a duplexer 80, a receiver 81, a transmitter 82, a deserializer 83, The processor 84, serializer 85, and PLL circuit 86 are integrated on a semiconductor chip constituting the LSI.

  The clock data recovery circuit 3, the waveform equalization circuit 4, and the Viterbi decoder 5 included in the transceiver 800 of FIG. 8 are the first embodiment of the present invention shown in FIG. 1 and the embodiment of the present invention shown in FIG. 2. The third embodiment of the present invention in FIG. 6 and the fourth embodiment of the present invention in FIG. 7 have the same configuration, have the same functions, and execute the same operations as those.

  The duplexer 80 supplies the reception signal RX of the RF reception signal or optical transmission reception signal received by the wireless antenna or the optical fiber to the input terminal of the receiver 81, while the RF transmission signal or optical transmission transmission signal of the output terminal of the receiver 81 Is transmitted to a wireless antenna or an optical fiber.

  When an RF reception signal is received as the reception signal RX, the receiver 81 performs frequency down conversion from the RF reception signal to the baseband reception signal. When an optical transmission reception signal is received as the reception signal RX, the receiver 81 performs light / electricity / conversion from the optical transmission reception signal to the reception electric signal using the light receiving element and the reception amplifier.

  When an RF transmission signal is transmitted as the transmission signal TX, the transmitter 82 performs frequency up-conversion from the baseband transmission signal to the RF transmission signal. When the optical transmission transmission signal is transmitted as the transmission signal TX, the transmitter 82 performs electric / light / conversion from the transmission electric signal to the optical transmission transmission signal using the drive amplifier and the light emitting element.

  By the way, in the transceiver 800 of FIG. 8, waveform degradation occurs in the received signal RX due to signal loss or the like in wireless transmission or optical transmission. The clock data recovery circuit 3, the waveform equalization circuit 4, the Viterbi decoder 5, the demodulation circuit 6, and the error correction circuit 7 included in the transmitter / receiver 800 of FIG. 8 receive the received signal RX regardless of the waveform deterioration of the received signal RX. It accurately reproduces the data and clock contained in it. The correctly reproduced serial data is converted into parallel data by a deserializer (DES) 83 and further decoded by the processor 84, and the decoded data is supplied to the host computer 801. The recovered clock signal Re-CLK accurately reproduced from the reception signal RX whose waveform has been deteriorated by the clock data recovery circuit (CDR) 3 is supplied to the deserializer (DES) 83 that performs serial / parallel conversion for timing adjustment. Is done.

  Transmission data from the host computer 801 is encoded by the processor 84, and the encoded data is converted from a parallel transmission signal to a serial transmission signal by a serializer (SER) 85. The serial transmission signal is converted into a transmission signal TX by the transmitter 82, and the transmission signal TX is transmitted via the duplexer 80. The conversion operation from the parallel transmission signal to the serial transmission signal by the serializer 85 is executed in response to the clock signal CLK supplied from the PLL circuit 86.

[Embodiment 6]
FIG. 9 is a diagram showing a configuration of an optical disc recording / reproducing apparatus in which a circuit for detecting jitter serving as a recording quality index is added to the first embodiment of the present invention shown in FIG. The output terminal of the virtual resampling circuit 303 is connected to the input terminal of the asymmetry correction circuit 8, and the output terminal of the asymmetry correction circuit 8 is connected to the input terminal of the jitter detection circuit 9. The asymmetry correction circuit 8 generally calculates the positive / negative asymmetry of the compensation digital signals V (1), V (2), V (3), V (4). Correct with feedback loop. The jitter detection circuit 9 calculates the timing at which the zero level is crossed and outputs the amount of jitter with the virtual VCO. According to the sixth embodiment of the present invention shown in FIG. 9, the output of the virtual resampling circuit 303 is used as a point for detecting jitter, but the output of the waveform equalization circuit 4 is connected to the input terminal of the jitter detection circuit 9. Can also be detected. Furthermore, the Viterbi decoding circuit 5 can also detect and detect jitter from a reference level not shown in the Viterbi decoding circuit. By adjusting the disk recording waveform using the jitter amount calculated by the jitter detection circuit 9 as an index of recording quality, a high-quality recording disk can be produced.

  Although the invention made by the present inventor has been specifically described based on various embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. Yes.

  For example, the present invention is not limited to an optical disk such as a CD, DVD, or BD that is a removable disk that can be attached to and detached from the recording / reproducing apparatus, but a fixed disk such as a non-removable hard disk that is fixed to the recording / reproducing apparatus. It can be applied to the recording / reproducing apparatus.

DESCRIPTION OF SYMBOLS 100 ... Optical disk 101 ... Motor 102 ... Optical pick-up 201 ... Pick-up interface circuit 3 ... Clock data recovery circuit (CDR)
DESCRIPTION OF SYMBOLS 4 ... Waveform equalization circuit 5 ... Viterbi decoder 6 ... Demodulation circuit 7 ... Error correction circuit 300 ... Clock generator (CLK_Gen)
301: Analog / digital converter (A / D_Conv)
302 ... Rate detection circuit (Rate_Det)
303 ... Virtual resampling circuit (Re-Sampling)
304: Virtual voltage controlled oscillator (Virtual_VCO)
305 ... Phase comparator (PD)
306 ... Virtual loop filter (Virtual_LF)
307: Subtracter (Sub)
SW1 ... 1st switch SW2 ... 2nd switch

Claims (20)

The clock data recovery circuit includes a clock generator, an analog / digital converter, a detection circuit, a data correction unit, a timing generation unit, a phase comparator, and a loop filter.
In response to a sampling clock generated from the clock generator, the analog / digital converter can perform A / D conversion of an analog input signal to a digital output signal;
A plurality of digital output signals sequentially generated from the output terminal of the analog / digital converter are supplied to an input terminal of the data correction unit, and a plurality of correction digital signals sequentially generated at the output terminal of the data correction unit are Supplied to the input terminal of the phase comparator,
The output signal of the phase comparator is supplied to the timing generation unit via the loop filter, and information on a plurality of resampling timings generated from the timing generation unit is supplied to the data correction unit,
The detection circuit can generate sampling error information of a ratio between a channel period of the analog input signal and a sampling period of the sampling clock;
In response to the sampling period and the sampling error information, the timing generator delays each of a plurality of delay times adjusted by the sampling error information from a plurality of A / D conversion timings by the analog / digital converter. The plurality of re-sampling timings generated can be generated;
The data correction unit is respectively corrected with a plurality of correction rates adjusted corresponding to the plurality of delay times from the plurality of digital output signals sequentially generated from the output terminal of the analog / digital converter. A clock data recovery circuit, wherein a plurality of correction digital signals can be sequentially generated at the plurality of re-sampling timings. The analog input signal includes a positive amplitude, a negative amplitude, and a cross point between the positive amplitude and the negative amplitude;
The phase is set such that the cross point is positioned approximately in the middle between the first re-sampling timing and the second re-sampling timing respectively positioned immediately before and immediately after the cross point between the plurality of re-sampling timings. The clock data recovery circuit according to claim 1, wherein the comparator and the loop filter control the timing generation unit.   The detection circuit is supplied at the sampling period of the sampling clock by supplying the analog input signal in which the time from the rising to the next rising is set to a predetermined value to the detection circuit during the initialization operation. 3. The clock data recovery circuit according to claim 2, wherein time is measured a plurality of times, and the sampling error information is generated from an average value of the measurement results of the plurality of times. The plurality of delay times adjusted by the timing generation unit are sequentially set to large delay times as time passes,
4. The clock data according to claim 3, wherein the plurality of correction factors used to generate the plurality of correction digital signals in the data correction unit are sequentially set to a large correction factor as time elapses. Recovery circuit. The input terminal of the Viterbi decoder is connected to the output terminal of the data correction unit,
5. The clock data recovery circuit according to claim 4, wherein the plurality of correction digital signals sequentially generated from the output terminal of the data correction unit are supplied to the input terminal of the Viterbi decoder.   A waveform equalization circuit is connected between the output terminal of the data correction unit and the input terminal of the Viterbi decoder, an input terminal of a demodulation circuit is connected to an output terminal of the Viterbi decoder, and the demodulation circuit 6. The clock data recovery circuit according to claim 5, wherein an input terminal of an error correction circuit is connected to the output terminal. The clock data recovery circuit is built in a disk recording / reproducing device,
The said clock data recovery circuit reproduces | regenerates the data component and clock component which were contained in the said analog input signal reproduced | regenerated from the recording disc driven by the said disc recording / reproducing apparatus. Clock data recovery circuit. The clock data recovery circuit is built in a semiconductor integrated circuit containing a semiconductor memory,
The clock data recovery circuit reproduces a clock component, a command, an address, and data included in serial data supplied from the outside to the semiconductor memory of the semiconductor integrated circuit. Clock data recovery circuit. The clock data recovery circuit is built in a semiconductor integrated circuit containing a data processing function block,
The clock data recovery circuit reproduces a clock component, a command, and data included in serial data supplied from the outside to the data processing function block of the semiconductor integrated circuit. Clock data recovery circuit. The clock data recovery circuit is built in a semiconductor integrated circuit including a transceiver including a receiver and a transmitter,
The clock data recovery circuit according to claim 6, wherein the clock data recovery circuit reproduces a clock component and data included in a reception signal supplied from the outside to the receiver of the semiconductor integrated circuit. . An operation method of a clock data recovery circuit comprising a clock generator, an analog / digital converter, a detection circuit, a data correction unit, a timing generation unit, a phase comparator, and a loop filter,
In response to a sampling clock generated from the clock generator, the analog / digital converter can perform A / D conversion of an analog input signal to a digital output signal;
A plurality of digital output signals sequentially generated from the output terminal of the analog / digital converter are supplied to an input terminal of the data correction unit, and a plurality of correction digital signals sequentially generated at the output terminal of the data correction unit are Supplied to the input terminal of the phase comparator,
The output signal of the phase comparator is supplied to the timing generation unit via the loop filter, and information on a plurality of resampling timings generated from the timing generation unit is supplied to the data correction unit,
The operation method is as follows:
Generating, by the detection circuit, sampling error information of a ratio between a channel period of the analog input signal and a sampling period of the sampling clock;
In response to the sampling period and the sampling error information, the timing generator delays each of a plurality of delay times adjusted by the sampling error information from a plurality of A / D conversion timings by the analog / digital converter. Generating said plurality of re-sampling timings,
The data correction unit corrects each of the plurality of digital output signals sequentially generated from the output terminal of the analog / digital converter with a plurality of correction rates adjusted corresponding to the plurality of delay times. And a step of sequentially generating a plurality of corrected digital signals at the plurality of re-sampling timings. The analog input signal includes a positive amplitude, a negative amplitude, and a cross point between the positive amplitude and the negative amplitude;
The phase is set such that the cross point is positioned approximately in the middle between the first re-sampling timing and the second re-sampling timing respectively positioned immediately before and immediately after the cross point between the plurality of re-sampling timings. The method of claim 11, wherein the comparator and the loop filter control the timing generator.   The detection circuit is supplied at the sampling period of the sampling clock by supplying the analog input signal in which the time from the rising to the next rising is set to a predetermined value to the detection circuit during the initialization operation. 13. The operation method of the clock data recovery circuit according to claim 12, wherein time is measured a plurality of times, and the sampling error information is generated from an average value of the measurement results of the plurality of times. The plurality of delay times adjusted by the timing generation unit are sequentially set to large delay times as time passes,
14. The clock data according to claim 13, wherein the plurality of correction factors used for generating the plurality of correction digital signals in the data correction unit are sequentially set to a large correction factor as time elapses. How the recovery circuit works. The input terminal of the Viterbi decoder is connected to the output terminal of the data correction unit,
15. The clock data recovery circuit according to claim 14, wherein the plurality of corrected digital signals sequentially generated from the output terminal of the data correction unit are supplied to the input terminal of the Viterbi decoder.   A waveform equalization circuit is connected between the output terminal of the data correction unit and the input terminal of the Viterbi decoder, an input terminal of a demodulation circuit is connected to an output terminal of the Viterbi decoder, and the demodulation circuit 16. The operation method of the clock data recovery circuit according to claim 15, wherein the output terminal of the error correction circuit is connected to an input terminal of the error correction circuit. The clock data recovery circuit is built in a disk recording / reproducing device,
The clock data recovery circuit reproduces a data component and a clock component included in the analog input signal reproduced from the recording disk driven by the disk recording / reproducing apparatus. Operation method of clock data recovery circuit. The clock data recovery circuit is built in a semiconductor integrated circuit containing a semiconductor memory,
The clock data recovery circuit reproduces a clock component, a command, an address, and data included in serial data supplied from the outside to the semiconductor memory of the semiconductor integrated circuit. Operation method of clock data recovery circuit. The clock data recovery circuit is built in a semiconductor integrated circuit containing a data processing function block,
The clock data recovery circuit reproduces a clock component, a command, and data included in serial data supplied from the outside to the data processing function block of the semiconductor integrated circuit. Operation method of clock data recovery circuit. The clock data recovery circuit is built in a semiconductor integrated circuit including a transceiver including a receiver and a transmitter,
The clock data recovery circuit according to claim 16, wherein the clock data recovery circuit regenerates a clock component and data included in a reception signal supplied from the outside to the receiver of the semiconductor integrated circuit. How it works.

Images