JP2011124848A - Viterbi decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up trace back processing in viterbi decoding. <P>SOLUTION: In the viterbi decoding, when the trace back processing is performed based on selection path information showing a survival path calculated by an ACS operation, if a state at time N is established in a state A, the processing is performed by reading the selection path information of states of 2<SP>k</SP>pieces at time (N-k) which can transit to the state A at the time N from among the states at the time (N-k) that is k time before the time N from a path memory, memory access is performed at an earlier stage to conceal memory access latency in comparison with conventional trace back processing, and the trace back processing is executed at high speed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a Viterbi decoding apparatus.

  In a communication system that transmits information by wireless communication or wired communication, an error may occur in the transmitted information depending on the state of the communication path. In order to transmit information correctly, convolutional coding is one of coding methods that makes information redundant and enables error correction. As one of convolutional code decoding methods, Viterbi decoding for decoding based on the Viterbi algorithm is known. For example, the transmission side device convolutionally encodes transmission data and sends the encoded data (convolutional code) to the transmission path. The reception-side apparatus performs Viterbi decoding on the encoded data (convolutional code) received via the transmission path, and decodes the transmission data.

  In Viterbi decoding, ACS (Add-Compare-Select) calculation is performed using received data, and transmission data is decoded by performing a traceback process based on the result of the ACS calculation. The ACS calculation obtains the probability (likelihood) of a path (route) related to a state transition according to received data based on a state transition diagram called a trellis diagram. In the ACS calculation, for each state, a path metric is calculated for each path using the path metric of the surviving path in the previous calculation (Add), and the path metrics for each path are compared (Compare). Select the (high) path as the surviving path (Select).

  In the traceback process, the state transition of the encoder is sequentially determined by tracing back the maximum likelihood path (survival path) selected by the ACS operation from the end, and transmission data is obtained. In the trellis diagram, two paths extend from each state. In the path memory in which information indicating the surviving path obtained by the ACS operation is stored, 1-bit selection indicating which one of the candidates that can be taken in the state one hour before is more likely for each state. Stores path information. In the traceback process, by acquiring the selected path information in the state of time N stored in the path memory, the path to time (N-1) is determined and the state of time (N-1) is determined. Transmission data is obtained by repeating this operation while going back in time.

  Various techniques for improving processing efficiency and the like have been proposed for Viterbi decoding. For example, a Viterbi decoding device has been proposed in which a plurality of ACS arithmetic processes are continuously pipelined in parallel, thereby improving the efficiency of the ACS arithmetic process and increasing the speed of the Viterbi decoding process (for example, (See Patent Document 1). In addition, a technique has been proposed that enables comparison operations in ACS operations and storage of information bits indicating surviving paths selected by ACS operations in a register (see, for example, Patent Document 2). ). A technique has been proposed in which a path memory is divided into a plurality of parts, a value of a shift register in a traceback circuit is decoded, a chip select signal is generated, and a path memory for obtaining data is selected (for example, see Patent Document 3). .) It has a trace-back unit that sequentially reads out the transition information obtained by the ACS operation from the path memory using the maximum likelihood state information, and sequentially reads out the state number obtained by tracing the maximum likelihood path back by the path cutoff length. A maximum likelihood decoder has been proposed (see, for example, Patent Document 4).

JP-A-10-107651 Japanese Patent No. 3358996 Japanese Patent No. 3277856 JP 2003-258650 A

  As described above, in the conventional traceback process, the selected path information at the time N state is read from the path memory, and the state (path) at the time (N−1) is determined based on the selected path information. Then, the selected path information at time (N-1) corresponding to the determined state is read from the path memory, and the state (path) at time (N-2) is determined based on the selected path information. In other words, in the traceback processing, reading of the selected path information from the path memory and determination of the state (path) based on the selected path information are sequentially repeated, and the bits are determined in order bit by bit. Transmission data is required. However, since reading of the selected path information from the path memory and determination of the state based on the selected path information cannot be performed in parallel, multiple bits are required to determine one bit, and the processing speed is slow. there were.

According to one aspect of the present invention, a calculation unit that calculates a survivor path based on convolutionally encoded data, a memory unit that stores path information indicating the obtained survivor path, and a stored path information A Viterbi decoding device is provided that includes a traceback unit that traces back state transitions and outputs a decoding result. When the state of the time N is determined to be the first state, the traceback unit determines that the time N among the states at the time (N−k) k times before (k is a predetermined integer equal to or greater than 2). Then, the path information of 2 ^k states at the time (N−k) at which the transition to the first state can be performed is read from the memory unit and processed.

The disclosed Viterbi decoding apparatus performs processing by reading in advance from the memory unit the path information of 2 ^k states at the time (N−k) at which the state can transition to the determined time N state, so that the memory access latency is hidden. Therefore, the traceback process can be speeded up.

It is a figure which shows the structural example of the Viterbi decoding apparatus in embodiment of this invention. It is a figure for demonstrating a convolutional code. It is a figure for demonstrating the traceback process in Viterbi decoding in this embodiment. It is a figure which shows the structural example of the trace back part in 1st Embodiment. It is a figure which shows the structural example of the processor which has an ALU array. It is a figure which shows the structural example of the arithmetic processing part in this embodiment. It is a figure for demonstrating the operation | movement in 1st Embodiment. It is a figure for demonstrating the operation | movement in 1st Embodiment. It is a figure which shows the structural example of the trace back part in 2nd Embodiment. It is a figure which shows the structural example of the selection process part shown in FIG. It is a figure which shows the structural example of the address generation part shown in FIG. It is a figure for demonstrating the operation | movement in 2nd Embodiment. It is a figure which shows the other structural example of the trace back part in 2nd Embodiment. It is a figure which shows the structural example of the selection process part shown in FIG. It is a figure which shows an example of the arrangement image of the storage data in a path memory.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating a configuration example of a Viterbi decoding apparatus according to an embodiment of the present invention. The Viterbi decoding apparatus according to the present embodiment includes a branch metric calculation unit 11, an ACS (Add-Compare-Select) calculation unit 12, a path metric memory 13, a path memory 14, and a traceback unit 15.

  The branch metric calculation unit 11 receives convolutionally encoded data that is the object of decoding processing. The branch metric calculation unit 11 calculates a branch metric (for example, a Hamming distance of the code) in the trellis diagram based on the input data.

  The ACS calculation unit 12 performs ACS calculation for each state in the trellis diagram. That is, the ACS calculation unit 12 first calculates the branch metric calculated by the branch metric calculation unit 11 and the path metric of the surviving path in the previous calculation stored in the path metric memory 13 for all paths to the state. Add (Add). Next, the ACS calculation unit 12 compares the path metrics after the addition (Compare), and selects the path with the smaller path metric (minimum) as the surviving path (Select). The ACS calculation unit 12 performs the above calculation for each state in the trellis diagram. The selected path information indicating the surviving path selected by the calculation in the ACS calculation unit 12 and the path metric of the path are stored in the path memory 14 and the path metric memory 13, respectively.

  The traceback unit 15 performs a traceback process on the result of the Viterbi calculation performed by the branch metric calculation unit 11 and the ACS calculation unit 12 described above, and outputs the result. The traceback unit 15 reads the selected path information obtained by the calculation in the ACS calculation unit 12 from the path memory 14, determines the state transition in the trellis diagram retrospectively, and outputs it as decoded transmission data.

An outline of processing in the traceback unit 15 of the Viterbi decoding apparatus in the present embodiment will be described with reference to FIGS.
First, the convolutional code decoded by the Viterbi decoding apparatus will be described with reference to FIG. In the following description, convolutional coding with a constraint length of 3 and a coding rate of 1/2 will be described as an example in order to avoid complicated description.

  FIG. 2A is a diagram illustrating an example of a convolutional encoder. The convolutional encoder shown in FIG. 2A has flip-flops 21 and 22 and EXOR circuits (exclusive OR operation circuits) 23, 24 and 25. The input in is input to a shift register in which flip-flops 21 and 22 as 1-bit delay elements are connected in series. The EXOR circuit 23 calculates an exclusive OR of the input in and the output of the flip-flop 22 (2-bit delayed output of the input in), and outputs the result as a code g0. The EXOR circuits 24 and 25 calculate the exclusive OR of the input “in” and the outputs of the flip-flops 21 and 22 (the 1-bit delayed output and the 2-bit delayed output of the input “in”) and output the result as a code g1.

  In the convolutional encoder shown in FIG. 2A, the output is determined by the current and the input in for two cycles immediately before. By inputting the input “in” to the convolutional encoder, the internal state (values held by the flip-flops 21 and 22) in the convolutional encoder and the output codes g0 and g1 are determined. When the state transition of the internal state in the convolutional encoder shown in FIG. 2A is shown in time series, a trellis diagram shown in FIG. 2B is obtained. In FIG. 2B, S00, S01, S10, and S11 indicate internal states in the convolutional encoder. The state Sab indicates a state in which the value “a” is held in the flip-flop 21 and the value “b” is held in the flip-flop 22.

  As shown in FIG. 2B, for example, when the internal state is S00 and the input in is “0”, the code (g0, g1) = (00) is output, the internal state becomes S00, and the input in If “1”, the code (g0, g1) = (11) is output, and the internal state becomes S10. Similarly, when the internal state is S01 and the input in is “0”, the code (g0, g1) = (11) is output and the internal state is S00, and if the input in is “1”, The code (g0, g1) = (00) is output and the internal state is S10. When the internal state is S10 and the input in is “0”, the code (g0, g1) = (01) is output and the internal state is S01. If the input in is “1”, the code (G0, g1) = (10) is output and the internal state becomes S11. When the internal state is S11 and the input in is “0”, the code (g0, g1) = (10) is output and the internal state is S01. If the input in is “1”, the code (G0, g1) = (01) is output and the internal state is S11.

  As shown in FIG. 2B, there are two paths for each state in the trellis diagram. The Viterbi decoding apparatus performs an ACS operation for each state based on the input code from the initial state toward the end state (in the time series direction of the received signal), and is likely to have one of the two paths (high likelihood) ) Select the path as the survival path. In addition, selection path information indicating the surviving path in each state is stored in the path memory. Then, from the end state to the initial state, a traceback process is performed based on the selected path information stored in the path memory, and the most probable path (maximum likelihood path) is determined between the initial state and the end state. Output.

  Here, as is clear from the trellis diagram, there are two states one hour before that can transition to a certain state. For this reason, when the state at time N is determined, the candidates for the states that can be taken at the previous time (N-1) are two, that is, the state that is actually taken and the possible state. In addition, there are two candidate states that can be taken at the previous time (N-2) for the actual state and the possible state at time (N-1). There are four states. For example, as shown in FIG. 3, when the state at time N is confirmed at ST02, the candidate states that can be taken at time (N-1) are the two states ST03 and ST04, and taken at time (N-2). The candidate states to obtain are the four states ST05, ST06, ST07, and ST07.

That is, when the state at time N is determined, there are 2 ^k states that can be taken at the time (N−k) before k times. Therefore, when the Viterbi decoding apparatus according to the present embodiment knows the state at time N, it uses the fact that the state at time k (Nk) before the k time is in 2 ^k states, and traceback is performed. Process. When the state at time N is determined in the traceback process, the Viterbi decoding apparatus according to the present embodiment reads the selected path information (however, k ≧ 2) at time (N−k) from the path memory according to the result, and performs processing. I do. In this way, the memory access is performed at an earlier stage as compared with the conventional traceback process in which the selected path information at time (N-1) is read from the path memory after the state at time N is fixed. To conceal memory access latency and speed up traceback processing.

  Hereinafter, details of the traceback unit 15 of the Viterbi decoding apparatus according to the present embodiment will be described. In the first embodiment described below, a path (state) is determined by one bit per cycle in the traceback process. In the second embodiment, a plurality of bits are passed per cycle in the traceback process. (State) can be determined. In the following description, when a data string is illustrated in bit representation, the upper side or the right side of the illustrated data string is the lower bit side. That is, the uppermost or rightmost bit in the illustrated data string is the least significant bit (LSB), and the lowermost or leftmost bit is the most significant bit (MSB: Most Significant Bit). To do.

(First embodiment)
FIG. 4 is a diagram illustrating a configuration example of the traceback unit in the first embodiment.
In FIG. 4, reference numerals 31, 33, 35, and 37 are data registers, and reference numerals 32, 34, and 36 are arithmetic processing units. Reference numeral 38 denotes a control register, 39 denotes an address generation unit, and 40 denotes a memory. The memory 40 corresponds to the path memory 14 as will be described later, but is shown in FIG. 4 for convenience of explanation.

  The data register 31 holds the data DAT output from the memory 40. The data registers 33, 35, and 37 hold data output from the arithmetic processing units 32, 34, and 36, respectively. The arithmetic processing units 32, 34, and 36 receive the data held in the data registers 31, 33, and 35, respectively. The arithmetic processing units 32, 34, and 36 perform a bit extraction operation for extracting specific bit data from the input data, and output data obtained by the operation (extracted bit data). The control register 38 supplies information (extracted bit number information) that specifies the number of bits to be extracted in the bit extraction operation to the arithmetic processing units 32, 34, and 36.

  In the present embodiment, the number of bits specified by the extracted bit number information from the control register 38 by the arithmetic processing units 32, 34, and 36 is 4 bits, 2 bits, and 1 bit, respectively. Therefore, the significant bits in the output data from the arithmetic processing unit 32 are 4 bits, and the significant bits in the output data from the arithmetic processing unit 34 are 2 bits. Similarly, significant bits are 1 bit in the output data from the arithmetic processing unit 36. The arithmetic processing units 32, 34, and 36 store one significant bit in the output data of the arithmetic processing unit 36 as data register 37 as information (extraction bit position information) for designating the position of the bit to be extracted in the bit extraction operation. Is supplied through. The arithmetic processing units 32, 34, and 36 take out the bit at the position corresponding to the extracted bit position information from the significant bits in the input data.

The memory 40 corresponds to the path memory 14 shown in FIG. The memory 40 stores selected path information indicating surviving paths for each state in the trellis diagram as data. The memory 40 outputs the selected path information stored in the address ADD supplied from the address generation unit 39 as data DAT. The address generation unit 39 receives 1 significant bit in the output data of the arithmetic processing unit 36 via the data register 37, that is, 1 bit output as the final selection result. Based on the input 1-bit selection path information that has been input, the address generation unit 39 has 8 (= 2 ³ ) states that can be taken three times before the time determined by the selection path information. An address ADD for reading the selected path information from the memory 40 is generated and output. For example, if the significant 1-bit selection path information that is input determines the state at time N (referred to as state A), the address generating unit 39 may change to state A at time N (N -3) The address ADD for reading out the information relating to the eight states from the memory 40 is generated.

  Here, the traceback unit shown in FIG. 4 may be configured using a processor having an ALU (Arithmetic and Logic Unit) array as shown in FIG. 5, for example. FIG. 5 is a diagram illustrating a configuration example of a processor having an ALU array. The processor shown in FIG. 5 includes an instruction cache 51, a controller 52, a register file 53, a scalar execution unit 54, a load / store unit 55, a dispatch memory 56, an ALU array 57, an address generation unit 58, and a DMA controller 59.

  The controller 52 performs control related to each functional unit in the processor based on the instruction read from the instruction cache 51. The register file 53 holds data to be calculated. The scalar execution unit 54 performs arithmetic processing according to instructions from the controller 52. The load / store unit 55 executes processing related to the load instruction / store instruction. The load / store unit 55 loads (reads) data from the dispatch memory 56 or the like to a register, or stores (writes) data from the register to the dispatch memory 56 or the like. The dispatch memory 56 is a memory in which data obtained by executing arithmetic processing is stored.

  The ALU array 57 includes a plurality of ALUs arranged in an array and a pipeline register that divides a pipeline stage by the plurality of ALUs. The ALU is an arithmetic unit including a plurality of arithmetic units. The pipeline register is composed of, for example, a flip-flop. The ALU array 57 can process a composite operation with a single instruction. For example, it can process a bit extraction operation for extracting data of a specific bit from input data with a single instruction. The ALU array 57 can perform various arithmetic processes by instructing each ALU which instruction is to be operated and which data is to be used. The address generator 58 generates an address for accessing the dispatch memory 56 from the output of the ALU array 57. The DMA controller 59 performs control related to DMA transfer performed between the dispatch memory 56 in the processor and a device outside the processor.

  For example, the functions of the data registers 31, 33, 35, and 37, the arithmetic processing units 32, 34, and 36, and the control register 38 shown in FIG. 4 are realized by the ALU array 57 shown in FIG. Further, for example, the function of the address generation unit 39 shown in FIG. 4 is realized by the address generation unit 58 shown in FIG. 5, and the function of the memory 40 shown in FIG. 4 is realized by the dispatch memory 56 shown in FIG. By doing so, the traceback unit shown in FIG. 4 can be realized by the processor shown in FIG.

FIG. 6 is a diagram illustrating an internal configuration example of the arithmetic processing unit in the present embodiment.
As illustrated in FIG. 6A, the arithmetic processing unit 71 includes a multiplication unit 72, a shift calculation unit 73, a mask output unit 74, and a logical product calculation unit 75.

  The multiplier 72 receives the extracted bit number information S that specifies the number of bits to be extracted in the bit extraction operation and the extracted bit position information a that specifies the bit position to be extracted. The multiplier 72 multiplies the extracted bit number information S and the extracted bit position information a, and outputs the multiplication result (S × a). The shift calculation unit 73 receives the input data X and the multiplication result (S × a) in the multiplication unit 72. The shift calculation unit 73 shifts the bits of the input data X by (S × a) bits to the right (lower bit side) and outputs the result. That is, the shift calculation unit 73 shifts the (i + (S × a)) bit in the input data X to the i-th bit and outputs it.

  The mask output unit 74 has a table composed of mask patterns selected according to the extracted bit number information S as shown in FIG. 6B, for example. The mask output unit 74 receives the extracted bit number information S and outputs a mask pattern corresponding to the extracted bit number information S. In the example shown in FIG. 6, the value of the extracted bit number information S is set to an integer of 0 to 16, and the mask output unit 74 has a mask pattern corresponding to each value. However, in the traceback processing in the present embodiment, the value of the extracted bit number information S can take only a power integer value of 2, so that the mask output unit 74 outputs only the mask pattern corresponding to the power value of 2 integer. You may make it have. In addition, since the upper limit value of the extracted bit number information S is determined according to the configuration, a mask pattern corresponding to a value larger than the upper limit value of the extracted bit number information S may not be provided.

  The AND operation unit 75 receives the output of the shift operation unit 73 and the output of the mask output unit 74. The AND operation unit 75 performs an AND operation on the output of the shift operation unit 73 and the output (mask pattern) of the mask output unit 74 for each bit, and outputs the operation result as output data Y.

  The arithmetic processing unit 71 configured as described above is the (a + 1) -th data (S + 1) when the input data X is divided in units of S bits from the lower side in accordance with the extracted bit number information S and the extracted bit position information a ( S bit width) is selected and output as output data Y. That is, the arithmetic processing unit 71 performs arithmetic processing represented by Y = {X >> (S * a)} & (mask pattern). Here, “A >> B” represents a B-bit right shift (shift to the lower side) of the data string A.

  For example, if the input data X is “0000_0000_0000_0000_0000_0000_1111_1111” (binary notation), the extracted bit number information S is 1 and the extracted bit position information a is 3, the arithmetic processing unit 71 outputs “0000_0000_0000_0000_0000_0000_0000_0001” as the output data Y. For example, if the input data X is “0000_0000_0000_0000_0000_0000_1111_1111”, the extracted bit number information S is 3, and the extracted bit position information a is 2, the arithmetic processing unit 71 outputs “0000_0000_0000_0000_0000_0000_0000_0011” as the output data Y.

  Next, the operation of the traceback unit in the first embodiment will be described with reference to FIGS. 7 and 8 are diagrams for explaining the operation of the traceback unit in the first embodiment. FIG. 7 shows the flow of processing for information relating to the state at a certain time. FIG. 8 shows the data flow in the traceback unit. 7 and 8, the same components as those shown in FIG. 4 are denoted by the same reference numerals. In FIG. 8, D (31), D (33), D (35), and D (37) are output data of the data registers 31, 33, 35, and 37 (data stored in the registers, respectively). ).

First, the operation will be described with reference to FIG.
In the trace back processing in the first embodiment, the state at time (N + 1) is determined, and the selected path information (“0” or “1”) at the time (N + 1) state is output as the output data of the data register 37. Suppose that The selected path information at the time (N + 1) is supplied to the arithmetic processing units 32, 34, and 36 as the extracted bit position information “a” and also supplied to the address generation unit 39.

  The arithmetic processing unit 36 determines the state at time N (referred to as state A) based on the supplied selected path information at time (N + 1), and outputs the selected path information at time N. Further, the address generation unit 39 relates to the state at the time (N-3) three times before the time N based on the selected path information at the time (N + 1) that determines the state at the time N as described above. An address ADD for reading the selected path information from the memory 40 (path memory 14) is generated and output. The address ADD generated at this time is for reading the selected path information (8 bits) relating to the eight states at the time (N-3) that can become the state A at the time N. As a result, among the selected path information related to the state at the time (N-3) three times before the time N, the selected path information related to the eight states that can be in the state A at the time N is read from the memory 40. Is output to the data register 31 as data DAT. The 8-bit information is byte-loaded when loaded from the memory 40, is arranged in 8 bits from the least significant bit in the data string, and is input to the data register 31.

  Then, in the next clock cycle, the selected path information related to the eight states at time (N-3) is input to the arithmetic processing unit 32 as input data X. Further, “4” is input as the extracted bit number information S to the arithmetic processing unit 32, and the selected path information (“0” or “1”) at the time N state from the data register 37 as the extracted bit position information a. ) Is entered. Based on the selected path information in the state at time N input as the extracted bit position information a, the arithmetic processing unit 32 uses the upper 4 bits from the selected path information in the eight states at time (N-3). Alternatively, the lower 4 bits are selected and output. In this way, the time (N-3) according to the state at the time (N-1) determined by the selected path information at the time N state from the selected path information at the eight states at the time (N-3). The selected path information (4 bits) relating to the four states in (4) is selected and input to the data register 33.

  Further, in the next clock cycle, the selected path information related to the four states at time (N-3) is input to the arithmetic processing unit 34 as input data X. Further, “2” is input as the extracted bit number information S to the arithmetic processing unit 34, and the selected path information at the time (N−1) is input from the data register 37 as the extracted bit position information a. . Based on the selected path information of the state at time (N-1) input as the extracted bit position information a, the arithmetic processing unit 34 determines the higher rank from the selected path information of the four states at time (N-3). 2 bits on the side or 2 bits on the lower side are selected and output. In this way, the time according to the state at time (N-2) determined by the selected path information at the time (N-1) state from the selected path information at the four states at time (N-3). Selected path information (2 bits) relating to the two states in (N-3) is selected and input to the data register 35.

  Subsequently, in the next clock cycle, the selected path information related to the two states at time (N-3) is input to the arithmetic processing unit 36 as input data X. Further, “1” is input to the arithmetic processing unit 36 as the extracted bit number information S, and the selected path information at the time (N−2) is input from the data register 37 as the extracted bit position information a. . Based on the selected path information of the state at time (N-2) that is input as the extracted bit position information a, the arithmetic processing unit 36 determines the higher rank from the selected path information of the two states at time (N-3). 1 bit on the side or 1 bit on the lower side is selected and output. That is, the state at time (N-3) is confirmed, and the selected path information in that state is output.

  The trace back process is executed by sequentially processing the above operations for each clock cycle as shown in FIG. That is, based on the selected path information in the state of time k output from the data register 37, where k is an arbitrary integer, the time (k-4) at which the state (k-1) can be determined is determined. The selected path information related to the eight states is read out. Further, based on the selected path information in the state at time k, states that can be taken at time (k-3), time (k-2), and time (k-1) by the arithmetic processing units 32, 34, and 36. Each is limited to one-half.

  For example, during the period TA shown in FIG. 8, the state of time N determined by the selected path information (time N) at the time (N + 1) output from the data register 37 can be obtained. The selected path information relating to the eight states at time (N-3) is read out. Further, the arithmetic processing unit 32 selects the selected path information at the time (N + 1) (the state at the time N) from the selected path information regarding the eight states at the time (N−2) output from the data register 31. The selected path information related to the four states is selected and output based on the above. Similarly, the arithmetic processing unit 34 selects the selected path information (state at time N) from the selected path information regarding the four states at time (N−1) output from the data register 33. ) To select and output the selected path information relating to the two states. The arithmetic processing unit 36 selects the selected path information relating to the state at time N based on the selected path information relating to the state at time (N + 1) from the selected path information relating to the two states at time N output from the data register 35. Select to output.

According to the first embodiment, when the state at time N is determined, the selected path information of 2 ^k states at time (N−k) before k times that can transit to the state is read from the memory and traced. Perform back processing. As a result, the memory access is performed at an earlier stage as compared with the conventional traceback process in which the selected path information at the time (N−1) is read from the path memory after the state at the time N is fixed and the process is performed. Access latency can be hidden. Further, the determination of the state in the traceback process and the reading of the selected path information from the memory can be performed in parallel, and one bit can be determined for each cycle. Therefore, the traceback process can be executed at a higher speed than in the prior art.

(Second Embodiment)
FIG. 9 is a diagram illustrating a configuration example of the traceback unit in the second embodiment.
In FIG. 9, 91, 93, 95, 97, 98, 100, 102, 103 are data registers, and 92, 94, 96, 99, 101 are arithmetic processing units. Reference numeral 104 denotes a control register, 105 denotes a selection processing unit, and 106 denotes an address generation unit. Reference numeral 107 denotes a memory corresponding to the path memory 14, which is shown in FIG. 9 for convenience of explanation.

  The data register 91 holds the data DTA output from the memory 107, and the data register 98 holds the data DTB output from the memory 107. The data registers 93, 95, 97, 100, and 102 hold data output from the arithmetic processing units 92, 94, 96, 99, and 101, respectively. The data register 103 holds data output from the data register 102.

  The arithmetic processing units 92, 94, 96, 99, and 101 are configured in the same manner as the arithmetic processing unit in the first embodiment shown in FIG. The arithmetic processing units 92, 94, 96, 99, and 101 receive the data held in the data registers 91, 93, 95, 98, and 100, respectively. The arithmetic processing units 92, 94, 96, 99, and 101 perform a bit extraction operation for extracting specific bit data from the input data, and output data obtained by the operation (extracted bit data). The control register 104 supplies extracted bit number information that specifies the number of bits to be extracted in the bit extraction calculation to the arithmetic processing units 92, 94, 96, 99, and 101.

  In the trace back unit in the second embodiment shown in FIG. 9, the number of bits specified by the extracted bit number information from the control register 104 by the arithmetic processing units 92, 94, and 96 is 8 bits, 2 bits, and 1 bit, respectively. It is. The number of bits specified by the arithmetic processing units 99 and 101 by the extracted bit number information from the control register 104 is 4 bits and 1 bit, respectively. Accordingly, the significant bits of the output data from the arithmetic processing unit 92 are 8 bits, and the significant bits of the output data from the arithmetic processing unit 94 are 2 bits. The output data from the arithmetic processing unit 96 Of these, the significant bit is 1 bit. Similarly, significant bits are 4 bits in the output data from the arithmetic processing unit 99, and significant bits are 1 bit in the output data from the arithmetic processing unit 101.

  In addition, the output of the selection processing unit 105 is supplied to the arithmetic processing units 92, 94, 99, and 101 as extracted bit position information that specifies the position of the bit to be extracted in the bit extraction operation. The output of the data register 102 is supplied to the arithmetic processing unit 96 as extracted bit position information. The arithmetic processing units 92, 94, 96, 99, and 101 extract bits at positions corresponding to the extracted bit position information from significant bits in the input data.

  The memory 107 corresponds to the path memory 14 and stores selected path information indicating the surviving path for each state in the trellis diagram as data. The memory 107 outputs the selected path information stored in the address ADD supplied from the address generation unit 106 as data DTA and DTB.

FIG. 10 is a diagram illustrating a configuration example of the selection processing unit 105 illustrated in FIG.
The selection processing unit 105 includes AND circuits (logical product operation circuits) 111 and 112 and an OR circuit (logical sum operation circuit) 113. The AND circuit 111 receives the signal A0 and the signal B0 and outputs the calculation result. In addition, the AND circuit 112 receives the signal A1 and the inverted signal B0, and outputs the calculation result. The OR circuit 113 receives the output of the AND circuit 111 and the output of the AND circuit 112 and outputs the calculation result.

  Here, each of the signals A0, A1, and B0 is a 1-bit signal. Of the significant 2 bits of the output of the data register 95, the upper 1 bit is input as the signal A0, and the lower 1 bit is input as the signal A1. Further, a significant bit of the output of the data register 102 is input as the signal B0. Note that with 1 being an arbitrary number, a significant 1-bit output from the data register 102 is selected path information in the state of time j, and a significant 2-bit output from the data register 95 remains as a candidate (j -1) is the selected path information.

  The selection processing unit 105 selects and outputs one of the signals A0 and A1 according to the signal B0 by the AND circuits 111 and 112 and the OR circuit 113. Further, the selection processing unit 105 outputs the signal B0 as it is. That is, the selection processing unit 105 selects and outputs one bit from the significant two-bit output from the data register 95 according to the significant one-bit output from the data register 102, and also outputs from the data register 102. A significant 1-bit output is output as it is. That is, the selection processing unit 105 outputs the selected path information in the state of time j output from the data register 102, and at the time (j−1) from the output of the data register 95 based on the output from the data register 102. Selects and outputs the selected path information of the state.

FIG. 11 is a diagram illustrating a configuration example of the address generation unit 106 illustrated in FIG. 9.
As shown in FIG. 11A, the address generation unit 106 includes an offset buffer 131, shift calculation units 132 and 134, a logical sum calculation unit 133, a word buffer 135, and constant addition units 136 and 137. Note that FIG. 11A illustrates an example of an address generation unit that is applied to a decoding device that decodes a convolutional code by a convolutional encoder having a constraint length of 9 (the number of states is 256). It is assumed that the selection path information of each state is stored in FIG.

  FIG. 15 is a diagram illustrating an example of an arrangement image of selected path information in each state in the memory 107 (when the number of states is 256). For example, the selected path information related to each state at time N is stored in the area of address values 0 to 31 in the memory 107, and the selected path information related to each state at time (N−1) is stored to the address values 32 to 63 in the memory 107. It is assumed that it is stored in this area. Similarly, it is assumed that the selected path information relating to each state at time (N−k) is stored in the area of address values 32k to (32k + 31) in the memory 107. In FIG. 15, “◯” indicates selected path information in each state, and “0” or “1” is stored.

  The offset buffer 131 is a buffer that holds (k−1) -bit data when the constraint length related to the convolutional code is k. In this example, the offset buffer 131 is a buffer that holds 8-bit data, and includes, for example, eight flip-flops. The offset buffer 131 receives the output of the OR operation unit 133 and holds it. The shift operation unit 132 shifts the output of the offset buffer 131 leftward (upper bit side) by 2 bits, that is, shifts the i-th bit in the output of the offset buffer 131 to the (i + 2) -bit and outputs the result. . The OR operation unit 133 receives the output of the shift operation unit 132 and the 2-bit output from the selection processing unit 105, performs an OR operation on each bit, and outputs an operation result. That is, the offset buffer 131, the shift operation unit 132, and the logical sum operation unit 133 connect the two bits output from the selection processing unit 105 to the lower side of the output of the logical sum operation unit 133 one cycle before, and The upper 2 bits are truncated and output.

  The word buffer 135 is a buffer for holding a word address. The word buffer 135 receives the output of the constant adder 136 and holds it. Here, in this example, one word is 32 bytes. The constant adder 136 receives the output of the word buffer 135, adds “2” thereto, and outputs the result. That is, the word buffer 135 and the constant adder 136 output from the word buffer 135 a value incremented by “2” for each cycle.

  The address generation unit 106 generates addresses address1 and address2 based on the output of the logical sum operation unit 133 and the output of the word buffer 135, and outputs them to the memory 107 as the address ADD. Here, the address address1 is an address for reading data input to the data register 91 as data DTA from the memory 107, and an address address2 is an address for reading data input to the data register 98 as data DTB from the memory 107. It is. The address address1 is a value obtained by adding “1” by the constant adder 136 to the output of the word buffer 135 as the upper side, and the output of the OR operation unit 133 is shifted leftward by 1 bit by the shift operation unit 134 (upper The value shifted to the bit side) is generated by bit concatenation as the lower side. The address address2 is generated by bit concatenation with the output of the word buffer 135 as the upper side and the output of the logical sum operation unit 133 as the lower side. Since the address for accessing the memory 107 is in units of bytes, addresses excluding the lower 3 bits are output as addresses address1 and address2, respectively.

  For example, two bits “b1” and “a1” are input to the address generation unit 106 in the first cycle from the selection processing unit 105, and two bits “b2” and “a2” are input in the second cycle. Assume that two bits “b3” and “a3” are input in the third cycle. Note that the initial values of the offset buffer 131 and the word buffer 135 are each bit “0”. At this time, the address generation unit 106 generates and outputs addresses address1 and address2 for each cycle as shown in FIG. 11B.

Next, the operation of the traceback unit in the second embodiment whose example is shown in FIG. 9 will be described. FIG. 12 is a diagram for explaining the operation of the traceback unit in the second embodiment.
In the traceback processing in the second embodiment, the selected path information (“0” or “1”) at the time N state is output from the data register 102 and the time remaining as a candidate from the data register 95 (N−1) ) State selected path information is output.

  At this time, the selection processing unit 105 selects one of the two-state selection path information at the time (N−1) from the data register 95 based on the selection path information at the time N state from the data register 102. The selection processing unit 105 outputs the selected path information at the time N state from the data register 102 and the selected path information at the time (N−1) state from the selected data register 95. That is, the selection processing unit 105 outputs the selected path information in the state of time N and the selected path information in the state of time (N−1). In addition, the selected path information at the time N state from the data register 102 is supplied to the arithmetic processing unit 96 as the extracted bit position information a, and the arithmetic processing unit 96 generates a time (N−) based on the selected path information at the time N state. The state of 1) is determined (state A), and the selected path information of the state at time (N-1) is output.

  The selected path information at the time N state and the selected path information at the time (N-1) state output from the selection processing unit 105 are supplied to the arithmetic processing units 92, 94, 99, and 101 as the extracted bit position information a. And is supplied to the address generator 106. The address generation unit 106 generates addresses address1 and address2 based on the selected path information at the time N state and the selected path information at the time (N-1) state, and outputs them to the memory 107 as the address ADD. Thus, of the selected path information in the state at time (N-7) six times before time (N-1), 32 states that can be in state A at time (N-1) are selected. The path information (32 bits) is read from the memory 107 and input to the data register 91 as data DTA. Of the selected path information in the state at time (N-6) five times before time (N-1), the selected paths in 16 states that can be in state A at time (N-1). Information is read from the memory 107 and input to the data register 98 as data DTB.

  Then, in the next clock cycle, the selection path information relating to the 32 states at time (N-7) output from the data register 91 is input as input data X to the arithmetic processing unit 92. Further, “8” is input to the arithmetic processing unit 92 as the extracted bit number information S, and the selection path information at the time (N−2) state and the state at the time (N−3) from the selection processing unit 105. Selected path information is input as extracted bit position information a (0 to 3). Based on the extracted bit position information a that has been input, the arithmetic processing unit 92 divides the selected path information related to the 32 states at time (N-7) in units of 8 bits from the lower order (a + 1). The first selected path information (8 bits) is selected and output. In this way, the time according to the state of time (N-4) determined by the selected path information of the state at time (N-3) from the selected path information regarding the 32 states at time (N-7). Selected path information relating to the eight states in (N-7) is selected and input to the data register 93.

  Further, the selection path information relating to the 16 states at time (N-6) output from the data register 98 is input as input data X to the arithmetic processing unit 99. Further, “4” is input to the arithmetic processing unit 99 as the extracted bit number information S, and the selection path information at the time (N−2) state and the state at the time (N−3) from the selection processing unit 105. Selected path information is input as extracted bit position information a (0 to 3). The arithmetic processing unit 99 divides the selected path information related to the 16 states at time (N-6) based on the input extracted bit position information a (a + 1) when divided in units of 4 bits from the lower side. The first selected path information (4 bits) is selected and output. In this way, the time according to the state of the time (N-4) determined by the selected path information of the state at the time (N-3) from the selected path information regarding the 16 states at the time (N-6). Selected path information relating to the four states in (N-6) is selected and input to the data register 100.

  Furthermore, in the next clock cycle, the selected path information relating to the eight states at time (N-7) output from the data register 93 is input to the arithmetic processing unit 94 as input data X. Further, “2” is input to the arithmetic processing unit 94 as the extracted bit number information S, and the selection path information at the time (N−4) state and the state at the time (N−5) from the selection processing unit 105. Selected path information is input as extracted bit position information a (0 to 3). The arithmetic processing unit 94 (a + 1) when the selected path information related to the eight states at time (N-7) is divided in units of 2 bits from the lower side based on the input extracted bit position information a. The first selected path information (2 bits) is selected and output. In this way, the time according to the state at the time (N-6) determined by the selected path information at the time (N-5) from the selected path information at the eight states at the time (N-7). Selected path information relating to the two states in (N-7) is selected and input to the data register 95.

Further, the selected path information relating to the four states at time (N-6) output from the data register 100 is input as input data X to the arithmetic processing unit 101. Further, “1” is input to the arithmetic processing unit 101 as the extracted bit number information S, and the selection path information at the time (N−4) state and the state at the time (N−5) from the selection processing unit 105. Selected path information is input as extracted bit position information a (0 to 3). The arithmetic processing unit 101 divides the selected path information related to the four states at the time (N-6) based on the input extracted bit position information a in units of 1 bit from the lower order (a + 1). The first selected path information (1 bit) is selected and output. In this manner, the state at time (N-6) is determined based on the selected path information at the state at time (N-5), and the selected path information at that state is input to the data register 102.
The trace back process is executed by performing the above operations in parallel for two clocks sequentially for each clock cycle and performing the process for each time.

  In the above description, the traceback unit that outputs the result of 2 bits during one cycle is shown as an example. However, the present invention is not limited to this. A traceback unit that outputs a result of an arbitrary plurality of bits per cycle can be configured. For example, a traceback unit that outputs a 3-bit result per cycle may be configured as shown in FIG.

FIG. 13 is a diagram illustrating another configuration example of the traceback unit in the second embodiment.
In FIG. 13, 151, 153, 155, 157, 158, 160, 162, 163, 164, 166, 167, 168 are data registers, and 152, 154, 156, 159, 161, 165 are arithmetic processing units. . Reference numeral 169 denotes a control register, 170 denotes a selection processing unit, and 171 denotes an address generation unit. Reference numeral 172 denotes a memory corresponding to the path memory 14, which is shown in FIG. 13 for convenience of explanation.

  The data registers 151, 158 and 164 hold the data output from the memory 172. The data registers 153, 155, 157, 160, 162, and 166 hold data output from the arithmetic processing units 152, 154, 156, 159, 161, and 165, respectively. The data registers 163, 167, and 168 hold the data output from the data registers 162, 166, and 167, respectively.

  Each of the arithmetic processing units 152, 154, 156, 159, 161, and 165 is configured in the same manner as the arithmetic processing unit in the first embodiment shown in FIG. The arithmetic processing units 152, 154, 156, 159, 161 and 165 receive the data held in the data registers 151, 153, 155, 158, 160 and 164, respectively. The arithmetic processing units 152, 154, 156, 159, 161, and 165 perform a bit extraction operation for extracting specific bit data from the input data, and output data obtained by the operation (extracted bit data). The control register 169 supplies extracted bit number information that specifies the number of bits to be extracted in the bit extraction operation to the arithmetic processing units 152, 154, 156, 159, 161, and 165.

  In the traceback unit illustrated in FIG. 13, the number of bits specified by the extracted bit number information from the control register 169 by the arithmetic processing units 152, 154, and 156 is 4 bits, 2 bits, and 1 bit, respectively. The number of bits specified by the arithmetic processing unit 159 by the extracted bit number information from the control register 169 is 2 bits, and the arithmetic processing units 161 and 165 specify the number of bits specified by the extracted bit number information from the control register 169. Is 1 bit.

  In addition, the output of the selection processing unit 170 is supplied to the arithmetic processing units 152, 159, and 165 as extracted bit position information that specifies the position of the bit to be extracted in the bit extraction operation. The arithmetic processing units 154 and 161 are supplied with the output of the data register 166 as extracted bit position information, and the arithmetic processing unit 156 is supplied with the output of the data register 162 as extracted bit position information. The arithmetic processing units 152, 154, 156, 159, 161, and 165 take out the bit at the position corresponding to the extracted bit position information from the significant bits in the input data.

  The memory 172 corresponds to the path memory 14 and stores selected path information indicating surviving paths for each state in the trellis diagram as data. The memory 172 outputs the selected path information stored at the address supplied from the address generation unit 171 as data.

FIG. 14 is a diagram illustrating a configuration example of the selection processing unit 170 illustrated in FIG.
The selection processing unit 170 includes selector circuits 191 to 194. The selector circuit 191 receives significant 2 bits at the output of the data register 160 and significant 1 bit at the output of the data register 166. Based on the 1-bit output from the data register 166, the selector circuit 191 selects 1 bit from significant 2 bits in the output of the data register 160 and outputs it to the outside.

The selector circuits 192 and 193 receive 2 significant bits at the output of the data register 153 and 2 significant bits at the output of the data register 166. The selector circuits 192 and 193 select and output 1 bit from 2 bits input from the data register 166 based on the 1-bit output from the data register 166. The selector circuit 194 receives the outputs of the selector circuits 192 and 193 and the output of the selector circuit 191. The selector circuit 194 selects and outputs one of the outputs of the selector circuits 192 and 193 based on the output of the selector circuit 191. That is, the selector circuits 192, 193, 194 select one significant bit from the significant 4 bits in the output of the data register 153 based on the output of the data register 166 and the output of the selector circuit 191 and output the selected bit to the outside.
A significant bit in the output of the data register 166 is also output to the outside as it is.

  According to the above configuration, the selection processing unit 170 outputs the selected path information in the state of the time j output from the data register 166 and, based on the output from the data register 166, the time ( The selected path information in the state of j-1) is selected and output. Further, the selection processing unit 170 determines the time from the output of the data register 153 based on the output from the data register 166 and the selected path information of the state at the time (j−1) selected from the output of the data register 160 based on the output. The selected path information in the state (j-2) is selected and output.

  Note that the operation of the trace back unit shown in FIG. 13 is different in the relative relationship of the times that the arithmetic processing units 152, 154, 156, 159, 161, and 165 calculate, but the trace shown in FIG. The basic operation is the same as that of the back section.

According to the second embodiment, as in the first embodiment, the memory access latency can be concealed by performing memory access earlier than the conventional traceback processing, and the state of the traceback processing can be hidden. Confirmation and reading of the selected path information from the memory can be performed in parallel. Further, the state at a plurality of times can be determined during one cycle period simply by arranging a plurality of arithmetic processing units as shown in FIG. 6 capable of performing the bit extracting operation in parallel. Therefore, it is possible to determine the data for 1 bit in one cycle or less, and the traceback process can be executed at high speed.
The traceback unit in the second embodiment shown in FIGS. 9 and 13 may be configured using a processor having an ALU array as shown in FIG. 5 as in the first embodiment. good.

  In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 11 Branch metric calculating part 12 ACS calculating part 13 Path metric memory 14 Path memory 15 Trace back part 31, 33, 35, 37 Data register 32, 34, 36 Operation processing part 38 Control register 39 Address generation part 40 Memory

Claims (5)

An arithmetic unit that calculates a survivor path in the trellis diagram based on the convolutionally encoded data;
A memory unit for storing path information indicating a surviving path obtained by the arithmetic unit;
A traceback unit that traces back state transitions in the trellis diagram based on the path information stored in the memory unit and outputs a decoding result;
The traceback unit is
When the state at time N is determined to be the first state, among the states at time (N−k) before k times (k is a predetermined integer equal to or greater than 2) with respect to time N, A Viterbi decoding apparatus, wherein the path information of 2 ^k states at a time (Nk) at which transition to one state can be performed is read from the memory unit and processed. The traceback unit is
A read address is generated based on information indicating that the state at time N is the first state, and the path information of 2 ^k states at time (N−k) is ^obtained from the memory unit. reading,
According to the state of each time from time (N−1) to time (N−k + 1) sequentially determined from the path information of 2 ^k states at the time (N−k) read out, the state The Viterbi decoding apparatus according to claim 1, wherein the path information in the state at the time (N−k) that can transit to is sequentially selected.   3. The Viterbi decoding apparatus according to claim 1, wherein the information indicating that the state at the time N is the first state is the path information at the determined time (N + 1). 4.   4. The Viterbi decoding apparatus according to claim 1, wherein the traceback unit determines a state of a plurality of consecutive times during one cycle period. The traceback unit is
A plurality of the path information in the state at the time (N−k) that can transit to the state according to the state at each time from the time (N−1) to the time (N−k + 1) that are sequentially determined. The arithmetic circuit of
5. The Viterbi decoding apparatus according to claim 1, further comprising a plurality of registers that hold the path information selected by the arithmetic circuit.

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