JP5177028B2 - Decryption device - Google Patents

Description

  The present disclosure relates generally to electronic circuits, and more particularly to a decoding device.

  In wireless communication, errors due to noise on the communication path occur. As a countermeasure against such an information error, information with high redundancy is generated and transmitted by code conversion according to a predetermined rule on the transmission side. On the receiving side, even if a certain amount of information error is included in the received information, the decoding process is performed based on the recognition that the transmission information should comply with the above rules, thereby correcting the error and correcting the error. Can be restored.

  As such a decoding technique, there is a Viterbi decoding process for maximum likelihood estimation of a convolutionally encoded signal. In the Viterbi decoding process, an ACS (Add, Compare, Select) process and a traceback process are executed. At this time, a trellis diagram showing the internal state at each time and the transition path from the internal state at a certain time to the internal state at the next time is used.

  In the ACS, first, in the trellis diagram, the distance between each path that transitions from each internal state at the time of interest N to the internal state at the next time N + 1 and the received data is calculated as a branch metric. By adding this branch metric to the path metric of the entire route up to the target time N, the path metric of the route up to the next time N + 1 is calculated. Further, for each internal state at time N + 1, path metrics are compared between two routes that reach the same internal state, and the one with a small metric value (distance) is selected. For each internal state at time N + 1, 1-bit information indicating which of the two paths reaching from one hour before is selected is assigned. This 1-bit information is data indicating a surviving path and is stored in the path memory. By repeating the above processing, surviving path data is stored in the path memory for each internal state from the initial time to the final time.

  In the traceback, the transmission data is restored (decoded) by following the path selected by the ACS process forward from the final internal state. Specifically, surviving path data corresponding to the target internal state at the target time is read from the path memory. Whether the read data is 0 or 1 indicates which of the two internal states that can be taken one hour before is the one with the highest likelihood. The internal state one hour before is determined according to the read surviving path data. By determining the internal state, a decoding result at the time is obtained. By repeating the reading of data from the path memory and the determination of the internal state one time ago, the entire received data is decoded.

  As described above, in the conventional traceback, data is read from the path memory every time in the decoding process at each time. Thus, accessing the memory every time is inefficient, and the processing time of the Viterbi decoding process becomes long.

JP-A-10-150369 Japanese Patent No. 3358996 JP-A-11-74800 JP 2007-174561 A

  In view of the above, there is a demand for a decoding device that has high memory access efficiency in traceback of Viterbi decoding processing and can execute decoding processing at high speed.

The decoding apparatus includes a state register that stores data indicating an internal state at the time of interest, and a memory that stores surviving path data of the first bit number for each time for all times, and a predetermined preceding time from the time of interest. The partial data of the surviving path data having a second bit number smaller than the first bit number for each of the plurality of times until is selected according to the contents of the status register, and the partial data is read for each of the plurality of times One bit is selected according to the contents of the status register from the partial data at the last time among the plurality of times, and at any time that is not the last time among the plurality of times. In the bit selection process for selecting one bit from the partial data, the last time from the time after the arbitrary time is selected. An arithmetic unit that selects one bit from the partial data for each of the plurality of times by selecting bits according to the partial data at one or more times until the time and the contents of the status register; only containing, the arithmetic unit includes a plurality of selectors provided corresponding to said plurality of times, the 1 bit from the partial data at an arbitrary time is not the last time of the plurality of times The selector to select selects at least the 1-bit selector output respectively selected by the corresponding selector from the partial data at one or more times from the time following the arbitrary time to the last time as an input. characterized in that it.

  According to at least one embodiment of the present disclosure, since survivor path data is read from a memory and trace back processing is performed for a plurality of times, a high-speed decoding process with high memory access efficiency is realized. be able to.

It is a figure which shows an example of a structure of a decoding apparatus. It is a figure which shows a trellis diagram. It is a figure for demonstrating survival path data. It is a figure which shows an example of a structure of an address generator. It is a figure which shows the storage position of the survival path data in a memory bank. It is a figure which shows packing of the data read from the memory. It is a figure which shows an example of a structure of the calculator which performs a trace back. It is a figure for demonstrating operation | movement of each selector of a calculating unit. It is a figure explaining the update operation of a status register. It is a figure which shows the execution efficiency at the time of applying the structure which collects a trace back process with respect to several time with respect to various different time numbers. It is a figure which shows the modification of a structure of an address generator. It is a figure which shows another example of a structure of an address generator. It is a figure which shows the input / output relationship of a computing unit at the time of using the general purpose register shown in FIG. 12 as a status register. It is a figure explaining the update operation of a status register. It is a figure which shows an example of a structure of an OFDM receiver.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram illustrating an example of a configuration of a decoding device. A decoding device 10 shown in FIG. 1 includes an instruction unit 11, a register file 12, an arithmetic unit 13, and a memory access unit 14. The decryption device 10 is connected to the memory banks 20-1 to 20-4 that store the surviving path data.

  The decoding device 10 may be configured by combining a processing device such as a CPU (Central Processing Unit) and dedicated hardware. For example, the instruction unit 11 is a part that performs a control operation on each part of the decoding apparatus 10 by decoding and executing an instruction sequence read from the memory, and corresponds to a process execution part of the CPU. The register file 12 is a part that stores data used when the instruction unit 11 executes various processes, and corresponds to a general-purpose register of the CPU. The arithmetic unit 13 includes a Viterbi arithmetic unit 16 and corresponds to dedicated hardware for performing predetermined processing. The Viterbi computing unit 16 includes at least a computing unit for executing the traceback processing of the present invention, and may further include a computing unit for executing the ACS processing.

  The memory access unit 14 includes an address generator 17 and a packing unit 18. The address generator 17 generates a read address for selectively reading partial data of desired survivor path data from each of the memory banks 20-1 to 20-4, and each of the memory banks 20-1 to 20-4. Is supplied with a read address. The packing unit 18 combines the partial data of the surviving path data read from each of the memory banks 20-1 to 20-4 in accordance with the read address generated by the address generator 17 into one data. The packing unit 18 supplies the collected data to the register file 12.

  FIG. 2 is a diagram showing a trellis diagram. In FIG. 2, each ◯ mark corresponds to the internal state at each time. The internal state here corresponds to the state of 0 or 1 in a plurality of internal registers of the convolutional encoder on the transmission side. If the number of internal states at each time is, for example, 256, each internal state (each circle mark in the figure) corresponds to one bit pattern indicated by 32-bit data. For example, “00000000” is one internal state, and “00000001” is another internal state. There are two paths for each internal state to transition from the internal state at a certain time (for example, N-2) to the internal state at the next time (N-1). This is because when 1-bit transmission data is input to the encoder on the transmission side and the internal state transitions by this 1-bit input, the next transition from the current internal state corresponds to 0 or 1 of the input 1-bit. It shows that there are two internal states. Further, there are two paths for each internal state to transition from the internal state at the previous time (N-3) to the internal state at a certain time (for example, N-2). This is because when 1-bit transmission data is evicted and the internal state transitions in response to 1-bit transmission data input to the encoder on the transmission side, the current internal state corresponds to 0 or 1 of 1-bit to be evicted. It shows that there are two internal states before the transition to the state.

  Through the above-described ACS processing, 1-bit information indicating which of the two routes reaching from one hour ago is selected for each internal state at each time. This 1-bit information is data indicating a surviving path.

  FIG. 3 is a diagram for explaining survival path data. Internal states 30 through 36 are shown for times N-2 through N. In order to make the illustration easy to see, the circles indicating other internal states are not shown. A value of 0 or 1 shown inside the circle of each internal state is the surviving path data of the internal state. Also, the two routes leading to each internal state are associated with the surviving path data value, the upper route is associated with 0, and the lower route is associated with 1. When surviving path data is assigned to each internal state at each time by the ACS process, the likely path is traced forward by the traceback process.

  In the example of FIG. 3, consider a case where a plausible route is traced forward from the internal state 30 at time N. First, the surviving path data of the internal state 30 at time N is referred to. The value of this surviving path data is zero. Therefore, the upper path of the two paths leading to the internal state 30 is the surviving path, and the internal state 31 is likely to be the internal state at the time N−1 that is the source of transition to the internal state 30. Therefore, next, the surviving path data of the internal state 31 at time N-1 is referred to. The value of this surviving path data is 1. Therefore, the lower path of the two paths reaching the internal state 31 is the surviving path, and the internal state 34 is likely to be the internal state at the time N-2 from which the transition to the internal state 31 is made. In this way, the maximum likelihood path as shown by the thick line in FIG. 3 is found.

  Returning to FIG. 2, consider a case where a likely route is traced forward from the hatched internal state 25 at time N. In this case, of the internal states at time N-1, the internal states that can transition to the internal state 25 at time N are the two internal states hatched at time N-1. Among the internal states at time N-2, the internal states that can finally reach the internal state 25 at time N are the four internal states hatched at time N-2. Further, among the internal states at time N-3, the internal states that can finally reach the internal state 25 at time N are the eight internal states that are hatched at time N-3.

  Therefore, when tracing back from the internal state 25 at time N, it may be necessary for the traceback process for the previous time N−1 without referring to the value of the surviving path data in the internal state 25 at time N. The number of viable survivor path data is limited. That is, the surviving path data that may be necessary for the traceback process at time N-1 is surviving path data in the two internal states hatched at time N-1. Similarly, the number of surviving path data that may be required for the traceback process for the previous time N-2 is limited. That is, the surviving path data that may be necessary for the traceback process at time N-2 is surviving path data in the four internal states hatched at time N-2. Further, similarly, for the time N-3, the surviving path data that may be necessary for the traceback processing is the surviving path data in the eight internal states hatched at the time N-3.

  Let us consider reading the surviving path data for a plurality of times preceding the time of interest collectively without reading the surviving path data one hour before from the memory every time at the time of the traceback process. For example, if the number of internal states is 256, the surviving path data has 256 bits at each time. Therefore, it is not possible to read all the surviving path data for a plurality of times preceding the target time without considering that the number of surviving path data that may be necessary for the traceback process is limited. Considering the bus width etc., it is practically impossible. However, as shown in FIG. 2, the survivor path data that may be required for the traceback process is limited. By taking this into consideration, survivor path data that may be necessary for the traceback process can be read out collectively for a plurality of times. This is possible because the bit width of the data to be read is relatively small (for example, the bit width of the data to be read at time N-3 is 8).

  The decoding device 10 shown in FIG. 1 is connected to four memory banks 20-1 to 20-4. This corresponds to a case where the surviving path data at four times from the time of interest to the previous preceding time three times are read together. For example, when the surviving path data at two times from the time of interest to the previous preceding time are read together, the number of memory banks may be two. Similarly, in the case where the surviving path data at eight times from the time of interest to the seven preceding preceding time are read together, the number of memory banks may be eight. In the present invention, the number of surviving path data to be read collectively, that is, the number of times to read the surviving path data collectively is not limited to a specific number.

  FIG. 4 is a diagram illustrating an example of the configuration of the address generator 17. The address generator 17 includes an address connection unit 41 and address buffers 42-1 to 42-4. The general purpose registers 12A and 12B may be general purpose registers in the register file 12 of FIG. The general-purpose register 12A stores, as a base address, the start address of an area where surviving path data at each time is stored in the memory space. The base address of the general-purpose register 12A is counted up or down as appropriate according to the processing target time. The general-purpose register 12B functions as a state register that stores data indicating the internal state at the time of interest. For example, in FIG. 2, when the path is traced forward from the internal state 25 at the time of interest N, the bit pattern of the internal state 25 is stored in the general-purpose register 12B. In this example, the internal state is 8 bits, and there are 256 internal states for each time. Note that the number of internal states is not limited to 256, and may be any number of internal states. The number of bits in the status register is a number corresponding to the number of internal states.

  The address connection unit 41 supplies predetermined 5 bits among the 8-bit data “abcdefgh” stored in the general-purpose register 12B to the address buffers 42-1 to 42-4 as lower 5 bits. The address connection unit 41 further supplies the base address stored in the general-purpose register 12A as upper bits to the address buffers 42-1 to 42-4.

  Specifically, “abcde” of the 8-bit data “abcdefgh” is supplied to the address buffer 42-1 as the lower 5 bits. Also, “bcdef” of the 8-bit data “abcdefgh” is supplied to the address buffer 42-2 as the lower 5 bits. Also, “cdefg” of the 8-bit data “abcdefgh” is supplied to the address buffer 42-3 as the lower 5 bits. Further, “defgh” of the 8-bit data “abcdefgh” is supplied to the address buffer 42-4 as the lower 5 bits. Here, the storage address ards_4k-0 of the address buffer 42-1 is an address for reading surviving path data at the time of interest. The storage address ards_4k-1 of the address buffer 42-2 is an address for reading the surviving path data at the time immediately before the time of interest. The storage address ards_4k-2 of the address buffer 42-3 is an address for reading the surviving path data at the time two times before the time of interest. The storage address ards_4k-3 of the address buffer 42-4 is an address for reading surviving path data at a time three times before the time of interest.

  One byte (8-bit partial data) is selected from the 256-bit surviving path data at each time by the lower 5 bits of the address buffers 42-1 to 42-4. That is, when 256-bit surviving path data is considered as 32 pieces of 1-byte data, 1 byte of 32 bytes is selected by a 5-bit address. As can be seen from FIG. 2, when attention is paid to an internal state having a certain time of interest, the position of the internal state immediately before the transition to the target internal state depends on the position of the target internal state. Therefore, the position of the internal state at the time immediately before the transition to the target internal state can be specified from the position information of the internal state of interest. Similarly, from the information on the position of the target internal state, it is possible to specify the position of the internal state at the time two times before that can be shifted to that. Furthermore, the position of the internal state at the previous three times can also be specified. Such position dependency is constant regardless of time. Since there is such a dependency relationship, it is possible to identify an internal state that can transition to the target internal state at the target time based on the bit pattern “abcdefgh” of the internal state indicating the position of the target internal state at the target time. . That is, it is possible to specify the position of the surviving path data that may be necessary for the traceback processing within the memory.

  FIG. 5 is a diagram showing the storage position of the surviving path data in the memory banks 20-1 to 20-4. .., 4k-3, 4k-2, 4k-1, and 4k are shown in the columns of time 0, 1, 2, 3,. , 4k-3, 4k-2, 4k-1, 4k, the 256-bit chunk of the surviving path data. If there are a total of N + 1 times, 0, 1, 2, 3,..., 4k-3, 4k-2, 4k-1, 4k correspond to times 0-N. In FIG. 5, in order to clearly indicate that data is stored every four times in each memory bank, 4 k that is four times the variable is used as a variable.

  Thus, the memory banks 20-1 to 20-4 store the surviving path data of the first bit number (for example, 256 bits) for each time for all times. The address generator 17 of the memory access unit 14 states the partial data of the surviving path data having a second bit number (for example, 8 bits) smaller than the first bit number for each of a plurality of times from the time of interest to a predetermined preceding time. The selection is made according to the contents of the register 12B. That is, 8-bit data (byte data) is selected by address generation as shown in FIG. The partial data selected in this way is read out in parallel from each of the memory banks 20-1 to 20-4 for each of a plurality of times (for example, the time of interest, one hour before, two hours before, three times before). It is.

FIG. 6 is a diagram illustrating packing of data read from the memory. In FIG. 6, the same components as those in FIGS. 1 to 5 are referred to by the same numerals, and a description thereof will be omitted. The packing unit 18 shown in FIG. 1 collects 8-bit data read in parallel from each of the memory banks 20-1 to 20-4, generates one 32-bit data, and stores it in the register file 12. This 32-bit data is supplied. Hereinafter, the general-purpose register 12C in the register file 12 that stores 32-bit data is referred to as a packed path memory PPM.

  FIG. 7 is a diagram illustrating an example of a configuration of an arithmetic unit that executes traceback. The computing unit 51 shown in FIG. 7 may be included in the Viterbi computing unit 16 shown in FIG. The computing unit 51 receives the lower 3 bits of the stored data of the general-purpose register 12B which is a status register (the contents of which are shown as array data state [7: 0]) and the stored data of the packed path memory 12C. The computing unit 51 outputs the surviving path data selected from the stored data in the packed path memory 12C to the general-purpose register 12D as the computation result.

  As described above, the packed path memory 12C has 4 partial data (8-bit surviving path data) for each of a plurality of times (in this example, the time of interest, one hour before, two hours before, and three times before). Is stored. The computing unit 51 includes selectors (multiplexers) 52 to 55. The selector 52 selects 1 bit according to the contents of the status register 12B from the partial data (1 byte data) at the last time (time of interest) among the plurality of times. The selectors 53 to 55 perform bit selection processing for selecting one bit from partial data (1 byte data) at an arbitrary time that is not the last time among the plurality of times. In this bit selection process, bit selection is performed in accordance with partial data (one byte data) at one or more times from the next time to the last time of the arbitrary time and the contents of the status register 12B. Thereby, one bit is selected from the partial data of the surviving path data for each of the plurality of times.

  FIG. 8 is a diagram for explaining the operation of each selector of the computing unit 51. In FIG. 8, the same components as those of FIG. 7 are referred to by the same numerals. For example, in the lower 8 bits of the packed path memory 12C, the partial data “0101010010” of the surviving path data at the current time 4k is stored. The selector 52 selects the darkly hatched bit “0” from the partial data “01010010” based on the value of the lower 3 bits “fgh” of the contents of the status register. Specifically, since “fgh” is “010”, the least significant bit is b0, and the second bit b2 is selected. This means that one of the 32 bytes out of 256 bits is selected by the upper 5 bits “abcde” in the contents “abcdefgh” of the status register, and 1 bit in 1 byte is selected by the remaining 3 bits “fgh”. It corresponds to the selection.

  When the selectors 53 to 55 select one bit from partial data at a time other than the last time 4k among the times 4k-3 to 4k, one or a plurality of selectors 53 to 55 from the next time to the last time 4k are selected. At least one bit selected from the partial data at the time is used. This will be described below.

  The selector 53 includes selectors 53A and 53B. In the packed path memory 12C, for example, the second 8 bits from the bottom store the partial data “11101001” of the surviving path data 4k−1 one hour before the current time. The selector 53A selects the 0th, 2nd, 4th, and 6th bits b0, b2, b4, and b6 from the partial data “11101001” according to the value of the 1 bit “0” selected by the selector 52. The selector 53B selects the bit b4 among the bits b0, b2, b4, and b6 according to the lower 2 bits “gh” of the contents of the status register. That is, since “gh” is “10”, the least significant bit b0 is set to 0th in the arrangement of bits b0, b2, b4, and b6, and the second bit b4 from the bottom is selected. The bit b4 is a bit “1” that is deeply hatched.

  The selector 54 includes selectors 54A to 54C. For example, the third 8 bits from the bottom of the packed path memory 12C store the partial data “110000001” of the surviving path data 4k-2 two hours before the current time. The selector 54A selects the 0th, 1st, 4th, and 5th bits b0, b1, b4, and b5 from the partial data “11000001” according to the value of 1 bit “0” selected by the selector 52. The selector 54B selects bits b0, b1, b4, b5 from b1, b5 according to the value of 1 bit “1” selected by the selector 53. Further, the selector 54C selects the bit b1 of the bits b1 and b5 according to the least significant bit “h” of the contents of the status register. That is, since “h” is “0”, the 0th bit b1 from the bottom is selected in the sequence of bits b1 and b5. The bit b1 is a deeply hatched bit “0”.

  The above-described processing of the selectors 53 and 54 is bit selection processing for selecting one bit from partial data at an arbitrary time that is not the last time k and is not the first time 4k-3. In this bit selection process, bit selection is performed in accordance with one bit selected from partial data at one or more times from the next time to the last time of the bit selection target time and the contents of the status register.

  Furthermore, a bit selection process for selecting one bit from partial data at the first time among a plurality of times will be described below. In this bit selection process, bit selection is performed according to one bit selected from partial data at one or a plurality of times from the next time 4k-2 to the last time 4k after the first time 4k-3. The selector 55 includes selectors 55A to 55C. For example, the fourth 8 bits from the bottom of the packed path memory 12C store the partial data “11100101” of the surviving path data 4k-3 three times before the current time. The selector 55A selects the 0th, 1st, 2nd, and 3rd bits b0, b1, b2, and b3 from the partial data “11100101” according to the value of the 1 bit “0” selected by the selector 52. The selector 55B selects bits b0, b1, b2, and b3 to b2 and b3 according to the value of 1 bit “1” selected by the selector 53. Further, the selector 55C selects bits b2 to b2 according to the value of 1 bit “0” selected by the selector 54. The bit b2 is a bit “0” that is darkly hatched.

  As described above, the surviving path data 0, 1, 0, 1 are sequentially selected to become decoded data “ijkl”. The decoded data “ijkl” is stored in the general-purpose register 12D as shown in FIG. As described below, the contents “abcdefgh” of the current status register is updated with the data “ijkl”.

  FIG. 9 is a diagram for explaining the update operation of the status register. When the decoding process (traceback process) is completed for the times 4k-3 to 4k, the decoding process (traceback process) is performed for the next times 4 (k-1) -3 to 4 (k-1). Execute. At this time, the time 4 (k−1) is the time of interest, but it is necessary to obtain the maximum likelihood internal state of this time of interest. In the example of the trellis diagram of FIG. 2, the number of internal states at each time is 16, and the internal state is 4 bits. In the figure, the internal state at the top is “0000”, the internal state at the bottom is “1111”, and the internal states are arranged so that the binary value increases from top to bottom in the meantime. It is out. Examining the transition pattern of this trellis diagram reveals the following. If the upper path (“0”) is selected when tracing forward from a certain internal state, the 4-bit bit pattern of the internal state is shifted 1 bit to the left (doubled), and the lowest bit is set to “0”. The value of the inserted lower 4 bits is the internal state one hour before. If the lower path ("1") is selected when tracing forward from the internal state, the 4-bit bit pattern of the internal state is shifted 1 bit to the left (doubled), and the lowest bit is "1". The 4-bit value with inserted is the internal state one hour before. Here, the values of “0” in the upper path and “1” in the lower path are the values of the selected 1-bit survivor path data. Therefore, the internal state at time 4 (k−1) is “efghijkl” obtained by shifting the original internal state “abcdefgh” to the left by 4 bits and inserting the decoded data “ijkl” into the lower 4 bits.

  In FIG. 9, the general-purpose register 12D stores the decoded data “ijkl” calculated by the calculator 51. First, the contents “abcdefgh” of the general-purpose register 12B, which is a status register, are shifted to the left by 4 bits to become “efgh0000”. Next, an OR operation is performed on the contents “efgh0000” of the general-purpose register 12B and the contents “0000ijkl” of the general-purpose register 12D to update the contents of the general-purpose register 12B, which is a status register, to “efghijkl”. The bit shift process and the OR process may be executed as a normal CPU shift instruction and arithmetic instruction by the instruction unit 11 of FIG. In this case, the bit shift process and the OR process each take one cycle, and the entire status register update takes two cycles in total.

  In the conventional configuration, the traceback processing at each time requires one cycle for reading the memory and two cycles for updating the status register, which requires three cycles in total. Therefore, if the traceback process is performed for four times, it takes 12 cycles. On the other hand, in the configuration in which the traceback processing is performed collectively for the plurality of times described above, it takes 1 cycle for memory reading, 1 cycle for decoding operation (bit selection processing in FIG. 8), 2 cycles for status register update, It will take 4 cycles in total. Therefore, the conventional 12 cycles are shortened to 4 cycles, and a significant speed improvement can be realized.

  FIG. 10 is a diagram showing the execution efficiency when the configuration in which the traceback processing is collectively performed for a plurality of times is applied to various numbers of times. As described in the above embodiment, when the number of times for performing the traceback processing collectively is 4 (the number of stages N = 4 in FIG. 10), the number of memory banks is 4, the bit width of partial data is 8, and the packed data The width of the path memory is 32 and the number of execution cycles is 4. At this time, the execution efficiency indicating the number of cycles per stage is 1.00. The number of stages N = 1 in FIG. 10 corresponds to the configuration of the prior art, and the execution efficiency is 4.00. Also, for example, when the number of multiple times of traceback processing collectively is 2 (number of stages N = 2 in FIG. 10), the number of memory banks is 2, the bit width of partial data is 2, and the width of the packed path memory is 4. The number of execution cycles is 4. The execution efficiency in this case is 2.00.

  FIG. 11 is a diagram illustrating a modification of the configuration of the address generator 17. In FIG. 11, the same components as those of FIG. 4 are referred to by the same numerals, and a description thereof will be omitted. The address generator 17 includes an address connection unit 41B and address buffers 42-1 to 42-4. Each of the general-purpose registers 12B-1 to 12B-4 is a register that stores necessary bits in data indicating an internal state at a corresponding time. The address connection unit 41B supplies the data stored in the general-purpose registers 12B-1 to 12B-4 to the respective address buffers 42-1 to 42-4 as the lower 5 bits. Specifically, the stored data “abcde” of the general-purpose register 12B-1 is supplied to the address buffer 42-1 as the lower 5 bits. The stored data “bcdef” in the general-purpose register 12B-2 is supplied to the address buffer 42-2 as the lower 5 bits. The stored data “cdefg” of the general-purpose register 12B-2 is supplied to the address buffer 42-3 as the lower 5 bits. Further, the data “defgh” stored in the general-purpose register 12B-4 is supplied to the address buffer 42-4 as the lower 5 bits. With such a configuration, the connection configuration of the address connection unit 41B can be simplified.

  FIG. 12 is a diagram showing still another example of the configuration of the address generator 17. 12, the same components as those in FIG. 4 are referred to by the same numerals, and a description thereof will be omitted. The address generator 17 includes an address connection unit 41E and address buffers 42-1 to 42-4. The general-purpose register 12E is a 32-bit register that collectively stores necessary bits of data indicating the internal state at a plurality of times. The address connection unit 41E supplies four 5-bit data appropriately selected from the 32-bit data stored in the general-purpose register 12E to the address buffers 42-1 to 42-4 as the lower 5 bits.

  Specifically, “abcde” of the lower 8 bits of data “abcdefgh” of the address connection unit 41E is supplied to the address buffer 42-1 as lower 5 bits. Also, “bcdef” of the second 8-bit data “bcdefgh_” from the bottom of the address connection unit 41E is supplied to the address buffer 42-2 as the lower 5 bits. Further, “cdefg” of the third 8-bit data “cdefgh__” from the bottom of the address connection unit 41E is supplied to the address buffer 42-3 as the lower 5 bits. Further, “defgh” of the fourth 8-bit data “defgh___” from the bottom of the address connection unit 41E is supplied to the address buffer 42-4 as the lower 5 bits. Here, a blank “_” bit is don't care. With such a configuration, the connection configuration of the address connection unit 41E can be made relatively simple.

  FIG. 13 is a diagram showing the input / output relationship of the arithmetic unit when the general-purpose register 12E shown in FIG. 12 is used as a status register. In FIG. 13, the same components as those of FIG. 7 are referred to by the same numerals, and a description thereof will be omitted. The lower 3 bits of the general-purpose register 12E which is a status register (the contents of which are indicated as array data state [31: 0]) are input to the computing unit 51. The computing unit 51 outputs the surviving path data selected from the stored data in the packed path memory 12C to the 32-bit general-purpose register 12E as the computation result. At this time, the 4-bit data “ijkl” as the result of the operation is stored redundantly in four locations of the 32-bit general-purpose register 12E.

  FIG. 14 is a diagram for explaining the update operation of the status register 12E. In FIG. 14, the general-purpose register 12F stores the decoded data “ijkl” calculated by the calculator 51 at four locations. First, the contents of the general-purpose register 12E, which is a status register, are shifted to the left by 4 bits. Next, unnecessary bit portions are set to 0 by masking the contents of the general-purpose register 12E with predetermined mask data. Finally, an OR operation is performed on the contents of the general-purpose register 12E after masking and the contents of the general-purpose register 12F to update the contents of the general-purpose register 12E that is a status register. The bit shift process, the mask process, and the OR process may be executed as a normal CPU shift instruction, mask instruction, operation instruction, and the like by the instruction unit 11 of FIG.

  FIG. 15 is a diagram illustrating an example of a configuration of an OFDM receiver. The receiver 60 of FIG. 15 includes a receiving circuit 71, a path search unit 72, an FFT processing unit 73, a channel estimator 74, and an error correction unit 75. The OFDM reception signal (radio signal) received by the antenna is demodulated into a baseband signal by the reception circuit 71 and further converted into a digital reception signal. Based on the synchronization point estimated by the synchronization processing as the frame start point, the FFT processing unit 73 performs FFT (Fast Fourier Transform) processing and demodulates the received signal. The channel estimator 74 performs channel estimation processing for detecting a phase shift of the received signal based on the demodulated signal from the FFT processing unit 73. The error correction unit 75 includes a Viterbi decoder 76 and corrects an error in the digital reception signal by executing a Viterbi decoding process. As the Viterbi decoder 76, the decoding apparatus 10 shown in FIG. 1 may be used.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

The present invention includes the following contents.
(Appendix 1)
A status register that stores data indicating the internal state at the time of interest;
From the memory storing the surviving path data of the first bit number for each time for all times, the second bit number smaller than the first bit number for each of a plurality of times from the time of interest to a predetermined preceding time A memory access unit that selects partial data of survivor path data according to the contents of the status register, and reads the partial data for each of the plurality of times;
One bit is selected from the partial data at the last time among the plurality of times according to the contents of the status register, and one bit is selected from the partial data at any time other than the last time among the plurality of times. In the bit selection process for selecting a bit, by selecting a bit according to the partial data at one or more times from the time after the arbitrary time to the last time and the contents of the status register And a calculation unit that selects one bit from the partial data for each of the plurality of times.
(Appendix 2)
In the bit selection process of selecting one bit from the partial data at an arbitrary time that is not the last time among the plurality of times, the arithmetic unit is from the time next to the arbitrary time to the last time. The decoding apparatus according to claim 1, wherein bit selection is performed using at least one bit selected from each of the partial data at one or a plurality of times.
(Appendix 3)
In the bit selection process for selecting one bit from the partial data at an arbitrary time which is not the last time and not the first time among the plurality of times, the arithmetic unit is a time next to the arbitrary time. The decoding apparatus according to claim 1 or 2, wherein a bit is selected according to one bit selected from the partial data at one or a plurality of times from to the last time and the contents of the status register .
(Appendix 4)
In the bit selection process of selecting one bit from the partial data at the first time among the plurality of times, the calculation unit is configured to select one or more from the time next to the first time to the last time. 4. The decoding device according to any one of appendices 1 to 3, wherein bit selection is performed in accordance with one bit selected from each of the partial data at the time.
(Appendix 5)
Store the data indicating the internal state at the time of interest in the status register,
From the memory storing the surviving path data of the first bit number for each time for all times, the second bit number smaller than the first bit number for each of a plurality of times from the time of interest to a predetermined preceding time Selecting partial data of survivor path data according to the contents of the status register, and reading the partial data for each of the plurality of times;
One bit is selected from the partial data at the last time among the plurality of times according to the contents of the status register,
In the bit selection process of selecting one bit from the partial data at an arbitrary time that is not the last time of the plurality of times, one or more of the time from the next time to the last time of the arbitrary time A traceback method in Viterbi decoding, comprising each step of selecting bits according to the partial data of time and the contents of the status register.
(Appendix 6)
In the bit selection process of selecting one bit from the partial data at an arbitrary time that is not the last time among the plurality of times, the bit selecting step includes the last time from the time next to the arbitrary time. 6. The traceback method according to appendix 5, wherein bit selection is performed using at least one bit selected from the partial data at one or a plurality of times until the time.
(Appendix 7)
In the bit selection process of selecting one bit from the partial data at an arbitrary time that is not the last time and not the first time among the plurality of times, the bit selecting step is performed after the arbitrary time. The trace according to claim 5 or 6, wherein a bit is selected according to one bit selected from the partial data at one or a plurality of times from the time to the last time and the contents of the status register Back way.
(Appendix 8)
In the bit selection process of selecting one bit from the partial data at the first time among the plurality of times, the bit selecting step includes one from the time following the first time to the last time. 6. The traceback method according to any one of appendices 5 to 5, wherein a bit is selected according to one bit selected from each of the partial data at a plurality of times.
(Appendix 9)
A receiving circuit for converting a radio signal into a digital received signal;
A decoding device that performs a Viterbi decoding process on the digital reception signal, the decoding device,
A status register that stores data indicating the internal state at the time of interest;
From the memory storing the surviving path data of the first bit number for each time for all times, the second bit number smaller than the first bit number for each of a plurality of times from the time of interest to a predetermined preceding time A memory access unit that selects partial data of survivor path data according to the contents of the status register, and reads the partial data for each of the plurality of times;
One bit is selected from the partial data at the last time among the plurality of times according to the contents of the status register, and one bit is selected from the partial data at any time other than the last time among the plurality of times. In the bit selection process for selecting a bit, by selecting a bit according to the partial data at one or more times from the time after the arbitrary time to the last time and the contents of the status register A receiver for selecting one bit from the partial data for each of the plurality of times.

DESCRIPTION OF SYMBOLS 10 Decoding apparatus 11 Instruction unit 12 Register file 13 Arithmetic unit 14 Memory access unit 20-1 thru | or 20-4 Memory bank

Claims (3)

A status register that stores data indicating the internal state at the time of interest;
From the memory storing the surviving path data of the first bit number for each time for all times, the second bit number smaller than the first bit number for each of a plurality of times from the time of interest to a predetermined preceding time A memory access unit that selects partial data of survivor path data according to the contents of the status register, and reads the partial data for each of the plurality of times;
One bit is selected from the partial data at the last time among the plurality of times according to the contents of the status register, and one bit is selected from the partial data at any time other than the last time among the plurality of times. In the bit selection process for selecting a bit, by selecting a bit according to the partial data at one or more times from the time after the arbitrary time to the last time and the contents of the status register , it looks including an arithmetic unit for selecting one bit from the partial data with respect to each of the plurality of times,
The arithmetic unit includes a plurality of selectors provided corresponding to the plurality of times, respectively, and a selector that selects one bit from the partial data at an arbitrary time other than the last time among the plurality of times is Bit selection is performed using at least a 1-bit selector output selected by the corresponding selector from the partial data at one or a plurality of times from the next time to the last time as an input. > A decoding device characterized by that. In the bit selection process for selecting one bit from the partial data at an arbitrary time which is not the last time and not the first time among the plurality of times, the arithmetic unit is a time next to the arbitrary time. the last one from the time or times of the partial data from claim 1 Symbol placement of a decoding device, characterized in that the bit selected according to the respective selected 1 bit and the contents of the status register from . In the bit selection process of selecting one bit from the partial data at the first time among the plurality of times, the calculation unit is configured to select one or more from the time next to the first time to the last time. The decoding apparatus according to claim 1 or 2 , wherein bit selection is performed according to one bit selected from each of the partial data at the time.

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