JP2011124288A - Tft panel for color display and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TFT panel which has small variance in device characteristics even when an overlapping scanning region is formed in a low-temperature process. <P>SOLUTION: A TFT panel for color display includes: a substrate where thin film transistors are arrayed in columns and a plurality of mutually parallel control regions are successively arranged; and a planarizing film disposed on the substrate. The control regions includes: control regions X where thin film transistors X having a channel formed of a semiconductor layer having a large maximum crystal grain size are arranged in columns; and control regions Y where thin film transistors Y having a channel formed of a semiconductor layer having a small maximum crystal grain size are arranged in columns, wherein an inter-center distance between control regions X is 3n (n: an integer equal to or larger than 1) times as long as short axes of the control regions. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a color display TFT panel and a manufacturing method thereof.

  An active matrix organic EL display, a liquid crystal display, and the like include a TFT panel in which a thin film transistor (TFT) for controlling each sub-pixel is built in, and a pixel disposed on the TFT panel.

  The TFT built in the TFT panel has a gate electrode, a source electrode and a drain electrode, and a channel connecting the source electrode and the drain electrode. An example of the material of the channel includes a polycrystalline silicon (poly-Si) layer having high carrier mobility.

  As a method for forming a channel made of polycrystalline silicon, a low temperature process is known (see, for example, Patent Document 1 and Patent Document 2). The low temperature process is a method that utilizes the property that amorphous silicon melts and recrystallizes in the process of re-solidification. More specifically, the low temperature process generally includes a step of forming an amorphous silicon layer on the substrate and a step of irradiating a laser, a thermal plasma jet, or the like to the amorphous silicon layer formed on the substrate. The amorphous silicon layer irradiated with the laser or the thermal plasma jet melts instantaneously and resolidifies immediately. Silicon is crystallized in the process of re-solidification, and a channel made of polycrystalline silicon is obtained.

  Such a low temperature process has a merit that a channel made of a polycrystalline silicon layer can be manufactured at a low cost because the maximum temperature during the process is relatively low at 600 ° C. or less.

  FIG. 1A is a schematic diagram for explaining a microcrystallization method of a semiconductor layer (amorphous silicon layer) using a thermal plasma jet disclosed in Patent Document 1. FIG. As shown in FIG. 1A, in the method disclosed in Patent Document 1, the substrate 101 is irradiated with a thermal plasma jet ejected from a thermal plasma nozzle 10.

  The thermal plasma nozzle 10 includes an electrode rod 11, an electrode cylinder 12, and a jet port 13. A coolant channel 14 is disposed in the electrode cylinder 12. When a voltage is applied between the electrode rod 11 of the thermal plasma nozzle 10 having such a configuration and the electrode cylinder 12, arc discharge is generated between the two electrodes. During the generation of the arc discharge, an inert gas such as an argon gas is allowed to flow between the electrode rod 11 and the electrode cylinder 12, thereby ejecting a thermal plasma jet 15 from the ejection port 13 to form on the substrate 101. The semiconductor layer (amorphous silicon layer) 103a is irradiated. Thus, the amorphous semiconductor layer 103a is microcrystallized, and a microcrystalline semiconductor layer 103p is formed.

  On the other hand, there is a limit to the region that can be irradiated with the thermal plasma jet. Therefore, when a TFT panel for a large display is manufactured by the low temperature process disclosed in Patent Document 1, the substrate 101 on which the semiconductor layer is formed is scanned with the thermal plasma jet 15 a plurality of times as shown in FIG. 1B. Then, the semiconductor layer 103 on the substrate is microcrystallized.

JP 2008-53632 A JP 2009-75523 A

  However, when the semiconductor layer is microcrystallized by scanning the substrate a plurality of times as disclosed in Patent Document 1, a part of the scanning region is overlapped so that an amorphous semiconductor layer does not remain. For this reason, when manufacturing a TFT panel for a large display, an area that is scanned twice (hereinafter also referred to as “overlapping scanning area”) occurs.

  In the semiconductor layer in the overlapping scanning region, the crystal grain size of the semiconductor layer in a region that is scanned only once (hereinafter also referred to as “single scanning region”) differs greatly from the crystal grain size of the semiconductor layer. The crystal grain size of the semiconductor layer greatly affects the threshold voltage and mobility of the channel formed of the semiconductor layer (see FIG. 3).

  For this reason, characteristics such as threshold voltage and mobility vary in a TFT having a channel formed of a semiconductor layer in the overlapping scanning region. Such variation in TFT characteristics leads to variation in luminance of the color display (hereinafter also referred to as “luminance unevenness”).

  The present invention has been made in view of this point, and an object of the present invention is to suppress display luminance unevenness due to variations in device characteristics of a TFT panel even when an overlapping scanning region occurs in a low temperature process.

The first of the present invention relates to the following TFT panel.
[1] A TFT panel having a substrate in which thin film transistors are arranged in a row and a plurality of control regions parallel to each other are continuously arranged, and a planarization film disposed on the substrate, the control region Includes a control region X in which thin film transistors X having channels made of semiconductor layers having a large maximum crystal grain size are arranged in a row, and a thin film transistor Y having channels made of semiconductor layers having a small maximum crystal grain size in a row. The control region Y is included, and the distance between the centers of the control regions X is 3n [n is an integer of 1 or more] times the minor axis of the control region.
[2] The substrate includes an R control region in which thin film transistors for controlling sub-pixels emitting red light are arranged in a row, and a thin film transistor for controlling sub-pixels emitting green light in a row. The G control region and the B control region in which thin film transistors for controlling sub-pixels emitting blue light are arranged in rows are alternately arranged, and all the control regions X include the R control region, the G control region, and the G control region. The TFT panel for a color display according to [1], which is a control region or the B control region.
[3] The color display TFT panel according to [2], wherein all the control regions X are the G control regions.
[4] The maximum crystal grain size of the semiconductor layer of the thin film transistor X is 100 nm or more, and the maximum crystal grain size of the semiconductor layer of the transistor Y is 70 to 80 nm, any one of [1] to [3] TFT panel for color display as described in 1.

The second aspect of the present invention relates to the organic EL display shown below.
[5] The TFT panel according to [2] or [3] is provided, and a coloring region R in which two or more sub-pixels emitting red light are arranged in a row on the planarizing film of the TFT panel; Color development regions G in which two or more green light emitting sub-pixels are arranged in a row and color development regions B in which two or more blue light emission sub-pixels are arranged in a row are alternately arranged. In the organic EL display, each thin film transistor in the R control region is connected to a pixel electrode of each sub pixel in the color development region R, and each thin film transistor in the G control region is connected to each color pixel in the color development region G. An organic EL display that is connected to a pixel electrode of a sub-pixel, and each thin film transistor in the B control region is connected to a pixel electrode of each sub-pixel in the coloring region B.

A third aspect of the present invention relates to a method for manufacturing a TFT panel shown below.
[6] An R control region in which thin film transistors for controlling subpixels emitting red light are arranged in a row, and a G control region in which thin film transistors for controlling subpixels emitting green light are arranged in a row A TFT for color display, comprising: a substrate on which B control regions in which thin film transistors for controlling sub-pixels emitting blue light are arranged in a row are arranged; and a planarization film disposed on the substrate. A method for manufacturing a panel, comprising: preparing a substrate on which an amorphous semiconductor layer is formed; and scanning the substrate on which the amorphous semiconductor layer is formed with a first scanning region and a second scanning region. Scanning with a thermal plasma jet such that the second scanning region and the third scanning region partially overlap along the scanning direction, and the first scanning region and the second scanning region And Microcrystallizing the semiconductor layer in the third scanning region; patterning the microcrystallized semiconductor layer to form thin film transistor channels in the R control region, the G control region, and the B control region. The major axes of the R control region, the G control region, and the B control region are parallel to the scanning direction, and the minor axes of the R control region, the G control region, and the B control region are the same as the first scanning region. It is larger than the short axis of the overlapping scanning area A where the second scanning area overlaps and the overlapping scanning area B where the second scanning area and the third scanning area overlap, and the overlapping scanning area A and the overlapping scanning area B And the center-to-center distance is n [n is an integer greater than or equal to 1] times the sum of the minor axis of the R control region, the minor axis of the G control region, and the minor axis of the B control region. Color display Manufacturing method of use TFT panel.

  According to the present invention, it is possible to easily correct a TFT having a channel formed of a semiconductor layer in the overlapping scanning region by adjusting the positions and sizes of the overlapping scanning region and the control region. Therefore, according to the present invention, it is possible to suppress display luminance unevenness due to variations in device characteristics of the TFT panel.

Schematic diagram showing a conventional method for microcrystallization of a semiconductor layer disclosed in Patent Document 1 Sectional view of thermal plasma nozzle used in the present invention A graph showing the relationship between the voltage applied to the gate electrode of a TFT and the current flowing between the source and drain The figure which shows the 2nd step of Embodiment 1 of this invention. The figure which shows the 2nd step of Embodiment 1 of this invention. The figure which shows the 2nd step of Embodiment 1 of this invention. The top view of the board | substrate after the 3rd step of Embodiment 1 of this invention The figure which shows the 2nd step of Embodiment 2 of this invention. The figure which shows the organic electroluminescent display of Embodiment 3 of this invention. The figure which shows the organic electroluminescent display of Embodiment 3 of this invention. Plan view of TFT panel included in organic EL display of Embodiment 3 of the present invention

1. TECHNICAL FIELD The present invention relates to a method for manufacturing a TFT panel for a color display by a low temperature process. The TFT panel manufactured by the manufacturing method of the present invention includes a substrate, a thin film transistor (hereinafter also referred to as “TFT”), and a planarizing film.

  On the surface of the substrate, linear R control regions, linear G control regions, and linear B control regions are alternately arranged. The sizes of the R control region, the G control region, and the B control region are preferably the same.

  In the R control area, TFTs for controlling sub-pixels emitting red light are arranged in a row; in the G control area, TFTs for controlling sub-pixels emitting green light are arranged in a row; In the B control region, thin film transistors for controlling sub-pixels that emit blue light are arranged in a row. Therefore, from the TFT panel of the present invention, a region in which red subpixels are arranged in a row (color development region R) and a region in which green subpixels are arranged in a row (color development) on the planarizing film of the TFT panel. A color display panel can be obtained in which regions G) and regions in which blue subpixels are arranged in a row (coloring region B) are alternately arranged (see FIG. 9).

  The sizes of the R control region, the G control region, and the B control region are the same as the sizes of the coloring region R, the coloring region G, and the coloring region B.

  The “TFT for controlling the sub-pixel” includes at least a driving TFT. Further, the “TFT for controlling the sub-pixel” may further include a switching TFT or another TFT.

  Each TFT includes a source electrode and a drain electrode, a channel made of a semiconductor layer that connects the source electrode and the drain electrode, a gate electrode that controls the channel, and a gate insulating film that insulates the gate electrode from the source electrode and the drain electrode. And having.

The manufacturing method of the TFT panel of the present invention is as follows:
1) First step of preparing a substrate on which an amorphous semiconductor layer is formed; and 2) scanning the substrate on which the amorphous semiconductor layer is formed with a thermal plasma jet or a laser to microcrystallize the amorphous semiconductor layer. A second step to
3) patterning the microcrystallized semiconductor layer to form a channel for each TFT in the R control region, the G control region, and the B control region;
4) A fourth step of forming a planarizing film on the substrate. Each step will be described in detail below.

  1) In the first step, a substrate on which an amorphous semiconductor layer is formed is prepared.

Examples of the material of the substrate include silicon carbide (SiC), alumina (Al ₂ O ₃ ), aluminum nitride (AlN), glass, silicon, germanium wafer, and the like.

A silicon oxide film (SiO _x : 0 <x ≦ 2), a silicon nitride film (Si ₃ N _x 0 <x ≦ 4), or the like may be disposed between the substrate and the semiconductor layer. By covering the surface of the substrate with a silicon oxide film or a silicon nitride film, impurities can be prevented from entering the semiconductor layer from the substrate.

  For silicon oxide films, silicon nitride films, etc., the substrate is cleaned with pure water or alcohol, and then atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), plasma chemical vapor deposition It may be formed on the surface of the substrate by a CVD method such as a PECVD method or a film forming method such as a sputtering method.

  The semiconductor layer is, for example, a silicon layer. A method for forming the semiconductor layer on the substrate is not particularly limited, and examples thereof include a CVD method such as APCVD method, LPCVD method, and PECVD method, or a physical vapor deposition method (PVD method) such as sputtering method and vapor deposition method.

2) In the second step, the substrate on which the amorphous semiconductor layer is formed is scanned with a thermal plasma jet or laser to microcrystallize the amorphous semiconductor layer. Specifically, the first scanning region is scanned to microcrystallize the amorphous semiconductor layer in the first scanning region; the second scanning region is scanned, and the amorphous semiconductor layer in the second scanning region is micronized. Crystallization; the third scanning region is scanned, and the amorphous semiconductor layer in the third scanning region is microcrystallized.
In the present invention, the substrate is scanned such that the first scanning region and the second scanning region partially overlap along the scanning direction; and the second scanning region and the third scanning region partially overlap along the scanning direction. (See FIGS. 4 to 6).

  Here, “scanning the substrate with a thermal plasma jet or laser” means moving the thermal plasma jet or laser relative to the substrate while irradiating the substrate with the thermal plasma jet or laser. In order to move the thermal plasma jet or laser relative to the substrate, the thermal plasma jet source or laser source may be moved, the substrate may be moved, or both may be moved.

The “scanning region” means a region where the semiconductor layer is microcrystallized by scanning with one thermal plasma jet or laser. More specifically, "scanning area"
The term “region heated by a thermal plasma jet or laser” means a region heated to 600 to 1100 ° C. This is because a semiconductor layer made of amorphous silicon or the like is usually microcrystallized by heating at 600 to 1100 ° C. Further, “microcrystallize” means that the crystal grain size of the semiconductor layer is 10 to 80 nm.

  The width of a region that can be processed by scanning with a thermal plasma jet ejected from one head is 1 to 100 mm, and the width of a region that can be processed by scanning with a laser irradiated from one head is 1 to 200 mm. The sizes of the first scanning region, the second scanning region, and the third scanning region are preferably the same, but may be different.

  In the present invention, the first scanning region, the second scanning region, and the third scanning region may be sequentially scanned (see the first embodiment), or may be scanned simultaneously (see the second embodiment).

  When scanning the first scanning region, the second scanning region, and the third scanning region in order, after scanning the first scanning region, the laser light source or the thermal plasma source is moved to the scanning direction end of the second scanning region, The second scanning area is scanned. Then, after scanning the second scanning region, the laser light source or the thermal plasma source is moved to the scanning direction end of the third scanning region to scan the third scanning region (see FIGS. 4 to 6).

  On the other hand, when simultaneously scanning the first scanning region, the second scanning region, and the third scanning region, at least three laser light sources or thermal plasma sources are prepared, and the first scanning region, the second scanning region, and the third scanning region, respectively. The first scanning region, the second scanning region, and the third scanning region are simultaneously scanned (see FIG. 8).

  As described above, in the substrate, the first scanning region and the second scanning region partially overlap along the scanning direction; and the second scanning region and the third scanning region partially overlap along the scanning direction. Scanned. A region where the first scanning region and the second scanning region overlap is referred to as an overlapping scanning region A. A region where the second scanning region and the third scanning region overlap is referred to as an overlapping scanning region B. In the overlapping scanning region, the substrate is scanned twice with a thermal plasma jet or laser. The short axis of the overlapping scanning region is usually 100 μm or less and 10 to 100 μm.

  In this way, the crystal grain size of the semiconductor layer microcrystallized by scanning twice is different from the crystal grain size of the semiconductor layer microcrystallized only by one scan. Specifically, the crystal grain size of the semiconductor layer in a scanning region that is scanned only once (scanning region other than the overlapping scanning region; hereinafter also referred to as “single scanning region”) falls within the range of 10 nm to 80 nm, The crystal grain size of the semiconductor layer in the overlapping scanning region varies greatly from 10 nm to 1000 nm (1 μm). Thus, in the overlapping scanning region, the maximum crystal grain size of the semiconductor layer becomes large. In addition, the average crystal grain size of the semiconductor layer in the overlapping scanning region is 20 nm or more larger than the average crystal grain size of the semiconductor layer in the single scanning region.

  The substrate may be scanned with a laser or a thermal plasma jet, but is preferably scanned with a thermal plasma jet. Scanning with a thermal plasma jet can process a large area at a higher speed, so that the semiconductor layer can be crystallized at a lower cost. Further, when scanning with a thermal plasma jet, the heat treatment time is as short as msec order, so that stable microcrystals by SPC (Solid Phase Crystallization) can be obtained.

  Here, the “thermal plasma” is a thermal equilibrium plasma, and is an ultra-high temperature heat source having a temperature of about 10,000 K such as ions, electrons, and neutral atoms. “Thermal plasma jet” means a high-speed thermal plasma flow. Such a thermal plasma jet is ejected from a thermal plasma nozzle as shown in FIG.

  As shown in FIG. 2, the thermal plasma nozzle 10 includes an electrode rod 11, an electrode cylinder 12, and a jet port 13. A coolant channel 14 is disposed in the electrode cylinder 12. When a voltage is applied between the electrode rod 11 of the thermal plasma nozzle 10 having such a configuration and the electrode cylinder 12, arc discharge is generated between the two electrodes. The thermal plasma jet 15 can be ejected from the ejection port 13 by flowing an inert gas such as argon gas between the electrode rod 11 and the electrode cylinder 12 during the occurrence of arc discharge. As described above, the temperature of the thermal plasma is about 10,000 K, but the temperature of the thermal plasma jet ejected from the ejection port 13 is preferably about 600 to 1100 ° C.

  When the substrate is scanned with a thermal plasma jet, the flow rate of the inert gas is set to 1.0 to 6.0 L / sec, the power supplied to the thermal plasma nozzle is set to about 10 kW, and the gap G between the ejection port 13 and the substrate 101 is set. The scanning speed may be 5 to 200 mm and the scanning speed may be 100 to 2000 mm / second.

Thus, carrier mobility of the semiconductor layer can be improved by microcrystallizing the semiconductor layer in the second step. More specifically, the carrier mobility of the amorphous semiconductor layer is about 0.5 cm ² / Vs. By setting the crystal grain size of the semiconductor layer to 10 to 80 nm, the carrier mobility is 1 to 10 cm. It can be raised to ² / Vs.

  3) In the third step, the microcrystallized semiconductor layer is patterned to form channels for each TFT in the R control region, the G control region, and the B control region. The means for patterning the semiconductor layer is not particularly limited, and examples include wet etching and dry etching.

  In the present invention, the major axes of the R control region, the G control region, and the B control region are parallel to the scanning direction. The minor axes of the R control region, the G control region, and the B control region are larger than the minor axes of the overlapping scanning region A and the overlapping scanning region B. Usually, the short axis of the control region is 100 μm or more.

  The center-to-center distance between the overlapping scanning area A and the overlapping scanning area B is n times the sum of the minor axis of the R control area, the minor axis of the G control area, and the minor axis of the B control area. Here, “n” means an integer of 1 or more.

  As described above, in the overlapping scanning region scanned twice, the crystal grain size of the semiconductor layer greatly varies and becomes unstable. The crystal grain size of the semiconductor layer that is the channel affects the threshold voltage and mobility of the TFT. Specifically, if the crystal grain size of the semiconductor layer that is a channel is large, the threshold voltage of the TFT is low and the mobility is large, and if the crystal grain size of the semiconductor layer that is a channel is small, the threshold voltage of the TFT is high. , Mobility decreases.

  For this reason, in a TFT having a channel made of a semiconductor layer with an unstable crystal grain size in the overlapping scanning region (hereinafter also referred to as “TFT-X”), the threshold voltage is increased or decreased, and the mobility is increased. Or the TFT characteristics become unstable (see FIG. 3).

  However, in the present invention, the minor axes of the R control region, the G control region, and the B control region are set to be equal to or larger than the minor axes of the overlapping scanning region A and the overlapping scanning region B, and the centers of the overlapping scanning region A and the overlapping scanning region B are set. By making the distance between n times the sum of the short axis lengths of the R control region, the G control region, and the B control region, it becomes easy to correct the TFT-X, and variations in device characteristics of the TFT panel It becomes possible to suppress the luminance unevenness of the display.

  By controlling the size and position of the control region and the overlapping scanning region in this way, the mechanism that can suppress the display luminance unevenness due to the variation in the device characteristics of the TFT panel will be described later. The panel will be described in detail.

  In the TFT panel manufacturing method of the present invention, before the fourth step of forming the planarizing film, a step of forming a gate electrode, a step of forming a gate insulating film, and a source electrode and a drain electrode are further formed. Steps. The electrode and the gate insulating film are formed by, for example, a CVD method.

  The step of forming the gate electrode, the step of forming the gate insulating film, and the step of forming the source electrode and the drain electrode differ in order depending on whether the TFT included in the TFT panel is a top gate or a bottom gate.

  When the TFT is a top gate, the TFT is manufactured in the order of patterning a semiconductor layer, forming a source electrode and a drain electrode, forming a gate insulating film, and forming a gate electrode.

  On the other hand, when the TFT is a bottom gate, the TFT is manufactured in the order of a step of forming a gate electrode, a step of forming a gate insulating film, a step of patterning a semiconductor layer, and a step of forming a source electrode and a drain electrode. .

  4) In the fourth step, a planarizing film is formed on the substrate. The planarization film is formed so as to cover the TFT disposed on the substrate. The material of the planarizing film is not particularly limited as long as it is insulative. For example, acrylic or polyimide is used.

  Thus, according to the present invention, it is possible to manufacture a TFT panel having no variation in device characteristics.

2. Next, the TFT panel manufactured by the above-described manufacturing method of the present invention will be described.

  The TFT panel of the present invention includes a substrate, a TFT disposed on the substrate, and a planarization film disposed on the substrate so as to cover the TFT.

  A plurality of control regions parallel to each other are continuously arranged on the substrate. The control region includes an R control region in which TFTs for controlling sub-pixels emitting red light are arranged in a row, and a G control region in which TFTs for controlling sub-pixels emitting green light are arranged in a row. And a B control region in which TFTs for controlling sub-pixels emitting blue light are arranged in rows. That is, in the TFT panel of the present invention, the R control region, the G control region, and the B control region are alternately arranged on the substrate.

Examples of the material of the substrate include silicon carbide (SiC), alumina (Al ₂ O ₃ ), aluminum nitride (AlN), glass, silicon, germanium wafer, and the like.

The surface of the substrate may be covered with a silicon oxide film (SiO _x : 0 <x ≦ 2) or a silicon nitride film (Si ₃ N _x 0 <x ≦ 4). By covering the surface of the substrate with a silicon oxide film or a silicon nitride film, it is possible to prevent impurities from entering the semiconductor layer described later from the substrate.

  Each TFT includes a source electrode and a drain electrode, a channel made of a semiconductor layer that connects the source electrode and the drain electrode, a gate electrode that controls the channel, and a gate insulating film that insulates the gate electrode from the source electrode and the drain electrode. And having.

  Examples of semiconductor layer materials include group 4 elements such as silicon and germanium, group 4 elements such as silicon / germanium, silicon carbide and germanium carbide, and group 3 elements such as gallium / arsenic and indium / antimony. And a compound compound of a cadmium selenium group 2 element and a group 6 element. As described above, the semiconductor layer of the present invention is microcrystallized by scanning with a thermal plasma jet or a laser.

  The control region of the present invention includes a control region (hereinafter also referred to as “control region X”) in which TFTs (TFT-X) having a channel made of a semiconductor layer having a large maximum crystal grain size are arranged in a line, and a maximum crystal And a control region (hereinafter also referred to as “control region Y”) in which TFTs (TFT-Y) each having a channel made of a semiconductor layer having a small particle size are arranged in a row. As described above, the TFT-X is a TFT having a channel formed of a semiconductor layer in the overlapping scanning region described in the “manufacturing method of the TFT panel of the present invention”; the TFT-Y is “the manufacturing method of the TFT panel of the present invention”. This is a TFT having a channel made of a semiconductor layer in the single scanning region described above. For this reason, the control area X in the TFT panel includes an overlapping scanning area in the manufacturing process of the TFT panel, and the control area Y includes a single scanning area in the manufacturing process of the TFT panel (see FIG. 7).

  As described above, the maximum crystal grain size of the semiconductor layer in the overlapping scanning region is larger than the maximum crystal grain size of the semiconductor layer in the single scanning region. For this reason, the maximum crystal grain size of the semiconductor layer of TFT-X is usually larger than the maximum crystal grain size of the semiconductor layer of TFT-Y. More specifically, the maximum crystal grain size of the semiconductor layer of TFT-X is 100 nm or more, and the maximum crystal grain size of the semiconductor layer of TFT-Y is 70 to 80 nm. Further, the average crystal grain size of the semiconductor layer of TFT-X is 20 nm or more larger than the average crystal grain size of the semiconductor layer of TFT-X.

  Further, as described above, the crystal grain size (10 nm to 1000 nm) of the semiconductor layer in the overlapping scanning region differs greatly from the crystal grain size (10 nm to 80 nm) of the semiconductor layer in the single scanning region. For this reason, the crystal grain size of the semiconductor layer of TFT-X also varies in the range of 10 nm to 1000 nm and becomes unstable.

  The crystal grain size of the semiconductor layer can be calculated by measuring the crystal grain size of the semiconductor layer from the SEM photograph of the semiconductor layer.

  As described above, the center-to-center distance between the overlapping scanning regions is 3n times the short axis of the control region (n times the sum of the short axis lengths of the R control region, the G control region, and the B control region). Has been. Therefore, even in a finished TFT panel, the center-to-center distance between the control regions X is 3n times the short axis of the control region.

  As described above, in the TFT panel, the R control region, the G control region, and the B control region are alternately arranged. For this reason, when the distance between the centers of the control regions X is 3n times the short axis of the control region, all the control regions X become the R control region, the G control region, or the B control region.

The control area X may be an R control area, a G control area, or a B control area, but is preferably a control area of a sub-pixel having the highest light emission efficiency.
The following table is a table showing the luminous efficiency (cd / A) of the sub-pixel in the organic EL display.

  As shown in Table 1, in the organic EL display, the luminous efficiency of the sub-pixel that emits green light is the highest. For this reason, when a TFT panel is used for an organic EL display, it is preferable that all the control areas X are G control areas.

  As described above, the crystal grain size of the semiconductor layer of TFT-X included in the control region X varies greatly and becomes unstable. For this reason, in the control region X, the threshold voltage and mobility of the TFT-X vary. When the threshold voltage varies, the current flowing between the source and the drain varies even when the same gate voltage is applied. In addition, when the mobility varies, the channel current easily flows, so even when the same gate voltage is applied, the current flowing between the source and the drain varies. Such variations in TFT characteristics (threshold voltage and mobility) lead to luminance unevenness between pixels of the display.

  In order to suppress display luminance unevenness due to variations in TFT characteristics (threshold voltage and mobility), it is necessary to correct TFT-X.

  Here, “correcting the TFT-X” means adjusting the voltage applied to the gate electrode of the TFT-X or adjusting the potential difference between the source electrode and the drain electrode of the TFT-X. It means canceling out the difference in voltage and mobility.

  FIG. 3 is a graph showing the relationship between the voltage applied to the gate electrode of the TFT and the current flowing between the source electrode and the drain electrode. The vertical axis represents the current flowing between the source electrode and the drain electrode, and the horizontal axis represents the voltage applied to the gate electrode. Curve X (X-1, X-2) shows the relationship between the gate voltage and the source-drain current in TFT-X; curve Y shows the gate voltage and the source-drain current in TFT-Y. Show the relationship.

  As described above, in TFT-Y, there is little variation in the crystal grain size of the semiconductor layer serving as a channel. For this reason, in the TFT-Y, the threshold voltage is stabilized. Therefore, as shown in FIG. 3, in the TFT-Y, when the gate voltage is constant, the current (Ia) flowing between the source and drain of the TFT-Y is also constant.

  On the other hand, in the TFT-X, the variation in crystal grain size of the semiconductor layer serving as a channel is large. For this reason, in the TFT-X, the threshold voltage becomes unstable, and the relationship between the gate voltage and the current between the source and the drain varies in the range from the curve X-1 to the curve X-2 shown in FIG. Therefore, in TFT-X, even if the gate voltage is constant, the current flowing between the source and drain of TFT-X varies in the range of Ib to Ic.

  Such a variation in current between the source and drain leads to uneven brightness of the display. For this reason, the TFT-X is required to make the amount of current flowing between the source and drain of the TFT-X constant by correction.

Specifically, the current flowing between the source and drain of the TFT-X having the characteristics of the curve X-1 by reducing the gate voltage of the TFT-X or reducing the potential difference between the source electrode and the drain electrode. Can be made the same as the current flowing between the source and drain of the TFT-Y.
Further, by increasing the gate voltage of the TFT-X or increasing the potential difference between the source electrode and the drain electrode, the current flowing between the source and the drain of the TFT-X having the characteristics of the curve X-2 is reduced. It can be the same as the current flowing between the source and drain of -Y.

  By correcting the TFT-X in this manner, luminance unevenness due to variations in characteristics of the TFT-X can be suppressed.

  In the present invention, the control region X is the control region of the sub-pixel having the highest light emission efficiency (for example, the G control region in the case of an organic EL display having the sub-pixel of the light emission efficiency shown in Table 1). It is easy to correct.

  Since the sub-pixel with high light emission efficiency can be driven with a low current, the amount of current flowing between the source and drain of the TFT that controls the sub-pixel with high light emission efficiency is set to be relatively small. For this reason, it is easy to further increase the amount of current flowing between the source and drain by correction.

  On the other hand, a subpixel with low luminous efficiency (for example, a subpixel that develops blue color in the case of an organic EL display) requires a large amount of current to obtain a certain luminance. For this reason, the amount of current flowing between the source and drain of the TFT that controls the sub-pixel having low light emission efficiency is often already set high. For this reason, it may not be possible to further increase the amount of current flowing between the source and drain by correction.

  Thus, according to the present invention, it is possible to suppress luminance unevenness due to variations in device characteristics of the TFT panel.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[Embodiment 1]
In Embodiment 1, a manufacturing method of a TFT panel using one plasma source will be described.

  The manufacturing method of the TFT panel of this embodiment includes 1) a first step of preparing a substrate 101 on which an amorphous semiconductor layer 103a is formed, and 2) heating the substrate 101 on which an amorphous semiconductor layer 103a is formed. A second step of microcrystallizing the amorphous semiconductor layer 103a by scanning with the plasma jet 15 (FIGS. 4 to 6), and 3) patterning the microcrystallized semiconductor layer 103p, and thereby controlling the R control regions 220R, G It has a third step for forming the channels of the respective TFTs in the control region 220G and the B control region 220B (FIG. 7), and 4) a fourth step for forming a planarizing film on the substrate 101.

  1) In the first step, a substrate 101 on which an amorphous semiconductor layer 103a is formed is prepared. The substrate 101 is, for example, a glass substrate, and the semiconductor layer 103a is, for example, an amorphous silicon layer.

  2) In the second step, the substrate 101 on which the amorphous semiconductor layer 103a is formed is scanned with the thermal plasma jet 15 to microcrystallize the amorphous semiconductor layer 103a. In the present embodiment, the first scanning region 110, the second scanning region 120, and the third scanning region 130 are sequentially scanned with a thermal plasma jet ejected from one plasma source, and an amorphous state in the first scanning region 110 is obtained. The semiconductor layer 103a is microcrystallized; the amorphous semiconductor layer 103a in the second scanning region 120 is microcrystallized; and the amorphous semiconductor layer 103a in the third scanning region 130 is microcrystallized.

  FIG. 4 shows how the first scanning region 110 is scanned with the thermal plasma jet 15. The temperature of the thermal plasma jet 15 in the scanning region may be 600-1100 ° C. By scanning the first scanning region 110 with such a thermal plasma jet 15, the amorphous semiconductor layer 103 a in the first scanning region 110 is microcrystallized, and a microcrystalline semiconductor layer 103 p is formed.

  FIG. 5 shows how the second scanning region 120 is scanned with the thermal plasma jet 15. As shown in FIG. 5, the first scanning region 110 and the second scanning region 120 partially overlap along the scanning direction. By scanning the second scanning region 120 with the thermal plasma jet 15, the amorphous semiconductor layer 103a in the second scanning region 120 is microcrystallized, and a microcrystalline semiconductor layer 103p is formed.

  In the overlapping scanning region 140A where the first scanning region 110 and the second scanning region 120 overlap, the already microcrystallized semiconductor layer 103p is further scanned. Thus, the variation in the crystal grain size of the semiconductor layer 103p in the region scanned twice is larger than the variation in the crystal grain size of the semiconductor layer 103p in the region scanned only once.

  FIG. 6 shows how the third scanning region 120 is scanned with the thermal plasma jet 15. As shown in FIG. 6, the second scanning region 120 and the third scanning region 130 partially overlap along the scanning direction. By scanning the third scanning region 130 with the thermal plasma jet 15, the amorphous semiconductor layer 103a in the third scanning region 130 is microcrystallized, and a microcrystalline semiconductor layer 103p is formed.

  In the overlapping scanning region 140B where the second scanning region 120 and the third scanning region 130 overlap, the already microcrystallized semiconductor layer 103p is further scanned. Thus, the variation in crystal grain size of the semiconductor 103p in the region scanned twice is larger than the variation in crystal grain size of the semiconductor layer 103p in the region scanned only once.

  In this manner, by repeatedly scanning the substrate 101, all of the amorphous semiconductor layer 103a over the substrate 101 is changed to a microcrystalline semiconductor layer 103p. 4 to 6 illustrate the example in which the scanning direction of the substrate is one direction, the substrate may be scanned while folding the thermal plasma jet as shown in FIG. 1B.

  3) In the third step, the microcrystallized semiconductor layer 103p is patterned to form channels for the TFTs in the R control region 220R, the G control region 220G, and the B control region 220B. The means for patterning the semiconductor layer is, for example, wet etching or dry etching.

  FIG. 7 is a plan view of the substrate 101 after the semiconductor layer is patterned in the third step to form the channel of each TFT. In the region 210, a TFT channel 150 for controlling one subpixel is arranged. In each region 210, a channel 150a for driving TFT and a channel 150b for switching TFT are arranged. As described above, FIG. 7 illustrates an example in which the number of TFTs that control one subpixel is two, that is, the driving TFT and the switching TFT, but the number of TFTs that control one subpixel is two or more. May be. On the substrate 101, R control regions 220R, G control regions 220G, and B control regions 220B are alternately arranged.

  In the present embodiment, the major axes of the R control region 220R, the G control region 220G, and the B control region 220B are parallel to the scanning direction. The major axes of the R control region 220R, the G control region 220G, and the B control region 220B are larger than the minor axes of the overlapping scanning region 140A and the overlapping scanning region 140B.

  Further, the center distance d between the overlapping scanning region 140A and the overlapping scanning region 140B is n times the sum of the short axis of the R control region 220R, the short axis of the G control region 220G, and the short axis of the B control region 220B. . Here, “n” means an integer of 1 or more. Further, all the overlapping scanning areas (140A, 140B) overlap the G control area 220G.

  For this reason, in the present embodiment, all TFTs (TFT-X) having a channel formed of the semiconductor layer 103p in the overlapping scanning region 140 are arranged in the G control region 220G.

  4) In the fourth step, a planarizing film is formed on the substrate 101 by, for example, spin coating or die coating.

  As described above, in the present embodiment, the region in which the TFT-X is arranged is set as the control region of the sub-pixel having the highest light emission efficiency (for example, the G control region in the case of an organic EL display). Correction becomes easy. For this reason, according to the present embodiment, luminance unevenness due to variations in device characteristics of the TFT panel can be suppressed.

[Embodiment 2]
In the first embodiment, the manufacturing method of the TFT panel in which the substrate is scanned with the thermal plasma jet from one plasma source has been described. In the second embodiment, a manufacturing method of a TFT panel using two or more plasma sources will be described.

  The manufacturing method of the TFT panel of this embodiment includes 1) a first step of preparing a substrate 101 on which an amorphous semiconductor layer 103a is formed, and 2) heating the substrate 101 on which an amorphous semiconductor layer 103a is formed. A second step of microcrystallizing the amorphous semiconductor layer 103a by scanning with the plasma jet 15; and 3) patterning the microcrystallized semiconductor layer 103p to form an R control region 220R, a G control region 220G, and a B control region. A third step of forming a channel of each TFT of 220B, and 4) a fourth step of forming a planarizing film on the substrate 101.

  The manufacturing method of the present embodiment is the same as the manufacturing method of the first embodiment except for the second step. Therefore, in this embodiment, descriptions other than the second step are omitted.

  FIG. 8 shows a state of the substrate 101 scanned in the second step of the present embodiment. As shown in FIG. 8, in the second step of the present embodiment, three thermal plasma jets 15 simultaneously scan the first scanning region, the second scanning region, and the third scanning region. Each thermal plasma jet 15 is ejected from a separate plasma source (spout port).

  As shown in FIG. 8, the first scanning region 110, the second scanning region 120, and the third scanning region 130 are scanned, so that the semiconductor layers in the first scanning region 110, the second scanning region 120, and the third scanning region 130 are scanned. 103a is microcrystallized to form a microcrystalline semiconductor layer 103p.

  Also in the present embodiment, the first scanning region 110 and the second scanning region 120 partially overlap along the scanning direction; the second scanning region 120 and the third scanning region 130 are identical along the scanning direction. Duplicate parts. Therefore, the overlapping scanning region 140A where the first scanning region 110 and the second scanning region 120 overlap and the overlapping scanning region 140B where the second scanning region 120 and the third scanning region 130 overlap are scanned twice.

  Thus, according to the present embodiment, since the substrate is scanned with a plurality of thermal plasma jets, the area that can be scanned per unit time is large. For this reason, according to the present embodiment, in addition to the effects of the first embodiment, the TFT panel can be manufactured in a shorter time.

[Embodiment 3]
In Embodiment 3, an organic EL display having a TFT panel manufactured by the manufacturing method of the present invention will be described.

  FIG. 9A is a plan view of the organic EL display 300 of the present embodiment. As shown in FIG. 9A, the organic EL display 300 of the present embodiment includes a TFT panel 100 and a plurality of subpixels 310 arranged in a matrix on the TFT panel 100. The sub-pixel 310 includes a sub-pixel 310R that emits red light, a sub-pixel 310G that emits green light, and a sub-pixel 310B that emits blue light. The sub-pixel 310R, the sub-pixel 310G, and the sub-pixel 310B constitute one pixel.

  FIG. 9B is a sectional view of the sub-pixel 310 included in the organic EL display 300 shown in FIG. 9A. As shown in FIG. 9B, each subpixel 310 is disposed on at least the pixel electrode 311 disposed on the TFT panel 100, the organic functional layer 313 disposed on the pixel electrode 311, and the organic functional layer 313. Counter electrode (not shown). The organic functional layer 313 is delimited by a bank 301 disposed on the TFT panel 100. The bank 301 is an organic layer made of a polyimide resin having a height of about 1 μm.

  Further, on the flattening film of the TFT panel, a coloring region 320R in which the subpixels 310R are arranged in a row, a coloring region 320G in which the subpixels 310G are arranged in a row, and a subpixel 310B that emits blue light. The color development regions 320B arranged in a row are alternately arranged. The long axis of the coloring area 320 is parallel to the long axis of the control area 220 described later.

  Although FIG. 9 shows a form in which the organic functional layer of each sub-pixel is divided by the bank 301 disposed on the TFT panel 100, the organic functional layer is provided for each coloring region 320 as shown in FIG. 10A. It may be divided by the bank 301. As shown in FIG. 10A, when the organic functional layer is divided by the bank 301 for each color development area 320, the organic functional layers of the sub-pixels 310 in the color development area 320 are connected in a line.

  FIG. 10B is a cross-sectional view of the sub-pixel 310 included in the organic EL display 300 shown in FIG. 10A. As shown in FIG. 10B, when the organic functional layer is divided by the bank 301 for each color development region 320, the bank 301 is preferably disposed on the pixel regulation layer 302 surrounding the pixel electrode 311. The pixel regulating layer 302 is an inorganic insulating layer made of SiN having a thickness of 30 to 300 nm and disposed on the TFT panel 100 by a sputtering method or the like.

  FIG. 11 is a plan view of an organic EL display in which subpixels are omitted from the organic EL display of the present embodiment. That is, FIG. 11 is a plan view of the TFT panel 100.

  The TFT panel 100 includes a substrate 101, TFTs (driving TFT 160a and switching TFT 160b) disposed on the substrate 101, and a planarizing film (not shown) disposed on the substrate.

  On the substrate 101, the R control region 220R in which the TFTs (the driving TFT 160a and the switching TFT 160b) for controlling the subpixel 310R described above are arranged in a row, and the TFT for controlling the subpixel 310G in a row. The arranged G control areas 220G and the B control areas 220B in which TFTs for controlling the sub-pixels 310B are arranged in a line are alternately arranged. The sizes of the R control region 220R, the G control region 220G, and the B control region 220B are the same as the sizes of the coloring region 320R, the coloring region 320G, and the coloring region 320B.

  Each TFT 160 includes a source electrode and a drain electrode, a channel made of a semiconductor layer that connects the source electrode and the drain electrode, a gate electrode that controls the channel, and a gate insulating film that insulates the gate electrode from the source electrode and the drain electrode. (Not shown).

  The source or drain electrode of the TFT in the R control region 220R is connected to the pixel electrode of the subpixel 310R; the source electrode or drain electrode of the TFT in the G control region 220G is connected to the pixel electrode of the subpixel 310G; The source electrode or drain electrode of the TFT in the R control region 220G is connected to the pixel electrode of the sub-pixel 310G.

  As shown in FIG. 11, the control region includes a control region X in which TFTs (TFT-X) having a channel formed of a semiconductor layer having a large maximum crystal grain size are arranged in a row. As described above, the TFT-X is a TFT having a channel formed of a semiconductor layer in the overlapping scanning region described in the “manufacturing method of the TFT panel of the present invention”.

  The center distance d between the control regions 220 </ b> X is 3n times the short axis of the control region 220. For this reason, all the control areas 220X become the R control area 220R, the G control area 220G, or the B control area 220B. More specifically, all the control areas 220X are G control areas 220G.

  As described above, in the organic EL display panel according to the present embodiment, the control region 220X is set to the G control region 220G of the sub-pixel 310G having the highest light emission efficiency, thereby facilitating correction of the TFT-X.

  In this embodiment, an example in which the subpixel having the highest light emission efficiency is the subpixel G has been described. However, the light emission efficiency of the subpixel varies depending on the material. For this reason, depending on the material, not only the subpixel G but the subpixel R or the subpixel B may have the highest light emission efficiency. In this case, all the control regions 220X should be the R control region of the subpixel R or the B control region of the subpixel B having the highest light emission efficiency.

  Thus, according to the present embodiment, an organic EL display without luminance unevenness can be obtained.

  According to the present invention, by adjusting the position of the overlapping scanning region, it is possible to easily correct the characteristics of the TFT having a channel formed of a semiconductor layer in the overlapping scanning region. For this reason, according to the present invention, it is possible to provide a color display without luminance unevenness.

DESCRIPTION OF SYMBOLS 10 Thermal plasma nozzle 11 Electrode rod 12 Electrode cylinder 13 Jet outlet 14 Refrigerant flow path 15 Thermal plasma jet 100 TFT panel 101 Substrate 103 Semiconductor layer 110 1st scanning area 120 2nd scanning area 130 3rd scanning area 140 Overlapping scanning area 150 Channel 160 TFT
220 Control Area 300 Organic EL Display 301 Bank 302 Pixel Restriction Layer 310 Subpixel 311 Pixel Electrode 313 Organic Functional Layer 320 Coloring Area

Claims (6)

A TFT panel having a substrate in which thin film transistors are arranged in a row and a plurality of control regions parallel to each other are continuously arranged, and a planarization film disposed on the substrate,
In the control region, a thin film transistor X having a channel made of a semiconductor layer having a large maximum crystal grain size and a thin film transistor Y having a channel made of a semiconductor layer having a small maximum crystal grain size are arranged in a row. A control region Y arranged in a shape,
The center panel distance between the control regions X is 3n [n is an integer of 1 or more] times the short axis of the control region. The substrate includes an R control region in which thin film transistors for controlling subpixels emitting red light are arranged in a row, and a G control in which thin film transistors for controlling subpixels emitting green light are arranged in a row. The regions and the B control regions in which thin film transistors for controlling the sub-pixels emitting blue light are arranged in rows are alternately arranged,
2. The color display TFT panel according to claim 1, wherein all the control regions X are the R control region, the G control region, or the B control region.   The color display TFT panel according to claim 2, wherein all the control regions X are the G control regions.   The TFT panel for a color display according to claim 1, wherein the maximum crystal grain size of the semiconductor layer of the thin film transistor X is 100 nm or more, and the maximum crystal grain size of the semiconductor layer of the transistor Y is 70 to 80 nm. A TFT panel according to claim 2,
On the flattening film of the TFT panel, a coloring region R in which two or more red light emitting sub-pixels are arranged in a row and a coloring coloring region R in which two or more green light emitting sub-pixels are arranged in a row G and an organic EL display in which two or more blue light emitting sub-pixels are alternately arranged and a color development region B arranged in a row,
Each thin film transistor in the R control region is connected to a pixel electrode of each sub-pixel in the coloring region R;
Each thin film transistor in the G control region is connected to a pixel electrode of each sub-pixel in the coloring region G;
An organic EL display in which each thin film transistor in the B control region is connected to a pixel electrode of each sub-pixel in the coloring region B. An R control region in which thin film transistors for controlling subpixels emitting red light are arranged in a row, a G control region in which thin film transistors for controlling subpixels emitting green light are arranged in a row, and a blue color A TFT panel for a color display, comprising: a substrate in which B control regions in which thin film transistors for controlling subpixels for light emission are arranged in a row are alternately arranged; and a planarization film disposed on the substrate. A method,
Providing a substrate on which an amorphous semiconductor layer is formed;
In the substrate on which the amorphous semiconductor layer is formed, the first scanning region and the second scanning region partially overlap along the scanning direction, and the second scanning region and the third scanning region extend in the scanning direction. Scanning with a thermal plasma jet so as to partially overlap, and microcrystallizing the semiconductor layers in the first scanning region, the second scanning region, and the third scanning region;
Patterning the microcrystallized semiconductor layer to form thin film transistor channels in the R control region, G control region and B control region,
The major axes of the R control region, the G control region, and the B control region are parallel to the scanning direction, and the minor axes of the R control region, the G control region, and the B control region are the first scanning region and the first control region. Larger than the short axis of the overlapping scanning region A where the two scanning regions overlap and the overlapping scanning region B where the second scanning region and the third scanning region overlap, and the overlapping scanning region A and the overlapping scanning region B A center-to-center distance is n [n is an integer greater than or equal to 1] times the sum of the minor axis of the R control region, the minor axis of the G control region, and the minor axis of the B control region;
A manufacturing method of a TFT panel for a color display having

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